Electrostatic Discharge Protection Circuit and Integrated Circuit Chip

Abstract

The present invention discloses an electrostatic discharge protection circuit and an integrated circuit chip. The electrostatic discharge protection circuit is applied to the integrated circuit chip, and the integrated circuit chip includes a power supply terminal, a signal input terminal, and a ground terminal. The electrostatic discharge protection circuit includes a first protection circuit and a second protection circuit. The first protection circuit includes a first NMOS transistor. The second protection circuit includes a capacitor, a second NMOS transistor, and a third NMOS transistor. The first NMOS transistor and the second NMOS transistor share a gate coupling effect. This electrostatic discharge protection circuit enables the high-speed input PAD to still use a protection circuit with a gate coupling effect to improve the electrostatic discharge protection ability.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular, to an electrostatic discharge protection circuit and an integrated circuit chip. Background Art

[0002] As the semiconductor process technology becomes more and more advanced, the cost of integrated circuit chips is getting lower and lower, the area is getting smaller and smaller, the functions are getting stronger and stronger, and the processing speed is getting faster and faster. However, at the same time, the thickness of the transistor gate oxide layer is getting smaller and smaller, which poses higher and higher requirements for the design of electrostatic discharge protection (ESD) circuits. How to achieve good electrostatic discharge protection for high-speed integrated circuit chips is facing an even greater challenge.

[0003] To improve the electrostatic discharge protection of integrated circuit products, using the gate coupling effect is a commonly used method. Figure 1 It is a schematic diagram of an existing electrostatic discharge protection circuit applied to an integrated circuit chip shown according to an example. As Figure 1 shown, it can reduce the trigger voltage of NMOS transistor Mn10 and NMOS transistor Mn20, improve the electrostatic discharge ability of the NMOS transistor, and improve the reaction speed of the NMOS transistor for electrostatic discharge. However, if this method is used for the electrostatic discharge protection of the input pad (PAD) of a high-speed integrated circuit, it will affect the speed of the high-speed integrated circuit due to the existence of the capacitor C01 utilized by the gate coupling effect.

[0004] The above information disclosed in the background art section is only used to enhance the understanding of the background of the present invention, and thus it may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] In view of this, the present invention provides an electrostatic discharge protection circuit and an integrated circuit chip.

[0006] Other features and advantages of the present invention will become apparent through the following detailed description, or will be partially learned through the practice of the present invention.

[0007] According to one aspect of the present invention, there is provided an electrostatic discharge protection circuit applied to an integrated circuit chip. The integrated circuit chip includes a power supply terminal, a signal input terminal, and a ground terminal. The electrostatic discharge protection circuit includes a first protection circuit and a second protection circuit. The first protection circuit includes a first NMOS transistor. The second protection circuit includes a capacitor, a second NMOS transistor, and a third NMOS transistor. Wherein, one end of the capacitor is electrically connected to the power supply terminal, the other end of the capacitor is electrically connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is electrically connected to the ground terminal, and the gate of the third NMOS transistor is electrically connected to the power supply terminal. Wherein, the drain of the first NMOS transistor is electrically connected to the signal input terminal, the source of the first NMOS transistor is electrically connected to the ground terminal, and the gate of the first NMOS transistor is electrically connected to the drain of the third NMOS transistor. Wherein, the drain of the second NMOS transistor is electrically connected to the power supply terminal, the source of the second NMOS transistor is electrically connected to the ground terminal, and the gate of the second NMOS transistor is electrically connected to the drain of the third NMOS transistor.

[0008] According to an embodiment of the present invention, the electrostatic discharge protection circuit further includes a first resistor. The first end of the first resistor is electrically connected to the signal input terminal.

[0009] According to an embodiment of the present invention, the electrostatic discharge protection circuit further includes a third protection circuit. The third protection circuit includes a first PMOS transistor, a second PMOS transistor, and a fourth NMOS transistor. Wherein, the source of the first PMOS transistor is electrically connected to the power supply terminal, the drain of the first PMOS transistor is electrically connected to the second end of the first resistor, and the gate of the first PMOS transistor is electrically connected to the drain of the second PMOS transistor. The source of the second PMOS transistor is electrically connected to the power supply terminal, and the gate of the second PMOS transistor is electrically connected to the ground terminal. The source of the fourth NMOS transistor is electrically connected to the ground terminal, the drain of the fourth NMOS transistor is electrically connected to the second end of the first resistor, and the gate of the fourth NMOS transistor is electrically connected to the drain of the third NMOS transistor.

[0010] According to an embodiment of the present invention, the third protection circuit further includes a second resistor. The gate of the second PMOS transistor is electrically connected to the ground terminal through the second resistor.

[0011] According to an embodiment of the present invention, the electrostatic discharge protection circuit further includes: a third protection circuit; the third protection circuit includes: a first PMOS transistor, a second PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; wherein, the source of the first PMOS transistor is electrically connected to the power supply terminal, the drain of the first PMOS transistor is electrically connected to the second end of the first resistor, and the gate of the first PMOS transistor is electrically connected to the drain of the second PMOS transistor; the source of the second PMOS transistor is electrically connected to the power supply terminal, the gate of the second PMOS transistor is electrically connected to the ground terminal; the source of the fourth NMOS transistor is electrically connected to the ground terminal, the drain of the fourth NMOS transistor is electrically connected to the second end of the first resistor, and the gate of the fourth NMOS transistor is electrically connected to the drain of the fifth NMOS transistor; the source of the fifth NMOS transistor is electrically connected to the ground terminal, and the gate of the fifth NMOS transistor is electrically connected to the power supply terminal.

[0012] According to an embodiment of the present invention, the third protection circuit further includes: a second resistor and a third resistor; wherein, the gate of the second PMOS transistor is electrically connected to the ground terminal through the second resistor; the gate of the fifth NMOS transistor is electrically connected to the power supply terminal through the third resistor.

[0013] According to an embodiment of the present invention, the first protection circuit further includes: a diode, the positive electrode of the diode is electrically connected to the signal input terminal, and the negative electrode of the diode is electrically connected to the power supply terminal.

[0014] According to an embodiment of the present invention, the second protection circuit further includes: a fourth resistor; wherein, the gate of the third NMOS transistor is electrically connected to the power supply terminal through the fourth resistor.

[0015] According to another aspect of the present invention, there is provided an integrated circuit chip, including: a power supply terminal, a signal input terminal, a ground terminal, and the electrostatic discharge protection circuit.

[0016] According to an embodiment of the present invention, the integrated circuit chip further includes: an inverter, the inverter includes: a third PMOS transistor and a sixth NMOS transistor, the source of the third PMOS transistor is electrically connected to the power supply terminal, the drain of the third PMOS transistor is electrically connected to the drain of the sixth NMOS transistor, the gate of the third PMOS transistor is electrically connected to the signal input terminal through the first resistor, the gate of the sixth NMOS transistor is electrically connected to the signal input terminal through the first resistor, and the source of the sixth NMOS transistor is electrically connected to the ground terminal.

[0017] According to an embodiment of the present invention, the signal input terminal is used to receive a high-speed input signal.

[0018] According to the electrostatic discharge protection circuit provided by an embodiment of the present invention, by sharing the gate coupling effect between the input PAD NMOS transistor and the power clamp NMOS transistor, there is no capacitor used for the gate coupling effect electrically connected to the high-speed input PAD (such as Figure 1 the capacitor C01 in

[0019] ). On the one hand, the influence of the capacitor used for the gate coupling effect on the speed of the high-speed input PAD is eliminated, so that the high-speed input PAD can still adopt the protection circuit with the gate coupling effect to improve the electrostatic discharge protection ability; on the other hand, the chip area is saved and the chip manufacturing cost is reduced.

[0020] In addition, according to some embodiments, the electrostatic discharge protection circuit further improves the electrostatic discharge protection ability of the Charged Device Model (CDM) NMOS transistor, thereby improving the overall electrostatic discharge protection ability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] By referring to the accompanying drawings and describing its exemplary embodiments in detail, the above and other objects, features and advantages of the present invention will become more apparent.

[0022] Figure 1 FIG. is a circuit schematic diagram of an existing electrostatic discharge protection circuit applied to an integrated circuit chip shown according to an example.

[0023] Figure 2 FIG. is a circuit schematic diagram of an electrostatic discharge protection circuit applied to an integrated circuit chip shown according to an exemplary embodiment.

[0024] Figure 3 FIG. is a circuit schematic diagram of another electrostatic discharge protection circuit applied to an integrated circuit chip shown according to an exemplary embodiment.

[0025] Figure 4 FIG. is a circuit schematic diagram of yet another electrostatic discharge protection circuit applied to an integrated circuit chip shown according to an exemplary embodiment.

[0026] DESCRIPTION OF THE REFERENCE NUMERALS:

[0027] S0, S1, S2, S3 Integrated circuit chip

[0028] 10, 20, 30 Electrostatic discharge protection circuit

[0029] VDD Power supply terminal

[0030] VSS Ground terminal

[0031] INPUT signal input terminal

[0032] P11, P12, P13 First protection circuit

[0033] P21, P22, P23 Second protection circuit

[0034] P32, P33 Third protection circuit

[0035] Mn10, Mn11, Mn12, Mn13 First NMOS transistor

[0036] Mn20, Mn21, Mn22, Mn23 Second NMOS transistor

[0037] Mn30, Mn31, Mn32, Mn33 Third NMOS transistor

[0038] Mn40, Mn42, Mn43 Fourth NMOS transistor

[0039] Mn50, Mn52 Fifth NMOS transistor

[0040] Mn60, Mn61, Mn62, Mn63 Sixth NMOS transistor

[0041] Mn70 Seventh NMOS transistor

[0042] Mp10, Mp12, Mp13 First PMOS transistor

[0043] Mp20, Mp22, Mp23 Second PMOS transistor

[0044] Mp30, Mp31, Mp32, Mp33 Third PMOS transistor

[0045] CMOS0, CMOS1, CMOS2, CMOS3 Inverter

[0046] C01, C10, C11, C12, C13 Capacitor

[0047] Dp00, Dp01, Dp02, Dp03 Diode

[0048] R10, R11, R12, R13 First resistor

[0049] R20, R22, R23 Second resistor

[0050] R30, R32 Third resistor

[0051] R40, R41, R42, R43 Fourth resistor

[0052] R50 Fifth resistor Detailed Implementation Modes

[0053] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted.

[0054] In addition, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present invention. However, those skilled in the art will recognize that the technical solutions of the present invention can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be used. In other cases, well-known structures, methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present invention.

[0055] In the present invention, unless otherwise clearly defined and limited, terms such as "connected" and "coupled" should be understood in a broad sense. For example, they can be electrically connected or coupled; they can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0056] In addition, in the description of the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0057] Figure 2 is a circuit schematic diagram of an electrostatic discharge protection circuit applied to an integrated circuit chip shown according to an exemplary embodiment. As Figure 2 shown, the electrostatic discharge protection circuit 10 can be applied to the integrated circuit chip S1, where the integrated circuit chip S1 may include: a power supply terminal VDD, a signal input terminal INPUT, and a ground terminal VSS. The signal input terminal INPUT can be specifically implemented as an input PAD, for example.

[0058] Referring to Figure 2 , the electrostatic discharge protection circuit 10 includes: a first protection circuit P11 and a second protection circuit P21.

[0059] Among them, the first protection circuit P11 can be an electrostatic discharge protection circuit for discharging static electricity between the signal input terminal INPUT and the ground terminal VSS / power supply terminal VDD, which includes: an NMOS transistor Mn11. Among them, the drain of the NMOS transistor Mn11 is electrically connected to the signal input terminal INPUT, and the source of the NMOS transistor Mn11 is electrically connected to the ground terminal VSS.

[0060] The second protection circuit P21 can be an electrostatic discharge protection circuit for discharging static electricity between the power supply terminal VDD and the ground terminal VSS, which includes: a capacitor C11, an NMOS transistor Mn21, and an NMOS transistor Mn31. Among them, one end of the capacitor C11 is electrically connected to the power supply terminal VDD, and the other end of the capacitor C11 is electrically connected to the drain connection of the NMOS transistor Mn31; the drain of the NMOS transistor Mn31 is electrically connected to the gate of the NMOS transistor Mn11 in the first protection circuit P11; the source of the NMOS transistor Mn31 is electrically connected to the ground terminal VSS, and the gate of the NMOS transistor Mn31 is electrically connected to the power supply terminal VDD; the drain of the NMOS transistor Mn21 is electrically connected to the power supply terminal VDD, the source of the NMOS transistor Mn21 is electrically connected to the ground terminal VSS, and the gate of the NMOS transistor Mn21 is electrically connected to the drain of the NMOS transistor Mn31.

[0061] The working principle of the electrostatic discharge protection circuit 10 is as follows: when a positive static electricity pulse occurs at the signal input terminal INPUT, a high voltage is transmitted to one end of the capacitor C11 through the VDD power supply line, and a corresponding high potential is instantaneously coupled out at the other end of the capacitor C11. This high potential serves as the common gate voltage of the NMOS transistor Mn11 in the first protection circuit P11 and the NMOS transistor Mn21 in the second protection circuit P21. When the voltage amount by which this gate voltage is higher than their common source voltage is greater than the threshold voltages of the NMOS transistors Mn11 and Mn21, the NMOS transistors Mn11 and Mn21 change from the cut-off state during normal operation to the conducting state, and the static electricity is discharged to the ground terminal VSS.

[0062] In some embodiments, the electrostatic discharge protection circuit 10 may further include: a resistor R11, and the first end of the resistor R11 is electrically connected to the signal input terminal INPUT. The resistor R11 plays a blocking role to filter out the spikes of the static electricity voltage generated at the signal input terminal INPUT to avoid its influence on the internal circuit.

[0063] In some embodiments, the first protection circuit P11 may further include: a diode Dp01, the positive electrode of the diode Dp01 is electrically connected to the signal input terminal INPUT, and the negative electrode of the diode Dp01 is electrically connected to the power supply terminal VDD.

[0064] In some embodiments, the second protection circuit P21 may further include: a resistor R41; wherein, the gate of the NMOS transistor Mn31 is electrically connected to the power supply terminal VDD through the resistor R41.

[0065] The NMOS transistor Mn31 exists as a large resistor when the integrated circuit chip S1 is operating normally, and occupies a smaller chip area than a polysilicon resistor. The resistor R41 can play a role in buffering and protecting the NMOS transistor Mn31.

[0066] According to the electrostatic discharge protection circuit provided by the embodiment of the present invention, by electrically connecting the gates of the NMOS transistors Mn11 and Mn21 (both are electrically connected to the drain of the NMOS transistor Mn31), that is, these two NMOS transistors share the gate coupling effect, so that there is no capacitor used for the gate coupling effect electrically connected to the high-speed input PAD (such as Figure 1 the capacitor C01 in), on the one hand, the influence of the capacitor used for the gate coupling effect on the speed of the high-speed input PAD is eliminated, so that the high-speed input PAD can still use the protection circuit of the gate coupling effect to improve the electrostatic discharge protection ability; on the other hand, the chip area is saved and the chip manufacturing cost is reduced.

[0067] It should be clearly understood that the present invention describes how to form and use specific examples, but the principles of the present invention are not limited to any details of these examples. On the contrary, based on the teachings of the content disclosed in the present invention, these principles can be applied to many other embodiments.

[0068] Figure 3 is a circuit schematic diagram of another electrostatic discharge protection circuit applied to an integrated circuit chip shown according to an exemplary embodiment. As Figure 3 shown, the electrostatic discharge protection circuit 20 can be applied to the integrated circuit chip S2, wherein the integrated circuit chip S2 may include: a power supply terminal VDD, a signal input terminal INPUT, and a ground terminal VSS. The signal input terminal INPUT is an input PAD. Different from Figure 2 the electrostatic discharge protection circuit 10 shown, Figure 3 the electrostatic discharge protection circuit 20 shown further includes a third protection circuit P32.

[0069] Referring to Figure 3 the electrostatic discharge protection circuit 20 may include: a first protection circuit P12, a second protection circuit P22, and a third protection circuit P32.

[0070] Among them, the first protection circuit P12 can be an electrostatic discharge protection circuit for discharging static electricity between the signal input terminal INPUT and the ground terminal VSS / power supply terminal VDD, and it includes: an NMOS transistor Mn12. Among them, the drain of the NMOS transistor Mn12 is electrically connected to the signal input terminal INPUT, and the source of the NMOS transistor Mn12 is electrically connected to the ground terminal VSS.

[0071] The second protection circuit P22 can be an electrostatic discharge protection circuit for discharging static electricity between the power supply terminal VDD and the ground terminal VSS, and it includes: a capacitor C12, an NMOS transistor Mn22, and an NMOS transistor Mn32. Among them, one end of the capacitor C12 is electrically connected to the power supply terminal VDD, and the other end of the capacitor C12 is electrically connected to the drain connection of the NMOS transistor Mn32; the drain of the NMOS transistor Mn32 is electrically connected to the gate of the NMOS transistor Mn12; the source of the NMOS transistor Mn32 is electrically connected to the ground terminal VSS, and the gate of the NMOS transistor Mn32 is electrically connected to the power supply terminal VDD; the drain of the NMOS transistor Mn22 is electrically connected to the power supply terminal VDD, the source of the NMOS transistor Mn22 is electrically connected to the ground terminal VSS, and the gate of the NMOS transistor Mn22 is electrically connected to the drain of the NMOS transistor Mn32.

[0072] In some embodiments, the electrostatic discharge protection circuit 20 may further include: a resistor R12, and the first end of the resistor R12 is electrically connected to the signal input terminal INPUT. The resistor R12 plays a blocking role to filter out the spikes of the static voltage generated at the signal input terminal INPUT to avoid its impact on the internal circuit.

[0073] The third protection circuit P32 can be a CDM electrostatic discharge protection circuit for the internal circuit. The third protection circuit P32 may include: a PMOS transistor Mp12, a PMOS transistor Mp22, an NMOS transistor Mn42, and an NMOS transistor Mn52. Among them, the source of the PMOS transistor Mp12 is electrically connected to the power supply terminal VDD, the drain of the PMOS transistor Mp12 is electrically connected to the second end of the resistor R12, and the gate of the PMOS transistor Mp12 is electrically connected to the drain of the PMOS transistor Mp22; the source of the PMOS transistor Mp22 is electrically connected to the power supply terminal VDD, and the gate of the PMOS transistor Mp22 is electrically connected to the ground terminal VSS; the source of the NMOS transistor Mn42 is electrically connected to the ground terminal VSS, the drain of the NMOS transistor Mn42 is electrically connected to the second end of the resistor R12, and the gate of the NMOS transistor Mn42 is electrically connected to the drain of the NMOS transistor Mn52; the source of the NMOS transistor Mn52 is electrically connected to the ground terminal VSS, and the gate of the NMOS transistor Mn52 is electrically connected to the power supply terminal VDD.

[0074] The third protection circuit P32 is used for the electrostatic discharge of the charge accumulation generated by the internal circuit. The PMOS transistor therein constitutes an electrostatic discharge path between the power supply terminal VDD and the signal input terminal INPUT, and the NMOS transistor therein constitutes an electrostatic discharge path between the signal input terminal INPUT and the ground terminal VSS.

[0075] In some embodiments, the first protection circuit P12 may further include: a diode Dp02. The anode of the diode Dp02 is electrically connected to the signal input terminal INPUT, and the cathode of the diode Dp02 is electrically connected to the power supply terminal VDD.

[0076] In some embodiments, the second protection circuit P22 may further include: a resistor R42. Wherein, the gate of the NMOS transistor Mn32 is electrically connected to the power supply terminal VDD through the resistor R42.

[0077] The NMOS transistor Mn32 exists as a large resistor when the integrated circuit chip S2 is operating normally, and occupies less chip area than a polysilicon resistor. The resistor R42 can play a role in buffering and protecting the NMOS transistor Mn32.

[0078] In some embodiments, the third protection circuit P32 may further include: a resistor R22 and a resistor R32. Wherein, the gate of the PMOS transistor Mp22 is electrically connected to the ground terminal VSS through the resistor R22; the gate of the NMOS transistor Mn52 is electrically connected to the power supply terminal VDD through the resistor R32.

[0079] The PMOS transistor Mp22 and the NMOS transistor Mn52 exist as large resistors when the integrated circuit chip S2 is operating normally, and occupy less chip area than a polysilicon resistor. The resistor R22 plays a role in buffering and protecting the PMOS transistor Mp22, and the resistor R32 plays a role in buffering and protecting the NMOS transistor Mn52.

[0080] The electrostatic discharge protection circuit provided according to the embodiment of the present invention further includes a CDM electrostatic discharge protection circuit for the internal circuit, thereby further improving the overall electrostatic discharge protection ability of the chip.

[0081] Figure 4 It is a circuit schematic diagram of another electrostatic discharge protection circuit applied to an integrated circuit chip shown according to an exemplary embodiment. As Figure 4 shown, the electrostatic discharge protection circuit 30 can be applied to the integrated circuit chip S3, wherein the integrated circuit chip S3 may include: a power supply terminal VDD, a signal input terminal INPUT, and a ground terminal VSS. The signal input terminal INPUT is an input PAD. Different from Figure 2 the electrostatic discharge protection circuit 10 shown, Figure 4 the electrostatic discharge protection circuit 30 shown further includes a third protection circuit P33.

[0082] Refer to Figure 4 , the electrostatic discharge protection circuit 30 may include: a first protection circuit P13, a second protection circuit P23, and a third protection circuit P33.

[0083] Among them, the first protection circuit P13 may be an electrostatic discharge protection circuit for discharging static electricity between the signal input terminal INPUT and the ground terminal VSS / power supply terminal VDD, and it includes: an NMOS transistor Mn13. Among them, the drain of the NMOS transistor Mn13 is electrically connected to the signal input terminal INPUT, and the source of the NMOS transistor Mn13 is electrically connected to the ground terminal VSS.

[0084] The second protection circuit P23 may be an electrostatic discharge protection circuit for discharging static electricity between the power supply terminal VDD and the ground terminal VSS, and it includes: a capacitor C13, an NMOS transistor Mn23, and an NMOS transistor Mn33. Among them, one end of the capacitor C13 is electrically connected to the power supply terminal VDD, and the other end of the capacitor C13 is electrically connected to the drain of the NMOS transistor Mn33; the drain of the NMOS transistor Mn33 is electrically connected to the gate of the NMOS transistor Mn13; the source of the NMOS transistor Mn33 is electrically connected to the ground terminal VSS, and the gate of the NMOS transistor Mn33 is electrically connected to the power supply terminal VDD; the drain of the NMOS transistor Mn23 is electrically connected to the power supply terminal VDD, the source of the NMOS transistor Mn23 is electrically connected to the ground terminal VSS, and the gate of the NMOS transistor Mn23 is electrically connected to the drain of the NMOS transistor Mn33.

[0085] In some embodiments, the electrostatic discharge protection circuit 30 may further include: a resistor R13, and the first end of the resistor R13 is electrically connected to the signal input terminal INPUT. The resistor R13 plays a blocking role to filter out the spikes of the static voltage generated at the signal input terminal INPUT to avoid its influence on the internal circuit.

[0086] The third protection circuit P33 may be a CDM electrostatic discharge protection circuit for the internal circuit. The third protection circuit P33 may include: a PMOS transistor Mp13, a PMOS transistor Mp23, and an NMOS transistor Mn43. Among them, the source of the PMOS transistor Mp13 is electrically connected to the power supply terminal VDD, the drain of the PMOS transistor Mp13 is electrically connected to the second end of the resistor R13, and the gate of the PMOS transistor Mp13 is electrically connected to the drain of the PMOS transistor Mp23; the source of the PMOS transistor Mp23 is electrically connected to the power supply terminal VDD, and the gate of the PMOS transistor Mp23 is electrically connected to the ground terminal VSS; the source of the NMOS transistor Mn43 is electrically connected to the ground terminal VSS, the drain of the NMOS transistor Mn43 is electrically connected to the second end of the resistor R13, and the gate of the NMOS transistor Mn43 is electrically connected to the drain of the NMOS transistor Mn33 in the second protection circuit P23.

[0087] The third protection circuit P33 is used for the electrostatic discharge of the charge accumulation generated by the internal circuit. The PMOS transistor therein constitutes an electrostatic discharge path between the power supply terminal VDD and the signal input terminal INPUT, and the NMOS transistor therein constitutes an electrostatic discharge path between the signal input terminal INPUT and the ground terminal VSS.

[0088] In some embodiments, the first protection circuit P13 may further include: a diode Dp03. The anode of the diode Dp03 is electrically connected to the signal input terminal INPUT, and the cathode of the diode Dp03 is electrically connected to the power supply terminal VDD.

[0089] In some embodiments, the second protection circuit P23 may further include: a resistor R43. Wherein, the gate of the NMOS transistor Mn33 is electrically connected to the power supply terminal VDD through the resistor R43.

[0090] The NMOS transistor Mn33 exists as a large resistor when the integrated circuit chip S3 is working normally, and it occupies less chip area than a polysilicon resistor. The resistor R43 can play a role in buffering and protecting the NMOS transistor Mn33.

[0091] In some embodiments, the third protection circuit P33 may further include: a resistor R23. Wherein, the gate of the PMOS transistor Mp23 is electrically connected to the ground terminal VSS through the resistor R23.

[0092] The PMOS transistor Mp23 exists as a large resistor when the integrated circuit chip S3 is working normally, and it occupies less chip area than a polysilicon resistor. The resistor R23 plays a role in buffering and protecting the PMOS transistor Mp23.

[0093] According to the electrostatic discharge protection circuit provided by the embodiment of the present invention, the gate of the NMOS transistor Mn43 in the CDM electrostatic discharge protection circuit is further electrically connected to the gates of the NMOS transistor Mn13 in the first protection circuit P13 and the NMOS transistor M23 in the second protection circuit P23, that is, these three NMOS transistors share the gate coupling effect. Further, the electrostatic discharge protection ability of the internal circuit CDM NMOS transistor is improved, thereby improving the overall electrostatic discharge protection ability of the chip.

[0094] In addition, the embodiment of the present invention further provides an integrated circuit chip, which may be, for example, the integrated circuit chips S1, S2 or S3 shown above Figures 2 - 4 respectively include the above-mentioned electrostatic discharge protection circuits 10, 20 or 30.

[0095] In some embodiments, the integrated circuit chips S1, S2, or S3 may further include: inverters CMOS1, CMOS2, or CMOS3. Taking the inverter CMOS1 as an example, it includes: a PMOS transistor Mp31 and an NMOS transistor Mn61. The source of the PMOS transistor Mp31 is electrically connected to the power supply terminal VDD. The drain of the PMOS transistor Mp31 is electrically connected to the drain of the NMOS transistor Mn61. The gate of the PMOS transistor Mp31 is electrically connected to the signal input terminal INPUT through a resistor R11. The gate of the NMOS transistor Mn61 is electrically connected to the signal input terminal INPUT through a resistor R11. The source of the NMOS transistor Mn61 is electrically connected to the ground terminal VSS. The inverters CMOS1, CMOS2, or CMOS3 can implement an input buffering function.

[0096] In addition, the signal input terminal INPUT in the above-mentioned integrated circuit chips S1, S2, or S3 provided by the embodiments of the present invention can be used to receive high-speed input signals. That is to say, the integrated circuit chips S1, S2, or S3 can be high-speed integrated circuit chips.

[0097] In the integrated circuit chips S1, S2, or S3 disclosed in the embodiments of the present invention, by respectively using the NMOS transistor Mn11 in the first protection circuit P11 and the NMOS transistor Mn21 in the second protection circuit P21 to share a gate (such as Figure 2 ); the NMOS transistor Mn12 in the first protection circuit P12 and the NMOS transistor Mn22 in the second protection circuit P22 (such as Figure 3 ) share a gate; the NMOS transistor Mn13 in the first protection circuit P13, the NMOS transistor Mn23 in the second protection circuit P23, and the NMOS transistor Mn43 in the third protection circuit P33 (such as Figure 4 ) share a gate, the capacitor C01 is removed from the input PAD. On the one hand, it eliminates the influence of the capacitor used for the gate coupling effect in the prior art on the speed of the high-speed input PAD, so that the high-speed input PAD can still adopt the protection circuit of the gate coupling effect to improve the electrostatic discharge protection ability; on the other hand, it saves the chip area and reduces the manufacturing cost of the chip. In addition, the electrostatic discharge protection ability of the CDM NMOS transistor is improved, thereby improving the overall electrostatic discharge protection ability of the chip.

[0098] The above specifically shows and describes the exemplary embodiments of the present invention. It should be understood that the present invention is not limited to the detailed structures, setting methods, or implementation methods described here; on the contrary, the present invention intends to cover various modifications and equivalent settings included within the spirit and scope of the appended claims.

Claims

1. An electrostatic discharge protection circuit is applied to an integrated circuit chip, and the integrated circuit chip includes: A power supply terminal, a signal input terminal, and a ground terminal, characterized in that the electrostatic discharge protection circuit includes: a first protection circuit and a second protection circuit; the first protection circuit includes: a first NMOS transistor; the second protection circuit includes: a capacitor, a second NMOS transistor, and a third NMOS transistor; Wherein, one end of the capacitor is electrically connected to the power supply terminal, the other end of the capacitor is electrically connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is electrically connected to the ground terminal, and the gate of the third NMOS transistor is electrically connected to the power supply terminal; Wherein, the drain of the first NMOS transistor is electrically connected to the signal input terminal, the source of the first NMOS transistor is electrically connected to the ground terminal, and the gate of the first NMOS transistor is electrically connected to the drain of the third NMOS transistor; Wherein, the drain of the second NMOS transistor is electrically connected to the power supply terminal, the source of the second NMOS transistor is electrically connected to the ground terminal, and the gate of the second NMOS transistor is electrically connected to the drain of the third NMOS transistor.

2. The electrostatic discharge protection circuit according to claim 1, wherein It further includes a first resistor and a third protection circuit; the first end of the first resistor is electrically connected to the signal input terminal; The third protection circuit includes: a first PMOS transistor, a second PMOS transistor; wherein, the source of the first PMOS transistor is electrically connected to the power supply terminal, the drain of the first PMOS transistor is electrically connected to the second end of the first resistor, and the gate of the first PMOS transistor is electrically connected to the drain of the second PMOS transistor; the source of the second PMOS transistor is electrically connected to the power supply terminal, and the gate of the second PMOS transistor is electrically connected to the ground terminal.

3. The electrostatic discharge protection circuit according to claim 2, wherein The third protection circuit further includes: a fourth NMOS transistor; wherein, the source of the fourth NMOS transistor is electrically connected to the ground terminal, the drain of the fourth NMOS transistor is electrically connected to the second end of the first resistor, and the gate of the fourth NMOS transistor is electrically connected to the drain of the third NMOS transistor.

4. The electrostatic discharge protection circuit according to claim 3, characterized in that, The third protection circuit further includes: a second resistor; wherein, the gate of the second PMOS transistor is electrically connected to the ground terminal through the second resistor.

5. The electrostatic discharge protection circuit according to claim 2, characterized in that, The third protection circuit further includes: a fourth NMOS transistor and a fifth NMOS transistor; wherein, the source of the fourth NMOS transistor is electrically connected to the ground terminal, the drain of the fourth NMOS transistor is electrically connected to the second end of the first resistor, and the gate of the fourth NMOS transistor is electrically connected to the drain of the fifth NMOS transistor; the source of the fifth NMOS transistor is electrically connected to the ground terminal, and the gate of the fifth NMOS transistor is electrically connected to the power supply terminal.

6. The electrostatic discharge protection circuit according to claim 5, characterized in that The third protection circuit further includes: a second resistor and a third resistor; wherein, the gate of the second PMOS transistor is electrically connected to the ground terminal through the second resistor; the gate of the fifth NMOS transistor is electrically connected to the power supply terminal through the third resistor.

7. The electrostatic discharge protection circuit according to claim 1, wherein the first protection circuit further comprises: A diode, the positive electrode of the diode is electrically connected to the signal input terminal, and the negative electrode of the diode is electrically connected to the power supply terminal.

8. The electrostatic discharge protection circuit according to any one of claims 1-7, wherein the second protection circuit further comprises: A fourth resistor; wherein, the gate of the third NMOS transistor is electrically connected to the power supply terminal through the fourth resistor.

9. An integrated circuit chip, characterized in that, Including: A power supply terminal, a signal input terminal, a ground terminal, and an electrostatic discharge protection circuit according to any one of claims 2-8.

10. The integrated circuit chip according to claim 9, characterized in that, Further comprising: An inverter, the inverter comprising: a third PMOS transistor and a sixth NMOS transistor, a source of the third PMOS transistor being electrically connected to the power supply terminal, a drain of the third PMOS transistor being electrically connected to a drain of the sixth NMOS transistor, a gate of the third PMOS transistor being electrically connected to the signal input terminal through a first resistor, a gate of the sixth NMOS transistor being electrically connected to the signal input terminal through the first resistor, and a source of the sixth NMOS transistor being electrically connected to the ground terminal.

Images