Pulse signal generator using frequency hopping technology and working method thereof

Abstract

The present invention relates to a pulse signal generator using frequency hopping technology and a working method thereof. According to one embodiment, the pulse signal generator includes an edge combination portion that receives an input signal and outputs at least one digital window corresponding to the input signal in a frequency hopping manner using a switched capacitor, and a push-pull pulse generation portion that receives the output digital window and generates a pulse signal corresponding to the received digital window. The present invention can transmit a pulse signal in a frequency hopping manner by using a delay circuit based on a switched capacitor, thereby increasing the wireless communication speed and wireless communication distance without consuming additional power.

Description

Technical Field

[0001] The present invention relates to a pulse signal generator and a working method thereof, and more specifically, to a technical concept of generating and sending a pulse signal based on a frequency hopping technology. Background Art

[0002] Ultra Wide Band (UWB), one of the wireless communication technologies, has recently attracted much attention. UWB has advantages in ultra-high-speed wireless communication, low output, and efficient use of frequency. In addition, UWB technology has proposed the possibility of application in close-range ultra-high-speed wireless communication in daily life, so it is a technology that has received particular attention in the industry.

[0003] UWB technology uses very short pulses of less than 1 nanosecond for communication. In order to use pulses to send information, the basic pulses must be modulated.

[0004] The modulation method based on UWB technology has an on-off keying method that is a method of sending or not sending an impulse signal (ImpulseSignal) within a given time interval. The on-off keying method is a communication method that sends a synchronization pulse, and recognizes it as '1' when a pulse signal is sent after the synchronization pulse, and recognizes it as '0' when it is not sent. The data speed of this communication method is not very high. That is, in the case of this on-off keying method, the data rate is at the level of the pulse repetition frequency (PRF) as the period of sending the UWB signal.

[0005] In addition, according to the Federal Communications Commission (FCC) regulations, UWB technology is limited to a transmission power spectrum density of not more than -41.3 dBm / MHz in the range of 3.1 to 10.6 GHz.

[0006] Therefore, the reality is that UWB technology needs to apply a technology that can reduce the specified average power density and increase the amplitude of the pulse signal to extend the communication distance by moving the transmission frequency and transmitting pulse signals between 3.1GHz and 10.6GHz, namely frequency hopping technology.

[0007] In addition, the existing pulse signal generator uses a technology that uses a digitally-controlled oscillator (DCO) to replace the carrier of the pulse signal to perform frequency hopping. However, this technology is very sensitive to noise components such as parasitic capacitance (Parasitic Capacitor), and the actual implementation has a complex RF design, and the area occupied by components such as chips (Chip), inductors (Inductor), MIM capacitors (MIM Capacitor) is very large.

[0008] [Prior technical literature]

[0009] [Patent Literature]

[0010] (Patent Document 1) Korean registered patent No. 10-1358902, "Data communication, distance measurement, and position tracking using time-to-digital converter-multiple PPM" Summary of the invention

[0011] Technical issues

[0012] The object of the present invention is to provide a pulse signal generator and a working method thereof which transmits a pulse signal in a frequency hopping manner using a delay circuit based on a switched capacitor, thereby being able to increase the wireless communication speed and wireless communication distance without consuming additional power.

[0013] Furthermore, an object of the present invention is to provide a pulse signal generator and a working method thereof which can utilize the time difference between a synchronization pulse and a data pulse to transmit data, thereby increasing the wireless communication speed and the wireless communication distance.

[0014] Technical Solution

[0015] According to one embodiment, a pulse signal generator may include: an edge combining unit, which receives an input signal and outputs at least one digital window corresponding to the input signal in a frequency hopping manner using a switched capacitor; and a push-pull pulse generating unit, which receives the output digital window and generates a pulse signal corresponding to the received digital window.

[0016] According to one aspect, the edge coupling portion may have at least one delay cell including a plurality of switch capacitors.

[0017] According to one aspect, the edge combination unit may delay a rising edge of an input signal by an amount corresponding to a delay time of at least one delay unit, and output at least one digital window corresponding to the delayed rising edge.

[0018] According to one aspect, at least one delay unit can control the operation of multiple switch capacitors respectively through binary codes to adjust the delay time of the delay unit.

[0019] According to one aspect, the pulse signal generator may further include a counting section that generates a binary code through at least one D flip-flop.

[0020] According to one aspect, the input signal may be a signal for adjusting the time interval between a sync pulse (Sync Pulse) and a data pulse (Data Pulse) within one clock cycle.

[0021] According to one embodiment, the working method of the pulse signal generator may include: a step in which an edge combining unit receives an input signal and outputs at least one digital window corresponding to the input signal in a frequency hopping manner using a switched capacitor; and a step in which a push-pull pulse generating unit receives the output digital window and generates a pulse signal corresponding to the received digital window.

[0022] According to one aspect, the edge coupling portion may have at least one delay cell including a plurality of switch capacitors.

[0023] According to one aspect, in the step of outputting a digital window, a rising edge of an input signal may be delayed by an amount corresponding to a delay time of at least one delay unit, and at least one digital window corresponding to the delayed edge may be output.

[0024] According to one aspect, in the step of outputting a digital window, the counting unit generates a binary code (Binary Code) corresponding to the input signal through at least one D flip-flop (DFlip-Flop), and the edge combining unit can control the operation of multiple switching capacitors respectively through the binary code to adjust the delay time of the delay unit.

[0025] According to one aspect, the input signal may be a signal for adjusting the time interval between a sync pulse (Sync Pulse) and a data pulse (Data Pulse) within one clock cycle.

[0026] Technical Effects

[0027] According to one embodiment, a pulse signal can be transmitted in a frequency hopping manner by utilizing a switched capacitor-based delay circuit, thereby improving wireless communication speed and wireless communication distance without consuming additional power.

[0028] According to one embodiment, data can be transmitted by utilizing the time difference between a synchronization pulse and a data pulse, thereby improving wireless communication speed and wireless communication distance. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic diagram for illustrating a pulse signal generator according to an embodiment;

[0030] Figure 2 is a schematic diagram for explaining an example of the operation of a pulse signal generator according to an embodiment;

[0031] Figure 3 is a schematic diagram for illustrating a multiple pulse modulation transmitter according to an embodiment;

[0032] Figure 4 is a schematic diagram for explaining an example of a digital-to-time conversion unit according to an embodiment;

[0033] Figure 5a to Figure 5b is a schematic diagram for explaining an example of generating a pulse signal using a multiple pulse modulation transmitter according to an embodiment;

[0034] Figure 6 is a schematic diagram for explaining a synchronization device according to an embodiment;

[0035] Figure 7 is a schematic diagram for explaining an example of an analog processing unit according to an embodiment;

[0036] Figure 8 is a schematic diagram for explaining an example of a synchronization unit according to an embodiment;

[0037] Figures 9a to 9e is a schematic diagram for explaining an example of performing synchronization work using a synchronization device according to an embodiment;

[0038] Fig.10 is a schematic diagram for illustrating a working method of a pulse signal generator according to an embodiment;

[0039] Fig.11 is a schematic diagram for explaining a working method of a synchronization device according to an embodiment.

[0040] Description of Reference Numerals

[0041] 100: Pulse signal generator 110: Counting unit

[0042] 120: edge connection unit 130: push-pull pulse generation unit DETAILED DESCRIPTION

[0043] Various embodiments of the present invention are described below with reference to the accompanying drawings.

[0044] The embodiments and the terms used therein are not intended to limit the technology described herein to specific implementation forms, and should be understood to include various modifications, equivalents, and / or substitutes of the corresponding embodiments.

[0045] When describing various embodiments below, if it is determined that the specific description of related well-known functions or structures may obscure the main purpose of the present invention, the detailed description of the related contents will be omitted.

[0046] Furthermore, the following terms are defined according to their functions in various embodiments and may vary according to the intention or practice of the user or operator. Therefore, their definitions shall be subject to the full text of the specification.

[0047] In describing the drawings, similar reference numerals are used for similar components.

[0048] Expressions in the singular may include expressions in the plural as long as the context does not clearly indicate a different meaning.

[0049] Herein, expressions such as "A or B" or "at least one of A and / or B" may include all possible combinations of the items listed together.

[0050] Expressions such as “first”, “second”, “first” or “second” may modify corresponding components regardless of order or importance, and do not limit the corresponding components, but are only used to distinguish one component from other components.

[0051] When a certain component (e.g., a first component) is described as being "(functionally or communicatively) connected" or "accessed" to another component (e.g., a second component), the certain component is directly connected to the other component or may be connected through the other component (e.g., a third component).

[0052] In this specification, "configured to" can be used interchangeably with "suitable for", "having the ability of", "changed to", "made to", "capable of executing" or "designed to" depending on the situation, for example, in hardware or software.

[0053] In some cases, the expression “a device configured to…” may mean that the device, together with other devices or components, “is capable of performing…”.

[0054] For example, the sentence "a processor configured to perform A, B, and C" may refer to a dedicated processor for performing the corresponding tasks (e.g., an embedded processor) or a general-purpose processor that can perform the corresponding tasks by running one or more software programs stored in a storage device (e.g., a CPU or an application processor).

[0055] Furthermore, the term 'or' constitutes an inclusive logical or rather than an exclusive logical or.

[0056] That is, unless otherwise defined or not clear from the context of the text, the expression 'x uses a or b' means any one of the natural inclusive permutations.

[0057] In the above-mentioned specific embodiments, the constituent elements included in the invention are expressed in the singular or plural according to the specific embodiments suggested.

[0058] However, the singular or plural expressions are selected for the convenience of explanation to suit the situation presented, and the above-mentioned embodiments are not limited to singular or plural constituent elements. Even constituent elements expressed as plural may be changed to singular, or constituent elements expressed as singular may be composed of plural.

[0059] Furthermore, while specific embodiments have been described in the description of the invention, it is apparent that various modifications may be made without departing from the scope of the technical ideas encompassed by the various embodiments.

[0060] Therefore, the scope of the present invention should not be limited to the illustrated embodiments, but should be determined by the scope of the claims and the scope of equivalents to the claims.

[0061] Figure 1 is a schematic diagram for explaining a pulse signal generator according to an embodiment.

[0062] See also Figure 1 According to an embodiment, a pulse signal generator can transmit a pulse signal in a frequency hopping manner by using a switched capacitor-based delay circuit, thereby improving the wireless communication speed and wireless communication distance without consuming additional power.

[0063] Furthermore, the time difference between the synchronization pulse and the data pulse can be used to transmit data, thereby further improving the wireless communication speed and the wireless communication distance.

[0064] To this end, the pulse signal generator 100 according to one embodiment may include a counting section 110 , an edge combining section 120 , and a push-pull pulse generating section 130 .

[0065] For example, the edge combining unit 120 may be an edge combiner, and the push-pull pulse generating unit 130 may be a push-pull pulse generator.

[0066] According to an embodiment, the edge combining unit 120 can receive an input signal (Input Clock) and output at least one digital window corresponding to the input signal in a frequency hopping manner using a switched capacitor (Switched Capacitor).

[0067] For example, the input signal (Input Clock) may be a signal based on a digital clock.

[0068] Furthermore, the input signal may be a signal for adjusting the time interval between a sync pulse (Sync Pulse) and a data pulse (Data Pulse) within one clock cycle.

[0069] According to one aspect, when the input signal is a signal in which the time interval between the synchronization pulse and the data pulse is adjusted, the input signal may be a signal generated by a digital-to-time conversion unit of the multiple pulse modulation transmitter according to an embodiment.

[0070] A more detailed description of the multiple pulse modulation transmitter according to an embodiment will be described in the following embodiments. Figures 3 to 5b Explain more specifically.

[0071] According to one aspect, the edge coupling unit 120 may include at least one delay cell 121 including a plurality of switched capacitors.

[0072] Furthermore, the edge coupling unit 120 may include a plurality of combinatorial logics respectively connected to at least one delay unit 121 .

[0073] For example, at least one delay unit 121 may be connected in series to form a delay line.

[0074] Also, the plurality of combinational logics may include a plurality of AND gates connected to the at least one delay unit 121 , and a plurality of OR gates connected to outputs of the plurality of AND gates.

[0075] According to one aspect, the edge combining unit 120 can delay the rising edge of the input signal by a predetermined delay time (τ) corresponding to at least one delay unit 121. c) and outputs at least one digital window (EC) corresponding to the edge of the delay. 1～4 ).

[0076] According to one aspect, at least one delay unit 121 can be configured to transmit a signal through a binary code (Binary Code, B <0> , B <1> , ..., B <n>) respectively control a plurality of switched capacitors to adjust the delay time (τ) corresponding to at least one delay unit 121 c ).

[0077] In other words, at least one delay unit 121 can respectively pass the binary code (B <0> , B <1> , ..., B <n>) controls each corresponding to the binary code (B <0> , B <1> , ..., B <n>)'s switching operation of the switched capacitor.

[0078] That is, at least one delay unit 121 can respectively control the binary code (B <0> , B <1> , ..., B <n>) is changed, the size of all capacitors of the delay unit 121 is changed, thereby adjusting the delay time (τ c ).

[0079] For example, the delay unit 121 can be used to input the binary code B <0> The value of '1' will correspond to the binary code B <0> The switch of the switched capacitor is changed to the 'on' state, which can be <0> The value of '0' will correspond to the binary code B <0> The switch of the switched capacitor is changed to the 'off' state.

[0080] Furthermore, the delay unit 121 can be used to input the binary code B <n>The value of '1' will correspond to the binary code B <n>The switch of the switched capacitor is changed to the 'on' state, which can be <n>The value of '0' will correspond to the binary code B <n>The switch of the switched capacitor is changed to the 'off' state.

[0081] According to one aspect, the counting unit 110 may generate a binary code (B ) by at least one D flip-flop (D Flip-Flop; D FF). <0> , B <1> , ..., B <n>).

[0082] The counting unit 110, like the edge combining unit 120, can receive an input signal (Input Clock) and generate a delay time (τ) for adjusting each delay unit in at least one delay unit 121. c )'s binary code (B <0> , B <1> , ..., B <n>).

[0083] According to one aspect, when the input signal is a signal in which the time interval between the synchronization pulse and the data pulse is adjusted, the counting unit 110 may also receive a reference clock signal received as an input by a digital-to-time conversion unit of a multiple pulse modulation transmitter according to an embodiment instead of the input signal, and generate a binary code (B <0> , B <1> , ..., B <n>).

[0084] In addition, the push-pull pulse generating unit 130 according to one embodiment can receive the digital window (EC) output from the edge combining unit 120. 1～4 ), generating the corresponding digital window (EC 1～4 ) pulse signal.

[0085] The operation of the pulse signal generator 100 according to one embodiment is described in more detail as follows. The edge combining unit 120 can receive an input signal (Input Clock), and delay the rising edge of the input signal by a delay time (τ) equivalent to at least one delay unit 121. c ) to generate a digital window (EC 1～4 ).

[0086] Next, the push-pull pulse generator 130 can use the digital window (EC 1～4 ) charges (Charge) or discharges (Discharge) the output node (IMPULSE OUT) of the push-pull pulse generating unit 130 to the power supply voltage (VDD) level or the ground level (GND) to generate a pulse signal.

[0087] Here, the center frequency of the pulse signal can be compared with the delay time (τ c ). That is, the delay time (τ c ) increases, the center frequency of the pulse signal can be reduced, and the delay time (τ c ) decreases, the center frequency of the pulse signal can increase.

[0088] As described above, the pulse signal generator 100 according to one embodiment can be configured to generate a pulse signal by changing the binary code (B <0> , B <1> , ..., B <n>) changes the size of all capacitors of the delay unit 121, thereby adjusting the delay time (τ c That is, the pulse signal generator 100 can digitally adjust the delay time (τ c ).

[0089] Therefore, corresponding to the binary code (B <0> , B <1> , ..., B <n>) is composed of binary values, and the binary code (B <0> , B <1> , ..., B <n>) can be inversely proportional to the center frequency of the pulse signal.

[0090] In other words, the center frequency of the pulse signal in the pulse signal generator 100 according to one embodiment is proportional to the binary code (B <0> , B <1> , ..., B <n>) is inversely proportional to the code value, so it is possible to use this to change the binary code (B <0> , B <1> , ..., B <n>) code value while moving the center frequency of the pulse signal to achieve frequency hopping.

[0091] The pulse signal generator 100 according to an embodiment can be widely used in all fields using pulses. For example, it can be applied to devices used for communication, radar, distance measurement, and positioning, greatly increasing the communication distance, and enabling efficient signal processing in terms of identifying objects through changes in pulse frequency in each cycle.

[0092] Figure 2 is a schematic diagram for explaining an example of the operation of a pulse signal generator according to an embodiment.

[0093] In other words, Figure 2 It is used to illustrate the Figure 1 The schematic diagram of an example of the operation of the pulse signal generator according to one embodiment is described below. Figure 2 The contents described here are those that overlap with those described in the pulse signal generator according to one embodiment.

[0094] See also Figure 2 , reference numeral 200 represents a timing diagram of the operation of a pulse signal generator according to an embodiment.

[0095] Specifically, according to reference numeral 200 , an edge coupling section of a pulse signal generator according to an embodiment can receive a digital pulse-based input signal (CLOCK) and generate a plurality of digital windows EC1 , EC2 , EC3 , and EC4 through a switched capacitor-based delay unit.

[0096] Also, the push-pull pulse generating section of the pulse signal generator according to one embodiment can receive a plurality of digital windows EC1 , EC2 , EC3 , and EC4 as inputs, and output a pulse signal TX OUT corresponding to the received digital windows EC1 , EC2 , EC3 , and EC4 .

[0097] In addition, the counting unit of the pulse signal generator according to one embodiment can receive the input signal CLOCK and output a binary code (B<0:N>) for controlling the switching operation of the switch capacitor provided in the edge coupling portion.

[0098] Figure 3 is a schematic diagram for illustrating a multiple pulse modulation transmitter according to an embodiment.

[0099] See also Figure 3 According to an embodiment, a multiple pulse modulation transmitter 300 may include a digital-to-time conversion unit 310 and a pulse signal generation unit 320 .

[0100] For example, the multi-pulse modulation transmitter 300 may be a transmitter based on a digital multi-pulse modulation (D-MPPM) technology, and the digital-to-time converter 310 may include a digital-to-time converter (DTC).

[0101] According to one aspect, the pulse signal generating unit 320 may be a Figure 1 to Figure 2 The pulse signal generator according to one embodiment is described. Figure 3 In the description, descriptions overlapping with the description of the pulse signal generator according to one embodiment are omitted.

[0102] According to one embodiment, the digital-to-time conversion unit 310 receives a reference clock signal and a data signal, generates a signal including a sync pulse and a data pulse in one clock cycle, and can generate a signal with the time interval between the sync pulse and the data pulse adjusted.

[0103] According to one aspect, the digital-to-time conversion unit 310 can adjust the time interval between the synchronization pulse and the data pulse according to the bit of the data signal.

[0104] Specifically, the digital-to-time converter 310 can adjust the time between the synchronization pulse and the data pulse through the digital-to-time converter according to the bit value (number) of the input data signal, and modulate the time difference between the synchronization pulse and the data pulse.

[0105] In other words, according to one embodiment, the multiple pulse modulation transmitter 300 transmits data by adjusting the time interval between the synchronization pulse and the data pulse in one clock cycle, thereby increasing the communication distance by increasing the communication speed and the energy per bit (Energy Per Bit) of the pulse and increasing the size of the pulse signal (Impulse Signal).

[0106] More specifically, the digital-to-time conversion unit 310 uses the synchronization pulse as a start signal for the operation of the digital-to-time converter, and the data pulse carrying the input data signal as an interrupt signal for interrupting the digital-to-time converter, thereby being able to accurately determine the time interval between the synchronization pulse and the data pulse.

[0107] The digital-to-time conversion unit 310 can use a delay line including a plurality of delay cells connected in series to arrange a data pulse at a time position corresponding to input data.

[0108] For example, when 210 time positions are set within one cycle of a synchronization pulse, a data pulse can be configured and encoded at the time position corresponding to the bit of input data in the preset time position, and the position (time interval) of the data pulse can be measured based on the synchronization pulse to decode the input data.

[0109] To give a more specific example, when the input data signal is '00...000', the time position of the data pulse is encoded as '1', when the input data signal is '00...001', the time position of the data pulse is encoded as '2', when the input data signal is '00...010', the time position of the data pulse is encoded as '3', and when the input data signal is '11...111', the time position of the data pulse can be encoded as '2 n '(where n is a natural number).

[0110] Furthermore, when the input data signal is '00...000', the time position code of the data pulse is '2 n ', when the input data signal is '00...001', the time position encoding of the data pulse is '2 n -1', when the input data signal is '00...010', the time position encoding of the data pulse is '2 n -2', the time position of the data pulse can be encoded as '1' when the input data signal is '11...111'.

[0111] According to an embodiment, the pulse signal generating unit 320 can receive the signal with the adjusted time interval from the digital-to-time conversion unit 310 and generate an impulse signal (Impulse Signal) corresponding to the signal with the adjusted time interval by frequency hopping using a switched capacitor (Switched Capacitor).

[0112] Specifically, the pulse signal generating unit 320 includes a delay unit based on a switched capacitor, and thus can adjust the delay time of the delay unit based on the switched capacitor by changing the capacitance of all the delay units by changing the code of the switched capacitor.

[0113] The capacitance of all the delay units is inversely proportional to the pulse center frequency, so the pulse signal generating unit 320 can shift the frequency of the pulse signal for transmission.

[0114] In other words, the pulse signal generating unit 320 according to one embodiment can generate a pulse signal using a digital frequency hopping technique and transmit the generated pulse signal.

[0115] That is, the multiple pulse modulation transmitter 300 according to one embodiment can be effectively used in the operating room for wireless high-definition medical imaging to maximize the communication efficiency. Compared with the currently used transmitter based on D-MPPM technology, it does not require additional power and greatly increases the communication distance. It can improve the communication efficiency at a high speed (~ hundreds of Mb / s), low power (~ tens of mW), and medium distance (~ 10m) level.

[0116] Figure 4 FIG. 1 is a schematic diagram for explaining an example of a digital-to-time conversion unit according to an embodiment.

[0117] In other words, Figure 4 It is used to illustrate the Figures 1 to 3 The following is a schematic diagram of an embodiment of a digital-to-time conversion unit of a multiple pulse modulation transmitter according to an embodiment of the present invention. Figure 4 In the description, descriptions overlapping with the description of the multi-pulse modulation transmitter according to one embodiment are omitted.

[0118] See also Figure 4 The digital-to-time conversion unit 400 may include a digital-to-time converter 410 and an OR gate 420 .

[0119] Specifically, the digital-to-time converter 410 may receive a reference clock (Clock) signal and a data (Data) signal as inputs.

[0120] For example, the digital-to-time converter 410 may include an N-bit (where N is a natural number) MUX (Multiplexer) and a delay line connected to the input of the N-bit MUX.

[0121] The delay line is implemented as a series connection with a preset delay time (T M ) has at least one delay unit structure capable of delaying a reference clock (Clock) signal.

[0122] According to one aspect, the N-bit MUX receives a delayed reference clock signal and a data signal as inputs, adjusts the time interval between a synchronization pulse and a data pulse, and can provide the result to the OR gate 420 .

[0123] In addition, the OR gate 420 can receive the result value output from the N-bit MUX and the reference clock signal as inputs to generate a signal with the time interval between the synchronization pulse and the data pulse adjusted within one clock cycle. For example, the signal with the time interval adjusted can be a signal based on a digital pulse.

[0124] Figure 5a to Figure 5b FIG. 1 is a schematic diagram for explaining an example of generating a pulse signal using a multiple pulse modulation transmitter according to an embodiment.

[0125] In other words, Figure 5a to Figure 5b It is used to illustrate the Figures 1 to 4 The schematic diagram of an example of the operation of a multiple pulse modulation transmitter according to an embodiment is described below. Figure 5a to Figure 5b In the description, descriptions overlapping with the description of the multi-pulse modulation transmitter according to one embodiment are omitted.

[0126] See also Figure 5a to Figure 5b , reference numeral 510 represents a timing diagram of the operation of a multiple pulse modulation transmitter according to an embodiment, and reference numeral 520 represents a power spectrum density (PSD)-frequency (Frequency) characteristic of the frequency hopping operation of the multiple pulse modulation transmitter according to an embodiment.

[0127] Specifically, according to reference numeral 510, the digital-to-time conversion unit of the multiple pulse modulation transmitter according to one embodiment can receive a reference clock (Reference Clock) signal and a data signal (Input Data), generate a synchronization pulse (Sync-Pulse) and a data pulse (Data-Pulse) in one clock cycle (T), and adjust the time interval (τ) between the generated synchronization pulse (Sync-Pulse) and the data pulse (Data-Pulse) according to the number of bits of the data signal (InputData). Data ).

[0128] For example, the digital-to-time conversion unit can adjust the time position of the data pulse (Data-Pulse) based on the synchronization pulse (Sync-Pulse) to '1' when the bit value of the data signal (Input Data) is '00000', and can adjust the time position of the data pulse (Data-Pulse) based on the synchronization pulse (Sync-Pulse) to '32' when the bit value of the data signal (Input Data) is '11111'.

[0129] In other words, the digital-to-time conversion unit can adjust the initial time interval (τ) to the value of the bit of the data signal (Input Data) as '00000'. guard ), when the bit value of the data signal (Input Data) is '00001' to '11111', the preset time interval (τ Data ).

[0130] In addition, the counting section of the multiple pulse modulation transmitter according to one embodiment can generate binary codes '00000' to '11111' corresponding to the reference clock signal through at least one D flip-flop receiving the reference clock signal as an input.

[0131] That is, the edge coupling unit of the pulse signal generating unit of the multiple pulse modulation transmitter according to one embodiment can receive the binary code '00000' to '11111' from the counting unit to control the switching operation of the switching capacitor, and transmit the digital window controlled according to the switching operation to the push-pull pulse generating unit of the pulse generating unit, and the push-pull pulse generating unit can receive the output digital window and generate a pulse signal corresponding to the received digital window.

[0132] According to reference numeral 520, a multiple pulse modulation transmitter (Proposed) according to an embodiment can change the center frequency of a pulse signal by changing the working control of a switched capacitor of a binary code (B<0:N>), thereby being able to implement frequency hopping differently from an existing transmitter (Conventional).

[0133] Therefore, when using the multi-pulse modulation transmitter according to one embodiment, data is transmitted by utilizing the time difference between the synchronization pulse and the data pulse, thereby improving the wireless communication speed and the wireless communication distance.

[0134] Furthermore, by using a delay circuit based on a switched capacitor to transmit a pulse signal in a frequency hopping manner, the wireless communication speed and wireless communication distance can be further improved without consuming additional power.

[0135] Figure 6 is a schematic diagram for explaining a synchronization device according to an embodiment.

[0136] pass Figure 6 The synchronization device according to one embodiment of the present invention may be configured to receive Figures 1 to 5b A pulse signal receiver for a pulse signal generated by a multiple pulse modulation transmitter according to one embodiment is described.

[0137] Therefore, the following Figure 6 In the description, descriptions that overlap with the description of the multi-pulse modulation transmitter according to one embodiment are omitted.

[0138] See also Figure 6 According to an embodiment, a synchronization device 600 may include an analog processing unit 610 and a synchronization unit 620 .

[0139] For example, the synchronization device 600 according to an embodiment may be a synchronizer that synchronizes the clocks of signals transmitted and received between the multiple pulse modulation transmitter and the pulse signal receiver according to an embodiment.

[0140] According to an embodiment, the analog processing unit 610 can receive an impulse signal (Impulse Signal) and generate at least one detection pulse (Detected Pulse) corresponding to the received impulse signal.

[0141] According to one aspect, the pulse signal may be a signal for adjusting the time interval between a sync pulse (Sync Pulse) and a data pulse (Data Pulse) within one clock cycle.

[0142] In other words, the pulse signal received by the analog processing unit 610 may be a pulse signal output by a pulse signal generating unit of the multiple pulse modulation transmitter according to an embodiment.

[0143] Also, the at least one detection pulse may be a pulse signal based on a digital pulse corresponding to the synchronization pulse and the data pulse.

[0144] The synchronization unit 620 according to an embodiment can receive the detection pulse output from the analog processing unit 610 as an input, output a recovery clock corresponding to the detection pulse, and perform a synchronization operation based on the synchronization pulse of the pulse signal.

[0145] Figure 7 is a schematic diagram for explaining an example of an analog processing unit according to an embodiment.

[0146] In other words, Figure 7 It is used to illustrate the Figure 6 The schematic diagram of an embodiment of the analog processing unit of the synchronization device according to an embodiment is described below. Figure 7 In the description, descriptions overlapping with the description of the synchronization device according to one embodiment are omitted.

[0147] See also Figure 7 According to an embodiment, the analog processing unit 700 may include a low noise amplifier (Low Noise Amplifier; LNA) 710, an envelope detector (Envelope Detector) 720 and a comparator 730.

[0148] According to one aspect, the low noise amplifier 710 receives a pulse signal as input and is capable of amplifying the received pulse signal.

[0149] The envelope detector 720 can detect the peak point (Peak Point) of the amplified pulse signal.

[0150] The comparator 730 can generate at least one detection pulse corresponding to the pulse signal received corresponding to the peak point detected by the envelope detector 720 .

[0151] For example, the comparator 730 can compare the output of the envelope detector 720 with a reference level (ReferenceLevel, V th ), when the output signal of the envelope detector 720 is lower than the reference level (V th ), and outputs '1' when the output signal of the envelope detector 720 is higher than the reference level (Vth), and outputs '0'.

[0152] In other words, the comparator 730 can generate a detection pulse based on a digital pulse corresponding to the output signal of the envelope detector 720 .

[0153] Figure 8 FIG. 1 is a schematic diagram for explaining an example of a synchronization unit according to an embodiment.

[0154] In other words, Figure 8 It is used to illustrate the Figure 6 The following is a schematic diagram of an embodiment of a synchronization unit of a synchronization device according to an embodiment of the present invention. Figure 8 In the description, descriptions overlapping with the description of the synchronization device according to one embodiment are omitted.

[0155] See also Figure 8 According to an embodiment, the synchronization unit 800 may include a D flip-flop (D Flip-Flop) 810, a delay unit 820 and a combinatorial logic (Combinational Logic) 830.

[0156] According to one aspect, when a detection pulse output from an analog processing unit of a synchronization device according to an embodiment is applied to a clock port (CLK Port), the D flip-flop 810 may be triggered (Trigger) corresponding to an edge (Edge) of the detection pulse.

[0157] According to one aspect, when the period value of the DFF output signal corresponding to the Nth (where N is a natural number) clock cycle of the pulse signal is greater than the minimum period value of the data pulse included in the Nth clock cycle and less than the period value of the synchronization pulse included in the Nth clock cycle, the detection pulse corresponding to the data pulse included in the Nth clock cycle can be ignored, and the detection pulse corresponding to the synchronization pulse included in the N+1th clock cycle triggers the D flip-flop 810.

[0158] Furthermore, the D flip-flop 810 can charge the output node Q to the power supply voltage (VDD) level and then input the DFF output signal.

[0159] The delay unit 820 can delay the DFF output signal by an amount corresponding to a preset time.

[0160] Furthermore, the combinational logic 830 can receive the delayed DFF output signal to output a recovery clock (RecoveryClock), and control the D flip-flop to reset (Reset) so that the output node Q is discharged (Discharge).

[0161] Figures 9a to 9e FIG. 1 is a schematic diagram for explaining an example of performing a synchronization operation using a synchronization device according to an embodiment.

[0162] In other words, Figures 9a to 9e It is used to illustrate the Figures 6 to 8 The schematic diagram of an example of the operation of the synchronization device according to an embodiment is described below. Figures 9a to 9e In the description, descriptions overlapping with the description of the synchronization device according to one embodiment are omitted.

[0163] See also Figures 9a to 9e , reference numeral 910 represents a timing diagram of the operation of a synchronization device according to an embodiment, and reference numeral 920 represents a period value (τ) of a synchronization pulse (Sync Pulse) Sync-pulse ) and the period value (τ Data-pulse ).

[0164] Also, reference numeral 930 represents the maximum period value (τ Data-pulse,max ), reference numeral 940 represents the minimum period value of the data pulse (τ Data-pulse,min ), reference numeral 950 represents the relationship between a detection pulse (Detected Pulse) output from the analog processing unit (AFE OUT) and a recovery clock (Recovery Clock) generated by the synchronization unit.

[0165] According to reference numeral 910 , an analog processing unit of a synchronization device according to an embodiment can receive a pulse signal and generate at least one detection pulse (Detected Pulse) corresponding to the pulse signal.

[0166] Furthermore, the D flip-flop provided in the synchronization unit of the synchronization device according to one embodiment can be triggered (Trigger) in response to the edge (Edge) of the detection pulse (Detected Pulse) corresponding to the synchronization pulse (Sync Pulse), and the output node (DFF OUT) can be charged to the power supply voltage (VDD) level. That is, the D flip-flop can output the DFF output signal through the output node (DFF OUT).

[0167] The delay unit provided in the synchronization unit can delay the rising edge (Rising Edge) of the DFF output signal by a certain time (ΔT) and output the delayed DFF output signal (Node X).

[0168] The combinational logic included in the synchronization unit can generate a recovery clock (Recovery Clock) corresponding to the delayed DFF output signal (Node X).

[0169] In addition, since the cycle of the recovery clock is always the system clock, it can always be reset after a certain time (ΔT) from the triggered edge and trigger the next edge.

[0170] It can be confirmed from the reference numeral 920 that due to the Nth cycle (N th Period) and the SyncPulse of the N+1th cycle (N+1 th The frequency (f Sync-Pulse ) is always constant, and the position of the data pulse (Data Pulse) is changed by the input data signal, so the frequency (f Data-Pulse ) is different for each cycle.

[0171] According to reference numerals 930 to 950, it is possible to confirm the maximum period value (τ Data-pulse,max ) in the Nth clock cycle (N th Period) is 0, and in the N+1th clock cycle (N+1 th Period) is 2 M (where M is an integer).

[0172] Similarly, it is possible to confirm the minimum period value (τ Data-pulse,min ) in the Nth clock cycle (N th Period) is 2 M (where M is a natural number), in the N+1th clock cycle (N+1 th Period) is 0.

[0173] That is, the frequency (f Data-Pulse ) In the case of a D-MPPM having characteristics that are different in each period, a result such as that shown in FIG. 950 can be exhibited.

[0174] When expressing reference numeral 950 by a mathematical expression, it can be expressed by the following mathematical expression 1.

[0175] [Mathematical formula 1]

[0176] τ Data-pulse,min (1 / f Data-Pulse,min )<τ synchronization

[0177] Among them, τ Synchronization Reference numeral 910 denotes ΔT.

[0178] In addition, ΔT should be smaller than the period of the sync pulse (τ Sync-pulse ), so the following mathematical formula 2 should also be satisfied.

[0179] [Mathematical formula 2]

[0180] τ synchronization <τ sync-pulse

[0181] That is, according to a synchronization device of an embodiment, the period value (τ Synchronization ) is greater than the minimum period value (τ) of the data pulse (Data Pulse) included in the Nth clock cycle. Data-Pulse,min ), which is less than the period value (τ) of the sync pulse (Sync Pulse) included in the Nth clock cycle. Sync-pulse ) in the case of a pulse having a certain period, it is possible to automatically synchronize to a pulse having a certain period in a system utilizing two pulses having different frequencies, thereby enabling synchronization to be achieved very efficiently.

[0182] As a result, the synchronization device according to one embodiment can efficiently achieve synchronization using a logic circuit that consumes almost no power, and thus can achieve synchronization of transceivers using ultra-low power.

[0183] Furthermore, the synchronization device according to an embodiment is implemented by a stable digital structure, and thus can be easily applied to various circuits such as frequency division and frequency multiplication.

[0184] Furthermore, the synchronization device according to one embodiment can synchronize to the synchronization pulse regardless of other system clock input and shifted pulses by utilizing the frequency difference between the synchronization pulse and the data pulse of the signal whose time interval between the synchronization pulse and the data pulse is adjusted.

[0185] Fig.10 is a schematic diagram for explaining a working method of a pulse signal generator according to an embodiment.

[0186] In other words, Fig.10 It is used to illustrate the Figures 1 to 5b A schematic diagram of a working method of a pulse signal generator of a multiple pulse modulation transmitter according to an embodiment of the present invention is provided. Fig.10 In the description, descriptions overlapping with the description of the multi-pulse modulation transmitter according to one embodiment are omitted.

[0187] Therefore, the following omits Figure 6 The description is repeated in the description of the multiple pulse modulation transmitter according to one embodiment.

[0188] See also Fig.10 In step 1010, according to a working method of a pulse signal generator of an embodiment, the edge combination portion is capable of receiving an input signal and outputting at least one digital window corresponding to the input signal in a frequency hopping manner using a switched capacitor.

[0189] According to one aspect, the input signal may be a signal in which the time interval between a sync pulse (Sync Pulse) and a data pulse (Data Pulse) is adjusted within one clock cycle.

[0190] According to one aspect, the edge coupling portion may include at least one delay cell including a plurality of switch capacitors.

[0191] According to one aspect, in step 1010, according to the working method of a pulse signal generator of one embodiment, it is possible to delay the rising edge (Rising Edge) of the input signal by an amount corresponding to the delay time of at least one delay unit, and output at least one digital window corresponding to the delayed edge.

[0192] More specifically, in step 1010, according to the working method of a pulse signal generator of an embodiment, the counting unit generates a binary code (Binary Code) corresponding to the input signal through at least one D flip-flop (D Flip-Flop), and the edge combining unit can control the operation of multiple switching capacitors respectively through the binary code to adjust the delay time of the delay unit.

[0193] Next, in step 1020, according to a working method of a pulse signal generator in one embodiment, the push-pull pulse generating unit can receive the output digital window and generate a pulse signal corresponding to the received digital window.

[0194] Fig.11 is a schematic diagram for explaining a working method of a synchronization device according to an embodiment.

[0195] In other words, Fig.11 It is used to illustrate the Figures 6 to 9e A schematic diagram of a working method of a synchronization device according to an embodiment is shown below. Fig.11 In the description, descriptions overlapping with the description of the synchronization device according to one embodiment are omitted.

[0196] See also Fig.11 In step 1110, according to a working method of a synchronization device of one embodiment, the analog processing unit is capable of receiving an impulse signal (Impulse Signal) and generating at least one detection pulse (Detected Pulse) corresponding to the received impulse signal.

[0197] According to one aspect, the pulse signal may be a signal in which the time interval between a sync pulse (Sync Pulse) and a data pulse (Data Pulse) is adjusted within one clock cycle.

[0198] That is, the pulse signal may be a signal output from a multiple pulse modulation transmitter according to one embodiment.

[0199] In other words, step 1110 of the working method of the synchronization device according to one embodiment can be performed by Fig.10 Step 1020 of the described working method of the pulse signal generator according to one embodiment is performed later.

[0200] According to one aspect, in step 1111, according to a working method of a synchronization device of an embodiment, a low noise amplifier (Low Noise Amplifier; LNA) can receive a pulse signal as an input and amplify it.

[0201] Furthermore, in step 1112, according to a working method of a synchronization device in one embodiment, an envelope detector (Envelope Detector) can detect a peak point (Peak Point) of the amplified pulse signal.

[0202] Furthermore, in step 1113, according to the working method of the synchronization device of one embodiment, the comparator is capable of generating at least one detection pulse corresponding to the detected peak point.

[0203] Next, in step 1120, according to the working method of the synchronization device of one embodiment, the synchronization unit is capable of receiving at least one detection pulse as input, and outputting a recovery clock (Recovery Clock) corresponding to the at least one detection pulse to perform synchronization work of a synchronization pulse (Sync Pulse) based on a pulse signal.

[0204] According to one aspect, in step 1121, according to the working method of the synchronization device of one embodiment, when at least one detection pulse is applied to the clock port (CLK Port), the D flip-flop (DFlip-Flop) can be triggered (Trigger) corresponding to the edge (Edge) of at least one detection pulse, and charge (Charge) the output node to the power supply voltage (VDD) level to output the DFF output signal.

[0205] For example, in step 1121, according to the working method of the synchronization device of one embodiment, when the period value of the DFF output signal corresponding to the Nth (where N is a natural number) clock cycle of the pulse signal is greater than the minimum period value of the data pulse included in the Nth clock cycle and less than the period value of the synchronization pulse included in the Nth clock cycle, the D flip-flop can ignore the detection pulse corresponding to the data pulse included in the Nth clock cycle, and the detection pulse corresponding to the synchronization pulse included in the N+1th clock cycle is triggered.

[0206] Furthermore, in step 1122, according to the working method of the synchronization device of one embodiment, the delay unit can delay the DFF output signal by an amount equivalent to a preset time.

[0207] Furthermore, in step 1123, according to a working method of a synchronization device in one embodiment, a combinatorial logic can receive a delayed DFF output signal and output a recovery signal, and control the D flip-flop to reset (Reset) so that the output node is discharged.

[0208] As a result, when the present invention is used, data can be transmitted using the time difference between the synchronization pulse and the data pulse, thereby increasing the wireless communication speed and wireless communication distance.

[0209] Furthermore, when the present invention is used, a pulse signal can be transmitted in a frequency hopping manner using a delay circuit based on a switched capacitor, thereby further improving the wireless communication speed and wireless communication distance without consuming additional power.

[0210] Furthermore, since synchronization can be efficiently achieved using a logic circuit that consumes almost no power, synchronization of transceivers can be achieved with ultra-low power.

[0211] Furthermore, since the synchronization device is realized by a stable digital structure, it can be easily applied to various circuits such as frequency division and frequency multiplication.

[0212] Furthermore, by utilizing the frequency difference between the synchronization pulse and the data pulse of the signal in which the time interval between the synchronization pulse and the data pulse is adjusted, synchronization to the synchronization pulse can be achieved regardless of other system clock inputs and shifted pulses.

[0213] The above-described device can be implemented by hardware components, software components and / or a combination of hardware components and software components. For example, the device and components described in the embodiment can be implemented by one or more general-purpose computers or special-purpose computers such as processors, controllers, arithmetic logic units (ALUs), digital signal processors (digital signal processors), microcomputers, field programmable gata arrays (FPGAs), programmable logic units (PLUs), microprocessors, or other devices capable of running and responding to instructions. The processing device can run an operating system (OS) and one or more software applications executed on the operating system. In addition, the processing device can respond to the software operation to access, store, operate, process, and generate data. For ease of understanding, there is a situation in which the description is based on the use of a processing device, but a person skilled in the art can know that the processing device may include multiple processing elements and / or multiple types of processing elements. For example, the processing device may include multiple processors or a processor and a controller. Furthermore, other processing configurations such as parallel processors are also possible.

[0214] Software may include a computer program, code, instructions, or a combination of more than one of these, which may configure a processing device to work as required, or independently or collectively command a processing device. With respect to software and / or data, in order to be parsed by a processing device or to provide instructions or data to a processing device, it may be permanently or temporarily embodied in a certain type of machine, component, physical device, virtual device, computer storage medium or device, or a transmitted signal wave. The software may be distributed on computer systems connected by a network and stored or executed in a distributed manner. The software and data may be stored on one or more computer-readable storage media.

[0215] The method according to the embodiment can be implemented as a program command that can be executed by a variety of computer components and stored in a computer-readable storage medium. The computer-readable storage medium may include program instructions, data files, data structures, etc. or a combination thereof. The program instructions stored in the medium may be specially designed and constructed for the embodiment, but may also be well-known and used by technicians in the field of computer software. The computer-readable storage medium may be, for example, a magnetic medium such as a hard disk, a floppy disk, and a tape, an optical storage medium such as an optical media such as a CD-ROM, a DVD, a magnetic-optical medium such as a floppy disk, and a hardware device specially constructed for storing and executing program commands such as a ROM, a RAM, and a flash memory. Examples of program commands include not only machine codes obtained by a compiler, but also high-level language codes that can be run by a computer through an interpreter, etc. The hardware device may be configured to work as one or more software modules in order to perform the work of the embodiment, and vice versa.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A pulse signal generator, characterized in that: include: an edge combining section that receives an input signal and outputs at least one digital window corresponding to the input signal in a frequency hopping manner using a switched capacitor; as well as a push-pull pulse generating unit, which receives the output digital window, generates a pulse signal corresponding to the received digital window, and outputs the generated pulse signal to a synchronization device that generates at least one detection pulse, wherein the at least one detection pulse corresponds to the pulse signal; The edge combining portion has at least one delay unit including a plurality of the switch capacitors; The at least one delay unit controls the operation of the plurality of switch capacitors to adjust the delay time of the delay unit by respectively controlling the operation of the plurality of switch capacitors through a binary code corresponding to the input signal; The input signal is a signal generated by receiving a reference clock signal and a data signal to include a synchronization pulse and a data pulse in one clock cycle, and a time interval between the data pulse and the synchronization pulse is based on a bit value of the data signal; The synchronization device comprises: When the at least one detection pulse is applied to the clock port, a first D flip-flop is triggered corresponding to an edge of the at least one detection pulse, and charges an output node to a power supply voltage level to output a D flip-flop DFF output signal; A delay section that delays the DFF output signal by an amount corresponding to a preset time; and A recovery clock corresponding to the delayed DFF output signal is output to perform a synchronous operation, and a combinational logic that resets the first D flip-flop to discharge the output node is controlled by the recovery clock.

2. The pulse signal generator according to claim 1, characterized in that: The edge combination unit delays the rising edge of the input signal by an amount corresponding to the delay time of the at least one delay unit, and outputs the at least one digital window corresponding to the delayed rising edge.

3. The pulse signal generator according to claim 1, characterized in that: Also includes: A counting unit generates the binary code by at least one D flip-flop.

4. A working method of a pulse signal generator, characterized in that: include: The edge combining unit receives an input signal and outputs at least one digital window corresponding to the input signal in a frequency hopping manner using a switched capacitor; as well as The push-pull pulse generating unit receives the output digital window, generates a pulse signal corresponding to the received digital window, and outputs the generated pulse signal to a synchronization device that generates at least one detection pulse, wherein the at least one detection pulse corresponds to the pulse signal; The edge combining portion has at least one delay unit including a plurality of the switch capacitors; In the step of outputting the digital window, Generate a binary code corresponding to the input signal, and the edge combining unit controls the operation of the plurality of switch capacitors to adjust the delay time of the delay unit through the binary code; The input signal is a signal generated by receiving a reference clock signal and a data signal to include a synchronization pulse and a data pulse in one clock cycle, and a time interval between the data pulse and the synchronization pulse is based on a bit value of the data signal; The synchronization device comprises: When the at least one detection pulse is applied to the clock port, a first D flip-flop is triggered corresponding to an edge of the at least one detection pulse, and charges an output node to a power supply voltage level to output a D flip-flop DFF output signal; A delay section that delays the DFF output signal by an amount corresponding to a preset time; and A recovery clock corresponding to the delayed DFF output signal is output to perform a synchronous operation, and a combinational logic that resets the first D flip-flop to discharge the output node is controlled by the recovery clock.

5. The working method of the pulse signal generator according to claim 4, characterized in that: In the step of outputting the digital window, The rising edge of the input signal is delayed by an amount corresponding to the delay time of the at least one delay unit, and the at least one digital window corresponding to the delayed rising edge is output.

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