Method of sealing an opening and method of forming an integrated assembly

Abstract

Some embodiments include a method of forming an integrated assembly. A structure is formed to include a structure having an exposed surface, and includes an opening proximate to the structure. A gap extends into the opening. A first material is deposited to form a mass along the exposed surface of the structure. Particles are sputtered from the mass and across the gap. The particles aggregate to form a sealant material that captures voids within the opening.

Description

Technical Field

[0001] Methods of sealing openings and methods of forming integrated assemblies. Background Art

[0002] Memory is a type of integrated circuit and is used in computer systems to store data. An example memory is DRAM (Dynamic Random Access Memory). DRAM cells may each include a transistor combined with a capacitor. DRAM cells may be arranged in an array; word lines extend along the rows of the array, and digit lines extend along the columns of the array. The word lines may be coupled to the transistors of the memory cells. Each memory cell may be uniquely addressed by a combination of one of the word lines and one of the digit lines.

[0003] Some DRAMs may have digit lines coupled to portions of the active area, and may have capacitors coupled to interconnects that extend to other portions of the active area. The interconnects may be close to the digit lines, and parasitic capacitances may problematically occur between the interconnects and the digit lines. It would be desirable to develop architectures that mitigate or even completely prevent such parasitic capacitances; and to develop methods of forming such architectures.

[0004] A strategy to mitigate parasitic capacitance is to utilize low-k regions between adjacent conductive components. A particularly desirable low-k region is a void region. However, adequately sealing the void region may be problematic. Therefore, it is desirable to develop methods suitable for sealing the void region. Such methods are expected to be applicable to a wide range of integrated applications, including but not limited to solutions to mitigate or prevent the above-mentioned problems regarding parasitic capacitance between interconnects and digital lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A schematic cross-sectional side view of an example construction during an example processing stage of an example method is shown.

[0006] Figure 2 is a schematic cross-sectional side view of an example reaction chamber.

[0007] Figures 3 to 7 is a schematic diagram of the area where the instance is constructed. Figure 3 and 5 is a schematic cross-sectional top view; and Figure 4 , 6 and 7 are schematic cross-sectional side views. Figure 3 The view is along Figure 4 and 6 Line 3-3. Figure 4 The view is along Figure 3 , 5 , 6 and 7 lines 4-4. Figure 5 The view is along Figure 4 , 6And the line of 7 is 5-5. Figure 6 The view is along Figure 3 , 4 And the line of 5 is 6-6. Figure 7 The view is along Figure 3 , 4 And the line of 5 is 7-7.

[0008] Figure 8 is along with Figure 4 The same cross-sectional view is shown in Figures 3 to 7 After the instance processing phase Figures 3 to 7 structure.

[0009] Fig. 9 is with Figure 8 The same processing stage Figure 8 Schematic cross-sectional view of region “Q” of FIG.

[0010] Figures 10 to 16 yes Fig. 9 The area "Q" is in Fig. 9 Schematic cross-sectional view of an example processing stage following a processing stage of .

[0011] Fig.17 is a schematic diagram of a region of an example memory array. DETAILED DESCRIPTION

[0012] Some embodiments include a method of forming an integrated assembly wherein a sealant material is provided across an opening to capture a void within the opening. The sealant material may be formed by a process that includes initially forming a mass along a structure associated with the integrated assembly, the structure being proximate to the opening. Subsequently, particles are sputtered out of the mass and deposited on the opening, the deposited particles agglomerating to form the sealant material. Some embodiments include an architecture in which a void is along a sidewall of a first conductive structure and is covered by an insulating sealant material. A second conductive structure may be separated from the first conductive structure by an intermediate region that includes the void. Due to the low dielectric constant of the void, the intermediate region has a low dielectric constant; therefore, problematic parasitic capacitance between the first conductive structure and the second conductive structure may be avoided. In some embodiments, the first conductive structure may be a digital line and the second conductive structure may be an interconnect that extends to a capacitor (or other suitable charge storage structure). Reference Figures 1 to 17 Example embodiments are described.

[0013] refer to Figure 1 , which shows a structure 300 at a preliminary processing stage "A". The structure includes a substrate 302 and a pair of structures 304 and 306 above the substrate. An opening 308 is between structures 304 and 306, and a gap 310 extends into the opening.

[0014] Substrate 302 may include any suitable composition; and may include conductive materials, insulating materials, and / or semiconductor materials. Similarly, structures 304 and 306 may include any suitable composition; and may include conductive materials, insulating materials, and / or semiconductor materials. Substrate 302, structure 304, and structure 306 may all include the same composition as one another; or at least one of them may include a different composition relative to one or both of the others.

[0015] In some embodiments, structure 306 may be considered to correspond to a post or rail.Structure 306 has a top surface 307, and has sidewall surfaces 309 extending downwardly from the top surface.

[0016] The mass 312 is formed along the upper region of the structure 306, as shown in FIG. Figure 1 3. Agglomerates 312 are shown at processing stage "B" of FIG. 312 are along top surfaces 306 of structures 307, and along upper sections of sidewall surfaces 309 of such structures.

[0017] Agglomerates 312 may be formed by depositing first material 314 along some exposed surfaces of structure 306 , wherein such deposition is performed under conditions that form the material along the tallest features of construction 300 .

[0018] The first material 314 may include any suitable composition; and in some embodiments may include one or more elements selected from Group 14 of the periodic table (eg, may include silicon, carbon, germanium, etc.).

[0019] The deposition of the first material 314 may utilize any suitable precursor; and in some embodiments may utilize a precursor including one or both of a halide and a hydride of at least one element selected from Group 14 of the periodic table (e.g., may include SiCl 4 、SiH 4 The resulting first material 314 may include a combination of an element selected from Group 14 of the periodic table (e.g., silicon) and one or more other components of the precursor. For example, in some embodiments, the first material 314 may include silicon combined with one or both of chlorine and hydrogen.

[0020] The deposition of material 314 may utilize any suitable method, including, for example, one or more of chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and the like.

[0021] Example conditions that may be used for deposition of material 314 may include a bias voltage on construction 300 in a range of about 50 volts (V) to about 2000 V when the construction is in a suitable reaction chamber (e.g., a dry etch chamber). The conditions may include one or more suitable precursors flowing into a reaction chamber (e.g., silicon tetrachloride, SiCl4) along with one or more suitable inert carrier gases (e.g., argon, nitrogen, helium, etc.). 4 ). The deposition may be performed while maintaining the environment within the reaction chamber at a temperature in the range of about 10° C. to about 100° C. and a pressure in the range of about 1 mTorr to about 200 mTorr. Plasma conditions may or may not be utilized during the deposition. If plasma conditions are utilized, the plasma may be remote from the structure 300 or may directly contact the surface of the structure 300.

[0022] Particles are sputtered from agglomerates 312 and such particles aggregate to form sealant material 316 that extends across gap 310 and captures voids 318 within opening 308, as shown in FIG. Figure 1 308. In some embodiments, some sealant material 316 may extend into opening 308. However, the sealant material typically does not fill the opening, and thus typically there is a void within the opening.

[0023] The conditions for sputtering particles from mass 312 may be oxidizing conditions, and sealant material 316 may include oxidized elements of first material 314 from process stage "B". For example, in some embodiments, first material 314 may include one or more elements from Group 14 of the periodic table (e.g., such as silicon), and sealant material 316 may include oxides of one or more elements from Group 14 of the periodic table (e.g., may include silicon dioxide). The oxidizing conditions may also convert first material 312 of mass 314 into material 320 including oxidized components of first material 314. For example, material 320 may include oxides of one or more elements from Group 14 of the periodic table. In addition, the oxidizing conditions may remove halides (e.g., chlorine) and / or hydrogen from material 314, such that material 320 and sealant material 316 consist of or consist essentially of one or more oxides of elements from Group 14 of the periodic table (e.g., silicon oxide, germanium oxide, etc.).

[0024] Example conditions that may be used for sputtering particles from agglomerates 312 and the associated formation of sealant material 316 may include a bias voltage on construction 300 in a range of about 50 volts (V) to about 2000 V when the construction is in a suitable reaction chamber (e.g., a dry etching chamber). Sputtering particles from agglomerates 312 may occur in the same reaction chamber as that used to form agglomerates 312, or may occur in a reaction chamber different from that used to form agglomerates. In some embodiments, the bias voltage used during deposition of agglomerates 312 may be referred to as a first bias voltage, and the bias voltage used during sputtering particles from agglomerates 312 may be referred to as a second bias voltage. The first bias voltage and the second bias voltage may be the same as each other, or may be different from each other.

[0025] The conditions used during sputtering of particles from the mass 312 may include one or more suitable oxidizing agents (e.g., diatomic oxygen, O 2 ; Ozone, O 3 ; Hydrogen peroxide, H 2 O 2 ; etc.) along with one or more suitable inert carrier gases (e.g., argon, nitrogen, helium, etc.) are flowed into the reaction chamber. Sputtering of particles from the mass 312 can be performed while maintaining the environment within the reaction chamber at a temperature in the range of about 10° C. to about 100° C. and a pressure in the range of about 1 mTorr to about 500 mTorr. Plasma conditions may or may not be utilized during sputtering. If plasma conditions are utilized, the plasma may be remote relative to the structure 300, or may directly contact the surface of the structure 300.

[0026] In some embodiments, deposition of agglomerates 312 (processing step "B") and sputtering of particles from the agglomerates to form sealant material 316 (processing step "C") are performed in the same reaction chamber as one another. In such embodiments, sputtering may occur simultaneously with some deposition (i.e., chemistries associated with the deposition may be in the reaction chamber at the same time as chemistries associated with the sputtering). Alternatively, sputtering may occur substantially entirely after deposition (i.e., chemistries associated with the sputtering may be provided in the reaction chamber only after chemistries associated with the deposition are completely, or at least substantially, exhausted from the chamber).

[0027] In embodiments where sputtering of particles from mass 312 occurs simultaneously with at least some deposition of mass 312, the environment within the reaction chamber for sputtering and deposition may contain a combination of a halogen-containing precursor (e.g., silicon tetrachloride) and / or a hydrogen-containing precursor (e.g., silane) with one or more oxygen-containing chemicals (e.g., diatomic oxygen, ozone, hydrogen peroxide, etc.). The chemicals may or may not be dispersed within the plasma.

[0028] In some embodiments, pinholes or other defects may extend partially or completely through the sealant material 316. Such defects may or may not be a problem. To the extent that defects are considered problematic, this can be mitigated by treating the sealant material. For example, the sealant material may be subjected to a thermal anneal at a temperature of at least about 500° C. to collapse the pinholes and / or otherwise solidify the problematic defects. Alternatively or additionally, a layer may be deposited on the sealant material to cover the pinholes and / or other defects. In some embodiments, such layers may include insulating materials; for example, silicon nitride and / or silicon dioxide. After the optional material layer 322 is disposed over the sealant material 316, processing step "D" shows the construction 300. Material 322 may include the same composition as sealant material 316 (e.g., both may include silicon oxide, consist essentially of silicon oxide, or consist of silicon oxide); or may include a different composition relative to the sealant material (e.g., sealant material 316 may include silicon dioxide, while material 322 includes silicon nitride).

[0029] Material 322 may be provided at any suitable thickness; and in some embodiments, the thickness may be about to about within the range.

[0030] Figure 1 The various processing stages can be performed in any suitable reaction chamber or any suitable combination of reaction chambers. Figure 2 An example reaction chamber 400 is schematically shown. A chuck 402 is provided to hold a substrate 404 in the chamber. The substrate 404 may be a substrate comprising a Figure 1 The semiconductor wafer of the construction 300 of the embodiment of the present invention is shown in FIG. 4. The chamber 400 includes an interior region 406 that maintains the environment within the chamber. Openings 408 and 410 extend through the walls of the chamber and are used to allow materials to flow into and out of the chamber. A valve (not shown) may be provided across the openings 408 and 410.

[0031] use Figure 1 The process of forming the void 318 may be useful during the manufacture of the integrated circuit. For example, the void may correspond to a low-k (low dielectric constant) insulating region suitable for electrically isolating adjacent conductive structures from each other. The advantage of using a low-k region is that this can reduce parasitic capacitance compared to an insulating region with a higher dielectric constant.

[0032] For processing similar Figure 1 An example application is the manufacture of integrated DRAM. Figures 3 to 17 An example process for manufacturing DRAM is described.

[0033] refer to Figures 3 to 7A portion of an example construction 10 is shown. Such constructions may be formed using any suitable method. Construction 10 is an example of an initial construction that may be used for some embodiments described herein, and it should be understood that other constructions may be used in place of construction 10.

[0034] The structure 10 includes a plurality of active regions 12 extending upward from a semiconductor substrate 14. Some of the active regions 12 are labeled 12a-f so that they can be distinguished relative to each other and relative to other active regions. All of the active regions 12 can be substantially identical to each other; the term "substantially identical" means identical within reasonable tolerances of manufacturing and measurement.

[0035] Active region 12 and semiconductor substrate 14 include semiconductor material 16. Such semiconductor materials may include any suitable composition; and in some embodiments, may include, consist essentially of, or consist of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, and the like; the term III / V semiconductor material refers to a semiconductor material including elements selected from Group III and Group V of the periodic table (Group III and Group V are old designations, now referred to as Group 13 and Group 15). In some embodiments, semiconductor material 16 may include, consist essentially of, or consist of silicon dioxide. The silicon may be in any suitable form; and in some embodiments may be single crystal silicon.

[0036] Base 14 may be referred to as a semiconductor substrate. The term "semiconductor substrate" refers to any construction including a semiconducting material, including but not limited to bulk semiconducting material (alone or in an assembly including other materials) such as a semiconducting wafer and a layer of semiconducting material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrate described above.

[0037] Active regions 12 are separated from one another by intermediate regions comprising insulating material 18. Insulating material 18 may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

[0038] The word lines (i.e., access lines) 20 extend in a first direction, which may ultimately correspond to the row direction of the memory array; and the digit lines (i.e., sensing lines, bit lines) 22 extend in a second direction, which may ultimately correspond to the column direction of the memory array. In the illustrated embodiment, the second direction of the bit lines 22 is substantially orthogonal to the first direction of the word lines 20. In order to allow the active area 12 to be fully illustrated, the active area 12 is not shown. Figure 3 In fact, the word line passes through the active area 12, as shown in FIG. Figure 5As shown in .

[0039] Word line 20 includes conductive material 24, and bit line 22 includes conductive material 26. Conductive materials 24 and 26 may include any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, conductive materials 24 and 26 may have the same composition as one another; and in other embodiments, conductive materials 24 and 26 may have different compositions relative to one another.

[0040] Insulating material 28 is over word line 20. Such insulating materials may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of silicon dioxide. Insulating material 28 may be the same composition as insulating material 18, or may be a different composition relative to insulating material 18.

[0041] Gate dielectric material 30 extends around a lower region of word line 20 and between the word line and active region 12. Gate dielectric material 30 may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of silicon dioxide.

[0042] Word lines 20 include transistor gates along active regions 12. Each of the active regions can be considered to include a digit line contact portion 32 and a capacitor contact portion 34. The transistor gate electrically couples the digit line contact portion with the capacitor contact portion. Figure 5 The digit line contact portion 32 and the capacitor contact portion 34 are depicted in order to help the reader understand the relative position of the word line 20 with respect to the digit line contact portion 32 and the capacitor contact portion 34. However, it should be understood that the digit line contact portion 32 and the capacitor contact portion 34 are actually located at a greater distance than the active area. Figure 5 The part is high, such as Figure 4 and 6 Described in.

[0043] Digit line contact portion 32 is coupled to electrical interconnect 36, which in turn is coupled to digit line 22. Interconnect 36 includes conductive material 38. Conductive material 38 may include any suitable conductive composition, such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0044] The digit lines 22 are labeled 22a-d so that they can be distinguished relative to each other. Figure 4 A cross section is shown in which digit lines 22a and 22c are coupled to digit line contact location 32 and in which digit lines 22b and 22d pass over capacitor contact location 34. Passing digit lines 22b and 22d are separated from underlying capacitor contact location 34 by insulating materials 40 and 42. Such insulating materials may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of silicon dioxide, silicon nitride, etc. Insulating materials 40 and 42 may be the same composition as one another, or may be different compositions from one another.

[0045] The digit lines 22 can be considered as conductive structures having a top surface 41 and sidewall surfaces 43; each of the digit lines has a pair of Figure 4 The opposite side wall surface 43 of the cross section.

[0046] Insulating material 44 is over top surface 41 of conductive structure 22. Insulating material 44 may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of silicon nitride.

[0047] Insulating material 46 is along sidewall surfaces 43 of conductive structure 22. Insulating material 46 may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of silicon nitride. Note that in some embodiments, materials 44 and 46 may include a common composition (e.g., silicon nitride) and thus may be incorporated into a single insulating structure.

[0048] Figure 4 Conductive structures 22 are shown separated from one another by intermediate regions 48. Insulating material 46 may be considered to be formed within such intermediate regions.

[0049] refer to Figure 8 ,exist Figures 3 to 7 After the processing stage of the present invention, a region of the structure 10 is shown; wherein the region is along the above relative to Figure 4 The same cross-sections as described are shown.

[0050] Figure 8The processing stage of FIG. 4 has additional insulating materials 50 and 52 formed within intermediate region 48. Insulating materials 50 and 52 may include any suitable composition. In some embodiments, material 50 is a sacrificial material that may be selectively removed relative to materials 44, 46, and 52. In some embodiments, sacrificial material 50 may include, consist essentially of, or consist of silicon dioxide, while materials 44, 46, and 52 may all include, consist essentially of, or consist of silicon nitride.

[0051] In some embodiments, materials 46, 50, and 52 may be considered together to form track 54, wherein such tracks are relatively Figure 8 The cross section of the sheet extends into and out of the sheet. Figure 3 ).

[0052] Track 54 may be considered to include sacrificial material 50 between a pair of panels 56 ; where such panels include non-sacrificial material 46 and 52 .

[0053] Conductive material 58 is formed in intermediate regions 48 between tracks 54. Conductive material 58 forms conductive interconnects 60 that extend to capacitor contact locations 34 of active region 12.

[0054] Conductive material 58 may include any suitable conductive composition, such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0055] Subsequent processing involves Figure 8 The structure is made in the upper part of the structure 10. These upper parts are Figure 8 The region "Q" is schematically shown in FIG. Fig. 9 The following embodiments are shown and used to describe the following embodiments. Fig. 9 The processing stage and Figure 8 The processing stages are the same.

[0056] refer to Fig.10 , portions of materials 50, 52, and 58 within intermediate region 48 are recessed. This can be accomplished using a mask (not shown) to protect some areas of construction 10 while exposing other areas to an appropriate etch that recesses the exposed areas. The protective mask can then be removed to leave Fig.10 Alternatively, at least some portion of the mask may remain in Fig.10 at the processing stage.

[0057] refer to Fig.11 , sacrificial material 50( Fig.10 ) is selectively removed relative to materials 44, 46, 52 and 58 to leave openings 62 between panels 56. The bottom of opening 62 is at Fig.11 Not shown; but will be Figure 8 The materials shown in 18 and 40 are covered.

[0058] refer to Fig.12 ,exist Fig.11 The construction 10 is shown at a processing stage after the processing stage of Figure 1 Specifically, materials 26, 38, 44, and 46 can be considered to form a similar Figure 1 The structure of the structure 306 is described.

[0059] Mass 312 is formed over the top of insulating materials 44 and 46 and along an upper section of the sides of structure 306 .

[0060] The mass 312 is similar to the above reference Figure 1 The mass described and includes material 314. Fig.12 The mass 312 can be utilized with reference Figure 1 The same processing as described is formed.

[0061] refer to Fig.13 ,exist Fig.12 The construction 10 is shown at a processing stage after the processing stage of FIG. Specifically, particles are sputtered from the mass 312 and used to form a sealant material 316 that extends across the opening 62 and captures voids 318 within the opening (i.e., similar to Figure 1 of the processing of stage “C”). Fig.13 The sealant material 316 can be utilized Figure 1 The processing conditions are generated.

[0062] An optional treatment is to treat the sealant material 316 to fill any pinholes present in such material and / or cure other potential defects. Such treatment may include the above referenced Figure 1 The method may include heat treatment and / or may include forming a material layer 322 over the sealant material 316. Optionally, the material layer 322 may be formed over the sealant material 316. Fig.13 322, such materials may be referred to as second insulating materials to distinguish them from first insulating materials 44.

[0063] refer to Fig.14, insulating material 68 is formed over masses 320, over insulating structures below such masses (i.e., structures including insulating material 44), across encapsulant material 316, and across conductive interconnect 60. In some embodiments, masses 320 may be removed prior to forming insulating material 68. Insulating material 68 extends over optional material 322. In some embodiments, insulating material 68 may be referred to as a second insulating material to distinguish it from first insulating material 44; and in some embodiments, insulating material 68 may be referred to as a third insulating material to distinguish it from first insulating material 44 and second insulating material 322.

[0064] Insulating material 68 may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of silicon nitride.

[0065] refer to Fig.15 , second insulating material 68, encapsulant material 316, optional material 322 (if such optional materials are present), and portions of material 320 of mass 312 are removed. Such removal exposes regions 70 of conductive interconnect 60. Removal of materials 316, 322, 320, and 68 may be accomplished by anisotropic etching of such materials, which forms materials 68, 316, 322 (if such optional materials are present), and 320 into spacers 72.

[0066] refer to Fig.16 , the exposed area 70 of the interconnect 60 is coupled to a capacitor 74. Each capacitor has a node 75 connected to the interconnect 60, and has another node 77 connected to a reference voltage 78. The reference voltage can be ground or any other suitable voltage. Nodes 75 and 77 are separated from each other by a dielectric region 79. Such dielectric regions can include any suitable dielectric material.

[0067] Capacitor 74 is an example of a charge storage device that may be coupled to conductive interconnect 60. In other embodiments, other suitable charge storage devices may be utilized. Thus, it should be understood that so-called capacitor contact locations 34 may be more generally referred to as charge storage device contact locations.

[0068] Fig.16 The configuration includes a conductive structure 22 having a top surface 41 and sidewall surfaces 43 (only some of which are labeled). An insulating material 44 is above the top surface. A void 318 is along the sidewall surfaces and is laterally separated from these sidewall surfaces by insulating material 46. In some embodiments, insulating materials 44 and 46 can be referred to as first insulating materials and second insulating materials, respectively. These first insulating materials and second insulating materials can include the same composition as each other (for example, can both include silicon nitride), or can include different compositions from each other.

[0069] The voids 318 have a low dielectric constant, thus forming low dielectric constant regions between the digit lines 22 and the conductive interconnects 60. Such low dielectric constant regions can reduce or even completely eliminate problematic parasitic capacitance between the conductive structures 22 and the conductive interconnects 60, compared to conventional configurations lacking such low dielectric constant regions.

[0070] Fig.16 The configuration of can be considered to correspond to a region of a memory array 90 (e.g., a DRAM array). The memory array includes memory cells including access transistors (e.g., including a transistor along the Figures 3 to 7 A transistor having a gate of one of the word lines 20). Fig.17 An example memory array 90 is described. The memory array includes digit lines (DL1-DL4) corresponding to digit lines 22a-d, and includes word lines (WL1-WL4) corresponding to word lines 20. Memory cells 80 include transistors 82 coupled to capacitors 74. Each of the transistors includes a gate 84 along one of the word lines 20. Each of the memory cells 80 can be uniquely addressed by a combination of a word line and a digit line.

[0071] Fig.17 The memory array 90 is a DRAM array, wherein each of the memory cells 80 includes a transistor and a capacitor. In other embodiments, similar Fig.16 In addition, it should be understood that the methods described herein can be used to form other integrated assemblies in addition to or in place of memory arrays. For example, the methods can be applied to the manufacture of logic, sensors, etc.

[0072] The assemblies and structures discussed above may be used in integrated circuits (the term "integrated circuit" refers to an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication demodulators, processor modules, and application-specific modules, and may include multi-layer multi-chip modules. The electronic system may be any of a variety of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0073] Unless otherwise stated, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0074] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. The terms are considered synonymous in this disclosure. The use of the term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may be a premise basis within this disclosure to provide language changes to simplify subsequent claims and is not intended to indicate any significant chemical or electrical differences.

[0075] The specific orientations of the various embodiments in the drawings are for illustration purposes only, and in some applications, the embodiments may be rotated relative to the orientations shown. The descriptions and appended claims provided herein relate to any structures having the described relationships between the various features, regardless of whether these structures are in a specific orientation of the drawings or rotated relative to such orientations.

[0076] To simplify the drawings, the cross-sectional views of the drawings show only the features within the cross-sectional plane and not the material behind the cross-sectional plane unless otherwise stated.

[0077] When a structure is referred to above as being "on," "adjacent," or "against" another structure, it can be directly on the other structure, or intervening structures may also be present. Conversely, when a structure is referred to as being "directly on," "directly adjacent," or "directly against" another structure, there are no intervening structures present.

[0078] Structures (eg, layers, materials, etc.) may be referred to as "vertically extending" to indicate that the structures extend generally upward from an underlying base (eg, substrate). Vertically extending structures may extend substantially vertically relative to an upper surface of the base, or may not extend vertically.

[0079] Some embodiments include a method of forming an integrated assembly. A structure is formed to include a structure having an exposed surface, and includes an opening proximate to the structure. A gap extends into the opening. A first material is deposited to form a mass along the exposed surface of the structure. Particles are sputtered from the mass to form a sealant material that extends across the gap and captures voids within the opening.

[0080] Some embodiments include a method of forming an integrated assembly. A construction is formed to include, in cross-section, a conductive structure having a top surface and a pair of opposing sidewall surfaces extending downward from the top surface. The construction also includes insulating material above the top surface and includes tracks along the sidewall surfaces. Each of the tracks includes sacrificial material along a panel of non-sacrificial material. The sacrificial material is removed to leave an opening between the sidewall surface and the panel of non-sacrificial material. A mass is formed above the top of the insulating material and along an upper section of the sides of the insulating material. Particles are sputtered out of the mass to form a sealant material that extends across the opening and captures voids within the opening.

[0081] Some embodiments include a method of forming an integrated assembly. A construction is formed to include a pair of digital lines separated from each other by an intermediate region along a cross section. Each of the digital lines has a top surface and a pair of opposing sidewall surfaces extending downward from the top surface. The construction includes an insulating structure above the top surface and includes a track along the sidewall surface. The track includes a sacrificial material sandwiched between a pair of panels. The construction includes a conductive interconnect within the intermediate region. The insulating structure includes a first insulating material. The sacrificial material is removed to leave an opening between the panels. A mass is formed above the top of the insulating structure and along an upper section of the sides of the insulating structure. Particles are sputtered from the mass to form a sealant material that extends across the opening and covers the gap within the opening. A second insulating material is formed across the insulating structure, across the sealant material, and across the conductive interconnect. A portion of the second insulating material is removed to expose an area of ​​the conductive interconnect. The exposed area of ​​the conductive interconnect is coupled to a charge storage device.

Claims

1. A method of forming an integrated assembly, comprising: forming a construct to include a structure having an exposed surface and an opening proximate to the structure; The formation includes a slit extending into the opening; depositing a first material to form masses along the exposed surface of the structure; as well as Particles are sputtered from the mass to form a sealant material that extends across the gap and captures voids within the opening.

2. The method of claim 1 , wherein the structure has a top surface and a pair of opposite sidewall surfaces extending downward from the top surface in a cross-section; and wherein the deposition forms the agglomerates along the top surface of the structure and along upper sections of the sidewall surfaces of the structure.

3. The method of claim 1, further comprising treating the sealant material to fill any pinholes present in the sealant material. The method of claim 3 , wherein the processing comprises depositing a layer of insulating material over the encapsulant material. The method of claim 4 , wherein the insulating material comprises the same composition as the sealant material. The method of claim 5 , wherein the insulating material and the encapsulant material both comprise silicon dioxide.

7. The method of claim 4, wherein the insulating material comprises a different composition than the encapsulant material.

8. The method of claim 7, wherein the insulating material comprises silicon nitride, and wherein the encapsulant material comprises silicon dioxide.

9. The method of claim 1 wherein said sputtering occurs simultaneously with some of said depositing.

10. The method of claim 9, wherein the depositing and the sputtering are performed in a reaction chamber in the presence of a chemical comprising SiCl4 and one or more of O2, O3, H2O2.

11. The method of claim 1 wherein said sputtering occurs substantially entirely after said depositing.

12. The method of claim 1, wherein the agglomerates include one or more elements selected from Group 14 of the periodic table.

13. The method of claim 1, wherein the mass comprises silicon.

14. The method of claim 1, wherein the mass comprises at least one element selected from Group 14 of the periodic table; and wherein the depositing utilizes a precursor comprising one of a halide or a hydride of the at least one element.

15. The method of claim 14, wherein the agglomerates include silicon combined with one or both of chlorine and hydrogen. The method of claim 15 , wherein the sealant material comprises silicon dioxide. The method of claim 16 , wherein the sputtering is performed under oxidizing conditions.

18. The method of claim 17, wherein the sputtering is performed using one or both of ozone and hydrogen peroxide.

19. A method of forming an integrated assembly, comprising: forming a structure to include, in cross section, a conductive structure having a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface; The construction further includes an insulating material above the top surface and includes a track along the sidewall surface; Each of the rails includes a sacrificial material along a panel of non-sacrificial material; removing the sacrificial material to leave an opening between the sidewall surface of the non-sacrificial material and the face plate; forming a mass over a top portion of the insulating material and along an upper section of a side of the insulating material; as well as Particles are sputtered from the mass to form a sealant material that extends across the opening and captures voids within the opening.

20. The method of claim 19, further comprising treating the sealant material to fill any pinholes present in the sealant material.

21. The method of claim 20, wherein the insulating material is a first insulating material, and wherein the processing comprises depositing a layer of a second insulating material over the encapsulant material.

22. The method of claim 19, wherein the agglomerates include one or more elements selected from Group 14 of the periodic table.

23. The method of claim 19, wherein the mass comprises silicon.

24. The method of claim 19, wherein the sealant material comprises silicon dioxide.

25. The method of claim 19, wherein the sputtering is performed under oxidizing conditions.

26. A method of forming an integrated assembly, comprising: forming a configuration to include, along a cross-section, a pair of digit lines separated from each other by an intermediate region; Each of the digit lines has a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface; the construction includes an insulating structure above the top surface and includes tracks along the sidewall surfaces; The track includes a sacrificial material sandwiched between a pair of panels; the construction includes a conductive interconnect within the intermediate region; the insulating structure includes a first insulating material; removing the sacrificial material to leave an opening between the panels; forming a mass over a top portion of the insulating material and along an upper section of a side of the insulating material; sputtering particles from the mass to form a sealant material that extends across the opening and covers voids within the opening; forming a second insulating material across the insulating structure, across the encapsulant material, and across the conductive interconnect; removing a portion of the second insulating material to expose an area of ​​the conductive interconnect; as well as The exposed region of the conductive interconnect is coupled to a charge storage device.

27. The method of claim 26, further comprising treating the sealant material to fill any pinholes present in the sealant material.

28. The method of claim 27, wherein the processing comprises depositing a third layer of insulating material over the encapsulant material.

29. The method of claim 28, wherein the third insulating material comprises the same composition as the sealant material.

30. The method of claim 28, wherein the third insulating material comprises a different composition than the encapsulant material.

31. The method of claim 26, wherein the agglomerates include one or more elements selected from Group 14 of the periodic table.

32. The method of claim 26, wherein the sealant material comprises silicon dioxide.

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