A method for manufacturing a deep trench isolation grid structure

Abstract

The present invention provides a CMOS image sensor and its pixel structure, as well as a manufacturing method for a deep trench isolation grid structure in the pixel structure. The manufacturing method of the above-mentioned deep trench isolation grid structure specifically includes: providing a stacked layer, the top of the above-mentioned stacked layer is a silicon epitaxial layer; forming a plurality of deep trenches in a grid shape in the above-mentioned silicon epitaxial layer; depositing a first isolation layer and a second isolation layer on the sidewall and bottom of each deep trench in sequence; and depositing a third isolation layer filling each deep trench on the upper surface of the above-mentioned second isolation layer, so that the first isolation layer, the second isolation layer and the third isolation layer in the plurality of deep trenches constitute a multiple isolation grid. The deep trench isolation grid structure formed by the manufacturing method provided by the present invention can effectively reduce the electronic crosstalk between adjacent grids, thereby effectively improving the device performance of the CMOS image sensor and its pixel structure containing the above-mentioned deep trench isolation grid structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices and manufacturing thereof, and in particular to a CMOS image sensor and a pixel structure thereof, and a manufacturing method of a deep trench isolation grid structure therein. Background Art

[0002] In the field of semiconductor technology, the stacked CMOS image sensor (Ultra-Thin Stacked CMOS Image Sensor, UTS CIS) is made of separately manufactured logic wafers and pixel wafers bonded together through a bonding process. Since the logic wafer and the pixel wafer are manufactured separately, the manufacturing process is flexible and low-cost. Another advantage of this process is that the logic device and the pixel device do not affect each other, and the performance can be maximized to a higher degree. The stacked CIS usually includes two silicon wafers, a logic wafer, whose main function is to provide the CIS's logic function circuits, timing circuits, storage units, etc. The other pixel wafer, whose main function is to provide the CIS's pixel units, photodiodes, etc.

[0003] In the process of preparing pixel wafers, deep trench isolation (DTI) grid filling is a key process. Traditional existing processes use high dielectric constant films and silicon oxide to fill the formed deep trenches to form deep trench isolation between adjacent photosensitive elements. Since the pixel wafer contains multiple photosensitive elements in an array, the formed deep trench isolation presents a grid shape.

[0004] In the prior art, the high dielectric constant film and silicon oxide can play an isolating role because the interface charges captured by the high dielectric constant film can form a potential barrier, thereby blocking the electronic crosstalk between adjacent grids. It is understandable that the strength of the electronic crosstalk directly affects the pixel performance of the image sensor, and the ever-shrinking size of semiconductor devices in the semiconductor field exacerbates the electronic crosstalk.

[0005] However, in the semiconductor field, the pursuit of the continuous reduction of the size of semiconductor devices is still in progress. The development of semiconductor devices roughly follows Moore's Law, that is, the number of transistors in dense integrated circuits doubles approximately every two years. The current semiconductor process is moving towards 20 nanometers. Here is just a reference, a silicon atom is about 0.2 nanometers, which means that the distance between two independent components manufactured by the 20-nanometer process is only one hundred silicon atoms.

[0006] The aggravation of electronic crosstalk caused by the continuous reduction in the size of semiconductor devices can no longer be alleviated by forming a high dielectric constant film and deep trench isolation of silicon oxide in the existing technology.

[0007] In view of this, there is an urgent need in the art for a deep trench isolation grid and a manufacturing method thereof, which can further reduce the electronic crosstalk between the deep trench isolation grids, thereby providing a basis for improving the device performance of pixel units and CMOS image sensors. Summary of the invention

[0008] A brief summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceived aspects, and is neither intended to identify the key or critical elements of all aspects nor to define the scope of any or all aspects. Its only purpose is to give some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that will be given later.

[0009] In order to solve the problem of electronic crosstalk between photosensitive elements of a CMOS image sensor caused by the ever-shrinking size of semiconductor devices in the prior art, one aspect of the present invention provides a method for manufacturing a deep trench isolation grid structure, specifically comprising:

[0010] Providing a stacked layer, wherein the top of the stacked layer is a silicon epitaxial layer;

[0011] forming a plurality of deep trenches in a grid shape in the silicon epitaxial layer;

[0012] sequentially depositing a first isolation layer and a second isolation layer on the sidewall and bottom of each deep trench; and

[0013] A third isolation layer filling each deep trench is deposited on the upper surface of the second isolation layer, so that the first isolation layer, the second isolation layer and the third isolation layer in the plurality of deep trenches form a multiple isolation grid.

[0014] In an embodiment of the above manufacturing method, optionally, sequentially depositing the above first isolation layer and the above second isolation layer further comprises:

[0015] Simultaneously depositing a first isolation layer and a second isolation layer in sequence on the upper surface of the silicon epitaxial layer;

[0016] Depositing the third isolation layer further comprises:

[0017] Depositing a third isolation material layer filling each deep trench and covering the second isolation layer formed on the upper surface of the silicon epitaxial layer; and

[0018] The third isolation material layer is etched back to at least retain the third isolation material layer inside each deep trench as the third isolation layer.

[0019] In one embodiment of the above manufacturing method, optionally, the above etching back is bias etching, wherein

[0020] The third isolation material layer remaining in the opening area of ​​the deep groove at the edge of the grid is the third isolation layer.

[0021] In one embodiment of the above manufacturing method, optionally, the above manufacturing method further includes:

[0022] Before the step of forming the plurality of deep trenches, an alignment mark for the offset etching is formed on the upper surface of the silicon epitaxial layer; wherein

[0023] The etching back is performed based on the alignment mark.

[0024] In one embodiment of the above manufacturing method, optionally, the third isolation layer is a metal layer;

[0025] The third isolation layer is externally connected to a voltage via the third isolation material layer in the opening area of ​​the deep trench at the edge of the grid.

[0026] In an embodiment of the manufacturing method, optionally, the second isolation layer is used as an etch stop layer in the etching back.

[0027] In an embodiment of the above manufacturing method, optionally, the thickness of the third isolation dielectric layer covering the second isolation layer formed on the upper surface of the silicon epitaxial layer is 200-300 angstroms.

[0028] In an embodiment of the above manufacturing method, optionally, the third isolation layer is a metal layer; the above manufacturing method further includes:

[0029] A metal lead layer connected to the third isolation layer is formed above the stacked layer so that the third isolation layer is externally connected to a voltage.

[0030] In one embodiment of the above manufacturing method, optionally, the third isolation layer is a metal aluminum layer; and depositing the third isolation layer further comprises:

[0031] Depositing a metal pad layer made of titanium nitride on the upper surface of the second isolation layer; and

[0032] The metal aluminum layer is deposited on the upper surface of the metal pad layer.

[0033] In an embodiment of the above manufacturing method, optionally, the first isolation layer is a high dielectric constant film.

[0034] In one embodiment of the above manufacturing method, optionally, the second isolation layer is a silicon oxide film formed by plasma enhanced atomic layer deposition.

[0035] In one embodiment of the above manufacturing method, optionally, the thickness of the above silicon oxide film is 250-270 angstroms.

[0036] In an embodiment of the above manufacturing method, optionally, the deep groove is rectangular or inverted trapezoidal.

[0037] In an embodiment of the above manufacturing method, optionally, the above stacked layer further includes a photodiode layer located below the above silicon epitaxial layer.

[0038] Another aspect of the present invention further provides a pixel structure of a CMOS image sensor, the pixel structure comprising a photodiode and a deep trench isolation grid structure located above the photodiode, wherein the deep trench isolation grid structure is manufactured by any one of the embodiments of the manufacturing method described above.

[0039] Another aspect of the present invention further provides a CMOS image sensor, wherein the CMOS image sensor comprises the pixel structure of the CMOS image sensor described above.

[0040] The deep trench isolation grid structure formed by the manufacturing method provided by the present invention includes multiple isolation layers, so that the electronic crosstalk between adjacent photosensitive elements can be more effectively suppressed. This provides the possibility of effectively improving the device performance of the CMOS image sensor and its pixel unit including the above-mentioned deep trench isolation grid structure. In addition, the manufacturing method of the deep trench isolation grid structure provided by one aspect of the present invention has a simple process flow, which is compatible with the existing process flow, and thus has operability and universality. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above features and advantages of the present invention can be better understood after reading the detailed description of the embodiments of the present disclosure in conjunction with the following drawings. In the drawings, the components are not necessarily drawn to scale, and components with similar related properties or features may have the same or similar reference numerals.

[0042] Figure 1 , 2 , 3A, 3B, and 4 illustrate the manufacturing process flow of forming a deep trench isolation grid in the prior art. Figure 3B Zoomed in Figure 3A Deep trench isolation grid structure in.

[0043] Figure 5 The flowchart of the method for manufacturing the deep trench isolation grid provided by the present invention is shown.

[0044] Figure 6 , 7 , 8A, 8B, 9A, 9B and Fig.10 The method for manufacturing the deep trench isolation grid provided by the present invention is illustrated. Figure 8B Zoomed in Fig. 8A The deep trench isolation grid structure in Fig. 9B Zoomed in Fig.9A Deep trench isolation grid structure in.

[0045] Reference numerals

[0046] Stacking layer 100

[0047] PAD Area 110

[0048] UTS Region 120

[0049] Metal shielding area 130

[0050] Pixel area 140

[0051] Silicon epitaxial layer 200

[0052] Deep Groove 210

[0053] Deep trench isolation grid structure 300, 400

[0054] High dielectric constant film 310, 410

[0055] Silicon oxide 320, 420

[0056] Oxide buffer layers 311, 411

[0057] Metal aluminum layer 430, 430'

[0058] Metal pad 431

[0059] Metal lead layer 500 DETAILED DESCRIPTION

[0060] The present invention relates to semiconductor processes and devices. More specifically, an embodiment of the present invention provides a method for manufacturing a deep trench isolation grid structure. The deep trench isolation grid structure formed by the manufacturing method provided by the embodiment of the present invention can effectively reduce the electronic crosstalk between adjacent sensory elements, providing a basis for improving the device performance of a CMOS image sensor and its pixel structure. The present invention also provides other embodiments, including a CMOS image sensor and its pixel structure.

[0061] The following description is given to enable those skilled in the art to implement and use the invention and incorporate it into a specific application context. Various modifications, as well as various uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein are applicable to a wide range of embodiments. Thus, the present invention is not limited to the embodiments given herein, but should be granted the broadest scope consistent with the principles and novel features disclosed herein.

[0062] In the following detailed description, many specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the practice of the present invention need not be limited to these specific details. In other words, known structures and devices are shown in block diagram form without detailed display to avoid obscuring the present invention.

[0063] The reader is reminded of all documents and literature filed simultaneously with this specification and open to public inspection, and the contents of all such documents and literature are incorporated herein by reference. Unless otherwise directly stated, all features disclosed in this specification (including any attached claims, abstracts and drawings) can be replaced by alternative features for achieving the same, equivalent or similar purposes. Therefore, unless otherwise explicitly stated, each feature disclosed is only an example of a group of equivalent or similar features.

[0064] Note that, where used, the symbols left, right, front, back, top, bottom, positive, negative, clockwise and counterclockwise are used only for convenience and do not imply any specific fixed direction. In fact, they are used to reflect the relative position and / or direction between the various parts of the object.

[0065] As used herein, the terms "over," "under," "between," and "on" refer to the relative position of a layer relative to other layers. Likewise, for example, a layer deposited or placed above or below another layer may be directly in contact with the other layer or may have one or more intervening layers. Additionally, a layer deposited or placed between layers may be directly in contact with the layers or may have one or more intervening layers. In contrast, a first layer "above" a second layer is in contact with the second layer. Additionally, the relative position of one layer relative to other layers is provided (assuming that deposition, modification, and removal of thin films are performed relative to a starting substrate without regard to the absolute orientation of the substrate).

[0066] As mentioned above, deep trench isolation grid filling is a key process in the process of preparing pixel wafers. Figure 1 , 2 , 3A, 3B, and 4 illustrate the manufacturing process flow of forming a deep trench isolation grid in the prior art. First, Figure 1 As shown, the logic wafer and the pixel wafer have been bonded together through a bonding process. Figure 1 The horizontal dashed line in FIG. 1 illustrates the bonding interface. After bonding, a stacked layer 100 including a logic wafer and a pixel wafer is provided. Figure 1In the structure shown, a silicon epitaxial layer 200 of a predetermined thickness has been formed on the top of the stacked layer. Those skilled in the art can determine the thickness of the silicon epitaxial layer 200 as needed, and the thickness of the silicon epitaxial layer 200 should not unduly limit the protection scope of the present invention.

[0067] Figure 1 The stacked layer structure of different areas of the CMOS image sensor is shown in FIG. The CMOS image sensor includes at least a PAD area 110, a UTS area 120, a metal shielding area 130 and a pixel area 140. The PAD area 110 is used for later testing, the UTS area 120 is used to connect the pixel wafer to the logic wafer, the metal shielding area 130 is used for grounding, and the pixel area 140 is the main part of a pixel wafer, and its main function is to provide mobile phone light. It can be understood that although in Figure 1 In the structure shown, these areas are arranged from left to right, but in actual applications, these four areas can be set in different areas of the wafer as needed, and do not necessarily exist as shown in FIG. Figure 1 The cross-sectional structure is shown.

[0068] Then, if Figure 2 As shown, a deep trench 210 is formed in the silicon epitaxial layer 200 so as to form a deep trench isolation, i.e., DTI, Deep Trench Isolation, in the deep trench 210. The concept of deep trench isolation is relative to the concept of shallow trench isolation STI, Shallow Trench Isolation. Shallow trench isolation is usually only formed on the surface of the dielectric layer, while the deep trench is formed deeper inside the dielectric layer. In one embodiment, the thickness of the above-mentioned silicon epitaxial layer 200 is 3um, and the depth of the deep trench 210 can reach 1.5um. It can be understood that the method for forming the deep trench 210 can be implemented according to existing or future methods, and the method for forming the deep trench 210 should not unduly limit the scope of protection of the present invention.

[0069] In addition, as described above, since the pixel wafer includes a plurality of photosensitive elements in an array, the plurality of deep trenches formed appear to be in a grid shape from a top view.

[0070] Then, if Figure 3A As shown, a high dielectric constant film layer 310 and a silicon oxide 320 are deposited on the upper surface of the silicon epitaxial layer 200 and in the deep trench 210 to form a deep trench isolation grid structure 300 in the deep trench 210 . Figure 3B The deep trench isolation grid structure 300 in the deep trench 210 region is magnified. Figure 3BAs shown, further, an oxide buffer layer 311 is included between the deep trench 210 and the high dielectric constant film 310. In addition, in the prior art, the silicon oxide 320 is usually formed by atomic layer deposition.

[0071] Then, if Figure 4 As shown, after the deep trench isolation grid structure 300 is formed, various metal wiring layers 500 are formed on the silicon epitaxial layer 200 according to actual needs to realize various functions of the CMOS image sensor.

[0072] As described above, the deep trench isolation grid structure 300 including the high dielectric constant film layer 310 and the silicon oxide 320 can play an isolation role mainly because the interface charges captured by the high dielectric constant film can form a potential barrier, thereby blocking the electronic crosstalk between adjacent photosensitive elements. It can be understood that such an isolation method is a passive barrier formation method. In the case where the distance between the grids is continuously reduced, resulting in the continuous increase of the electronic crosstalk between the grids, the effect of relying solely on the passive formation of a potential barrier to block the electronic crosstalk between adjacent photosensitive elements is not excellent. It is necessary to propose a method that can more effectively block the electronic crosstalk between adjacent photosensitive elements.

[0073] Based on this, the present invention provides a method for manufacturing a deep trench isolation grid structure, which can effectively solve the problem of electronic crosstalk between adjacent photosensitive elements when the size of semiconductor devices continues to shrink. Figure 5 To understand the manufacturing method of the deep trench isolation grid structure provided by the present invention. Figure 5 As shown, the manufacturing method of the deep trench isolation grid structure provided by the present invention includes step S100: providing a stacking layer, the top of the stacking layer is a silicon epitaxial layer; step S200: forming a plurality of deep trenches in a grid shape in the silicon epitaxial layer; step S300: depositing a first isolation layer and a second isolation layer in sequence on the sidewall and bottom of each deep trench; and step S400: depositing a third isolation layer filling each deep trench on the upper surface of the second isolation layer, so that the first isolation layer, the second isolation layer and the third isolation layer in the plurality of deep trenches constitute a multiple isolation grid.

[0074] Please combine the following Figure 6 , 7 , 8A, 8B, 9A, 9B and Fig.10 To better understand the implementation method of the manufacturing method of the deep trench isolation grid structure provided by the present invention.

[0075] first, Figure 6Schematic diagram showing step S100: providing a stacked layer 100, wherein the top of the stacked layer is a silicon epitaxial layer 200. As described above, the stacked layer 100 includes a logic wafer and a pixel wafer bonded by a bonding process. Figure 6 The horizontal dotted line in the figure shows the bonding interface. The pixel wafer is above the dotted line, and the logic wafer is below the dotted line.

[0076] In such Figure 6 In the structure shown, a silicon epitaxial layer 200 of a predetermined thickness has been formed on the top of the stacked layer. Those skilled in the art can determine the thickness of the silicon epitaxial layer 200 as needed, and the thickness of the silicon epitaxial layer 200 should not unduly limit the protection scope of the present invention.

[0077] Figure 6 The stacked layer structure of different areas of the CMOS image sensor is shown in FIG. The CMOS image sensor includes at least a PAD area 110, a UTS area 120, a metal shielding area 130 and a pixel area 140. The PAD area 110 is used for later testing, the UTS area 120 is used to connect the pixel wafer to the logic wafer, the metal shielding area 130 is used for grounding, and the pixel area 140 is the main part of a pixel wafer, and its main function is to provide mobile phone light. It can be understood that although in Figure 6 In the structure shown, these areas are arranged from left to right, but in actual applications, these four areas can be set in different areas of the wafer as needed, and do not necessarily exist as shown in FIG. Figure 6 The cross-sectional structure is shown.

[0078] The deep trench isolation grid structure formed by the manufacturing method provided by the present invention is formed in the above-mentioned silicon epitaxial layer 200. In one embodiment, the deep trench isolation grid structure provided by the present invention is applied in a back-illuminated image sensor. That is, the stacked layer 100 also includes a photodiode layer formed below the silicon epitaxial layer.

[0079] Afterwards, please refer to Figure 7 To understand step S200, Figure 7As shown, a deep trench 210 is formed in the silicon epitaxial layer 200 so as to form a deep trench isolation, i.e. DTI, Deep Trench Isolation, in the deep trench 210. The concept of deep trench isolation is relative to the concept of shallow trench isolation STI, Shallow Trench Isolation. Shallow trench isolation is usually only formed on the surface of the dielectric layer, while the deep trench is formed deeper inside the dielectric layer. In one embodiment, the thickness of the above-mentioned silicon epitaxial layer 200 is 3um, and the depth of the deep trench 210 can reach 1.5um. In the manufacturing method provided by the present invention, the deep trench formed has a cross-sectional shape of a rectangle or an inverted trapezoid, so that an isolation grid structure with the largest possible volume can be formed to ensure effective elimination of electronic crosstalk between adjacent photosensitive elements. It can be understood that the method for forming the deep trench 210 can be implemented according to existing or future methods, and the method for forming the deep trench 210 should not unduly limit the scope of protection of the present invention.

[0080] In addition, as described above, since the pixel wafer includes a plurality of photosensitive elements in an array, the plurality of deep trenches formed appear to be in a grid shape from a top view.

[0081] In one embodiment, before forming the deep trench 210 in the silicon epitaxial layer 200, the manufacturing method provided by the present invention further includes: adding an etching alignment mask, and first forming an alignment mark for subsequent metal bias etching (Bias ETCH) on the upper surface of the silicon epitaxial layer through photolithography and etching processes.

[0082] Since the stacking of the photoresist layer for subsequent metal deviation etching requires an alignment point, and since the top of the stacked layer currently processed by the present invention is actually the back of the wafer, that is, the silicon substrate part, there is no alignment mark on the back of the wafer. Therefore, it is necessary to form an alignment mark before the photo layer, and the photoresist thickness requirement meets the etching requirement to have enough residual amount.

[0083] Then, please combine Fig. 8A , 8B , 9A, 9B to understand step S300 and step S400. First, please refer to Fig. 8A ,like Fig. 8A As shown, a high dielectric constant film layer 410 , a silicon oxide layer 420 , and a metal aluminum layer 430 are deposited on the upper surface of the silicon epitaxial layer 200 and in the deep trench 210 to form a deep trench isolation grid structure 400 in the deep trench 210 . Figure 8B The deep trench isolation grid structure 400 in the deep trench 210 region is magnified. Figure 8BAs shown, further, an oxide buffer layer 411 is included between the deep trench 210 and the high dielectric constant film 410 , so that the high dielectric constant film 410 can be better formed on the upper surface of the silicon epitaxial layer 200 .

[0084] like Figure 8B As shown, in order to better form the metal aluminum layer 430, in a preferred embodiment provided by the present invention, before forming the metal aluminum layer 430, it also includes forming a metal pad layer 431 made of tantalum nitride TaN material, so that the metal aluminum layer 430 can be formed more firmly and fitly in the deep groove 210 through the metal pad layer 431.

[0085] from Figure 8B It can be seen that the oxide buffer layer 411, the high dielectric constant film 410, the silicon oxide layer 420 and the metal pad layer 431 are all thin film layers, that is, formed on the sidewalls and bottom of the deep trench 210, but do not fill the deep trench 210. The metal aluminum layer 430 further fills the entire deep trench 210 and also covers the entire silicon epitaxial layer.

[0086] In the above-mentioned embodiment, the high dielectric constant film 410 is formed by diffusion furnace and physical vapor deposition. The silicon oxide layer 420 is formed by plasma enhanced atomic layer deposition (PEALD), that is, chemical vapor deposition. The metal pad layer 431 and the metal aluminum layer 430 are formed by physical vapor deposition.

[0087] In the above embodiment, the thickness of the formed silicon oxide layer 420 is in the range of 260±10 angstroms, i.e., between 250-270 angstroms. The thickness of this portion of the silicon oxide layer 420 needs to ensure that it can be used as an etching stop layer during the subsequent metal layer etching to protect the high dielectric constant film layer 410 below the silicon oxide layer 420. At the same time, the thickness of the silicon oxide layer 420 before etching cannot be too thick, otherwise the deep trench 210 will be filled in advance, resulting in the inability to smoothly fill the subsequent metal layer.

[0088] The thickness range of the formed metal pad layer 431 made of tantalum nitride can be determined according to existing or future process standards, and the limitation on the thickness of the metal pad layer 431 should not unduly limit the protection scope of the present invention.

[0089] The thickness of the metal aluminum layer 430 covering the silicon epitaxial layer is in the range of 200-300 angstroms. It is understandable that in order to ensure that the metal aluminum layer 430 can completely fill the deep trench 210, it is necessary to keep a margin for the deposition of the metal aluminum layer 430. However, since the metal aluminum layer formed on the silicon epitaxial layer will be etched away later, it is not desirable that the thickness of the metal aluminum layer covering the silicon epitaxial layer is too thick, so as to reduce the amount of etching of the metal aluminum layer on the substrate later.

[0090] In the deep trench isolation grid structure 400 provided by the present invention, it includes a multiple isolation structure of a high dielectric constant film 410, a silicon oxide layer 420 and a metal aluminum layer 430. For the multiple isolation grid structure provided by the present invention, it can not only block the crosstalk between adjacent grids through the potential barrier formed by the passively captured interface charges of the high dielectric constant film and the silicon oxide layer, but also, due to the metal properties of the metal aluminum layer 430, the metal aluminum layer 430 can be actively grounded, and a physical negative voltage can be applied during the later test to achieve a balanced potential barrier between adjacent grids, thereby curbing the crosstalk of electrons in the photodiode. In other words, the multiple isolation structure of the present invention can further enhance the effect of curbing the crosstalk of electrons in the photodiode by actively and passively forming a balanced potential barrier.

[0091] As for the metal aluminum layer 430, it is desired to be formed inside the deep trench 210. Therefore, step S400 further includes a step of etching back the metal aluminum layer covering the silicon epitaxial layer. In the embodiment provided by the present invention, since the metal aluminum layer 430 needs to be grounded and then connected to an external voltage, it is also necessary to form the lead pins of the metal aluminum layer 430.

[0092] In order to simplify the process flow, in the above-mentioned step of etching back the metal aluminum layer, the metal aluminum bias etching method is used to retain the metal aluminum layer in the deep groove opening area at the edge of the grid without being etched, so that this part of the retained metal aluminum layer can be directly used as a lead pin, so that it can be directly connected to the metal lead layer later.

[0093] Fig.9A A schematic diagram is shown after the metal aluminum layer 430 is etched back. Fig. 9B The deep groove area, especially the film structure of the deep groove area at the edge of the grid, is magnified. It can be seen that after the biased etching, the metal aluminum layer 430' located at the deep groove opening area at the edge of the grid, which is higher than the silicon epitaxial layer, is retained, thereby directly forming a pin that can be connected to the back-end metal lead layer, and no additional process is required to form a connector that connects the metal aluminum layer to the back-end metal lead layer. It can be understood that the alignment mark formed before forming the deep groove 210 described in the previous text is used to achieve the biased etching of the metal aluminum layer in this step.

[0094] Because the metal aluminum layer covering the silicon epitaxial layer in the deep groove opening area at the edge of the grid is directly used as a pin connected to the rear-end metal lead layer, it is necessary to form a metal aluminum layer with a thickness ranging from 200 to 300 angstroms in the front-end step of forming the metal aluminum layer, which can also ensure that it can be used as a pin.

[0095] For the metal aluminum layer in other areas, the silicon oxide layer 420 is used as an etching stop layer so that the excess metal aluminum layer can be accurately removed. At the same time, due to the presence of the silicon oxide layer 420 as an etching stop layer, the high dielectric constant film layer 410 below the silicon oxide layer 420 can be well protected, thereby ensuring that the high dielectric constant film layer 410 can achieve the function of capturing interface charges to form a potential barrier to block the electronic crosstalk between adjacent grids.

[0096] Because the silicon oxide layer 420 needs to be used as an etching stop layer and can serve as a protective layer for the high dielectric constant film layer 410, it is necessary to form a silicon oxide layer with a thickness range of 260±10 angstroms in the step of forming the silicon oxide layer in the front process, so as to ensure that the etching back of the metal aluminum layer can stop on the silicon oxide layer and can have sufficient thickness to serve as a protective layer for the high dielectric constant film layer 410.

[0097] Then, if Fig.10 As shown, in the back-end process, a metal wiring layer 500 is formed on the silicon epitaxial layer so that each semiconductor element in the stacked layer 100 can realize its own function. It can be understood that since the deep trench isolation grid structure 300 in the prior art does not include a metal layer, the metal wiring layer 500 in the prior art as shown in FIG. 3 does not need to be connected to the deep trench isolation grid structure 300. The deep trench isolation grid structure 400 formed by the manufacturing method provided in the present application includes a metal aluminum layer 430, so it can be as shown in FIG. Fig.10 As shown, the metal lead layer 500 is connected to the entire metal aluminum layer 430 through the metal aluminum layer 430' serving as a lead, so that the metal aluminum layer 430 is grounded, and a negative voltage is applied in a subsequent process, so that adjacent grids can form a stable potential difference under the applied voltage to block electronic crosstalk.

[0098] So far, the manufacturing method of the deep trench isolation grid provided by one aspect of the present invention has been described. The deep trench isolation grid structure formed by the manufacturing method provided by one aspect of the present invention has multiple isolation layers, and the multiple isolation layers contain metal layers to which voltage can be applied, so that potential barriers can be actively formed to block electronic crosstalk. In addition, the manufacturing method provided by the present invention can directly form metal layers in the multiple isolation layers that can be connected to the back-end metal lead layer through a simple process flow, thereby not increasing the complexity of the process.

[0099] The present invention also provides a pixel structure of a CMOS image sensor, the pixel structure comprising a photodiode and a deep trench isolation grid structure located above the photodiode, wherein the deep trench isolation grid structure is manufactured by any one of the embodiments of the manufacturing method described above.

[0100] Another aspect of the present invention further provides a CMOS image sensor, wherein the CMOS image sensor comprises the pixel structure of the CMOS image sensor described above.

[0101] The CMOS image sensor and its pixel structure provided by another aspect of the present invention have a deep trench isolation grid structure formed according to one aspect of the present invention. Therefore, the electronic crosstalk between its photosensitive elements is effectively reduced, thereby effectively improving the device performance of the CMOS image sensor and its pixel structure.

[0102] Thus, embodiments of methods for manufacturing deep trench isolation grid structures and device structures formed therefrom have been described. Although the present disclosure has been described with respect to specific exemplary embodiments, it will be apparent that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the present disclosure. Accordingly, the specification and drawings should be regarded in an illustrative rather than a restrictive sense.

[0103] It should be understood that this specification will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, it can be seen that various features are combined together in a single embodiment for the purpose of streamlining the present disclosure. This method of the present disclosure should not be interpreted as reflecting the purpose of the claimed embodiment requiring more features than the features explicitly listed in each claim. On the contrary, as reflected in the attached claims, the creative subject matter lies in less than all the features of a single disclosed embodiment. Therefore, the attached claims are hereby incorporated into the detailed description, wherein each claim independently serves as a separate embodiment.

[0104] Reference to an embodiment or embodiments in this description means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of a circuit or method. The appearances of the phrase an embodiment in various places in the specification are not necessarily all referring to the same embodiment.

Claims

1. A method for manufacturing a deep trench isolation grid structure, characterized in that: include: Providing a stacked layer, the top of the stacked layer being a silicon epitaxial layer; forming a plurality of deep trenches in a grid shape in the silicon epitaxial layer; Depositing a first isolation layer and a second isolation layer in sequence on the sidewall and the bottom of each deep trench; as well as Depositing a third isolation layer filling each deep trench on the upper surface of the second isolation layer, so that the first isolation layer, the second isolation layer and the third isolation layer in the plurality of deep trenches form a multiple isolation grid; The sequentially depositing the first isolation layer and the second isolation layer further comprises: Simultaneously depositing a first isolation layer and a second isolation layer in sequence on the upper surface of the silicon epitaxial layer; Depositing the third isolation layer further comprises: Depositing a third isolation material layer filling each deep trench and covering the second isolation layer formed on the upper surface of the silicon epitaxial layer; and Carving back the third isolation material layer to at least retain the third isolation material layer inside each deep trench as the third isolation layer; The back etching is bias etching, wherein A third isolation material layer is also reserved in the opening area of ​​the deep groove at the edge of the grid as the third isolation layer; The manufacturing method further comprises: Before the step of forming the plurality of deep trenches, an alignment mark for the offset etching is formed on the upper surface of the silicon epitaxial layer; wherein performing the etching back based on the alignment mark; The third isolation layer is a metal layer, wherein the third isolation layer is externally connected to a voltage via a third isolation material layer in an opening area of ​​a deep groove at an edge of the grid that is retained.

2. The manufacturing method according to claim 1, characterized in that The second isolation layer is used as an etching stop layer in the etching back.

3. The manufacturing method according to claim 1, characterized in that: The thickness of the third isolation dielectric layer covering the second isolation layer formed on the upper surface of the silicon epitaxial layer is 200-300 angstroms.

4. The manufacturing method according to claim 1, characterized in that: The third isolation layer is a metal layer; the manufacturing method further includes: A metal lead layer connected to the third isolation layer is formed above the stacked layer so that the third isolation layer is externally connected to a voltage.

5. The manufacturing method according to claim 4, characterized in that: The third isolation layer is a metal aluminum layer; depositing the third isolation layer further comprises: Depositing a metal pad layer made of titanium nitride on the upper surface of the second isolation layer; and The metal aluminum layer is deposited on the upper surface of the metal pad layer.

6. The manufacturing method according to claim 1, characterized in that: The first isolation layer is a high dielectric constant film.

7. The manufacturing method according to claim 1, characterized in that: The second isolation layer is a silicon oxide film formed by plasma enhanced atomic layer deposition.

8. The manufacturing method according to claim 7, characterized in that: The thickness of the silicon oxide film is 250-270 angstroms.

9. The manufacturing method according to claim 1, characterized in that: The deep groove is rectangular or inverted trapezoidal.

10. The manufacturing method according to claim 1, characterized in that: The stacked layers further include a photodiode layer located below the silicon epitaxial layer.

11. A pixel structure of a CMOS image sensor, the pixel structure comprising a photodiode and a deep trench isolation grid structure located above the photodiode, characterized in that: The deep trench isolation grid structure is manufactured by the manufacturing method described in any one of claims 1-10.

12. A CMOS image sensor, characterized in that: The CMOS image sensor comprises the pixel structure of the CMOS image sensor according to claim 11.

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