Semiconductor structure

Abstract

The present invention provides a semiconductor structure, comprising: a substrate having an active region and an isolation region, an insulating layer located on the substrate, a seed layer located on the insulating layer, a compound semiconductor layer located on the seed layer, a gate structure located on the compound semiconductor layer and in the active region, an isolation structure located on the substrate and in the isolation region, a pair of via holes located in the isolation region and on both sides of the gate structure, and a source structure and a drain structure located on the substrate and on both sides of the gate structure. The pair of via holes passes through the isolation structure and contacts the seed layer. The source structure and the drain structure are electrically connected to the seed layer respectively through the pair of via holes. The semiconductor structure provided by the present invention can redistribute the electric field and increase the breakdown voltage to allow the semiconductor device to be applied to high voltage operation.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure having a pair of vias contacting a seed layer. Background Art

[0002] GaN-based semiconductor materials have many excellent material properties, such as high heat resistance, wide band-gap, and high electron saturation rate. Therefore, GaN-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, GaN-based semiconductor materials have been widely used in light emitting diode (LED) components, high-frequency components, such as high electron mobility transistor (HEMT) with heterojunction structure.

[0003] However, in the operation of high electron mobility transistor (HEMT) devices, the epitaxial layer located at the bottom of the device structure has many impurities with negative charges due to its own material characteristics. At this time, if a high voltage is applied, these negative charges will be attracted toward the upper layer device, affecting the operation of the upper layer device. In order to solve this problem in the prior art, the silicon substrate under the epitaxial layer is usually grounded to discharge the negative charges of the impurities. However, this method cannot be applied to various substrates.

[0004] With the development of GaN-based semiconductor materials, these semiconductor devices using GaN-based semiconductor materials are applied in more severe working environments, such as higher frequency, higher temperature or higher voltage. Therefore, semiconductor devices using GaN-based semiconductor materials still need to be further improved to overcome the challenges they face. Summary of the invention

[0005] Some embodiments of the present invention provide a semiconductor structure, comprising: a substrate having an active region and an isolation region, an insulating layer located on the substrate, a seed layer located on the insulating layer, a compound semiconductor layer located on the seed layer, a gate structure located on the compound semiconductor layer and in the active region, an isolation structure located on the substrate and in the isolation region, a pair of via holes located in the isolation region and on both sides of the gate structure, and a source structure and a drain structure located on the substrate and on both sides of the gate structure. The pair of via holes passes through the isolation structure and contacts the seed layer. The source structure and the drain structure are electrically connected to the seed layer through the pair of via holes, respectively.

[0006] Some embodiments of the present invention provide a semiconductor structure, comprising: a ceramic substrate having an active region and an isolation region, an insulating layer on the substrate, a seed layer on the insulating layer, a compound semiconductor layer on the seed layer, a gate structure on the compound semiconductor layer and in the active region, and a source structure and a drain structure on the substrate and on both sides of the gate structure. The source structure and the drain structure are electrically connected to the seed layer, respectively.

[0007] The semiconductor structure provided by the embodiment of the present invention electrically connects the source structure and the drain structure in the semiconductor structure to the seed layer on the substrate through a pair of via holes located in the isolation region of the substrate. By configuring the via holes, a voltage difference (i.e., the voltage difference between the source and the drain) can be generated inside the seed layer so that the electric field lines extend to the film layer (e.g., the insulating layer) located below the seed layer. The seed layer with a voltage difference inside will not shield the electric field lines in the high electric field region in the semiconductor structure, thereby redistributing the electric field and increasing the breakdown voltage, so as to allow the semiconductor device to be applied to high voltage operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components may be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0009] Figure 1A FIG. 4 is a schematic cross-sectional view of an exemplary semiconductor structure according to some embodiments of the present invention.

[0010] Figure 1B FIG. 2 is a schematic cross-sectional view of an exemplary semiconductor structure according to another embodiment of the present invention.

[0011] Figure 2A FIG. 1 is a partial top view of an exemplary semiconductor structure according to some embodiments of the present invention.

[0012] Figure 2B FIG. 2 is a partial top view of an exemplary semiconductor structure according to another embodiment of the present invention.

[0013] Figure 2C FIG. 2 is a partial top view of an exemplary semiconductor structure according to some other embodiments of the present invention.

[0014] Figure Number:

[0015] 100, 100', 100A, 100B, 100C~Semiconductor structure

[0016] 200~Substrate

[0017] 201~Active Zone

[0018] 202~Isolation Zone

[0019] 210~Insulation layer

[0020] 220~Seed layer

[0021] 230~Compound semiconductor layer

[0022] 231~Buffer layer

[0023] 232~Channel layer

[0024] 233~Barrier layer

[0025] 234~Doped compound semiconductor layer

[0026] 240~Isolation structure

[0027] 250~First dielectric layer

[0028] 260~Second dielectric layer

[0029] 270~Third dielectric layer

[0030] 280~Metal layer

[0031] 300~Gate structure

[0032] 301~Gate electrode

[0033] 302~Gate metal layer

[0034] 400~Source structure

[0035] 401~Source electrode

[0036] 402~Source contact

[0037] 403~Source metal layer

[0038] 500~Drain structure

[0039] 501~Drain electrode

[0040] 502~Drain contact

[0041] 503~Drain metal layer

[0042] 601, 602~conducting hole

[0043] 700, 800~Open

[0044] A-A'~Section DETAILED DESCRIPTION

[0045] The following disclosure provides many embodiments or examples for implementing different elements of the provided semiconductor structure. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, and it may also include an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference numbers and / or letters in different examples. Such repetition is for simplicity and clarity, and is not intended to represent the relationship between the different embodiments discussed.

[0046] In addition, spatially relative terms may be used, such as "below", "below", "lower", "above", "higher" and similar terms. These spatially relative terms are used to facilitate the description of the relationship between one (or some) element or feature and another (or some) element or feature in the diagram. These spatially relative terms include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the orientation after the rotation.

[0047] Here, the terms "about", "approximately" and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about", "approximately" and "generally", the meaning of "about", "approximately" and "generally" can still be implied.

[0048] Although the components in some of the embodiments described above are described in a specific order, these descriptions can also be performed in other logical orders. Other components can be added to the semiconductor structure in the embodiments of the present invention. In different embodiments, some components can be replaced or omitted.

[0049] The semiconductor structure provided by the embodiment of the present invention electrically connects the source structure and the drain structure in the semiconductor structure to the seed layer on the substrate through a pair of vias located in the isolation region of the substrate. By configuring the vias, a voltage difference (i.e., the voltage difference between the source and the drain) can be generated inside the seed layer so that the electric field lines extend to the film layer (e.g., the insulating layer) located below the seed layer. The seed layer with a voltage difference inside will not shield the electric field lines in the high electric field region in the semiconductor structure, thereby redistributing the electric field and increasing the breakdown voltage, so as to allow the semiconductor device to be applied to high voltage operation.

[0050] Figure 1A 1 is a schematic cross-sectional view of an exemplary semiconductor structure 100 according to some embodiments of the present invention. According to some embodiments of the present invention, the semiconductor structure 100 includes a substrate 200 having an active region 201 and an isolation region 202, an insulating layer 210 disposed on the substrate 200, a seed layer 220 disposed on the insulating layer 210, a compound semiconductor layer 230 disposed on the seed layer 220, a gate structure 300 disposed on the compound semiconductor layer 230 and located in the active region 210, a source structure 400 and a drain structure 500 disposed on the substrate 200 and located on both sides of the gate structure 300, and a pair of vias 601 and 602 passing through the isolation structure 240 disposed in the isolation region 202.

[0051] In some embodiments, the substrate 200 may be a doped (e.g., doped with a p-type or n-type dopant) or undoped semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, or a similar semiconductor substrate. In other embodiments, the substrate 200 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an aluminum oxide substrate (AlO) substrate, or a silicon carbide (SiC) substrate. 2 O 3 ) (or sapphire substrate) or other similar substrates. The above-mentioned ceramic substrate can be formed by high-temperature sintering of ceramic powder by powder metallurgy.

[0052] The insulating layer 210 disposed on the substrate 200 is a high-quality film layer with good thermal stability at high temperatures. In some embodiments, the insulating layer 210 is a high-quality silicon oxide insulating layer made of, for example, tetraethoxysilane (TEOS). In other embodiments, the insulating layer 210 is a dielectric layer formed by plasma-enhanced chemical vapor deposition (PECVD), such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other similar materials, or a combination of the foregoing. According to some embodiments of the present invention, the insulating layer 210 can provide a higher quality surface to facilitate the subsequent formation of other film layers of the semiconductor structure on its surface. In some embodiments, the thickness of the insulating layer can be in the range of about 0.5 microns to about 10 microns, for example, about 2 microns.

[0053] In some embodiments, the material of the seed layer 220 formed on the insulating layer 210 may be silicon. In other embodiments, the seed layer 220 may be formed of other semiconductor materials such as doped silicon carbide (e.g., doping nitrogen or phosphorus in silicon carbide can form an n-type semiconductor, while doping aluminum, boron, gallium, or beryllium forms a p-type semiconductor), group III-V compound semiconductor materials, or other similar materials. In still other embodiments, the seed layer 220 may comprise aluminum oxide (Al 2 O 3 ). In some embodiments, the seed layer 220 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), a combination of the foregoing, or a similar method conformally formed on the insulating layer 210.

[0054] In some embodiments, the compound semiconductor layer 230 formed on the seed layer 220 may comprise a buffer layer 231 disposed on the seed layer 220, a channel layer 232 disposed on the buffer layer 231, and a barrier layer 233 disposed on the channel layer 232.

[0055] The buffer layer 231 can mitigate the strain of the subsequent channel layer 232 formed above the buffer layer 231 to prevent defects from forming in the upper channel layer 232. The strain is caused by the mismatch between the channel layer 232 and the substrate 200. In some embodiments, the material of the buffer layer 231 can be AlN, GaN, Al x Ga 1-x N (where 0 < x < 1), a combination of the foregoing, or other similar materials. The buffer layer 231 can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), a combination of the foregoing, or a similar method. In some embodiments, the thickness of the formed buffer layer 231 can range from about 0.5 micrometers to about 10 micrometers, such as about 3 micrometers. It should be noted that although the buffer layer 231 is a single-layer structure in the embodiment shown as Figure 1A , the buffer layer 231 can also be a multi-layer structure (not shown) in other embodiments.

[0056] According to some embodiments of the present invention, a two-dimensional electron gas (2DEG) (not shown) is formed at the heterointerface between the channel layer 232 and the barrier layer 233. As Figure 1A The semiconductor structure 100 shown is a high electron mobility transistor (HEMT) using a two-dimensional electron gas (2DEG) as a conductive carrier. In some embodiments, the channel layer 232 may be a gallium nitride (GaN) layer, and the barrier layer 233 formed on the channel layer 232 may be an aluminum gallium nitride (AlGaN) layer, wherein the GaN layer and the AlGaN layer may have dopants (e.g., n-type dopants or p-type dopants) or no dopants. Both the channel layer 232 and the barrier layer 233 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), a combination of the foregoing, or other similar methods. In some embodiments, the thickness of the formed channel layer 232 may be in a range of about 300 nanometers to about 1 micrometer, such as about 0.6 micrometers. In some embodiments, the thickness of the formed barrier layer 233 may be in a range of about 5 nanometers to about 30 nanometers, such as about 25 nanometers.

[0057] Next, according to some embodiments of the present invention, an isolation structure 240 may be formed in the compound semiconductor layer 230 of the substrate 200 to define the active region 201 and the isolation region 202. In some embodiments, Figure 1A As shown, the bottom surface of the isolation structure 240 may be located in the buffer layer 231 included in the compound semiconductor layer 230. In other embodiments, the bottom surface of the isolation structure 240 may be flush with the bottom surface of the buffer layer 231 and in contact with the seed layer 220 (not shown). In some embodiments, by forming the isolation structure 240, the two-dimensional electron gas (2DEG) formed on the heterogeneous interface between the channel layer 232 and the barrier layer 233 can be isolated in the active region 201.

[0058] According to some embodiments of the present invention, the isolation structure 204 may be formed by destroying the crystal lattice structure of the compound semiconductor layer 230 at a predetermined position of the isolation structure 240, so that this portion of the compound semiconductor layer 230 loses the piezoelectric effect and cannot conduct electricity. In these embodiments, nitrogen (N), oxygen (O), or other suitable elements may be implanted into the compound semiconductor layer 230 (e.g., a gallium nitride layer) by an ion implantation process to destroy its lattice structure, thereby transforming the compound semiconductor layer 230 at the predetermined position of the isolation structure 240 into the isolation structure 240. In other embodiments, the material of the isolation structure 240 may be a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, the like, or a combination thereof, and a trench isolation structure may be formed in the compound semiconductor layer 230 by an etching process and a deposition process.

[0059] Next, a gate structure 300 is formed on the compound semiconductor layer 230 (e.g., the barrier layer 233) in the active region 201, a source structure 400 and a drain structure 500 are formed on both sides of the gate structure 300, and an interlayer dielectric layer (e.g., the first dielectric layer 250, the second dielectric layer 260, and the third dielectric layer 270) is formed on the compound semiconductor layer 230 to form a semiconductor structure 100. According to some embodiments of the present invention, the semiconductor structure 100 is a high electron mobility transistor (HEMT). In some embodiments, the gate structure 300 includes a gate electrode 301 and a gate metal layer 302, wherein the gate electrode 301 is located on the barrier layer 233, and the gate metal layer 302 is located on the gate electrode 301 and electrically connected thereto. In other embodiments, an optional doped compound semiconductor layer 234 may be included between the gate electrode 301 and the barrier layer 233, and the details thereof will be further described later. The source structure 400 includes a source electrode 401, a source contact 402, and a source metal layer 403 electrically connected to each other, and the drain structure 500 includes a drain electrode 501, a drain contact 502, and a drain metal layer 503 electrically connected to each other. In some embodiments, the source electrode 401 and the drain electrode 501 located on both sides of the gate electrode 301 are both located in the active region 201 and pass through the barrier layer 233 to contact the channel layer 232.

[0060] In some embodiments, the material of the gate electrode 301 may be a conductive material, such as a metal, a metal nitride, or a semiconductor material. In some embodiments, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, combinations thereof, or multiple layers thereof. The semiconductor material may be polycrystalline silicon or polycrystalline germanium. The conductive material may be formed on the blocking layer 233 by, for example, chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or other suitable deposition methods, and then the gate electrode 301 may be formed by a patterning process.

[0061] According to some embodiments of the present invention, before forming the gate electrode 301, a doped compound semiconductor layer 234 may be formed on the barrier layer 233, and then the gate electrode 301 may be formed on the doped compound semiconductor layer 234. By disposing the doped compound semiconductor layer 234 between the gate electrode 301 and the barrier layer 233, the generation of two-dimensional electron gas (2DEG) below the gate electrode 301 may be suppressed, so as to achieve a normally-off state of the semiconductor device 100. In some embodiments, the material of the doped compound semiconductor layer 234 may be p-type doped or n-type doped gallium nitride (GaN). The step of forming the doped compound semiconductor region 234 may include depositing a doped compound semiconductor layer (not shown) on the barrier layer 233 by an epitaxial growth process and performing a patterning process thereon to form the doped compound semiconductor layer 234 corresponding to the position where the gate electrode 301 is to be formed. In some embodiments, the thickness of the formed doped compound semiconductor layer 234 may be in the range of about 50 nanometers to about 100 nanometers.

[0062] The source electrode 401 and the drain electrode 501 formed on both sides of the gate electrode 301 and located in the active region 201 include substantially the same material as the gate electrode 301, and thus will not be described in detail herein. Figure 1A As shown, the source electrode 401 and the drain electrode 501 pass through the barrier layer 233 to contact the channel layer 231 .

[0063] In some embodiments, the gate metal layer 302, the source contact 402, the source metal layer 403, the drain contact 502, and the drain metal layer 503 may be formed by a deposition process and a patterning process, and the materials thereof include a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminide nitride (TiAlN), metal oxides, metal alloys, other suitable conductive materials, or combinations thereof.

[0064] According to some embodiments of the present invention, Figure 1AAs shown, the gate electrode 301 is buried in the first dielectric layer 250, and the gate metal layer 302 is buried in the first dielectric layer 250 and the second dielectric layer 260 formed on the first dielectric layer 250. In addition, the source contact 402 and the drain contact 502 located on both sides of the gate structure 300 pass through the first dielectric layer 250 and the second dielectric layer 260 formed on the compound semiconductor layer 230 and contact the source electrode 402 and the drain electrode 502 respectively, while the source metal layer 403 and the drain metal layer 503 are formed on the second dielectric layer 260 and are electrically connected to the source contact 402 and the drain contact 502 respectively.

[0065] In some embodiments, the first dielectric layer 250 and the second dielectric layer 260 may include one or more single-layer or multi-layer dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials. The low-k dielectric material may include, but is not limited to, fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. For example, the dielectric material may be deposited on the compound semiconductor layer 230 (e.g., the barrier layer 233) and the isolation structure 240 to form the first dielectric layer 250 and the second dielectric layer 260 by using a spin coating process (spin coating), chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), other suitable methods or a combination of the foregoing.

[0066] According to some embodiments of the present invention, Figure 1AThe semiconductor structure 100 includes a pair of vias 601 and 602 disposed in the isolation region 202 and located on both sides of the gate structure 300. In some embodiments, the pair of vias may be through-GaN vias (TGV). The vias 601 and 602 pass through the second dielectric layer 206, the first dielectric layer 250, the isolation structure 240, and the buffer layer 231 located in the isolation region 202 and contact the seed layer 220. In an embodiment in which the bottom surface of the isolation structure 240 directly contacts the seed layer 220, the vias 601 and 602 passing through the isolation structure 240 may directly contact the seed layer 220 without passing through the buffer layer 231 (not shown). By disposing the vias 601 and 602 in the isolation region 202 , it is possible to prevent the vias 601 and 602 from contacting the two-dimensional electron gas (2DEG) formed on the hetero-interface between the channel layer 232 and the barrier layer 233 and causing electrical anomalies.

[0067] Reference Figure 1A , the source structure 400 and the drain structure 500 are electrically connected to the seed layer 220 through the via hole 601 and the via hole 602, respectively. Specifically, the source structure 400 is electrically connected to the seed layer 220 by contacting the source metal layer 403 across the active region 201 and the isolation region 202 with the via hole 601, and the drain structure 500 is electrically connected to the seed layer 220 by contacting the drain metal layer 503 across the active region 201 and the isolation region 202 with the via hole 602. According to some embodiments of the present invention, the voltage difference generated inside the seed layer 220 electrically connected to the source structure 400 and the drain structure 500, respectively, may be substantially the same as the voltage difference between the source electrode 401 and the drain electrode 501.

[0068] According to some embodiments of the present invention, the formation of the vias 601 and 602 includes performing lithography and etching processes on the compound semiconductor layer 230, the isolation structure 240, the first dielectric layer 250, and the second dielectric layer 260 of the isolation region 202 to form a pair of holes (not shown) located on both sides of the gate structure 300. Then, a conductive material is filled into the pair of holes to form the vias 601 and 602. In some embodiments, the conductive material can be selected from the materials used to form the gate metal layer 302, the source contact 402, the source metal layer 403, the drain contact 502, and the drain metal layer 503, so they are not described here. According to some embodiments of the present invention, the apertures of the vias 601 and 602 can each be in the range of about 0.5 micrometers (micrometer, um) to about 5 micrometers. By configuring the vias 601 and 602, a voltage difference (i.e., the voltage difference between the source and the drain) can be generated inside the seed layer, so that the electric field lines extend to the film layer (e.g., the insulating layer) below the seed layer, thereby redistributing the electric field and increasing the breakdown voltage. Furthermore, applying the configuration of the vias 601 and 602 to a semiconductor device using a ceramic substrate can significantly improve its performance under high voltage operation.

[0069] Please refer to Figure 1B ,exist Figure 1B The semiconductor structure 100′ shown in FIG. Figure 1A The semiconductor structure 100 shown in FIG. 1 is substantially the same as the semiconductor structure 100 shown in FIG. 1 , except that the vias 601 and 602 included in the semiconductor structure 100 ′ further penetrate the seed layer 220 and contact the insulating layer 210. In some embodiments, the bottom surface of the vias 601 and 602 may be located in the insulating layer 210 (i.e., Figure 1B In other embodiments, the bottom surfaces of the vias 601 and 602 may contact the top surface of the insulating layer 210 (not shown).

[0070] In summary, by configuring the vias 601 and 602, a voltage difference (i.e., the voltage difference between the source electrode 401 and the drain electrode 501) can be generated inside the seed layer 220, so that the electric field lines extend to the insulating layer 210 located below the seed layer 220. The seed layer 220 having the voltage difference inside will not shield the electric field lines of the high electric field region (e.g., the compound semiconductor layer 230 located below the gate structure 300 in the active region 201) in the semiconductor structure 100 and 100', thereby redistributing the electric field. In this way, the insulating layer 210 in the semiconductor structure 100 and 100' can withstand the applied voltage together with the compound semiconductor layer 230 formed on the insulating layer 210, thereby increasing the breakdown voltage, so as to allow the semiconductor device 100 and 100' to be applied to high voltage operation.

[0071] It is worth noting that although only one pair of vias 601 and 602 are shown here, the embodiment of the present invention may also include multiple pairs of vias that electrically connect the source structure 400 and the seed layer 220 and the drain structure 500 and the seed layer 220 (not shown). In other embodiments, the number of vias that electrically connect the source structure 400 and the seed layer 220 may be different from the number of vias that electrically connect the drain structure 500 and the seed layer 220 (not shown).

[0072] According to some embodiments of the present invention, Figure 1A The semiconductor structure 100 shown in the figure may include a third dielectric layer 270 formed on the second dielectric layer 260, which covers the source metal layer 403 and the drain metal layer 503, and a metal layer 280 that passes through the third dielectric layer 270 and is electrically connected to the source metal layer 403 and the drain metal layer 503. In some embodiments, the material of the third dielectric layer 270 can be selected from the aforementioned materials used to form the first dielectric layer 250 and the second dielectric layer 260, and the material and formation method of the metal layer 280 are substantially the same as those of the source metal layer 403 and the drain metal layer 503, so they are not repeated here. It is worth noting that although the embodiment of the present invention only depicts a single-layer third dielectric layer 270 and a single-layer metal layer 280, the embodiment of the present invention is not limited thereto. The number of film layers of the third dielectric layer 270 and the metal layer 280 can be adjusted according to the product design.

[0073] According to some embodiments of the present invention, Figure 1A The semiconductor structure 100 shown in FIG. 1 may have various configurations in the top view, for example, Figure 2A , Figure 2B ,and Figure 2C For example, the semiconductor structures 100A, 100B, and 100C shown in FIG. Figure 1A The semiconductor structure 100 in Figure 2A The cross section AA' shown in FIG. 1 does not pass through the opening 700 of the seed layer 220. In other embodiments, Figure 1A The seed layer 220 of the semiconductor structure 100 shown in FIG. 1 may not have an opening (not shown).

[0074] Figure 2A FIG. 1 is a partial top view of an exemplary semiconductor structure 100A according to some embodiments of the present invention. It should be noted that in order to concisely describe the embodiments of the present invention and highlight the features thereof, not all structures of the semiconductor structure 100A are shown in FIG. Figure 2A In. Reference Figure 2A, the semiconductor structure 100A includes an active region 201, an isolation region 202 surrounding the active region 201, a gate structure 300, a source structure 400, and a drain structure 500 formed in the active region 210, vias 601 and 602 formed in the isolation region 202, and a seed layer 220 having a plurality of openings 700 in the active region 201. In some embodiments, the openings 700 of the seed layer 220 may expose the insulating layer 210 located below the seed layer 220. According to some embodiments of the present invention, in a top view, the openings 700 located in the active region 201 may be arranged in a matrix, i.e., Figure 2A For example, the matrix may include five rows and five columns of openings 700 aligned.

[0075] Figure 2B FIG. 1 is a partial top view of an exemplary semiconductor structure 100B according to another embodiment of the present invention. Figure 2B The semiconductor structure 100B shown in FIG. Figure 2A The semiconductor structure 100B differs from the semiconductor structure 100A in that the plurality of openings 700 of the seed layer 220 in the active region 201 of the semiconductor structure 100B are arranged in a staggered manner.

[0076] Figure 2C A partial top view of an exemplary semiconductor structure 100C is shown according to another embodiment of the present invention. Figure 2C The semiconductor structure 100C shown in FIG. Figure 2A , Figure 2B The semiconductor structures 100A and 100B shown in FIG. 1 are not described in detail here. The difference between the semiconductor structure 100C and the semiconductor structures 100A and 100B is that the seed layer 220 in the active region 201 of the semiconductor structure 100C has a plurality of long strip openings 800. Figure 2C As shown, the long axis of the long strip opening 800 extends parallel to the direction from the via 601 to the via 602 , and the long strip openings 800 are arranged in the active region 201 along the direction of their short axis.

[0077] According to some embodiments of the present invention, the plurality of openings of the seed layer 220 formed in the active region 201 can form a high impedance region to reduce the leakage current between the drain structure and the source structure. Figure 2A , Figure 2B ,and Figure 2C The shape, number, size, and arrangement of the openings of the seed layer 220 shown in the figure are merely exemplary. The configuration of the openings of the seed layer 220 can be adjusted according to product design, and the embodiments of the present invention are not limited thereto.

[0078] In summary, the semiconductor structure provided by the embodiment of the present invention can generate a voltage difference inside the seed layer by electrically connecting the source structure and the drain structure to the seed layer respectively through a pair of conductive holes, so that the electric field lines can extend to the film layer (such as the insulating layer) located below the seed layer. According to the embodiment of the present invention, the seed layer with a voltage difference inside will not shield the electric field lines of the high electric field region (such as the compound semiconductor layer located below the gate) in the semiconductor structure, thereby redistributing the electric field. In this way, the insulating layer in the semiconductor structure can withstand the applied voltage together with the compound semiconductor layer formed on the insulating layer, thereby increasing the breakdown voltage and improving the performance of the semiconductor structure.

[0079] Several embodiments are summarized above so that those skilled in the art can better understand the concepts of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: A substrate having an active region and an isolation region; an insulating layer, located on the substrate; a seed layer located on the insulating layer; a compound semiconductor layer located on the seed layer; a gate structure located on the compound semiconductor layer and in the active region; an isolation structure located on the substrate and in the isolation region; a pair of vias located in the isolation region and on both sides of the gate structure, wherein the pair of vias pass through the isolation structure and contact the seed layer; as well as A source structure and a drain structure are located on the substrate and on both sides of the gate structure, wherein the source structure and the drain structure are electrically connected to the seed layer through the pair of vias respectively.

2. The semiconductor structure according to claim 1, wherein: The compound semiconductor layer includes: a buffer layer, located on the seed layer; a channel layer located on the buffer layer and in the active region; and A blocking layer is located on the channel layer and in the active region.

3. The semiconductor structure according to claim 2, wherein: The thickness of the insulating layer is in the range of 0.5 micrometers to 10 micrometers, the thickness of the buffer layer is in the range of 0.5 micrometers to 10 micrometers, the thickness of the channel layer is in the range of 300 nanometers to 1 micrometer, and the thickness of the barrier layer is in the range of 5 nanometers to 30 nanometers.

4. The semiconductor structure according to claim 2, characterized in that The invention further comprises a dielectric layer located on the compound semiconductor layer.

5. The semiconductor structure according to claim 2, wherein: The gate structure includes: a gate electrode layer located on the barrier layer; and A gate metal layer is located on the gate electrode layer and is electrically connected to the gate electrode layer.

6. The semiconductor structure according to claim 5, characterized in that The invention further comprises a doped compound semiconductor layer, wherein the doped compound semiconductor layer is located between the gate electrode layer and the barrier layer.

7. The semiconductor structure according to claim 1, wherein: The pair of vias further penetrate the seed layer and contact the insulating layer.

8. The semiconductor structure according to claim 4, wherein: The source structure includes: a source electrode, located in the active region and contacting the channel layer through the barrier layer; a source contact located in the active region and penetrating through the dielectric layer to contact the source electrode; and A source metal layer is located on the dielectric layer and electrically connected to the source contact and one of the pair of vias.

9. The semiconductor structure according to claim 8, characterized in that The drain structure includes: a drain electrode located in the active region and contacting the channel layer through the barrier layer; a drain contact located in the active region and penetrating through the dielectric layer to contact the drain electrode; and A drain metal layer is located on the dielectric layer and electrically connects the drain contact and the other of the pair of vias.

10. The semiconductor structure according to claim 1, wherein: The seed layer includes silicon, silicon carbide, or aluminum oxide.

11. The semiconductor structure according to claim 1, wherein: The hole diameters of the pair of via holes are each in a range of 0.5 micrometers to 5 micrometers.

12. The semiconductor structure according to claim 1, wherein: In a top view, the seed layer includes a plurality of openings in the active region.

13. The semiconductor structure according to claim 12, wherein: In the top view, the plurality of openings are arranged in a matrix.

14. The semiconductor structure according to claim 12, wherein: In the top view, the plurality of openings are arranged alternately with each other.

15. A semiconductor structure, characterized in that: include: A ceramic substrate having an active region and an isolation region; an insulating layer, located on the ceramic substrate; a seed layer located on the insulating layer; a compound semiconductor layer located on the seed layer; a gate structure located on the compound semiconductor layer and in the active region; as well as A source structure and a drain structure are located on the ceramic substrate and on both sides of the gate structure, wherein the source structure and the drain structure are electrically connected to the seed layer respectively.

16. The semiconductor structure according to claim 15, wherein: Also includes: an isolation structure located on the ceramic substrate and in the isolation region; and A pair of via holes are located in the isolation region and at both sides of the gate structure, wherein the pair of via holes pass through the isolation structure and contact the seed layer, and the source structure and the drain structure are electrically connected to the seed layer through the pair of via holes respectively.

17. The semiconductor structure according to claim 16, wherein: The pair of vias further penetrate the seed layer and contact the insulating layer.

18. The semiconductor structure according to claim 15, wherein: The compound semiconductor layer includes: a buffer layer, located on the seed layer; a channel layer located on the buffer layer and in the active region; and A blocking layer is located on the channel layer and in the active region.

19. The semiconductor structure according to claim 15, wherein: The ceramic substrate is an aluminum nitride substrate, a silicon carbide substrate, or an aluminum oxide substrate.

20. The semiconductor structure according to claim 15, wherein: In the top view, the seed layer includes a plurality of elongated openings in the active region.

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