Thin film transistor and method for manufacturing the same, and display device

Abstract

The embodiment of the present invention provides a thin film transistor and a method for preparing the same, and a display device, which relate to the field of display technology and can improve the mobility of the thin film transistor. The thin film transistor includes an insulating layer arranged on a substrate, an active pattern including carbon nanotubes, a source electrode and a drain electrode; the active pattern includes a plurality of stripe sub-patterns extending along a first direction and arranged at intervals; along the first direction, one end of each stripe sub-pattern in the active pattern contacts the source electrode, and the other end contacts the drain electrode; the insulating layer includes a plurality of stripe-shaped grooves, the grooves correspond to the stripe sub-patterns one by one, and the orthographic projection of the grooves on the substrate completely overlaps with the orthographic projection of the stripe sub-pattern on the substrate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a thin film transistor and a manufacturing method thereof, and a display device. Background Art

[0002] In recent years, users' demands for high-quality display panels have gradually increased, and thus the requirements for thin-film transistors (TFTs) have also become increasingly higher.

[0003] Currently, low temperature polysilicon (LTPS) or oxide semiconductors are commonly used as active layer materials. However, if low temperature polysilicon is used as the active layer material of a TFT, there is a problem of poor uniformity and difficulty in realizing a large-size display panel. If an oxide semiconductor is used as the active layer material of a TFT, there is a problem of low mobility. Summary of the invention

[0004] Embodiments of the present invention provide a thin film transistor and a method for manufacturing the same, and a display device, which can improve the mobility of the thin film transistor.

[0005] To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

[0006] In a first aspect, a thin film transistor is provided, comprising an insulating layer arranged on a substrate, an active pattern comprising carbon nanotubes, a source electrode and a drain electrode; the active pattern comprises a plurality of strip sub-patterns extending along a first direction and arranged at intervals; along the first direction, one end of each strip sub-pattern in the active pattern is in contact with the source electrode, and the other end is in contact with the drain electrode; the insulating layer comprises a plurality of strip-shaped grooves, the grooves correspond one-to-one to the strip sub-patterns, and the orthographic projection of the grooves on the substrate completely overlaps with the orthographic projection of the strip sub-pattern on the substrate.

[0007] Optionally, the stripe sub-pattern is filled in the groove; and a surface of the stripe sub-pattern close to the substrate is flush with a bottom surface of the corresponding groove.

[0008] Optionally, the groove passes through the insulating layer; each of the grooves is filled with a modification pattern; the active pattern is arranged on the side of the modification pattern away from the substrate; the modification pattern corresponds to the strip sub-pattern one by one and is in direct contact with the strip sub-pattern, and the orthographic projection of the modification pattern on the substrate and the orthographic projection of the corresponding strip sub-pattern on the substrate completely overlap; wherein the material of the modification pattern does not chemically react with the material of the insulating layer.

[0009] Optionally, the thin film transistor is a bottom-gate thin film transistor; the insulating layer is arranged on the side of the active pattern close to the substrate; the groove does not pass through the insulating layer; or, the thin film transistor is a top-gate thin film transistor or a double-gate thin film transistor; the insulating layer is arranged on the side of the active pattern close to the substrate; the groove does not pass through the insulating layer.

[0010] Optionally, the thin film transistor is a bottom-gate thin film transistor; the thin film transistor also includes a gate insulating layer arranged on the substrate, and the gate insulating layer is arranged on the side of the insulating layer close to the substrate; or, the thin film transistor is a top-gate thin film transistor or a double-gate thin film transistor; the thin film transistor also includes a buffer layer arranged on the substrate, and the buffer layer is arranged on the side of the insulating layer close to the substrate.

[0011] Optionally, the thin film transistor is a bottom-gate thin film transistor; the thin film transistor also includes a gate insulating layer arranged on the substrate, the gate insulating layer is arranged on the side of the insulating layer close to the substrate, and the modification pattern is in direct contact with the gate insulating layer; or, the thin film transistor is a top-gate thin film transistor or a double-gate thin film transistor; the thin film transistor also includes a buffer layer arranged on the substrate, the buffer layer is arranged on the side of the insulating layer close to the substrate, and the modification pattern is in direct contact with the buffer layer.

[0012] Optionally, the material of the modified pattern is an amphoteric coupling agent, the amphoteric coupling agent is a silane coupling agent, and the material of the insulating layer is a hydrophobic insulating material; the material of the gate insulating layer in the bottom-gate thin-film transistor can chemically react with a carboxyl group; or, the material of the buffer layer in the top-gate thin-film transistor or the dual-gate thin-film transistor can chemically react with a carboxyl group.

[0013] Optionally, the width of the cross section of the stripe sub-pattern is greater than or equal to 500 nm and less than 1000 nm; wherein the cross section is perpendicular to the thickness direction of the substrate, and the width of the cross section is perpendicular to the first direction.

[0014] In a second aspect, a display device is provided, comprising an array substrate, wherein the array substrate comprises a pixel circuit, and the pixel circuit comprises a driving transistor; the driving transistor is the thin film transistor described in the first aspect.

[0015] In a third aspect, a method for preparing a thin film transistor is provided, characterized in that it includes: forming an insulating film on a substrate, forming a plurality of strip grooves extending along a first direction and arranged at intervals in the insulating film to obtain an insulating layer; forming an active pattern including carbon nanotubes on a side of the insulating layer away from the substrate; the active pattern includes a plurality of strip sub-patterns arranged at intervals; the strip sub-patterns correspond to the grooves one by one, and the orthographic projection of the strip sub-pattern on the substrate and the orthographic projection of the corresponding groove on the substrate completely overlap; forming a source and a drain on a side of the active pattern away from the substrate, and along the first direction, one end of each strip sub-pattern in the active pattern is in contact with the source and the other end is in contact with the drain.

[0016] The groove optionally passes through the insulating layer; after forming the insulating layer and before forming the active pattern, the method for preparing the thin film transistor further includes: filling a modification pattern into each of the grooves; the modification pattern is arranged on the side of the active pattern close to the substrate, the modification pattern corresponds to and directly contacts the strip sub-pattern one by one, and the orthographic projection of the modification pattern on the substrate and the orthographic projection of the corresponding strip sub-pattern on the substrate completely overlap; wherein the thin film transistor is a bottom-gate thin film transistor, and the modification pattern is in direct contact with a gate insulating layer arranged on the side of the insulating layer close to the substrate; or, the thin film transistor is a top-gate thin film transistor or a dual-gate thin film transistor, and the modification pattern is in direct contact with a buffer layer arranged on the side of the insulating layer close to the substrate; the material of the modification pattern does not chemically react with the material of the insulating layer.

[0017] The embodiment of the present invention provides a thin film transistor and a method for preparing the same, and a display device. The thin film transistor includes an active pattern, and the active pattern includes a plurality of stripe sub-patterns arranged at intervals. Each stripe sub-pattern includes one or more carbon nanotubes. The carbon nanotubes in each stripe sub-pattern are confined to the region where the stripe sub-pattern is located. Therefore, the arrangement of the carbon nanotubes in a stripe sub-pattern is limited. Compared with the region where the entire active pattern is located in the related art, the region where each stripe sub-pattern is located in the embodiment of the present invention is much smaller. Therefore, compared with the arrangement of multiple carbon nanotubes in any direction in the related art, the angle between the extension direction of the carbon nanotubes in the embodiment of the present invention and the first direction is smaller, and thus the angle between the multiple carbon nanotubes can be ignored. The multiple carbon nanotubes are arranged regularly as a whole, thereby improving the problem of low mobility of the thin film transistor caused by the irregular arrangement of multiple carbon nanotubes in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of the structure of a display device provided by an embodiment of the present invention;

[0020] Figure 2 A schematic top view of a thin film transistor provided by an embodiment of the present invention;

[0021] Figure 3 for Figure 2 A-A1 cross-sectional view;

[0022] Figure 4 A schematic diagram of the structure of a thin film transistor provided by an embodiment of the present invention;

[0023] Figure 5 A schematic diagram of the structure of a thin film transistor provided by an embodiment of the present invention;

[0024] Figure 6 A schematic diagram of the structure of a thin film transistor provided by an embodiment of the present invention;

[0025] Figure 7 A schematic diagram of the structure of a thin film transistor provided by an embodiment of the present invention;

[0026] Figure 8a A schematic diagram of the arrangement of carbon nanotubes provided for related technologies;

[0027] Figure 8b A schematic diagram of the arrangement of carbon nanotubes provided in an embodiment of the present invention;

[0028] Fig. 9 A schematic structural diagram of an insulating layer provided by an embodiment of the present invention;

[0029] Fig.10 A schematic diagram of the structure of a thin film transistor provided by an embodiment of the present invention;

[0030] Fig.11 A schematic diagram of the structure of a thin film transistor provided by an embodiment of the present invention;

[0031] Fig.12 A schematic diagram of the structure of a thin film transistor provided by an embodiment of the present invention;

[0032] Fig.13A schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0033] Fig.14 A schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0034] Fig.15 A schematic diagram of a process for preparing a thin film transistor provided by an embodiment of the present invention;

[0035] Fig.16 A schematic diagram of a process for preparing a thin film transistor provided by an embodiment of the present invention;

[0036] Fig.17 A schematic diagram of a process for preparing a thin film transistor provided by an embodiment of the present invention.

[0037] Reference numerals:

[0038] 1-frame; 2-display panel; 21-array substrate; 22-opposing substrate; 3-circuit board; 4-cover plate; 10-substrate; 11-strip sub-pattern; 111-carbon nanotube; 12-source; 13-drain; 14-insulating layer; 141-groove; 15-gate; 16-gate insulating layer; 17-buffer layer; 18-interlayer insulating layer; 19-auxiliary gate; 20-modified pattern; 31-driving transistor; 41-LED light-emitting unit; 42-first electrode; 43-light-emitting layer; 44-second electrode; 45-pixel defining layer. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] The display device can be used as a mobile phone, a tablet computer, a personal digital assistant (PDA), a car computer, etc. The embodiment of the present invention does not impose any special restrictions on the specific use of the display panel.

[0041] like Figure 1 As shown, the display device may include, for example, a frame 1, a display panel 2, a circuit board 3, a cover plate 4, and other electronic accessories including a camera and the like.

[0042] Taking the above-mentioned display panel 2 as a top-emitting light source as an example, the frame 1 may be a U-shaped frame, and the display panel 2 and the circuit board 3 are arranged in the frame 1. The cover plate 4 is arranged on the light-emitting side of the display panel 2, and the circuit board 3 is arranged on the side of the display panel 2 away from the cover plate 4.

[0043] The display panel 2 may be an organic light emitting diode (OLED) display panel, a light emitting diode (LED) display panel, a quantum dot light emitting diode (QLED) display panel, or a liquid crystal display panel.

[0044] The above-mentioned display panels 2 each include an array substrate 21 and an opposing substrate 22 , and the array substrate 21 includes a thin film transistor.

[0045] The embodiment of the present invention provides a thin film transistor, which can be used as the thin film transistor in the above array substrate 21. Of course, the thin film transistor can also be used for other substrates, which is not particularly limited in the embodiment of the present invention.

[0046] like Figure 2 and Figure 3 , Fig.16 As shown, the thin film transistor includes an insulating layer 14 arranged on a substrate 10, an active pattern including carbon nano-hangings, a source 12 and a drain 13; the active pattern includes a plurality of strip sub-patterns 11 extending along a first direction and arranged at intervals; along the first direction, one end of each strip sub-pattern 11 in the active pattern is in contact with the source 12, and the other end is in contact with the drain 13; the insulating layer 14 includes a plurality of strip-shaped grooves 141, the grooves 141 correspond to the strip sub-patterns 11 one by one, and the orthographic projection of the grooves 141 on the substrate 10 is completely overlapped with the orthographic projection of the strip sub-pattern 11 on the substrate 10.

[0047] Optionally, the thin film transistor may be a bottom-gate thin film transistor, a top-gate thin film transistor, or a dual-gate thin film transistor.

[0048] like Figure 4 and Figure 5 As shown, if the thin film transistor is a bottom-gate thin film transistor, the bottom-gate thin film transistor further includes a gate 15 and a gate insulating layer 16 sequentially disposed on the substrate 10. The gate 15 and the gate insulating layer 16 are disposed on the side of the active pattern close to the substrate 10.

[0049] like Figure 6As shown, if the thin film transistor is a top-gate thin film transistor, the top-gate thin film transistor further includes a gate insulating layer 16, a gate electrode 15, and an interlayer insulating layer 18, which are sequentially arranged on the side of the active pattern away from the substrate 10. Among them, the gate insulating layer 16, the gate electrode 15, and the interlayer insulating layer 18 are arranged on the side of the source electrode 12 and the drain electrode 13 close to the substrate 10, and the source electrode 12 and the drain electrode 13 are in contact with the active pattern through vias.

[0050] like Figure 7 As shown, if the thin film transistor is a dual-gate thin film transistor, the dual-gate thin film transistor further includes a gate insulating layer 16, a gate electrode 15, an interlayer insulating layer 18, and an auxiliary gate electrode 19, which are sequentially arranged on the side of the active pattern away from the substrate 10. Among them, the gate insulating layer 16, the gate electrode 15, and the interlayer insulating layer 18 are arranged on the side of the source electrode 12 and the drain electrode 13 close to the substrate 10, and the source electrode 12 and the drain electrode 13 are in contact with the active pattern through vias. The auxiliary gate electrode 19 is arranged on the side of the interlayer insulating layer 18 away from the substrate 10, and is electrically connected to the gate electrode 15 through the vias on the interlayer insulating layer 18.

[0051] Optionally, since the stripe sub-patterns 11 extend along the first direction, and along the first direction, one end of each stripe sub-pattern 11 in the active pattern contacts the source 12 and the other end contacts the drain 13. Therefore, the first direction is the direction in which the source 12 points to the drain 13.

[0052] Here, along the first direction, each stripe sub-pattern 11 has two opposite ends, so it is clear and unique that one end of the stripe sub-pattern 11 contacts the source electrode 12 and the other end contacts the drain electrode 13 .

[0053] Optionally, since the carbon nanotubes in the embodiment of the present invention are used as active patterns, the carbon nanotubes used in the embodiment of the present invention are semiconductor carbon nanotubes.

[0054] Here, the raw material of carbon nanotubes includes metallic carbon nanotubes and semiconductor carbon nanotubes. In the embodiment of the present invention, the metallic carbon nanotubes in the raw material of carbon nanotubes can be removed by centrifugation or the like to obtain the semiconductor carbon nanotubes.

[0055] For example, the metallic carbon nanotubes in the carbon nanotube raw material are removed by centrifugation. A polymer may be added to the carbon nanotube raw material first; and multiple semiconductor carbon nanotubes and metallic carbon nanotubes in the carbon nanotubes are dispersed into independent individuals by ultrasonic dispersion, and the polymer reacts with the semiconductor carbon nanotubes and wraps on the surface of the semiconductor carbon nanotubes to prevent any semiconductor carbon nanotube from contacting the metallic carbon nanotubes and other semiconductor carbon nanotubes; and then, according to the density difference between the semiconductor carbon nanotubes and the metallic carbon nanotubes, the semiconductor carbon nanotubes are separated by centrifugation.

[0056] On this basis, the polymer on the surface of the semiconductor carbon nanotube can also be removed, for example, by using a solvent.

[0057] Optionally, the number of the stripe sub-patterns 11 in the active pattern is not limited. The number of the stripe sub-patterns 11 in the active pattern is related to the size of the source 12 and the drain 13 , and the width of the cross section of each stripe sub-pattern 11 .

[0058] The cross section of the stripe sub-pattern 11 is a cross section along a direction perpendicular to the thickness of the substrate 10. The width of the cross section of the stripe sub-pattern 11 is perpendicular to the first direction.

[0059] Optionally, the sizes of the multiple stripe sub-patterns 11 in the active pattern may be the same or different.

[0060] Alternatively, those skilled in the art should know that the shape of the carbon nanotube can be approximately regarded as a cylinder, wherein the diameter of the carbon nanotube (the diameter of the bottom of the cylinder) is about 1 nm, and the length (the height of the cylinder) is about 1000 nm.

[0061] The embodiment of the present invention does not limit the width range of the cross-section of the plurality of stripe sub-patterns 11. The width of the cross-section of each stripe sub-pattern 11 should be at least greater than or equal to the diameter of a carbon nanotube and less than the length of the carbon nanotube to achieve the sequential arrangement of the plurality of carbon nanotubes.

[0062] For example, the width of the cross section of the stripe sub-pattern 11 is in the range of greater than or equal to 1 nm and less than 1000 nm.

[0063] The size of the stripe sub-pattern 11 along the first direction is not limited, and the size of the stripe sub-pattern 11 along the first direction is related to the distance between the source electrode 12 and the drain electrode 13 and the size of the carbon nanotube.

[0064] Optionally, the material of the source electrode 12 and the drain electrode 13 may include metal materials such as molybdenum (Mo), copper (Cu), molybdenum-niobium alloy (MoNb), and aluminum (Al); the material of the source electrode 12 and the drain electrode 13 may also include transparent conductive materials such as indium tin oxide (ITO).

[0065] The material of the gate 15 may include metal materials such as Mo, Cu, MoNb, and Al; the material of the gate 15 may also include transparent conductive materials such as ITO.

[0066] The source electrode 12, the drain electrode 13, and the gate electrode 15 may be a single layer or multiple layers. For example, the source electrode 12, the drain electrode 13, and the gate electrode 15 may include a single layer and the material may be copper; or the source electrode 12, the drain electrode 13, and the gate electrode 15 may include two layers, one of which may be made of chromium (Cr) and the other of which may be made of gold (Au).

[0067] Optional, such as Figure 4-Figure 7 As shown, the surface of the stripe sub-pattern 11 close to the substrate 10 is flush with the bottom surface of the corresponding groove 141. That is, the stripe sub-pattern 11 is directly formed in the corresponding groove 141. Here, the bottom surface of the groove 141 is the surface of the groove 141 close to the substrate 10.

[0068] The thickness of the stripe sub-pattern 11 is less than or equal to the depth of the corresponding groove 141; or, the distance between the surface of the stripe sub-pattern 11 away from the substrate 10 and the substrate 10 is greater than the distance between the surface of the insulating layer 14 away from the substrate 10 and the substrate 10.

[0069] Optional, such as Figure 10-12 As shown, other structures (such as the modification patterns described below, for ease of description, other structures are referred to as modification patterns hereinafter) are disposed in the groove 141 , and the modification pattern 20 is disposed on the side of the strip sub-pattern 11 close to the substrate 10 .

[0070] Here, the thickness of the modification pattern 20 is smaller than the depth of the corresponding groove 141. Fig.10 As shown, when the sum of the thicknesses of the modified pattern 20 and the strip sub-pattern 11 is greater than the depth of the corresponding groove 141, a portion of the strip sub-pattern 11 is filled in the corresponding groove 141, and the other portion is higher than the insulating layer 14 and away from the surface of the substrate 10; or, when the sum of the thicknesses of the modified pattern 20 and the strip sub-pattern 11 is less than or equal to the depth of the corresponding groove 141, the strip sub-pattern 11 is completely filled in the corresponding groove 141.

[0071] Or, if Fig.11 and Fig.12 As shown, the thickness of the modified pattern 20 is greater than or equal to the depth of the corresponding groove 141 , and all the stripe sub-patterns 11 are higher than the insulating layer 14 and away from the surface of the substrate 10 .

[0072] For the above, the groove 141 may or may not penetrate the insulating layer 14. The thickness direction of the stripe sub-pattern 11, the thickness direction of the modification pattern 20, and the depth direction of the groove 141 are all parallel to the thickness direction of the substrate 10. The depth of the groove 141 at each position may be the same or different. In the embodiment of the present invention, the maximum depth of the groove 141 is compared with the maximum thickness of the stripe sub-pattern 11 or the maximum thickness of the modification pattern 20.

[0073] In the related art, carbon nanotubes can be used as the material of the active pattern to solve the problems of poor uniformity, difficulty in realizing large-size display panels, and low mobility. Figure 8a As shown, the plurality of carbon nanotubes 111 in the active pattern made by the existing process are arranged disorderly. If the disorderly arranged carbon nanotubes 111 are used as the active pattern, the mobility of the thin film transistor is still low.

[0074] The embodiment of the present invention provides a thin film transistor, including an active pattern, the active pattern including a plurality of strip sub-patterns 11 arranged at intervals, each strip sub-pattern 11 including one or more carbon nanotubes 111. The carbon nanotubes 111 in each strip sub-pattern 11 are confined to the region where the strip sub-pattern 11 is located, so the arrangement of the carbon nanotubes 111 in a strip sub-pattern 11 is limited. Compared with the region where the entire active pattern is located in the related art, the region where each strip sub-pattern 11 in the embodiment of the present invention is located is much smaller, so compared with the arrangement of a plurality of carbon nanotubes 111 in any direction in the related art, the angle between the extension direction of the carbon nanotubes 111 in the embodiment of the present invention and the first direction is smaller (e.g., Figure 8b As shown), the angles between the multiple carbon nanotubes 111 can be ignored, and the multiple carbon nanotubes 111 are arranged regularly as a whole, thereby improving the problem of low mobility of the thin film transistor caused by the irregular arrangement of the multiple carbon nanotubes 111 in the related art.

[0075] Optional, such as Figure 4 and Figure 6 As shown, the thickness of the stripe sub-pattern 11 is exactly equal to the depth of the corresponding groove 141 .

[0076] Or, if Figure 5 and Figure 7 As shown, the thickness of the stripe sub-pattern 11 is smaller than the depth of the corresponding groove 141 .

[0077] Alternatively, the distance between the surface of the stripe sub-pattern 11 facing away from the substrate 10 and the substrate 10 is greater than the distance between the surface of the insulating layer 14 facing away from the substrate 10 and the substrate 10 .

[0078] In the embodiment of the present invention, an insulating layer 14 having a groove 141 may be first formed on the substrate 10 ; then, a stripe sub-pattern 11 may be directly formed in the groove 141 to obtain a plurality of stripe sub-patterns 11 arranged at intervals.

[0079] Optional, such as Figure 10-12As shown, the groove 141 passes through the insulating layer 14; each groove 141 is filled with a modification pattern 20; the active pattern is arranged on the side of the modification pattern 20 away from the substrate 10; the modification pattern 20 corresponds to the strip sub-pattern 11 one by one and is in direct contact with the strip sub-pattern 11, and the orthographic projection of the modification pattern 20 on the substrate 10 and the orthographic projection of the corresponding strip sub-pattern 11 on the substrate 10 completely overlap; wherein the material of the modification pattern 20 does not chemically react with the material of the insulating layer 14.

[0080] Optionally, the material of the modification pattern 20 is not limited. On the one hand, the material of the modification pattern 20 can chemically react with the carbon nanotubes 111, so that the stripe sub-pattern 11 is only formed on the modification pattern 20; on the other hand, when the groove 141 passes through the insulating layer 14, the material of the modification pattern 20 does not chemically react with the material of the insulating layer 14, so as to avoid the modification pattern 20 from being formed on the surface of the insulating layer 14 on the side away from the substrate 10, thereby avoiding the active pattern from being formed in the area other than the area where the groove 141 is located.

[0081] Optional, such as Fig.10 As shown, the thickness of the modification pattern 20 is smaller than the depth of the corresponding groove 141 .

[0082] Or, if Fig.11 and Fig.12 As shown, the thickness of the modification pattern 20 is exactly equal to the depth of the corresponding groove 141 .

[0083] Alternatively, the thickness of the modification pattern 20 is greater than the depth of the corresponding groove 141 .

[0084] In the embodiment of the present invention, the modification pattern 20 is first formed in the groove 141, and then the stripe sub-pattern 11 is formed on the side of the modification pattern 20 away from the substrate 10. Since the material of the modification pattern 20 does not chemically react with the material of the insulating layer 14, the modification pattern 20 is only formed in the groove 141; since the material of the modification pattern 20 can chemically react with the carbon nanotubes 111, the modification pattern 20 can firmly adsorb and fix the carbon nanotubes 111, so that the stripe sub-pattern 11 is only formed on the modification pattern 20. The multiple stripe sub-patterns 11 in the finally obtained active pattern are arranged at intervals, and the orthographic projection of each stripe sub-pattern 11 on the substrate 10 and the orthographic projection of the corresponding groove 141 on the substrate 10 just completely overlap.

[0085] Optional, such as Figure 4 As shown, the thin film transistor is a bottom-gate thin film transistor; the groove 141 does not penetrate the insulating layer 14 , and the insulating layer 14 is a gate insulating layer 16 .

[0086] Here, in the case where the thin film transistor is a bottom-gate thin film transistor, the thin film transistor may further include a buffer layer 17 disposed between the substrate 10 and the gate 15 .

[0087] Optional, such as Figure 6 As shown, the thin film transistor is a top-gate thin film transistor or a dual-gate thin film transistor ( Figure 6 Only a top-gate thin film transistor is shown); the thin film transistor also includes a buffer layer 17 arranged on the substrate 10, and the buffer layer 17 is arranged on the side of the active pattern close to the substrate 10; the groove 141 does not penetrate the insulating layer 14, and the insulating layer 14 is the buffer layer 17.

[0088] In the embodiment of the present invention, when the groove 141 does not penetrate the insulating layer 14, if the thin film transistor is a bottom-gate thin film transistor, the gate insulating layer 16 can be used as the insulating layer 14; if the thin film transistor is a top-gate thin film transistor or a double-gate thin film transistor, the buffer layer 17 can be used as the insulating layer 14. In this way, the manufacturing process of the thin film transistor can be simplified and the cost can be saved.

[0089] Optional, such as Figure 5 As shown, the thin film transistor is a bottom gate thin film transistor; the gate insulating layer 16 is arranged on the side of the insulating layer 14 close to the substrate 10. Alternatively, as Figure 7 As shown, the thin film transistor is a top-gate thin film transistor or a double-gate thin film transistor; the thin film transistor also includes a buffer layer 17 arranged on the substrate 10, and the buffer layer 17 is arranged on the side of the insulating layer 14 close to the substrate 10.

[0090] Optionally, the groove 141 may pass through the insulating layer 14 or may not pass through the insulating layer 14 . Figure 5 and Figure 7 Only the case where the groove 141 penetrates the insulating layer 14 is shown.

[0091] In an embodiment of the present invention, the insulating layer 14 may be disposed at different positions for different types of thin film transistors.

[0092] Optional, such as Fig.10 As shown, the thin film transistor is a bottom-gate thin film transistor; the gate insulating layer 16 is disposed on the side of the insulating layer 14 close to the substrate 10 , and the modification pattern 20 is in direct contact with the gate insulating layer 16 .

[0093] Optionally, the material of the modification pattern 20 may chemically react with the material of the gate insulating layer 16 , so that the modification pattern 20 is in direct contact with the gate insulating layer 16 .

[0094] Here, the material of the modified pattern 20 may be an amphoteric coupling agent, wherein one group of the amphoteric coupling agent chemically reacts with the carbon nanotubes 111 , and the other group chemically reacts with the material of the gate insulating layer 16 .

[0095] For example, the amphoteric coupling agent is a silane coupling agent, for example, 3-aminopropyltriethoxysilane (APTES). The material of the gate insulating layer 16 is silicon oxide (SiO x ), hafnium dioxide (HfO2), or a composite film of magnesium oxide (MgO) and HfO2. The material of the insulating layer 14 is a hydrophobic insulating material, such as silicon nitride (SiN x ).

[0096] The silane coupling agent includes amino and carboxyl groups. The carboxyl groups condense with the material of the gate insulating layer 16 to form a self-assembled monolayer; the amino groups chemically react with the carbon nanotubes 111 and adsorb them on the surface of the modified pattern 20 .

[0097] Or, if Fig.11 and Fig.12 As shown, the thin film transistor is a top-gate thin film transistor or a double-gate thin film transistor; the buffer layer 17 is arranged on the side of the insulating layer 14 close to the substrate 10 , and the modification pattern 20 is in direct contact with the buffer layer 17 .

[0098] Optionally, the material of the modification pattern 20 may chemically react with the material of the buffer layer 17 , so that the modification pattern 20 is in direct contact with the buffer layer 17 .

[0099] Here, the material of the modified pattern 20 may be an amphoteric coupling agent, wherein one group of the amphoteric coupling agent chemically reacts with the carbon nanotubes 111 , and the other group chemically reacts with the material of the buffer layer 17 .

[0100] For example, the amphoteric coupling agent is a silane coupling agent, such as APTES. The material of the buffer layer 17 is SiO x , HfO2, or a composite film of MgO and HfO2. The material of the insulating layer 14 is a hydrophobic insulating material, such as SiN x .

[0101] The silane coupling agent includes amino and carboxyl groups. The carboxyl groups condense with the material of the buffer layer 17 to form a self-assembled monolayer; the amino groups chemically react with the carbon nanotubes 111 and adsorb them on the surface of the modified pattern 20 .

[0102] In the embodiment of the present invention, when the groove 141 passes through the insulating layer 14, if the thin film transistor is a bottom-gate thin film transistor, the material of the modification pattern 20 can be chemically reacted with the material of the gate insulating layer 16 to fix the modification pattern 20 on the gate insulating layer 16; if the thin film transistor is a top-gate thin film transistor or a double-gate thin film transistor, the material of the modification pattern 20 can be chemically reacted with the material of the buffer layer 17 to fix the modification pattern 20 on the buffer layer 17.

[0103] Optional, such as Figure 8b As shown, the width of the cross section of the stripe sub-pattern 11 is in the range of greater than or equal to 500 nm and less than 1000 nm.

[0104] For example, the width of the cross section of the stripe sub-pattern 11 is 500 nm, 655 nm, or 1000 nm.

[0105] Since the diameter of the carbon nanotube 111 is about 1 nm and the length is about 1000 nm, the length of the carbon nanotube 111 is much larger than its diameter.

[0106] Based on this, in the embodiment of the present invention, since the length of the carbon nanotube 111 is much larger than its diameter, the smaller the width of the cross section of the stripe sub-pattern 11, the smaller the angle between each carbon nanotube 111 and the first direction. In the embodiment of the present invention, the carbon nanotube 111 is limited to a region with a width greater than or equal to 500nm and less than 1000nm, so that the angle between each carbon nanotube 111 and the first direction is small, and the angle between multiple carbon nanotubes 111 can be ignored, thereby improving the mobility of the thin film transistor.

[0107] The embodiment of the present invention further provides a display device, including an array substrate 21, such as Fig.13 and Fig.14 As shown, the array substrate 21 includes a pixel circuit, and the pixel circuit includes a driving transistor 31; the driving transistor 31 is a thin film transistor described in any of the above embodiments.

[0108] On the basis of the above, the pixel circuit further includes a switch transistor and a storage capacitor. The switch transistor can be a thin film transistor as described in any of the above embodiments, or the switch transistor can also be a thin film transistor in the prior art.

[0109] Here, taking the pixel circuit of 2T1C as an example, the pixel circuit includes at least one switching transistor, one driving transistor 31, and one storage capacitor. The source 12 of the switching transistor is connected to the data signal terminal, and the drain 13 is connected to the gate 15 of the driving transistor 31 and one end of the storage capacitor. The source 12 of the driving transistor 31 is connected to the VDD signal line or signal terminal, and the drain 13 is connected to the other end of the storage capacitor and one end of the light-emitting device (such as the first electrode or LED light-emitting unit below). The other end of the light-emitting device is connected to the VSS signal line or signal terminal.

[0110] Optionally, the display device may be an OLED display device, a QLED display device, or a LED display device.

[0111] like Fig.13 As shown, in the case where the display device is an OLED display device or a QLED display device, the OLED display device or the QLED display device includes an array substrate 21, and the array substrate 21 also includes a plurality of light-emitting devices arranged on the side of the thin film transistor away from the substrate 10, and the light-emitting devices include a first electrode 42, a light-emitting layer 43, and a second electrode 44 stacked in sequence, and the first electrode 42 is electrically connected to the drain 13 of the driving transistor 31. On this basis, the array substrate 21 also includes a pixel defining layer 45 arranged between adjacent light-emitting devices.

[0112] The first electrode 42 is an anode, and the second electrode 44 is a cathode; or the first electrode 42 is a cathode, and the second electrode 44 is an anode.

[0113] If the display device is an OLED display device, the light-emitting layer 43 is an organic light-emitting functional layer; if the display device is a QLED display device, the light-emitting layer 43 is a quantum dot light-emitting layer.

[0114] like Fig.14 As shown, in the case where the display device is an LED display device, the array substrate 21 also includes an LED light-emitting unit 41 arranged on the side of the thin film transistor away from the substrate 10, the LED light-emitting unit 41 is electrically connected to the drain 13 of the driving transistor 31, and the cathode of the LED light-emitting unit 41 is connected to the VSS signal line or signal terminal.

[0115] The embodiment of the present invention provides a display device. Since the driving transistor 31 generally requires a higher mobility, the thin film transistor of the embodiment of the present invention can be used as the driving transistor 31 to improve the light emitting efficiency.

[0116] The present invention also provides a method for preparing a thin film transistor. Fig.15 As shown, this can be achieved through the following steps:

[0117] S11, such as Fig.16As shown, an insulating film is formed on a substrate 10 , and a plurality of strip-shaped grooves 141 extending along a first direction and arranged at intervals are formed in the insulating film to obtain an insulating layer 14 .

[0118] Optional, such as Fig. 9 As shown, no matter one or more thin film transistors are disposed on the substrate 10 , the distance between the surface of the other parts of the insulating layer 14 except the groove 141 and the substrate 10 is the same.

[0119] Optionally, the method of forming the insulating layer may be different depending on the material of the insulating layer 14 .

[0120] For example, if the material of the insulating layer 14 includes an inorganic insulating material or a photosensitive material, a photolithography process may be used to form the insulating layer 14 including the plurality of grooves 141 .

[0121] S12, such as Fig.17 As shown, an active pattern including carbon nanotubes is formed on the side of the insulating layer 14 facing away from the substrate 10; the active pattern includes a plurality of strip sub-patterns 11 arranged at intervals; the strip sub-patterns 11 correspond one-to-one to the grooves 141, and the orthographic projection of the strip sub-pattern 11 on the substrate 10 and the orthographic projection of the corresponding groove 141 on the substrate 10 completely overlap.

[0122] Optionally, since the stripe sub-patterns 11 extend along the first direction, and along the first direction, one end of each stripe sub-pattern 11 in the active pattern contacts the source 12 and the other end contacts the drain 13. Therefore, the first direction, i.e., the direction of the source 12 to be formed points to the drain 13.

[0123] Here, along the first direction, each stripe sub-pattern 11 has two opposite ends, so it is clear and unique that one end of the stripe sub-pattern 11 contacts the source electrode 12 and the other end contacts the drain electrode 13 .

[0124] Optionally, since the carbon nanotubes 111 in the embodiment of the present invention are used as active patterns, the carbon nanotubes 111 used in the embodiment of the present invention are semiconductor carbon nanotubes.

[0125] Here, the raw material of carbon nanotubes includes metallic carbon nanotubes and semiconductor carbon nanotubes. In the embodiment of the present invention, the metallic carbon nanotubes in the raw material of carbon nanotubes can be removed by centrifugation, filtration, etc. to obtain the semiconductor carbon nanotubes.

[0126] For example, the metallic carbon nanotubes in the carbon nanotube raw material are removed by centrifugation. A polymer may be added to the carbon nanotube raw material first; and multiple semiconductor carbon nanotubes and metallic carbon nanotubes in the carbon nanotubes are dispersed into independent individuals by ultrasonic dispersion, and the polymer reacts with the semiconductor carbon nanotubes and wraps on the surface of the semiconductor carbon nanotubes to prevent any semiconductor carbon nanotube from contacting the metallic carbon nanotubes and other semiconductor carbon nanotubes; and then, according to the density difference between the semiconductor carbon nanotubes and the metallic carbon nanotubes, the semiconductor carbon nanotubes are separated by centrifugation.

[0127] On this basis, the polymer on the surface of the semiconductor carbon nanotube can also be removed, for example, by using a solvent.

[0128] Optionally, the number of the stripe sub-patterns 11 in the active pattern is not limited. The number of the stripe sub-patterns 11 in the active pattern is related to the size of the source 12 and the drain 13 to be formed, and the width of the cross section of each stripe sub-pattern 11 .

[0129] Optionally, the sizes of the multiple stripe sub-patterns 11 in the active pattern may be the same or different.

[0130] Alternatively, those skilled in the art should know that the shape of the carbon nanotube 111 can be approximately regarded as a cylinder, wherein the diameter of the carbon nanotube 111 (the diameter of the bottom of the cylinder) is about 1 nm, and the length (the height of the cylinder) is about 1000 nm.

[0131] The embodiment of the present invention does not limit the width range of the cross-section of the plurality of stripe sub-patterns 11. The width of the cross-section of each stripe sub-pattern 11 should be at least greater than or equal to the diameter of a carbon nanotube 111 and less than the length of the carbon nanotube to achieve the sequential arrangement of the plurality of carbon nanotubes.

[0132] For example, the width of the cross section of the stripe sub-pattern 11 is in the range of greater than or equal to 1 nm and less than 1000 nm.

[0133] The size of the stripe sub-pattern 11 along the first direction is not limited, and the size of the stripe sub-pattern 11 along the first direction is related to the distance between the source electrode 12 and the drain electrode 13 , and the size of the carbon nanotube 111 .

[0134] Optionally, the method of forming the active pattern is not limited.

[0135] For example, a carbon nanotube 111 solution may be formed on the substrate 10 by spraying, spin coating, scraping, inkjet printing, etc.; then, the carbon nanotube 111 solution is dried at high temperature to obtain a carbon nanotube film.

[0136] If a carbon nanotube solution is formed in the groove 141 by spraying, spin coating, scraping, etc., after obtaining the carbon nanotube film, it is necessary to form a photoresist on the side of the carbon nanotube film away from the substrate 10; the photoresist is exposed and developed to form a photoresist pattern; finally, the carbon nanotube film is etched to obtain the active pattern, and the photoresist pattern is peeled off.

[0137] If the carbon nanotube solution is formed by inkjet printing, the obtained carbon nanotube film is the active pattern.

[0138] S13. Reference Figure 4-Figure 7 As shown, a source 12 and a drain 13 are formed on the side of the active pattern away from the substrate 10 , and along the first direction, one end of each stripe sub-pattern 11 in the active pattern contacts the source 12 , and the other end contacts the drain 13 .

[0139] Optionally, the material of the source electrode 12 and the drain electrode 13 may include metal materials such as Mo, Cu, MoNb, Al, etc.; the material of the source electrode 12 and the drain electrode 13 may also include transparent conductive materials such as ITO, etc.

[0140] The source electrode 12 and the drain electrode 13 may be a single layer or multiple layers. For example, the source electrode 12 and the drain electrode 13 include a single layer made of copper; or the source electrode 12 and the drain electrode 13 include two layers, one of which is made of Cr and the other is made of Au.

[0141] An embodiment of the present invention provides a method for manufacturing a thin film transistor, which has the same technical effect as the aforementioned thin film transistor and will not be described in detail herein.

[0142] Optional, such as Figure 10-12 As shown, the groove 141 penetrates the insulating layer 14; after forming the insulating layer 14 and before forming the active pattern, the method for preparing the thin film transistor further includes: filling each groove 141 with a modification pattern 20; the modification pattern 20 is arranged on the side of the active pattern close to the substrate 10, the modification pattern 20 corresponds to and directly contacts the stripe sub-pattern 11, and the orthographic projection of the modification pattern 20 on the substrate 10 and the orthographic projection of the corresponding stripe sub-pattern 11 on the substrate 10 completely overlap. Fig.10 As shown, the thin film transistor is a bottom-gate thin film transistor, and the modification pattern 20 is in direct contact with the gate insulating layer 16 disposed on the side of the insulating layer 14 close to the substrate 10; or Fig.11 and Fig.12 As shown, the thin film transistor is a top gate thin film transistor or a double gate thin film transistor, and the modification pattern 20 is in direct contact with the buffer layer 17 disposed on the side of the insulating layer 14 close to the substrate 10. The material of the modification pattern 20 does not chemically react with the material of the insulating layer 14.

[0143] Optionally, the material of the modification pattern 20 is not limited. On the one hand, the material of the modification pattern 20 can chemically react with the carbon nanotubes 111, so that the stripe sub-pattern 11 is only formed on the modification pattern 20; on the other hand, when the groove 141 passes through the insulating layer 14, the material of the modification pattern 20 does not chemically react with the material of the insulating layer 14, so as to avoid the modification pattern 20 from being formed on the surface of the insulating layer 14 on the side away from the substrate 10, thereby avoiding the active pattern from being formed in the area other than the area where the groove 141 is located; on the other hand, if the thin film transistor is a bottom-gate thin film transistor, the material of the modification pattern 20 can also chemically react with the material of the gate insulating layer 16, so that the modification pattern 20 is fixed on the gate insulating layer 16; or, if the thin film transistor is a top-gate thin film transistor or a double-gate thin film transistor, the material of the modification pattern 20 can also chemically react with the material of the buffer layer 17, so that the modification pattern 20 is fixed on the buffer layer 17.

[0144] Here, the material of the modified pattern 20 may be an amphoteric coupling agent, wherein one group of the amphoteric coupling agent chemically reacts with the carbon nanotubes 111 , and the other group chemically reacts with the material of the gate insulating layer 16 (or the buffer layer).

[0145] For example, the amphoteric coupling agent is a silane coupling agent, such as APTES. The material of the gate insulating layer 16 is SiO x , HfO2, or a composite film of MgO and HfO2. The material of the insulating layer 14 (or buffer layer) is a hydrophobic insulating material, such as SiN x .

[0146] The silane coupling agent includes amino and carboxyl groups. The carboxyl groups condense with the material of the gate insulating layer 16 (or buffer layer) to form a self-assembled monolayer; the amino groups chemically react with the carbon nanotubes 111 and adsorb them on the surface of the modified pattern 20 .

[0147] Optional, such as Fig.10 As shown, the thickness of the modification pattern 20 is smaller than the depth of the corresponding groove 141 .

[0148] Or, if Fig.11 and Fig.12 As shown, the thickness of the modification pattern 20 is exactly equal to the depth of the corresponding groove 141 .

[0149] Alternatively, the thickness of the modification pattern 20 is greater than the depth of the corresponding groove 141 .

[0150] In the embodiment of the present invention, the modification pattern 20 is first formed in the groove 141, and then the stripe sub-pattern 11 is formed on the side of the modification pattern 20 away from the substrate 10. Since the material of the modification pattern 20 does not chemically react with the material of the insulating layer 14, the modification pattern 20 is only formed in the groove 141; since the material of the modification pattern 20 can chemically react with the carbon nanotubes 111, the modification pattern 20 can firmly adsorb and fix the carbon nanotubes 111, so that the stripe sub-pattern 11 is only formed on the modification pattern 20. At the same time, in the case where the groove 141 passes through the insulating layer 14, if the thin film transistor is a bottom-gate thin film transistor, the material of the modification pattern 20 can chemically react with the material of the gate insulating layer 16 to fix the modification pattern 20 on the gate insulating layer 16; if the thin film transistor is a top-gate thin film transistor or a double-gate thin film transistor, the material of the modification pattern 20 can chemically react with the material of the buffer layer 17 to fix the modification pattern 20 on the buffer layer 17.

[0151] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A thin film transistor, characterized in that: The device comprises an insulating layer disposed on a substrate, an active pattern including carbon nanotubes, a source electrode and a drain electrode; the carbon nanotubes are semiconductor carbon nanotubes; The active pattern includes a plurality of stripe sub-patterns extending along a first direction and arranged at intervals; Along the first direction, one end of each of the stripe sub-patterns in the active pattern is in contact with the source electrode, and the other end is in contact with the drain electrode; the width of the cross section of the stripe sub-pattern is greater than or equal to 500nm and less than 1000nm; the cross section is perpendicular to the thickness direction of the substrate, and the width of the cross section is perpendicular to the first direction; The insulating layer comprises a plurality of strip-shaped grooves, the grooves correspond to the strip-shaped sub-patterns one by one, and the orthographic projections of the grooves on the substrate completely overlap with the orthographic projections of the strip-shaped sub-patterns on the substrate; The groove passes through the insulating layer; Each of the grooves is filled with a modified pattern; The active pattern is arranged on the side of the modification pattern away from the substrate; the modification pattern corresponds to and directly contacts the stripe sub-patterns one by one, and the orthographic projection of the modification pattern on the substrate and the orthographic projection of the corresponding stripe sub-pattern on the substrate completely overlap; Wherein, the material of the modification pattern does not chemically react with the material of the insulating layer; the material of the modification pattern is an amphoteric coupling agent, and the amphoteric coupling agent is a silane coupling agent; The sum of the thickness of the modification pattern and the stripe sub-pattern is greater than the depth of the corresponding groove.

2. The thin film transistor according to claim 1, characterized in that: The thin film transistor is a bottom-gate thin film transistor; the insulating layer is arranged on a side of the active pattern close to the substrate; the groove does not penetrate the insulating layer; Alternatively, the thin film transistor is a top-gate thin film transistor or a dual-gate thin film transistor; the insulating layer is arranged on a side of the active pattern close to the substrate; and the groove does not penetrate the insulating layer.

3. The thin film transistor according to claim 1, characterized in that: The thin film transistor is a bottom-gate thin film transistor; the thin film transistor further comprises a gate insulating layer disposed on the substrate, the gate insulating layer being disposed on a side of the insulating layer close to the substrate; Alternatively, the thin film transistor is a top-gate thin film transistor or a double-gate thin film transistor; the thin film transistor further comprises a buffer layer disposed on the substrate, and the buffer layer is disposed on a side of the insulating layer close to the substrate.

4. The thin film transistor according to claim 1, characterized in that: The thin film transistor is a bottom-gate thin film transistor; the thin film transistor further comprises a gate insulating layer disposed on the substrate, the gate insulating layer is disposed on a side of the insulating layer close to the substrate, and the modified pattern is in direct contact with the gate insulating layer; Alternatively, the thin film transistor is a top-gate thin film transistor or a dual-gate thin film transistor; the thin film transistor also includes a buffer layer arranged on the substrate, the buffer layer is arranged on a side of the insulating layer close to the substrate, and the modification pattern is in direct contact with the buffer layer.

5. The thin film transistor according to claim 4, characterized in that: The material of the insulating layer is a hydrophobic insulating material; The material of the gate insulating layer in the bottom-gate thin film transistor may chemically react with a carboxyl group; or the material of the buffer layer in the top-gate thin film transistor or the dual-gate thin film transistor may chemically react with a carboxyl group.

6. A display device, characterized in that: An array substrate is included, wherein the array substrate includes a pixel circuit, and the pixel circuit includes a driving transistor; The driving transistor is a thin film transistor according to any one of claims 1 to 5.

7. A method for preparing a thin film transistor, characterized in that: include: An insulating film is formed on a substrate, and a plurality of strip-shaped grooves extending along a first direction and arranged at intervals are formed in the insulating film to obtain an insulating layer; the grooves penetrate the insulating layer; An active pattern including carbon nanotubes is formed on the side of the insulating layer away from the substrate; the carbon nanotubes are semiconductor carbon nanotubes; the active pattern includes a plurality of stripe sub-patterns arranged at intervals, the stripe sub-patterns correspond to the grooves one by one, and the orthographic projection of the stripe sub-pattern on the substrate and the orthographic projection of the corresponding groove on the substrate completely overlap; the width of the cross section of the stripe sub-pattern is greater than or equal to 500nm and less than 1000nm; the cross section is perpendicular to the thickness direction of the substrate, and the width of the cross section is perpendicular to the first direction; A source electrode and a drain electrode are formed on a side of the active pattern away from the substrate, and along the first direction, one end of each stripe sub-pattern in the active pattern is in contact with the source electrode, and the other end is in contact with the drain electrode; After forming the insulating layer and before forming the active pattern, the method for preparing the thin film transistor further includes: filling each of the grooves with a modified pattern; The modification pattern is arranged on the side of the active pattern close to the substrate, the modification pattern corresponds to the strip sub-pattern one by one and is in direct contact with the strip sub-pattern, the orthographic projection of the modification pattern on the substrate and the orthographic projection of the corresponding strip sub-pattern on the substrate completely overlap; the sum of the thickness of the modification pattern and the strip sub-pattern is greater than the depth of the corresponding groove; the material of the modification pattern does not chemically react with the material of the insulating layer; the material of the modification pattern is an amphoteric coupling agent, and the amphoteric coupling agent is a silane coupling agent.

8. The method for preparing a thin film transistor according to claim 7, characterized in that: The thin film transistor is a bottom-gate thin film transistor, and the modified pattern is in direct contact with a gate insulating layer disposed on a side of the insulating layer close to the substrate; or the thin film transistor is a top-gate thin film transistor or a double-gate thin film transistor, and the modified pattern is in direct contact with a buffer layer disposed on a side of the insulating layer close to the substrate; The material of the modification pattern does not chemically react with the material of the insulating layer.

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