A voltage-mode phase interpolator circuit

Abstract

The present invention discloses a voltage-mode phase interpolator circuit, comprising: a voltage-mode phase interpolator, wherein a power supply terminal of the voltage-mode phase interpolator is connected to an LDO current transistor controlled by a DLL lpf. The LDO current transistor controlled by the DLL lpf is used to control the power supply of the phase interpolation module. Only by optimizing the linearity of the phase interpolator at the normal operating voltage and room temperature, at different PVTs, the lpf of the DLL will find a suitable operating voltage to control the current of the phase interpolation module, so that at different PVTs, the phase interpolator can obtain a relatively satisfactory linearity.

Description

Technical Field

[0001] The present invention relates to a voltage-mode phase interpolator circuit. Background Art

[0002] In recent years, as the requirement for the data throughput of chip design has driven the chip industry to shift from low-speed data parallel connection to high-speed serial connection. In the design of high-speed serial transmission interface circuits, there are two basic SERDES (Serializer / Deserializer) interfaces: source synchronous and clock data recovery (CDR) protocols. The main difference between these two types lies in the clock. The source synchronous interface has a clock signal accompanying the data, such as the MIPI_PHY (mobile industry process interface) which has such a structure; CDR does not have a separate clock signal, but recovers the clock from the data, such as the USB3 / 3.1 (universal serial bus) or PCIE (peripheral component interconnect express) protocols. Usually, the CDR protocol operates at a higher data rate and a longer transmission distance, thus bringing great design challenges.

[0003] The phase interpolator is an important core module in CDR design. It reduces the bit error rate of data reception by controlling the clock delay to track the jitter of the input data in real time. Since the transmitted data speed is extremely fast, generally reaching Gb / s, it is often required that the clock delay of each stage in the design is in the ps-level clock unit. Therefore, the design of the phase interpolator for controlling the clock delay is a difficult point.

[0004] In actual design, there are many non-ideal factors (such as incompletely matched capacitive loads, noise coupling of signal lines, and PVT processes) that affect the performance of the phase interpolator. The traditional phase interpolation circuit is affected by the power supply voltage and temperature changes. The integral nonlinearity varies greatly in different interpolation steps (the interval change of each jump will be very large, and even cause the nonlinearity of the phase interpolator, thus affecting the CDR locking. If the phase interpolator is ideal, then its transfer function will be the same as Figure 2It coincides with the straight line 1 in []. Due to process problems, even if we adjust the behavior of the circuit to the straight line 1 under typical process and normal temperature (the traditional process corner in chip production, room temperature), the driving ability of the inverter varies greatly with the process under fast process and high temperature (the fast process corner in chip manufacturing, high temperature state) or slow process and low temperature (the slow process corner in chip manufacturing, low temperature state). As a result, signals 2, 3, and 4 appear in the transfer function of the phase interpolator, which will not only deteriorate the CDR jitter tolerance (the tolerance of the clock data recovery circuit to noise) ability, but even cause the CDR to lose lock in severe cases. Summary of the Invention

[0005] The object of the present invention is to provide a voltage-type phase interpolator circuit that can obtain relatively satisfactory linearity under different PVTs.

[0006] The technical solution to achieve the above object is:

[0007] A voltage-type phase interpolator circuit includes: a voltage-type phase interpolator, and the power supply terminal of the voltage-type phase interpolator is connected to an LDO current tube controlled by a DLL lpf.

[0008] Preferably, the voltage-type phase interpolator includes: a first data selector, a second data selector, a first inverter, a second inverter, and a third inverter, where

[0009] Two input terminals of the first data selector are connected to a clock signal clk0 with a 0-degree phase and a clock signal clk180 with a 180-degree phase; the control terminal receives a first phase selection signal of the clock signal clk0 and the clock signal clk180; the output terminal is connected to the input terminal of the first inverter and outputs a selected interpolation signal;

[0010] The control terminal of the first inverter receives a weight selection signal of the weights of the two interpolation signals output by the first data selector; the output terminal is connected to the input terminal of the third inverter;

[0011] The output terminal of the third inverter serves as the output terminal of the voltage-type phase interpolator;

[0012] Two input terminals of the second data selector are connected to a clock signal clk90 with a 90-degree phase and a clock signal clk270 with a 270-degree phase; the control terminal receives a second phase selection signal of the clock signal clk90 and the clock signal clk270; the output terminal is connected to the input terminal of the second inverter and outputs a selected interpolation signal;

[0013] The control terminal of the second inverter receives the weight selection signal of the weights of the two interpolation signals output by the second data selector; the output terminal is connected to the input terminal of the third inverter.

[0014] Preferably, the voltage-mode phase interpolator further includes a logic control unit configured to decode the required phase selection signal and weight selection signal from the input signal;

[0015] This logic control unit decodes and outputs a first phase selection signal and a second phase selection signal from the first input signal;

[0016] This logic control unit decodes and outputs a weight selection signal from the second input signal.

[0017] Preferably, the lpf outputs Vlpf to the LDO current transistor.

[0018] The beneficial effects of the present invention are as follows: Based on the voltage-mode phase interpolator, the present invention uses an LDO current transistor controlled by a DLL lpf to control the power supply of the phase interpolation module. By using the filter output voltage of the delay locked loop to simultaneously regulate the power supply of the voltage-mode phase interpolator and the power supply of the delay units of the delay locked loop, it is ensured that the voltage-mode linear interpolator can achieve good differential nonlinearity at different process corners. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is the circuit diagram of the voltage-mode phase interpolator circuit of the present invention;

[0020] Figure 2 is the schematic diagram of the transfer function of the voltage-mode phase interpolator circuit of the present invention. DETAILED DESCRIPTION

[0021] The present invention will be further described below in conjunction with the accompanying drawings.

[0022] Please refer to Figure 1 , the voltage-mode phase interpolator circuit of the present invention includes: a voltage-mode phase interpolator, the power supply terminal of which is connected to an LDO (low dropout voltage) current transistor 100 controlled by a DLL (delay locked loop) lpf (loop filter), that is: an LDO current transistor controlled by a DLL lpf is used to control the power supply of the voltage-mode phase interpolator. The lpf outputs a Vlpf (output signal of the filter) signal to the LDO current transistor.

[0023] Specifically, the voltage-mode phase interpolator includes: a first data selector 1, a second data selector 2, a first inverter 3, a second inverter 4, and a third inverter 5.

[0024] The two input terminals of the first data selector 1 are connected to the clock signal clk0 with a 0-degree phase and the clock signal clk180 with a 180-degree phase; the control terminal of the first data selector 1 receives the first phase selection signals phsel<0>&phselb<0> of the clock signal clk0 and the clock signal clk180, and phsel<0> and phselb<0> are a set of reverse signals. When phsel<0> = 1, clk0 is selected as one interpolation signal; if phsel<0> = 0, clk180 is selected as one interpolation signal. The output terminal of the first data selector 1 is connected to the input terminal of the first inverter 3, and the interpolation signal is output.

[0025] The control terminal of the first inverter 3 receives the weight selection signals Selb<31:0>&sel<31:0> representing the weights of the two interpolation signals. Selb<31:0> and sel<31:0> are a set of reverse signals, and at any moment, the sum of the weights of the two interpolation signals of the phase interpolator is guaranteed to be 32. The output terminal of the first inverter 3 is connected to the input terminal of the third inverter 5. The output terminal of the third inverter 5 is used as the output terminal of the voltage-mode phase interpolator.

[0026] The two input terminals of the second data selector 2 are connected to the clock signal clk90 with a 90-degree phase and the clock signal clk270 with a 270-degree phase; the control terminal receives the second phase selection signals phsel<1>&phselb<1> of the clock signal clk90 and the clock signal clk270, and phsel<1> and phselb<1> are a set of reverse signals. When phsel<1> = 1, clk90 is selected as the other interpolation signal; if phsel<1> = 0, clk270 is selected as the other interpolation signal. The output terminal of the second data selector 2 is connected to the input terminal of the second inverter 4. The control terminal of the second inverter 4 receives the weight selection signals Selb<31:0>&sel<31:0> representing the weights of the two interpolation signals. The output terminal of the second inverter 4 is connected to the input terminal of the third inverter 5.

[0027] The voltage-mode phase interpolator further includes: a logic control unit 6, whose main purpose is to decode the required phase selection signals and weight selection signals according to the input signals. That is: the logic control unit 6 receives the first input signal phase_sel<1:0> and the second input signal mixer_sel<31:0>, and decodes the first phase selection signals phsel<0>&phselb<0> and the second phase selection signals phsel<1>&phselb<1> from the first input signal phase_sel<1:0>; and decodes the weight selection signals Selb<31:0>&sel<31:0> from the second input signal mixer_sel<31:0>.

[0028] Interpolate between every two adjacent clock signals to generate a clock signal with any phase delay between 0 degrees and 360 degrees. Among them, clk0 / clk90 / clk180 / clk270 are four clocks with a phase difference of 90 degrees (where clk0 represents the 0-degree phase clock, clk90 represents the clock with a phase delay of 90 degrees relative to clk0, clk180 represents the clock with a phase delay of 180 degrees relative to clk0, and clk270 represents the clock with a phase delay of 270 degrees relative to clk0), and they come from the DLL circuit. The first multiplexer 1 and the second multiplexer 2 in the figure respectively select the signals for phase interpolation, and can respectively select to interpolate between clk0 / clk90, clk90 / clk180, clk180 / clk270, clk270 / clk0. The two selected signals serve as the inputs of the inverters (i.e., the first inverter 3 or the second inverter 4) at the rear stage of the MUX (multiplexer). The specific degree of phase interpolation is achieved by the weight selection signals Selb<31:0>&sel<31:0> to control the weights of the first inverter 3 or the second inverter 4.

[0029] In the prior art, the power supply voltage of the voltage-mode phase interpolator is controlled by core VDD (in general processes, the core voltage refers to the low-voltage device). The disadvantage is that at low temperature and low voltage, core VDD is too low, the capacitive load is too large, and the driving ability of the phase interpolator is insufficient, often resulting in functional failure. In the case of high temperature and high voltage, core VDD is too high, the driving ability of the phase interpolator is too strong, and it is more vulnerable to power supply voltage noise interference compared to the differential phase interpolator, thus affecting the linearity of the phase interpolator. Now it is controlled by the LDO current tube, and the influence of power supply voltage interference on the linearity of the phase interpolator will be reduced. At low temperature and low voltage, in order to output clock signals with the same delay, the lpf of the DLL will stabilize at a potential higher than the normal operating voltage, providing more current to the phase interpolator. At high temperature and high voltage, in order to output clock signals with the same delay, the lpf of the DLL will stabilize at a potential lower than the normal operating voltage, thereby providing a relatively low current to the phase interpolator. As long as the linearity of the phase interpolator at the normal operating voltage and room temperature is optimized, at different PVTs (process, voltage and temperature, representing the state when the voltage, process angle and temperature change during the process production), the lpf of the DLL will find a suitable operating voltage to control the current of the phase interpolation module. Therefore, at different PVTs, the phase interpolator will obtain relatively satisfactory linearity. Figure 2 The transfer function of the phase interpolator circuit in the middle will approximate from curves 2, 3, 4 to 1.

[0030] The above embodiments are only for illustrating the present invention and not for limiting the present invention. Those skilled in the relevant technical field can also make various transformations or modifications without departing from the spirit and scope of the present invention. Therefore, all equivalent technical solutions should also fall within the scope of the present invention and should be defined by each claim.

Claims

1. A voltage - type phase interpolator circuit, characterized in that, it includes: A voltage - type phase interpolator, the power supply terminal of which is connected to an LDO current tube controlled by a DLL lpf; The voltage - type phase interpolator includes: a first multiplexer, a second multiplexer, a first inverter, a second inverter and a third inverter, where, Two input terminals of the first multiplexer are connected to a clock signal clk0 with a 0 - degree phase and a clock signal clk180 with a 180 - degree phase; the control terminal receives a first phase - selection signal of the clock signal clk0 and the clock signal clk180; the output terminal is connected to the input terminal of the first inverter and outputs a selected interpolation signal; The control terminal of the first inverter receives a weight - selection signal of the weights of the two interpolation signals output by the first multiplexer; the output terminal is connected to the input terminal of the third inverter; The output terminal of the third inverter serves as the output terminal of the voltage - type phase interpolator; Two input terminals of the second multiplexer are connected to a clock signal clk90 with a 90 - degree phase and a clock signal clk270 with a 270 - degree phase; the control terminal receives a second phase - selection signal of the clock signal clk90 and the clock signal clk270; the output terminal is connected to the input terminal of the second inverter and outputs a selected interpolation signal; The control terminal of the second inverter receives a weight - selection signal of the weights of the two interpolation signals output by the second multiplexer; the output terminal is connected to the input terminal of the third inverter.

2. The voltage - type phase interpolator circuit according to claim 1, characterized in that, The voltage - type phase interpolator further includes: a logic control unit that decodes the required phase - selection signal and weight - selection signal according to the input signal; This logic control unit decodes the first input signal to output a first phase - selection signal and a second phase - selection signal; This logic control unit decodes the second input signal to output a weight - selection signal.

3. The voltage - type phase interpolator circuit according to claim 1, characterized in that, The lpf outputs Vlpf to the LDO current tube.

Images