Series-connected transistors

Abstract

Embodiments of the present disclosure generally relate to transistors in series. An apparatus including transistors connected in series is disclosed. In an embodiment, the apparatus includes a first transistor, a second transistor connected to the first transistor, and a third transistor connected to the second transistor, wherein the transistors are connected in series, and wherein the third transistor is configured to be controlled by a digital signal.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to French Patent Application No. 1904484, filed on April 26, 2019, the entire content of which is incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to electronic devices, and more particularly to a chip integrating one or more input-output circuits including connection pads. Background Art

[0004] Input-output circuits integrated in a chip including so-called "electricity-intolerant" connection pads are known. These electricity-intolerant pads generally have means for preventing possible current injection. In some cases, current injection via the connection pads has a harmful effect on the chip. Therefore, it is desirable to prevent these current injections by using diodes. One drawback of using these diode bars is that it limits the range of input voltages allowable by the circuit. This limitation is sometimes harmful to certain applications that require a larger voltage range.

[0005] Input-output circuits including so-called "electricity-tolerant" connection pads are also known. Compared with circuits equipped with electricity-intolerant pads, the range of allowable input voltages can be expanded by means of these circuits equipped with electricity-tolerant pads at the risk of reducing the chip and the degradation of the signals applied to the pads. For specific applications, it is especially possible to make the potential of these electricity-tolerant pads much higher than the power supply potential for supplying the chip. However, in some applications, the electricity-intolerant pads cannot be replaced by electricity-tolerant pads.

[0006] Currently, before manufacturing the chip, the type of pad (electricity-tolerant or electricity-intolerant pad) of each input-output circuit has been determined. Most of the time, this decision is determined by the target application. Once the chip has been manufactured, the type of pad of each input-output circuit can no longer be modified. Therefore, this brings poor flexibility to the existing input-output circuits. Summary of the Invention

[0007] Embodiments provide flexibility for existing input-output circuits.

[0008] One embodiment addresses all or some of the drawbacks of known input-output circuits.

[0009] One embodiment provides a device including, in series, a first transistor, a second transistor connected to the first transistor, and a third transistor connected to the second transistor, the third transistor being controlled by a digital signal.

[0010] According to one embodiment, the transistor is a MOS transistor.

[0011] According to one embodiment, the first transistor is a P-type transistor, the second transistor is an N-type transistor, and the third transistor is an N-type transistor.

[0012] According to one embodiment, the drain of the second transistor is connected to the drain of the first transistor, and the source of the second transistor is connected to the drain of the third transistor.

[0013] According to one embodiment, a reference potential is applied to the source of the third transistor.

[0014] According to one embodiment, a DC voltage is applied between the common gate of the first and second transistors and the source of the third transistor.

[0015] According to one embodiment, a digital signal is adapted to control the flow of current in a series combination in an on / off manner.

[0016] According to one embodiment, depending on the state of the digital signal controlling the third transistor, the series combination sometimes forms a diode and sometimes forms an open circuit.

[0017] One embodiment provides a device including only three transistors as described.

[0018] One embodiment provides an electronic chip including at least one such device.

[0019] According to one embodiment, the source of the first transistor of the device is coupled to at least one connection pad of the chip.

[0020] According to one embodiment, the supply voltage of the chip is applied between the common gate of the first and second transistors and the source of the third transistor.

[0021] One embodiment provides a method for controlling such a device, wherein a digital control signal is placed in a first state to provide a diode function and in a second state to enforce an open circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The foregoing features and advantages, and others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0023] Figure 1 An example electronic chip is illustrated schematically;

[0024] Figure 2 An example input / output circuit of the electronic chip is illustrated schematically;

[0025] Figure 3 Another example input-output circuit of an electronic chip is illustrated in schematic form;

[0026] Figure 4 An embodiment of the input-output circuit of an electronic chip is illustrated in schematic form; and

[0027] Figure 5 An embodiment of a diode switchable by a digital signal is illustrated in schematic form.

[0028] In the respective figures, similar features have been denoted by similar reference numerals. Specifically, structural and / or functional features common to the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties. Detailed Description

[0029] For clarity, only the operations and elements that contribute to an understanding of the embodiments described herein are described in detail. Specifically, the generation of the signals to be emitted by the input-output circuit and the processing of these signals are not described in detail, and the described embodiments are compatible with conventional applications of the input-output circuit.

[0030] Unless otherwise indicated, when referring to two elements connected together, it means a direct connection without any intermediate element other than a conductor, and when referring to two elements linked or coupled together, it means that the two elements can be linked or coupled by means of one or more other elements.

[0031] In the following disclosure, unless otherwise indicated, when referring to absolute position qualifiers (such as the terms "front", "rear", "top", "bottom", "left", "right", etc.), or relative position qualifiers (such as the terms "above", "below", "higher", "lower", etc.), or orientation qualifiers (such as "horizontal", "vertical", etc.), the orientation shown in the figures is referred to.

[0032] Unless specifically indicated otherwise, "about", "substantially", "essentially", and "approximately" mean within 10%, preferably within 5%.

[0033] Figure 1 An example of an electronic chip 1 is illustrated in schematic form.

[0034] In Figure 1 the example shown, the electronic chip 1 includes a circuit 3 or an input-output unit. The input-output circuit 3 allows the core 2 (CORE) of the chip 1 to communicate with the outside. Also in Figure 1In the example shown, each input-output circuit 3 is connected to the input terminal 11 (IN) of the core 2 of the chip 1, the output terminal 13 (OUT) of the core 2 of the chip 1, and the pad 15 (PAD), and this pad 15 allows, for example, the chip 1 to be connected to a connection element (not shown) positioned on the surface of a circuit board (not shown).

[0035] The input-output circuits 3 generally form input-output loops (I / O loops). For example, these input-output circuits 3 allow the core 2 of the chip 1 to exchange digital signals with the outside. The input-output circuits 3 generally ensure a protection function against electrostatic discharges that could damage the core 2 of the chip 1.

[0036] Figure 2 An example input-output circuit 3 of an electronic chip is diagrammatically illustrated.

[0037] In Figure 2 the example shown, the input-output circuit 3 (for example, one input-output circuit 3 of the input-output circuits 3 of the chip 1 as shown in Figure 1 ) consists of a leveling circuit 31 and a protection circuit 33. The leveling circuit 31 specifically includes two amplifiers or buffer circuits (buffers) 311 and 313, and the protection circuit 33 specifically includes two diodes 331 and 333.

[0038] Hereinafter, the buffer circuits 311 and 313 will be referred to as amplifiers, although it is obvious that they do not necessarily amplify the digital signals applied to their inputs. In addition to the voltage drops of one or more transistors constituting the circuits 311, 313 in the on state, the first function of the buffer circuits 311 and 313 is to bring the high input level and the low input level to the respective power supply potentials (in this example, the potential VDD and the ground GND) of the relevant circuits 311, 313.

[0039] In Figure 2 the output 3111 of the amplifier 311 of the leveling circuit 31 is connected to the input terminal 11 (IN) of the core 2 of the chip 1 ( Figure 1 ). The input 3133 of the amplifier 313 is connected to the output terminal 13 (OUT) of the core 2 of the chip 1 ( Figure 1 ). In this example, the output 3131 of the amplifier 313 and the input 3113 of the amplifier 311 are connected to each other via a common connection node 315. This connection node 315 is connected to the connection pad 15 (PAD) of the chip 1.

[0040] In Figure 2In it, both the positive power supply pin 3115 of the amplifier 311 and the positive power supply pin 3135 of the amplifier 313 are brought to the same potential VDD. This potential VDD typically corresponds to the power supply voltage of the chip 1 from a power supply (not shown). The voltage VDD is typically included between 1.8V and 3.6V. The negative power supply pin 3117 of the amplifier 311 is brought to any potential (not shown). The negative power supply pin 3137 of the amplifier 313 is brought to a reference potential (usually grounded, GND).

[0041] In Figure 2 In the example shown, the anode 3311 of the diode 331 of the protection circuit 33 is connected to the connection pad 15 of the chip 1. The cathode 3313 of the diode 331 is connected to the positive power supply pin 3115 of the amplifier 311 of the leveling circuit 31. The anode 3331 of the diode 333 is connected to the negative power supply pin 3137 of the amplifier 313 of the leveling circuit 31. The cathode 3333 of the diode 333 is connected to the connection pad 15 of the chip 1. Thus, when the anode 3331 of the diode 333 is grounded to GND, the cathode 3313 of the diode 331 is brought to the potential VDD. For the purpose of simplification, it is assumed that the following ground potential GND is zero (GND = 0V). Thus, the potential GND constitutes the reference potential for the circuit 1.

[0042] In Figure 2 In it, both the anode 3311 of the diode 331 and the cathode 3333 of the diode 333 of the protection circuit 33 of the chip 1 are connected in another connection node 335. Thus, the pad 15, the connection nodes 315 and 335, the anode 3311 of the diode 331, the cathode 3333 of the diode 333, the input 3113 of the amplifier 311, and the output 3131 of the amplifier 313 (except for the parasitic voltage drop in the conductor) are at the potential of the pad PAD, which is represented as VPAD.

[0043] When the diodes 331 and 333 of the protection circuit 33 are biased by a voltage greater than the threshold voltage (denoted as VSEUIL), the diodes 331 and 333 of the protection circuit 33 turn on (i.e., they conduct current). For the sake of simplicity, it is assumed hereinafter that both the diodes 331 and 333 have the same threshold voltage VSEUIL. The threshold voltage VSEUIL of a silicon diode (PN junction) is typically approximately 0.7v.

[0044] For the sake of simplicity, the avalanche phenomena potentially occurring in diodes 331 and 333 in the case of the application of a strong reverse voltage are ignored. Thus, diode 331 is considered to be turned on only when a voltage V1 of at least VSEUIL is applied between its anode 3311 and its cathode 3313. Otherwise (if voltage V1 is strictly lower than voltage VSEUIL), diode 331 is considered to be off (i.e., it does not let any current pass). In Figure 2 the example shown, voltage V1 is equal to VPAD – VDD.

[0045] Similarly, diode 333 is considered to be turned on only when it is assumed that a voltage V3 of at least VSEUIL is applied between its anode 3331 and its cathode 3333. Otherwise (if voltage V3 is strictly lower than voltage VSEUIL), diode 333 is considered to be off (i.e., it does not let any current pass). In Figure 2 the example shown, voltage V3 is equal to -VPAD.

[0046] Thus, theoretically, three operations can be carried out according to the value of voltage VPAD. In the first case, for input-output circuit 3, if voltage VPAD is strictly included between –VSEUIL and VDD + VSEUIL, diodes 331 and 333 are off (because both voltages V1 and V3 are strictly lower than voltage VSEUIL). In the second case, if voltage VPAD is less than or equal to -VSEUIL, diode 333 is turned on (because voltage V3 is greater than or equal to voltage VSEUIL), while diode 331 is off (because voltage V1 is strictly lower than voltage VSEUIL). And in the third case, if voltage VPAD is greater than or equal to VDD + VSEUIL, diode 331 is turned on (because voltage V1 is thus greater than or equal to voltage VSEUIL), while diode 333 is off (because voltage V3 is thus strictly lower than voltage VSEUIL).

[0047] The first case of operation corresponds to the normal scenario. In this scenario, the input-output circuit 3 of chip 1 accommodates on its pad 15 a voltage range VPAD included between -VSEUIL and VDD + VSEUIL. Thus, the pad 15 of circuit 3 is considered to be a "non-weldable pad".

[0048] The second case generally corresponds to an abnormal scenario due to a negative injection or a negative overvoltage on pad 15. In this scenario, diode 333 is turned on, so that current can flow from ground GND to pad 15, which makes it possible to protect the leveling circuit 31 from the negative overvoltage.

[0049] The third case generally corresponds to another abnormal scenario caused by a positive injection or a positive overvoltage on the pad 15. In this case, the diode 331 is turned on, so that current can flow from the pad 15 to the power supply of the chip 1, which enables the leveling circuit 31 to be protected from the positive overvoltage.

[0050] Therefore, the diodes 331 and 333 of the protection circuit 33 enable the leveling circuit 31 of the input-output circuit 3 to be protected from possible positive overvoltages or negative overvoltages. The diode 331 constitutes an injection path towards the power supply VDD. The diode 333 constitutes an extraction path from the ground GND.

[0051] A drawback associated with the implementation of the diodes 331 and 333 is that, during normal operation, the diodes are forced to avoid a voltage VPAD on the pad 15 of the chip 1 that exceeds approximately VDD + VSEUIL. This constraint may prevent the use of the chip 1 in applications where a voltage VPAD significantly greater than VDD + VSEUIL needs to be applied.

[0052] Figure 3 Another example input-output circuit 5 of an electronic chip is illustrated schematically.

[0053] For example, in Figure 3 The input-output circuit 5 shown is another input-output circuit of the chip 1. This input-output circuit 5 includes elements shared with the input-output circuit 3 shown in Figure 2 These shared elements will not be described in detail hereinafter.

[0054] Figure 3 The main difference between the input-output circuit 5 of Figure 2 and the input-output circuit 3 of

[0055] is that the circuit 5 does not include the diode 331. Therefore, in the input-output circuit 5, there cannot be an injection path towards the power supply VDD. Figure 2 ) allows in Figure 3The input-output circuit 5 shown in accepts a voltage range on its pads 15 that is greater than the allowable voltage range of circuit 3. For example, this allows the chip 1 to use the same pads 15 to transmit various types of signals depending on one or more applications. Thus, in particular, a voltage VPAD substantially greater than VDD can be applied on the pads 15 of circuit 5. This operation can also be supported by the design of amplifiers 331 and 333 to allow a voltage greater than VDD on the pads 15 without risking component degradation or triggering excessive leakage currents that could alter the signal integrity applied on the pads 15. Thus, for a supply voltage VDD of approximately 3V, a voltage VPAD of approximately 5V can typically be applied on the pads 15. The pads 15 of circuit 5 are considered "robust pads".

[0056] In Figure 3 the protection circuit 33 includes an additional component 51 (ESD) by means of which the leveling circuit 31 can be protected from possible electrostatic discharges. In this example, the component 51 is connected in parallel with the diode 333.

[0057] However, the chip 1 cannot thus be protected against a continuous positive voltage, and it must be ensured that the application (connected to the pads 15) does not apply a positive voltage greater than what the components of the chip 1 can support. In fact, the ESD protection of component 51 only protects against temporary overvoltages.

[0058] However, the input-output circuit 5 of the chip 1 cannot satisfy applications that require the diode 331 ( Figure 2 ). In other words, circuits 3 ( Figure 2 ) and 5 each have different advantages that are inherent in the presence or absence of the diode 331 ( Figure 2 ).

[0059] Figure 4 An embodiment of the input-output circuit 7 of an electronic chip is illustrated schematically.

[0060] According to this embodiment, the input-output circuit 7 shown in Figure 4 is, for example, another input-output circuit of the chip 1. The input-output circuit 7 includes elements shared with the input-output circuit 5 shown in Figure 3 . These shared elements will not be described in detail hereinafter.

[0061] In Figure 4 the main difference between the input-output circuit 7 shown in Figure 3 and the input-output circuit 5 shown in Figure 4In [description], the switchable diode 71 is connected to the connection node 335 through the first connection pin 711, to the ground GND through the second connection pin 713, to the terminal 17 of the chip 1 through the third connection pin 715, and to a power supply (not shown) that applies the potential VDD through the fourth connection pin 717.

[0062] Preferably, the terminal 17 is on the side of the chip core (not shown in Figure 4 ), which makes it possible to avoid modifying the number of pads external to the chip 1.

[0063] A digital signal (or on / off signal) denoted as CMD is applied to the terminal 17 of the chip 1. Thus, the digital signal CMD reaches the switchable diode 71 through its third pin 715. This digital signal CMD is adapted to control the switchable diode 71.

[0064] According to a preferred embodiment, the first state (preferably, the high state) of the control signal CMD allows the switchable diode 71 to behave as a diode, where the anode corresponding to the first pin 711 of the switchable diode 71 is brought to the potential VPAD, and the cathode corresponding to the second pin 713 of the switchable diode 71 is brought to the potential GND.

[0065] When the signal CMD is in the high state, everything operates as if the input-output circuit 7 shown in Figure 4 includes a diode between the terminal 15 of the chip 1 and the ground GND. In other words, the circuit 7 can thus be compared with the circuit 3 ( Figure 2 ), but the switchable diode 71 of the circuit 7 provides an injection path towards the ground GND, while the diode 331 of the circuit 3 provides an injection path towards the power supply VDD. When the signal CMD is in the high state, a circuit resumes the operation of the circuit 7 equivalent to the circuit 3 ( Figure 2 ), except that the positive overvoltage (VPAD≥VDD + VSEUIL) is no longer dissipated to the power supply VDD, but to the ground GND.

[0066] According to this embodiment, the second state (preferably, the low state) of the control signal CMD enables an open circuit to be formed between the first pin 711 and the second pin 713 of the switchable diode 71.

[0067] When the signal CMD is in the low state, the circuit 7 is thus equivalent to the circuit 5 shown in Figure 3 . When the signal CMD is in the low state, a circuit thus resumes the operation of the circuit 7 similar to the circuit 5 ( Figure 3 ).

[0068] Thus, depending on the state of the signal CMD applied to terminal 17 of chip 1, according to the preferred embodiment, sometimes a non-weld-resistant pad 15 (i.e., component 71 that behaves as a diode when the signal CMD is in the high state) can be obtained, and sometimes a weld-resistant pad 15 (i.e., component 71 that behaves as an open circuit when the signal CMD is in the low state) can be obtained.

[0069] Compared with circuit 3 ( Figure 2 ), and circuit 5 ( Figure 3 ), the advantage of circuit 7 of chip 1 is that it has a configurable pad 15 (as a weld-resistant pad or a non-weld-resistant pad) according to the state of the digital signal CMD applied to terminal 17 of chip 1. Therefore, this gives circuit 7 and (more specifically) chip 1 greater flexibility.

[0070] Figure 5 An embodiment of a diode that can be switched by a digital signal is illustrated schematically.

[0071] According to this embodiment, the switchable diode (e.g., the switchable diode 71 (SWID) of circuit 7 ( Figure 4 )) is preferably composed of a component in which a first transistor 73 (M1), a second transistor 75 (M2), and a third transistor 77 (M3) are connected in series.

[0072] The transistors 73, 75, and 77 of the switchable diode 71 are preferably MOS-type field effect transistors. In the example shown in Figure 5 , compared with transistor 73, the transistors 75 and 77 of the switchable diode 71 have different types of conductivity. Transistor 71 is preferably a P-type or P-channel MOS transistor (or P-channel MOSFET, PFET, PMOS, etc.), while both transistors 75 and 77 are N-type or N-channel MOS transistors (or N-channel MOSFET, NFET, NMOS, etc.).

[0073] According to the preferred embodiment, the first transistor 73 causes the source 731 of the first transistor 73 to be connected to terminal 15 of chip 1, the gate 733 of the first transistor 73 to be brought to the power supply potential VDD of chip 1, and the drain 735 of the first transistor 73 to be connected to the drain 755 of the second transistor 75.

[0074] Still according to this preferred embodiment, the second transistor 75 causes the source 751 of the second transistor 75 to be connected to the drain 775 of the third transistor 77, the gate 753 of the second transistor 75 to be brought to the power supply potential VDD of chip 1, and the drain 755 of the second transistor 75 to be connected to the drain 735 of the first transistor 73.

[0075] Still according to this preferred embodiment, the third transistor 77 has its source 771 grounded to GND, its gate 773 connected to terminal 17 of the chip 1, and its drain 775 connected to the source 751 of the second transistor 75.

[0076] Reference Figure 4 shows that: the source 731 of the first transistor 73 is connected to the first pin 711 of the switchable diode 71, the gates 733 of the first transistor 73 and 753 of the second transistor 75 are interconnected to form the fourth pin 717 of the switchable diode 71, the gate 773 of the third transistor 77 is connected to the third pin 715 of the switchable diode 75, and the source 771 of the third transistor 77 is connected to the second pin 713 of the switchable diode 71.

[0077] Most of transistors M2 and M3 are interconnected with the source 771 (grounded to GND) of transistor M3. Most of transistor M1 is connected to the source 731 (pad 15) of transistor M1.

[0078] Therefore, a DC voltage (VDD) (preferably the power supply voltage of the chip 1) is applied between the common gates 733 and 753 of the first transistor 73 and the second transistor 75 and the source 771 of the third transistor 77.

[0079] For the sake of simplicity, all transistors 73, 75, 77 are considered to have the same threshold voltage value (denoted as VTH).

[0080] If a voltage less than or equal to the voltage VTH is applied between the gate 733 of the first transistor 73 and the source 731 of the first transistor 73, then theoretically the first transistor 73 is turned on. If a voltage strictly greater than the voltage VTH is applied between the gate 733 of the first transistor 73 and the source 731 of the first transistor 73, then theoretically the first transistor 73 is turned off.

[0081] If a voltage greater than or equal to the voltage VTH is applied between the gate 753 of the second transistor 75 and the source 751 of the second transistor 75, then theoretically the second transistor 75 is turned on. If a voltage strictly lower than the threshold voltage VTH is applied between the gate 753 of the second transistor 75 and the source 751 of the second transistor 75, then theoretically the second transistor 75 is turned off.

[0082] If a voltage greater than or equal to the voltage VTH is applied between the gate 773 of the third transistor 77 and the source 771 of the third transistor 77, the third transistor 77 is theoretically turned on. If a voltage strictly lower than the threshold voltage VTH is applied between the gate 773 of the third transistor 77 and the source 771 of the third transistor 77, the third transistor 77 is theoretically turned off.

[0083] It has been observed above that the source 731 of the first transistor 73 is connected to the pad 15 of the chip 1. Therefore, the source 731 of the first transistor 73 is placed at the potential VPAD. The gate 773 of the third transistor 77 is connected to the terminal 17 of the chip 1. Therefore, the gate 773 of the third transistor 77 is controlled by the digital signal CMD.

[0084] It is assumed that the high state of the signal CMD (CMD = 1) is encoded by the application of a voltage greater than or equal to VTH on the terminal 17. Therefore, when the signal CMD is in the high state, the third transistor 77 is turned on.

[0085] It is assumed that the low state of the signal CMD (CMD = 0) is encoded by the application of a voltage strictly lower than VTH on the terminal 17. Therefore, when the signal CMD is in the low state, the third transistor 77 is turned off.

[0086] Therefore, depending on the potential VDD and VPAD and the corresponding values of the digital signal CMD, multiple operating cases of the switchable diode 71 can occur. The following table lists these different operating cases.

[0087] [Table 1]

[0088] Case VDD VPAD CMD Transistor 73 Transistor 75 Transistor 77 1 ≤VTH <VDD+VTH 0 Turn - off Turn - off Turn - off 2 ≤VTH ≥VDD + VTH 0 Turn - on Turn - off Turn - off 3 >VTH <VDD+VTH 0 Turn - off Turn - on Turn - off 4 >VTH ≥VDD + VTH 0 Turn - on Turn - on Turn - off 5 >VTH <VDD+VTH 1 Turn - off Turn - on Turn - on 6 >VTH ≥VDD + VTH 1 Turn - on Turn - on Turn - on

[0089] Therefore, if all the transistors 73, 75, 77 of the switchable diode 71 are turned on, current can theoretically only flow between the terminal 15 of the chip 1 and the ground GND. Based on the above table, it is confirmed that the switchable diode 71 is only turned on in case 6. Therefore, if the voltage VPAD is greater than or equal to VDD + VTH, if the signal CMD is in the high state and if the voltage VDD is greater than the threshold voltage VTH, the switchable diode 71 is turned on.

[0090] When the signal CMD is in the high state (cases 5 and 6), the switchable diode 71 therefore behaves as a diode with a threshold voltage equal to VTH. On the other hand, when the signal CMD is in the low state (cases 1 to 4), the switchable diode 71 behaves as an open circuit.

[0091] The switchable diode 71 and the diode 331 ( Figure 2) The difference is that when the chip 1 is disconnected from the voltage supply (i.e., when the power supply of the chip 1 is turned off and VDD = 0), the switchable diode 71 prohibits any current injection into the power supply VDD.

[0092] Assuming that the voltage VDD is zero (i.e., it is desired to keep the chip 1 turned off or disconnected from the voltage supply), applying a voltage to the pad 15 associated with the diode 331 (as shown with respect to Figure 2 ) can cause current injection into the power supply VDD. Therefore, there is a risk of preventing the disconnection or turning off of the chip 1. On the other hand, applying a voltage to the pad 15 associated with the switchable diode 71 does not cause current injection into the power supply VDD. Therefore, the chip 1 remains disconnected or turned off.

[0093] Therefore, the switchable diode 71 has the advantage of preventing the chip 1, which is desired to remain disconnected, from being involuntarily re-powered by the voltage applied on the pad 15.

[0094] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and those skilled in the art will readily appreciate other variations. In particular, with respect to the example applications of the input-output circuit, what is shown more specifically is more generally applicable to any electronic circuit in which it is desired to implement the switchable diode 71.

[0095] Finally, based on the functional descriptions provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.

Claims

1. A switchable diode device, comprising: A first external signal connection pin; A first transistor, including a first gate connection node and a first source / drain connection node directly connected to the first external signal connection pin; A second connection pin configured to be directly connected to a power supply voltage; A second transistor, including a second gate connection node and a second source / drain connection node directly connected to the second source / drain connection node of the first transistor, wherein both the first gate connection node and the second gate connection node are directly connected to the second connection pin; And A third connection pin; A fourth connection pin configured to be coupled to a reference voltage; A third transistor, including a third gate connection node, a third source / drain connection node connected to the second transistor, and a fourth source / drain connection node connected to the fourth connection pin; Wherein the third transistor is configured to be controlled by a digital signal using the third connection pin.

2. The device according to claim 1, wherein the transistor is a MOS transistor.

3. The device according to claim 2, Wherein the first transistor is a P-type transistor, Wherein the second transistor is an N-type transistor, and Wherein the third transistor is an N-type transistor.

4. The device according to claim 1, Wherein the second source / drain connection node is the drain of the second transistor, connected to the drain of the first transistor, and Wherein the third source / drain connection node is the drain of the third transistor, and the drain of the third transistor is connected to the source of the second transistor.

5. The device according to claim 1, wherein the current in the series connection of the transistors is controlled in an on / off manner by the digital signal.

6. The device according to claim 1, wherein the device is configured to function as a diode or as an open circuit based on the state of the digital signal controlling the third transistor.

7. The device according to claim 1, wherein the device is composed of three transistors.

8. The device according to claim 1, further comprising: A first connection pin; A second connection pin; A third connection pin; A fourth connection pin; The second transistor includes a second source / drain connection node; And The third transistor includes the fourth source / drain connection node.

9. The device according to claim 8, wherein: The first body connection node of the first transistor is connected to the first connection pin; and Both the second body connection node of the second transistor and the third body connection node of the third transistor are connected to the fourth connection pin.

10. The device according to claim 8, wherein: The first transistor includes a fifth source / drain connection node; The fifth source / drain connection node of the second transistor is connected to the first transistor using the fourth source / drain connection node; And The device does not include an additional connection node between the second source / drain connection node and the fifth source / drain connection node.

11. An electronic chip, comprising: At least one device according to claim 1.

12. The chip according to claim 11, wherein the first source / drain connection node of the first transistor is coupled to at least one connection pad of the chip.

13. The chip according to claim 11, wherein a voltage difference equal to the supply voltage of the chip is configured to be applied between the second connection pin and the fourth source / drain connection node, which is the source of the third transistor.

14. The device according to claim 12, wherein: the at least one connection pad is configured to function as a solder-resistant pad in response to the digital signal applied to the third transistor being in a first state; and the at least one connection pad is configured to function as a non-solder-resistant pad in response to the digital signal applied to the third transistor being in a second state.

15. A method for controlling a device to dynamically select between non-solder-resistant pad behavior and solder-resistant pad behavior of an external pad of an electronic chip, wherein the device includes a first P-type transistor, a second N-type transistor, and a third N-type transistor arranged in a series connection, the first P-type transistor being directly connected to a common connection node of the external pad and a leveling circuit connected to an electronic chip core, the method comprising: providing a substantially time-invariant supply voltage to a common gate connection node of the first P-type transistor and the second N-type transistor; selecting non-solder-resistant pad behavior for the external pad by providing a digital control signal in a first state to the third N-type transistor, such that the device provides a diode function; and selecting solder-resistant pad behavior for the external pad by providing a digital control signal in a second state to the third N-type transistor, such that the device provides an open circuit.

16. A switchable diode device, comprising: a first external signal connection pin; a first transistor, which is a P-type transistor and includes a first gate and a source connected to the first external signal connection pin, a second connection pin, configured to be directly connected to a supply voltage; a second transistor, which is an N-type transistor and includes a second gate, a third connection pin; a fourth connection pin, configured to be coupled to a reference voltage; and a third transistor, which is an N-type transistor and includes a third gate, wherein the drain of the second transistor is directly connected to the drain of the first transistor, wherein the first gate and the second gate are both directly connected to the second connection pin, wherein the source of the second transistor is connected to the drain of the third transistor, wherein the source of the third transistor is connected to the fourth connection pin, wherein the device is configured to function as a diode in response to a control signal applied to the third transistor using the third connection pin being in a first state, and wherein the device is configured to function as an open circuit in response to the control signal being in a second state.

17. The device according to claim 16, wherein the current in the series connection of the transistors is controlled in an on / off manner by the control signal.

18. The device according to claim 16, wherein the device is composed of three transistors.

19. The device according to claim 16, wherein: the first body connection node of the first transistor is connected to the first external signal connection pin; and both the second body connection of the second transistor and the third body connection of the third transistor are connected to the fourth connection pin.

20. The device according to claim 16, wherein: the device does not include an additional connection node between the drain of the first transistor and the drain of the second transistor.

21. The device according to claim 16, wherein: the first external signal connection pin is coupled to at least one connection pad of the chip; the at least one connection pad is configured to be used as a non-weldable pad in response to the control signal being in the first state; and the at least one connection pad is configured to be used as a weldable pad in response to the control signal being in the second state.

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