Display device and method of manufacturing the same

Abstract

Disclosed are a display device and a method for manufacturing the display device, wherein the display device includes: a display panel, including a display substrate having a display area and a pad area located around the display area, and a plurality of signal wirings arranged in the pad area of ​​the display substrate; a base film attached to the pad area of ​​the display substrate; a plurality of lead wirings arranged on the base film and connected to the plurality of signal wirings; and a first curable pattern arranged between adjacent lead wirings among the plurality of lead wirings, wherein a surface height of the first curable pattern from a surface of the base film is less than a surface height of the lead wiring from the surface of the base film.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2019-0053975, filed on May 8, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the present invention generally relate to a display device and a method of manufacturing the same, and more particularly, to a display device having improved reliability and a method for manufacturing the same. Background Art

[0004] The display device displays data in a graphical manner. Such a display device includes a substrate on which a display area and a non-display area are defined. Typically, a plurality of pixels are provided on the substrate in the display area, and a plurality of pads, etc. are provided on the substrate in the non-display area. A flexible film (such as a chip on film (COF) film) on which a drive circuit, etc. is mounted is bonded to the plurality of pads to transmit a drive signal to the pixels.

[0005] The flexible film may include a plurality of leads bonded to a plurality of pads. Each lead may be bonded to pads separated from each other. The leads may be bonded to the pads by an ultrasonic bonding process or the like.

[0006] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art. Summary of the invention

[0007] The display device constructed according to the exemplary embodiment of the present invention can prevent the lead wire from being peeled off from the base film of the printed circuit board.

[0008] Additional features of the inventive concept will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0009] The display device includes: a display panel, including a display substrate having a display area and a pad area located around the display area, and a plurality of signal wirings arranged in the pad area of ​​the display substrate; a base film attached to the pad area of ​​the display substrate; a plurality of lead wirings arranged on the base film and connected to the plurality of signal wirings; and a first curable pattern arranged between adjacent lead wirings among the plurality of lead wirings, wherein a surface height of the first curable pattern from the surface of the base film is less than a surface height of the lead wiring from the surface of the base film.

[0010] The first curable pattern may be spaced apart from the display substrate.

[0011] The first curable pattern may be in contact with at least a portion of a side surface of the lead wiring and a surface of the base film.

[0012] The first curable pattern may be bonded to at least a portion of a side surface of the lead wiring and a surface of the base film.

[0013] The display device may further include a second curable pattern arranged between adjacent signal wirings located on the display substrate, wherein a first portion of the second curable pattern contacts the first curable pattern, and a second portion of the second curable pattern does not contact the first curable pattern, the second curable pattern partially contacts the first curable pattern, and a gap is formed between the second curable pattern and the first curable pattern.

[0014] The first curable pattern may expose a lower end portion of a side surface of each of the lead wirings, and the second curable pattern may be in contact with the exposed lower end portion of the side surface of each of the lead wirings.

[0015] The second curable pattern may be in contact with a lower surface of each of the lead wirings facing an upper surface of a corresponding one of the signal wirings, and in contact with an upper surface of each of the signal wirings.

[0016] The first curable pattern may include a curable resin having a first average curing rate, and the second curable pattern may include a curable resin having a second average curing rate that is less than the first average curing rate.

[0017] The second curable pattern may be disposed closer to the display area than the first curable pattern.

[0018] The display device may further include an organic insulating pattern disposed on the display substrate and disposed between adjacent ones of the signal wirings, wherein the second curable pattern may be disposed between the organic insulating pattern and the first curable pattern.

[0019] A lower surface of the first curable pattern facing the organic insulation pattern may include a first lower surface having a first roughness and a second lower surface having a second roughness greater than the first roughness, and the second lower surface may overlap an upper surface of the organic insulation pattern in a thickness direction.

[0020] The second lower surface of the first curable pattern and the upper surface of the organic insulation pattern may include scratches.

[0021] The signal wiring can be directly connected to the lead wiring.

[0022] The signal wiring may be configured to be bonded to the lead wiring by ultrasonic bonding.

[0023] According to another exemplary embodiment, a method for manufacturing a display device includes the following steps: applying a first curable resin between adjacent lead wirings among lead wirings arranged on a base film, the surface height of the first curable resin being smaller than the surface height of the lead wirings; curing the applied first curable resin to form a first curable pattern; and connecting a signal wiring arranged on a display substrate to the lead wirings.

[0024] The step of coupling the signal wiring with the lead wiring may include bringing the signal wiring into direct contact with the lead wiring.

[0025] The step of bringing the signal wiring into direct contact with the lead wiring includes ultrasonically bonding the signal wiring to the lead wiring.

[0026] The step of curing the applied first curable resin includes forming a first curable pattern using a UV laser.

[0027] The method may further include the step of applying a second curable resin after the signal wiring disposed on the display substrate is coupled to the lead wiring.

[0028] The method may further include simultaneously curing the first curable pattern and the second curable resin after applying the second curable resin.

[0029] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings illustrate exemplary embodiments of the present invention and together with the description serve to explain the inventive concept. The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification.

[0031] Figure 1 is a plan view of a display device according to an exemplary embodiment.

[0032] Figure 2 yes Figure 1 A cross-sectional view of a display device.

[0033] Figure 3 It is the layout of the panel pad area and the layout of a portion of the printed circuit board when viewed from the top.

[0034] Figure 4 is a plan view showing the layout of a panel pad area of ​​a display panel and a printed circuit board attached to the panel pad area.

[0035] Figure 5 yes Figure 4 Magnified view of area A.

[0036] Figure 6 is along Figure 5 A cross-sectional view taken along line VI-VI'.

[0037] Figure 7 is along Figure 5 A cross-sectional view taken along line VII-VII'.

[0038] Figure 8 yes Figure 7 Magnified view of area B.

[0039] Fig. 9 is a cross-sectional view illustrating an ultrasonic bonding process in which a vibration transmitter of an ultrasonic device applies a load to a printed circuit board.

[0040] Fig.10 is a cross-sectional view illustrating an ultrasonic bonding process, in which a vibration transmitter of an ultrasonic device is separated from a printed circuit board.

[0041] Fig.11 is a cross-sectional view of a panel pad area and a printed circuit board attached to the panel pad area of ​​a display panel according to another exemplary embodiment.

[0042] Fig.12 yes Fig.11 An enlarged view of portion C of FIG.

[0043] Fig.13 is a flowchart illustrating a method for manufacturing a display device according to an exemplary embodiment.

[0044] Fig.14 , Fig.15 , Fig.16 , Fig.17 and Fig.18 is a cross-sectional view illustrating a method of manufacturing a display device according to an exemplary embodiment.

[0045] Fig.19 is a plan view of a display device according to still another exemplary embodiment.

[0046] Fig. 20 is a cross-sectional view of a display device according to still another exemplary embodiment. DETAILED DESCRIPTION

[0047] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. As used herein, "implementation" and "implementation" are interchangeable words, which are non-limiting examples of devices or methods using one or more inventive concepts in the inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments can be practiced without these specific details or by one or more equivalent arrangements. In other examples, known structures and devices are shown in block diagram form to avoid unnecessary obscurity of various exemplary embodiments. In addition, various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0048] Unless otherwise specified, the exemplary embodiments shown should be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0049] The use of cross hatching and / or shading in the drawings is generally used to make the boundaries between adjacent elements clear. Therefore, unless otherwise stated, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the exemplary embodiments can be implemented differently, a specific process can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously, or in an order opposite to the described order. Similarly, the same reference numerals represent the same elements.

[0050] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements. In addition, the DR1 axis, the DR2 axis, and the DR3 axis are not limited to the three axes of a rectangular coordinate system, such as the x-axis, the y-axis, and the z-axis, and may be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0051] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0052] For descriptive purposes, spatially relative terms such as "below," "under," "below," "down," "above," "upper," "above," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein and thereby describe the relationship of one element to another element(s) as shown in the accompanying drawings. In addition to the orientation depicted in the accompanying drawings, spatially relative terms are intended to include different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, elements described as being "below" or "below" other elements or features will then be oriented to be "above" the other elements or features. Thus, the exemplary term "below" can include both above and below orientations. In addition, the device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0053] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to also include plural forms unless the context clearly indicates otherwise. In addition, when the terms "comprises", "comprising", "includes" and / or "including" are used in this specification, the existence of the stated features, integral bodies, steps, operations, elements, components and / or its groups is specified, but the existence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or its groups is not excluded. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms, rather than as terms of degree, and therefore, are used to allow for the inherent deviation of the measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0054] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. Thus, deviations from the illustrated shapes caused by, for example, manufacturing techniques and / or tolerances should be expected. Therefore, the exemplary embodiments disclosed herein should not necessarily be interpreted as being limited to the specific illustrated shapes of the regions, but should include deviations from the shapes caused by, for example, manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore are not necessarily intended to be limiting.

[0055] As is customary in the art, some exemplary embodiments are described and illustrated in the accompanying drawings according to functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connectors, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also conceivable that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs certain functions and processors that perform other functions (e.g., one or more programmed microprocessors and associated electronic circuits). In addition, without departing from the scope of the inventive concept, each block, unit and / or module of some exemplary embodiments can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as that commonly understood by those skilled in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0057] Figure 1 is a plan view of a display device according to an exemplary embodiment. Figure 2 yes Figure 1 A cross-sectional view of a display device. Figure 3 It is the layout of the panel pad area and the layout of a portion of the printed circuit board when viewed from the top. Figure 4 It is a plan view showing the layout of a panel pad area of ​​a display panel and a printed circuit board connected to the panel pad area. Figure 5 yes Figure 4 Magnified view of area A shown in FIG. Figure 6 is along Figure 5 A cross-sectional view taken along line VI-VI'. Figure 7 is along Figure 5 A cross-sectional view taken along line VII-VII'. Figure 8 yes Figure 7 Magnified view of area B.

[0058] The display device displays moving images or still images. The display device can be used as a display screen of portable electronic devices such as mobile phones, smart phones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs), and display screens of various products such as televisions, notebooks, monitors, billboards, and the Internet of Things.

[0059] Reference Figures 1 to 8 , the display device 1 may include a display panel 100 for displaying an image, a printed circuit board 300 connected to the display panel 100 , and a main circuit board 500 connected to the printed circuit board 300 .

[0060] For example, an organic light emitting display panel may be used as the display panel 100. Hereinafter, the display panel 100 will be described with reference to the organic light emitting display panel. However, the inventive concept is not limited thereto, and in some exemplary embodiments, other types of display panels such as a liquid crystal display (LCD) panel, a quantum dot organic light emitting display (QD-OLED) panel, a quantum dot liquid crystal display (QD-LCD) panel, a quantum nano light emitting display (Nano NED) panel, a micro LED panel, etc. may be used as the display panel 100.

[0061] The display panel 100 includes a display area DA and a non-display area NA, in which a plurality of pixel areas are arranged, and the non-display area NA is arranged around the display area DA. When viewed from the top, the display area DA may have a substantially rectangular shape having right-angled corners or rounded corners. The display area DA may include a shorter side and a longer side. The shorter side of the display area DA may extend in a first direction DR1. The longer side of the display area DA may extend in a second direction DR2. However, the inventive concept is not limited thereto. For example, the display area DA may have a substantially circular or elliptical shape. In addition, the non-display area NA may be arranged adjacent to two shorter sides and two longer sides of the display area DA. In this case, the non-display area NA may surround each side of the display area DA and may form an edge of the display area DA. However, in some exemplary embodiments, the non-display area NA may be arranged adjacent to only the two shorter sides of the display area DA or only the two longer sides of the display area DA.

[0062] The non-display area NA of the display panel 100 further includes a panel pad area P_PA. The panel pad area P_PA may be disposed, for example, around one shorter side of the display area DA, however, the inventive concept is not limited thereto. In some exemplary embodiments, the panel pad area P_PA may be disposed around each of the two shorter sides of the display area DA, or around each of the shorter side and the longer side of the display area DA.

[0063] The printed circuit board 300 may include a printed base film 310 (or base film) and a driver integrated circuit 390 disposed on the printed base film 310. The printed base film 310 may include an insulating material.

[0064] The printed circuit board 300 may include: a first circuit area CA1 having one side attached to the panel pad area P_PA of the display panel 100; a second circuit area CA2 disposed on one side of the first circuit area CA1 in the second direction DR2; and a third circuit area CA3 disposed on one side of the second circuit area CA2 in the second direction DR2 and attached to the main circuit board 500. The driver integrated circuit 390 may be disposed on the second circuit area CA2 of the printed circuit board 300. The driver integrated circuit 390 may be, for example, a data driver integrated circuit, and may be implemented by using a chip on film (COF) technology.

[0065] The main circuit board 500 may include a circuit pad area attached to the third circuit area CA3 of the printed circuit board 300. A plurality of circuit pads may be provided in the circuit pad area of ​​the main circuit board 500 and connected to lead wiring provided in the third circuit area CA3 of the printed circuit board 300.

[0066] Reference Figure 2 , the display device 1 may further include a cover panel sheet 200 disposed below the display panel 100. The cover panel sheet 200 may be attached to the rear surface of the display panel 100. The cover panel sheet 200 includes at least one functional layer. The functional layer may perform a heat dissipation function, an electromagnetic wave shielding function, a grounding function, a buffering function, a strength enhancement function, a support function and / or a digitization function. The functional layer may be a sheet layer made of a sheet, a film layer made of a film, a film layer, a coating, a panel, a board, etc. The functional layer may include a single layer or a plurality of films or coatings stacked on each other. For example, the functional layer may be a supporting substrate, a heat radiation layer, an electromagnetic wave shielding layer, an impact absorbing layer, a digitizer, etc.

[0067] like Figure 2As shown in FIG. , the printed circuit board 300 may be bent downward in the third direction DR3. In this case, the other side of the printed circuit board 300 and the main circuit board 500 may be located below the cover panel sheet 200. The lower surface of the cover panel sheet 200 may be bonded to the main circuit board 500 by an adhesive layer, but is not limited thereto.

[0068] The display panel 100 may include a display substrate 101 , a plurality of conductive layers, a plurality of insulating layers for insulating the conductive layers, an organic layer EL, and the like.

[0069] The display substrate 101 extends over the entire display area DA and the non-display area NA. The display substrate 101 may support various elements disposed thereon. In an exemplary embodiment, the display substrate 101 may be a rigid substrate including a rigid material such as glass and quartz. However, the inventive concept is not limited thereto. For example, in some exemplary embodiments, the display substrate 101 may be a flexible substrate including a flexible material such as polyimide (PI).

[0070] The buffer layer 102 may be disposed on the display substrate 101. The buffer layer 102 may prevent moisture and oxygen from penetrating from the outside through the display substrate 101. The buffer layer 102 may include silicon nitride (SiN x ) layer, silicon oxide (SiO 2 ) layer and silicon oxynitride (SiO x N y ) layer.

[0071] The semiconductor layer 105 may be disposed on the buffer layer 102. The semiconductor layer 105 forms a channel of a thin film transistor. The semiconductor layer 105 is disposed in each pixel of the display area DA, and may be disposed in the non-display area NA in some exemplary implementations. The semiconductor layer 105 may include a source / drain region and an active region. The semiconductor layer 105 may include polycrystalline silicon.

[0072] The first insulating layer 111 may be disposed on the semiconductor layer 105. The first insulating layer 111 may be disposed on the entire surface of the display substrate 101. The first insulating layer 111 may be a gate insulating layer having a gate insulating function. The first insulating layer 111 may include a silicon compound, a metal oxide, and the like. For example, the first insulating layer 111 may include at least one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, and the like.

[0073] The first conductive layer 120 may be disposed on the first insulating layer 111. The first conductive layer 120 may include a gate electrode GE of a thin film transistor TFT, a first electrode CE1 of a storage capacitor Cst, and a gate signal line GSL. The gate signal line GSL may be disposed throughout the display area DA and the panel pad area P_PA. The first conductive layer 120 may include at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 120 may have a single layer or a multilayer structure.

[0074] The second insulating layers 112a and 112b may be disposed on the first conductive layer 120. The second insulating layers 112a and 112b may insulate the first conductive layer 120 from the second conductive layer 130. The second insulating layer 112a may be substantially disposed in the display area DA, and the second insulating layer 112b may be substantially disposed in the panel pad area P_PA. The second insulating layers 112a and 112b may include a material that may form the above-described first insulating layer 111. In the panel pad area P_PA, the second insulating layer 112b may include a plurality of contact holes CNT partially exposing the gate signal line GSL. Although in Figure 2 , the second insulating layer 112 b is illustrated as including two contact holes CNT, but the inventive concept is not limited thereto. In some exemplary embodiments, the second insulating layer 112 b may include three or more contact holes CNT.

[0075] The second conductive layer 130 may be disposed on the second insulating layers 112a and 112b. The second conductive layer 130 may include a second electrode CE2 of the storage capacitor Cst. The material of the second conductive layer 130 may be selected from materials that may form the above-described first conductive layer 120. The first electrode CE1 of the storage capacitor Cst and the second electrode CE2 of the storage capacitor Cst may form a capacitor through the second insulating layers 112a and 112b.

[0076] The third insulating layer 113 may be disposed on the second conductive layer 130. The third insulating layer 113 may include at least one material that may form the above-described first insulating layer 111. In some exemplary embodiments, the third insulating layer 113 may include an organic insulating material. The organic insulating material may be selected from materials that may form a first via layer VIA1, which will be described in more detail later.

[0077] The third conductive layer 140 may be disposed on the third insulating layer 113. The third conductive layer 140 may include a source electrode SE, a drain electrode DE, a high power supply voltage electrode ELVDDE, and a signal line PAD. The third conductive layer 140 may include at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer 140 may have a single layer or a multilayer structure. For example, the third conductive layer 140 may have a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc. In some exemplary embodiments, the third conductive layer 140 may include Ti / Al / Ti.

[0078] The signal line PAD of the third conductive layer 140 may overlap the gate signal line GSL of the first conductive layer 120 in the thickness direction and may be electrically connected to the gate signal line GSL through the contact hole CNT of the second insulating layer 112 b .

[0079] The first via layer VIA1 may be disposed on the third conductive layer 140. The first via layer VIA1 may include an organic insulating material. The organic insulating material may include at least one of polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB), etc.

[0080] At least some of the elements disposed on the third insulating layer 113 and the third conductive layer 140 in the display area DA may be omitted on some portions of the signal line PAD in the panel pad area P_PA. In this way, the signal line PAD disposed in the panel pad area P_PA may be exposed.

[0081] The printed circuit board 300 further includes a lead LE located on one surface of the first circuit area CA1 of the printed base film 310 and a circuit lead C_LE located on one surface of the third circuit area CA3. The lead LE is connected to the signal line PAD. According to the exemplary embodiment shown, the lead LE may be directly connected to the upper surface of the exposed signal line PAD. For example, the lead LE may be connected to the signal line PAD by ultrasonic bonding.

[0082] Ultrasonic bonding may be performed by an ultrasonic device 700. The ultrasonic device 700 may include a vibration generator 710, a vibrator 720 connected to the vibration generator 710, a pressurizer 730 for amplifying a vibration amplitude of the vibrator 720, and a vibration transmitter 740 connected to the vibrator 720.

[0083] The vibration generator 710 can convert electrical energy into vibration energy. The vibrator 720 can vibrate using the vibration energy converted by the vibration generator 710. The vibrator 720 can vibrate with an amplitude in the vibration direction. The amplitude of the vibrator 720 can be amplified in a direction parallel to the vibration direction by a pressurizer 730 connected to the vibrator 720. The vibration transmitter 740 can transmit the vibration of the vibrator 720 to the object to be joined by ultrasonic joining. The support member 750 fixes the upper and lower surfaces of the vibrator 720 to limit the up and down fluctuations of the vibrator 720 and the vibration transmitter 740 caused by vibration.

[0084] In an exemplary embodiment, the ultrasonic device 700 may contact the other surface of the printed circuit board 300 to apply a constant pressure in a downward direction so that the vibration transmitter 740 may effectively transmit the vibration to the printed circuit board 300. Figure 2 As shown in FIG. 7 , when the vibration transmitter 740 of the ultrasonic device 700 overlaps the printed circuit board 300 disposed therebelow, ultrasonic bonding may be performed.

[0085] The ultrasonic device 700 may vibrate in the vibration direction to vibrate the lead LE in the vibration direction. In this way, the signal line PAD may vibrate in the vibration direction due to the vibration transmitted through the lead LE. In this case, the vibration amplitude of the signal line PAD may be negligible. Therefore, the vibration amplitude of the vibration transmitter 740 in the vibration direction may be substantially equal to the distance that the lead LE moves on the signal line PAD in the vibration direction. In an exemplary embodiment, the vibration direction may be the second direction DR2. In other words, the vibration direction may be the direction in which the longer sides of the signal line PAD and the lead LE extend.

[0086] When the lead LE ultrasonically vibrates on the surface of the signal line PAD, frictional force is generated at the interface between the signal line PAD and the lead LE, so that frictional heat may be generated due to the frictional force. When the frictional heat is high enough to melt the materials of the signal line PAD and the lead LE, the melting area PADb of the signal line PAD adjacent to the lead LE and the melting area LEb of the lead LE adjacent to the signal line PAD may be melted. In this way, the signal line PAD may include a non-melting area PADa and a melting area PADb. Similarly, the lead LE may include a non-melting area LEa and a melting area LEb.

[0087] The non-melting area PADa may include only the material included in the signal line PAD. The non-melting area LEa may include only the material included in the lead line LE.

[0088] The material included in the lead LE may diffuse into the melting region PADb so that the material of the signal line PAD and the material of the lead LE may be mixed. The material included in the signal line PAD may diffuse into the melting region LEb so that the material of the lead LE and the material of the signal line PAD may be mixed.

[0089] In the melting area PADb and the melting area LEb, the signal line (hereinafter may also be referred to as signal wiring) PAD and the lead LE are solidified to be bonded to each other. The interface between the signal line PAD and the lead LE, that is, the interface between the melting area PADb and the melting area LEb, may have a non-flat shape.

[0090] For example, the lead LE may include a metal. The lead LE may include at least one metal selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). In an exemplary embodiment, the lead LE may include copper (Cu) and gold (Au). More specifically, the lead LE may include copper (Cu) disposed on the printed base film 310 and gold (Au) disposed on the copper (Cu). The copper (Cu) directly disposed on the printed base film 310 may not be directly connected to the signal line PAD, but is not limited thereto. In some exemplary embodiments, a portion of the signal line PAD may be directly connected to the copper (Cu) disposed on the printed base film 310. In addition, the gold (Au) disposed on the copper (Cu) may be directly connected to the signal line PAD. In this case, the Ti / Al / Ti of the signal line PAD can be mixed with the gold (Au) and / or copper (Cu) of the lead LE in the melting zone PADb, and the material contained in the signal line PAD can be diffused so that the gold (Au) and / or copper (Cu) of the lead LE can be mixed with the Ti / Al / Ti of the signal line PAD in the melting zone LEb.

[0091] As described above, in order to bond the signal line PAD with the lead line LE, the vibration transmitter 740 of the ultrasonic device 700 presses the upper surface of the printed base film 310 of the printed circuit board 300 in the third direction DR3 and applies vibration in the second direction DR2. In this way, as described above, the lead line LE provided on the printed base film 310 is bonded to the signal line PAD. After completing the ultrasonic bonding process, the vibration transmitter 740 of the ultrasonic device 700 is separated from the printed base film 310 in the third direction DR3. In this case, when the coupling force between the signal line PAD and the lead line LE is greater than the coupling force between the lead line LE and the printed base film 310, the lead line LE may be peeled off from the printed base film 310, which may cause cracks in the lead line LE. In this way, according to an exemplary embodiment, the first curable pattern IRP is provided between adjacent lead wirings LE in the display device 1, which will be described in more detail later, which can prevent the lead line LE from being peeled off from the printed base film 310.

[0092] The fourth conductive layer 150 may be disposed on the first through-hole layer VIA1. The fourth conductive layer 150 may include a data line DL, a connection electrode CNE, and a high power supply voltage line ELVDDL. The data line DL may be electrically connected to the source electrode SE of the thin film transistor TFT through a contact hole passing through the first through-hole layer VIA1. The connection electrode CNE may be electrically connected to the drain electrode DE of the thin film transistor TFT through a contact hole passing through the first through-hole layer VIA1. The high power supply voltage line ELVDDL may be electrically connected to the high power supply voltage electrode ELVDDE through a contact hole passing through the first through-hole layer VIA1. The fourth conductive layer 150 may include a material that may form the third conductive layer 140 described above.

[0093] The second via layer VIA2 is disposed on the fourth conductive layer 150. The second via layer VIA2 may include a material that may form the above-mentioned first via layer VIA1.

[0094] The anode electrode AND is disposed on the second via layer VIA2. The anode electrode AND may be electrically connected to the connection electrode CNE through a contact hole penetrating the second via layer VIA2.

[0095] The bank layer BANK may be disposed on the anode electrode AND. The bank layer BANK may include a contact hole through which the anode electrode AND is exposed. The bank layer BANK may include an organic insulating material or an inorganic insulating material. For example, the bank layer BANK may include at least one of a photoresist, a polyimide resin, an acrylic resin, a silicon compound, a polyacrylic resin, and the like.

[0096] The organic layer EL may be disposed on the upper surface of the anode electrode AND and the opening of the bank layer BANK. The cathode electrode CAT is disposed on the organic layer EL and the bank layer BANK. The cathode electrode CAT may be a common electrode disposed on a plurality of pixels.

[0097] The thin film encapsulation layer 170 is disposed on the cathode electrode CAT. The thin film encapsulation layer 170 may cover the organic light emitting diode OLED. The thin film encapsulation layer 170 may include a stack of inorganic layers and organic layers alternately disposed on each other. For example, the thin film encapsulation layer 170 may include a first inorganic encapsulation layer 171, an organic encapsulation layer 172, and a second inorganic encapsulation layer 173 sequentially stacked on each other.

[0098] The stacking structure and shape of the gate signal lines GSL and the signal lines PAD in the panel pad area P_PA are not limited to those shown in the drawings and may be modified.

[0099] For example, in some exemplary embodiments, the gate signal line GSL may include a plurality of patterns, and the signal line PAD disposed on the gate signal line GSL may have surface irregularities reflecting a step difference of the gate signal line GSL.

[0100] In some exemplary embodiments, an auxiliary pad of the second conductive layer 130 may be further provided between the gate signal line GSL and the signal line PAD. In this case, the size of the auxiliary pad may be smaller than the size of the signal line PAD when viewed from the top. The signal line PAD, the auxiliary pad, and the gate signal line GSL may overlap each other in the thickness direction and may be electrically connected to each other.

[0101] In some exemplary embodiments, the gate signal line GSL may be formed as the second conductive layer 130 , and the signal line PAD may be formed as the fourth conductive layer 150 .

[0102] Reference Figure 3 , a plurality of signal lines (hereinafter also referred to as signal wirings) PAD may be arranged along the first direction DR1. The plurality of signal wirings PAD may include, for example, a power pad, a data pad, and a panel dummy pad. The first direction DR1 may extend from one end of the panel pad area P_PA toward the display area DA. The second direction DR2 may refer to a direction intersecting with the first direction DR1. The plurality of signal wirings PAD may have a width greater than a width of a gate signal line (hereinafter also referred to as gate signal wiring) GSL in the second direction DR2. The plurality of signal wirings PAD may extend to the end of the display substrate 101 with an expanded width.

[0103] In addition, a plurality of lead wirings LE may be provided in the first circuit region CA1 and may be arranged along the first direction DR1. The plurality of lead wirings LE may include a power lead, a data lead, and a dummy lead. The plurality of lead wirings LE may extend from the driver integrated circuit 390 and may have a width extended in the second direction DR2 in the first circuit region CA1. Therefore, the lead wirings LE may have an increased connection area, and thus, as shown in FIG. Figure 4 As shown in FIG. 3 , the plurality of lead wirings LE may be extended to the end of the printed base film 310 with an expanded width.

[0104] The lead wiring LE having the expanded width may have a substantially rectangular shape. More specifically, the lead wiring LE having the expanded width may include a shorter side edge and a longer side edge.

[0105] When viewed from the top, the first curable pattern IRP may be formed around the lead wiring LE. The first curable pattern IRP may be disposed between adjacent lead wirings LE. The first curable pattern IRP may extend to the end of the first circuit area CA1 of the printed base film 310. When viewed from the top, the first curable pattern IRP may surround the longer side edge of the lead wiring LE and the shorter side edge adjacent to the driver integrated circuit 390, but may not surround the shorter side edge of the upper portion of the lead wiring LE.

[0106] The first curable pattern IRP may include a curable resin. The first curable pattern IRP may have a first average curing rate.

[0107] When viewed from the top, a second curable pattern UFR may be formed around the signal wiring PAD. The second curable pattern UFR may be disposed between adjacent signal wiring PADs. The second curable pattern UFR may extend to the end of the panel pad area P_PA of the display substrate 101. When viewed from the top, the second curable pattern UFR may surround the longer side edge of the signal wiring PAD and the shorter side edge adjacent to the display area DA, but may not surround the lower shorter side edge of the signal wiring PAD.

[0108] The second curable pattern UFR may include a curable resin. The second curable pattern UFR may have a second average curing rate lower than a first average curing rate of the first curable pattern IRP.

[0109] Reference Figure 4, the signal wiring PAD may be connected to the lead wiring LE, respectively. According to the exemplary embodiment shown, the signal wiring PAD and the lead wiring LE have substantially the same width. However, the inventive concept is not limited thereto, and in some exemplary embodiments, the signal wiring PAD and the lead wiring LE may have different widths in the second direction DR2. Specifically, in the second direction DR2, the width of the lead wiring LE may be smaller than the width of the signal wiring PAD. The signal wiring PAD may be directly connected to the lead wiring LE, and may be ultrasonically bonded. Figure 3 The first circuit area CA1 rotated 180 degrees is attached to the Figure 3 The panel pad area P_PA. When viewed from the top, the second curable pattern UFR may be formed around the lead wiring LE. The second curable pattern UFR may be disposed between adjacent lead wirings LE. The second curable pattern UFR may extend to the end of the first circuit area CA1 of the printed base film 310. As described above with reference to Figure 3 As described, when viewed from the top, the first curable pattern IRP may surround the longer side edge of the lead wiring LE and the lower shorter side edge of the lead wiring LE adjacent to the driver integrated circuit 390, but may not surround the upper shorter side edge of the lead wiring LE.

[0110] Before performing the ultrasonic bonding process on the signal line PAD and the lead line LE, the printed circuit board 300 is provided with a first curable pattern IRP2 (see Fig.16 ) is formed in the form of a first curable pattern IRP. However, the second curable pattern UFR is formed on the printed circuit board 300 and the display panel 100 after the ultrasonic bonding process. Therefore, the first curable pattern IRP is not disposed on the upper side of the end of the printed base film 310, for example, on the upper side in the first direction DR1, and the second curable pattern UFR may be extended further toward the upper side of the end of the printed base film 310 than the first curable pattern IRP. Specifically, the second curable pattern UFR may be extended to be closer to the display area DA than the first curable pattern IRP.

[0111] Reference Figure 5 The gate signal line GSL may be disposed from the display area DA to the panel pad area P_PA, and may have an expanded width in the second direction DR2 at least in a portion of the gate signal line GSL overlapping the signal line PAD of the panel pad area P_PA.

[0112] The second insulating layer 112b may include a plurality of contact holes CNT that connect the signal wiring PAD with the gate signal wiring GSL located therebelow. Figure 5Three contact holes CNTs arranged in a row in the first direction DR1 and spaced apart from each other are shown, but the inventive concept is not limited to a specific number and arrangement of the contact holes CNTs. In some exemplary embodiments, one, two, or four or more contact holes CNTs may be arranged in a plurality of rows.

[0113] Reference Figure 6 The second curable pattern UFR may be disposed on a portion of the second insulating layer 112b on which the signal line PAD is not disposed, and may be in direct contact with the second insulating layer 112b. The second curable pattern UFR may overlap the gate signal line GSL disposed below the second curable pattern UFR in the thickness direction on the portion of the second insulating layer 112b.

[0114] like Figure 6 As shown in FIG, the second curable pattern UFR disposed adjacent to the upper short side of the signal line PAD may contact the side surface of the signal line PAD and the side surface of the lead line LE. The second curable pattern UFR may also contact the side surface of the printed base film 310. In addition, the adjacent Figure 5 The second curable pattern UFR disposed at the lower short side of the signal line PAD may overlap the upper lead line LE in the thickness direction.

[0115] Reference Figure 7 , the second curable pattern UFR may be in contact with a portion of the lower surface of each lead wiring LE facing the upper surface of the signal wiring PAD, and in contact with a portion of the side surface of each lead wiring LE. The second curable pattern UFR may be in contact with the first curable pattern IRP in the thickness direction and may overlap with the first curable pattern IRP. The second curable pattern UFR may be disposed between adjacent signal wirings PAD.

[0116] The first curable pattern IRP may be disposed on the printed base film 310. The first curable pattern IRP may be disposed between adjacent lead wirings LE. The first curable pattern IRP may contact a portion of the lower surface of the printed base film 310 that is exposed between the lead wirings LE. The first curable pattern IRP may overlap with a second curable pattern UFR disposed thereunder. A portion of the first curable pattern IRP may contact the second curable pattern UFR disposed thereunder, and another portion thereof may not contact the second curable pattern UFR. Figure 7 As shown in the enlarged circle of , the lower surface of the first curable pattern IRP contacts the upper surface of the second curable pattern UFR disposed thereunder, and a gap may exist between them, so that the lower surface of the first curable pattern IRP may be partially separated from the upper surface of the second curable pattern UFR.

[0117] The first curable pattern IRP may not overlap the signal line PAD and the gate signal line GSL. However, as described above, when the width of the lead line LE in the second direction DR2 is smaller than the width of the signal line PAD in the second direction DR2, the first curable pattern IRP may partially overlap the signal line PAD located thereunder.

[0118] Reference Figure 8 , the lead LE may include a side surface LES2 and a lower surface LES1 facing the upper surface of the signal line PAD. The first curable pattern IRP may include a lower surface IRPa facing the second curable pattern UFR. The second curable pattern UFR may be in contact with a portion of the lower surface LES1 and a portion of the side surface LES2 of the lead LE. In addition, at least a portion of the second curable pattern UFR may be in contact with the lower surface IRPa of the first curable pattern IRP. The height of the first curable pattern IRP from the surface of the printed base film 310 may be less than the height of the lead LE from the surface of the printed base film 310. In this case, the first curable pattern IRP may be in contact with the side surface LES2 of the lead LE exposed by the second curable pattern UFR.

[0119] In some exemplary embodiments, the first curable pattern IRP may completely cover the side surface LES2 of the lead LE. Specifically, the height of the first curable pattern IRP from the surface of the printed base film 310 may be substantially the same as the height of the lead LE from the surface of the printed base film 310. In this case, the second curable pattern UFR may contact the lower surface LES1 of the lead LE, but not the side surface LES2 of the lead LE.

[0120] Reference Figure 2 , Fig. 9 and Fig.10 , by applying vibration and load downward to the printed circuit board 300 via the vibration transmitter 740 of the ultrasonic device 700, the printed base film 310 and the lead wiring LE can be lowered downward. As described above, the lead wiring LE can be directly connected to the signal wiring PAD, respectively. After the ultrasonic bonding process is completed, the vibration transmitter 740 of the ultrasonic device 700 is separated from the upper surface of the printed base film 310, so that the printed base film 310 and the lead wiring LE can rise back to their previous positions. As a result of the ultrasonic bonding, the second coupling force F2 between the signal line PAD and the lead LE can be greater than the first coupling force F1 between the lead LE and the printed base film 310. In this way, the lead wiring LE may be peeled off from the printed base film 310.

[0121] In view of the above, according to the exemplary embodiment, in the display device 1, the first curable pattern IRP is disposed between adjacent lead wirings LE, and thus, the lead wirings LE can be prevented from being peeled off from the printed base film 310. More specifically, as Fig.10 As shown in , the first curable pattern IRP is bonded to the adjacent lead wire LE with the third coupling force F3 and is bonded to the printed base film 310 with the fourth coupling force F4, so that the lead wire LE is attached to the printed base film 310 by the sum of the third coupling force F3 and the fourth coupling force F4. In this way, even if the second coupling force F2 is greater than the first coupling force F1, the increased force can substantially offset the difference between the first coupling force F1 and the second coupling force F2. In this way, even if the printed base film 310 and the lead wire LE rise back to their previous positions after the ultrasonic bonding process is completed, the lead wire LE can be prevented from peeling off from the printed base film 310.

[0122] The first curable pattern IRP may include a material having a high coupling force with each of the lead line LE and the printed base film 310 , respectively, to increase the third coupling force F3 and the fourth coupling force F4 .

[0123] In addition, when the printed base film 310 and the lead wiring LE rise after the ultrasonic bonding process is completed, the deformation rate of the printed base film 310 in the thickness direction in the portion where the lead wiring LE is not provided can be greater than the deformation rate of the printed base film 310 in the thickness direction in the portion where the lead wiring LE is provided. Therefore, according to an exemplary embodiment, the first curable pattern IRP has a lower surface height than the lead wiring LE and is spaced apart from the display substrate 101 provided thereunder, but the first curable pattern IRP includes a material having a higher curing rate than the above-mentioned second curable pattern UFR. Therefore, the deformation rate of the printed base film 310 where the lead wiring LE is not provided can be reduced. In this way, the edge of the lead wiring LE can be prevented from being peeled off from the printed base film 310 due to the larger deformation rate of the printed base film 310 where the lead wiring LE is not provided.

[0124] Hereinafter, a display device according to other exemplary embodiments will be described. In the following description, the same or similar elements will be referred to by the same or similar reference numerals, and redundant descriptions will be omitted or briefly described.

[0125] Fig.11 is a cross-sectional view of a panel pad area and a printed circuit board attached to the panel pad area of ​​a display panel according to another exemplary embodiment. Fig.12 yes Fig.11 An enlarged view of portion C of FIG.

[0126] In addition to providing an organic insulation pattern OIP between adjacent signal wirings PAD, Fig.11 and Fig.12 The display device 2 of the exemplary embodiment shown in FIG. 2 is substantially the same as the display device 1 .

[0127] More specifically, in the display device 2 according to the exemplary embodiment shown, an organic insulation pattern OIP may be further provided between adjacent signal wirings PAD. The organic insulation pattern OIP may be provided on the display substrate 101. The organic insulation pattern OIP may include the same Figure 2 The described first via layer VIA1 or the second via layer VIA2 are made of substantially the same material and may be formed together through the same process.

[0128] Since the organic insulating pattern OIP is disposed between adjacent signal wiring PADs, short circuits between adjacent signal wiring PADs can be prevented. In addition, when a load is applied to the printed base film 310, the organic insulating pattern OIP can prevent the portion of the printed base film 310 where the lead LE is not disposed from sinking too much.

[0129] The second curable pattern UFR may be disposed between the organic insulation pattern OIP and the first curable pattern IRP. An upper surface and a side surface of the organic insulation pattern OIP may be in direct contact with the second curable pattern UFR.

[0130] like Fig.12 As shown in , the lower surface IRPa-1 of the first curable pattern IRP-1 may include a first part IRPa and a second part IRPb. The first roughness of the first part IRPa may be less than the second roughness of the second part IRPb. In other words, the second roughness may be greater than the first roughness. The second part IRPb may overlap with the upper surface OIPa of the organic insulation pattern OIP. In addition, the upper surface OIPa of the organic insulation pattern OIP may include surface scratches. This is because when the vibration transmitter 740 of the ultrasonic device 700 applies a load downward to the printed circuit board 300, the second part IRPb may be brought into contact with the upper surface OIPa of the organic insulation pattern OIP, which may change the surface roughness of the organic insulation pattern OIP due to vibration.

[0131] According to the illustrated exemplary embodiment, in the display device 2 , the first curable pattern IRP- 1 is disposed between adjacent lead wirings LE, and thus, the lead wirings LE may be prevented from being peeled off from the printed base film 310 .

[0132] When the printed base film 310 and the lead wiring LE rise after the ultrasonic bonding process is completed, the deformation rate of the printed base film 310 in the thickness direction in the portion where the lead wiring LE is not provided can be greater than the deformation rate of the printed base film 310 in the thickness direction in the portion where the lead wiring LE is provided. According to the exemplary embodiment shown, the first curable pattern IRP-1 has a surface height lower than the surface height of the lead LE from the printed base film 310, and is spaced apart from the display substrate 101 provided thereunder, but includes a material having a higher curing rate than the above-mentioned second curable pattern UFR. Therefore, the deformation rate of the printed base film 310 in the portion where the lead wiring LE is not provided can be reduced. In this way, the edge of the lead wiring LE can be prevented from being peeled off from the printed base film 310 due to the larger deformation rate of the printed base film 310 in the portion where the lead wiring LE is not provided.

[0133] Fig.13 is a flowchart illustrating a method for manufacturing a display device according to an exemplary embodiment. Figures 14 to 18 is a cross-sectional view illustrating a method of manufacturing a display device according to an exemplary embodiment.

[0134] refer to Figures 13 to 15 , a first curable resin IRP1 having a surface height less than or equal to that of the lead wirings LE is applied between adjacent lead wirings LE provided on the printed base film 310 (step S10 ).

[0135] The step S10 of applying the first curable resin IRP1 may include forming a plurality of lead wirings LE on the printed base film 310, such as Fig.14 As shown in . For example, the lead wiring LE may be formed via a deposition process.

[0136] The lead wiring LE may include a metal. The lead wiring LE may include at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). In an exemplary embodiment, the lead wiring LE may include copper (Cu) and gold (Au). More specifically, the lead wiring LE may include copper (Cu) disposed on the printed base film 310 and gold (Au) disposed on the copper (Cu).

[0137] After forming the plurality of lead wirings LE on the printed base film 310 , the first curable resin IRP1 may be applied such that the surface height of the first curable resin IRP1 is less than or equal to the surface height of the lead wirings LE.

[0138] For example, the first curable resin IRP1 may include a photocurable resin.

[0139] The first curable resin IRP1 may be disposed on the printed base film 310. The first curable resin IRP1 may be disposed between adjacent lead wirings LE. The first curable resin IRP1 may contact a portion of the lower surface of the printed base film 310 exposed between the lead wirings LE. The first curable resin IRP1 may contact at least a portion of a side surface of the lead wiring LE.

[0140] Next, refer to Fig.13 and Fig.16 , the applied first curable resin IRP1 is cured to form a first curable pattern IRP2 (step S20 ).

[0141] The step S20 of curing the first curable resin IRP1 to form the first curable pattern IRP2 may be performed using an ultraviolet laser.

[0142] After the curing process using the ultraviolet laser, the first curable pattern IRP2 may have a third average curing rate. The third average curing rate may be less than the first average curing rate.

[0143] Next, refer to Fig. 9 and Fig.13 The signal wiring PAD and the lead wiring LE on the display substrate 101 are ultrasonically bonded or are ultrasonically bonded to each other.

[0144] More specifically, the signal wiring PAD and the lead wiring LE on the display substrate 101 may be ultrasonically bonded or ultrasonically bonded to each other by using the ultrasonic device 700. The printed base film 310 and the lead wiring LE may be lowered downward by applying vibration and load downward to the printed circuit board 300 via the vibration transmitter 740 of the ultrasonic device 700. As described above, the lead wiring LE may be directly connected to the signal wiring PAD, respectively.

[0145] When the lead LE ultrasonically vibrates on the surface of the signal line PAD, frictional force is generated at the interface between the signal line PAD and the lead LE, so that frictional heat can be generated due to the frictional force. When the frictional heat is high enough to melt the materials of the signal line PAD and the lead LE, the melting area PADb of the signal line PAD adjacent to the lead LE and the melting area LEb of the lead LE adjacent to the signal line PAD can be melted. More specifically, the signal line PAD may include a non-melting area PADa and a melting area PADb. Similarly, the lead LE may include a non-melting area LEa and a melting area LEb.

[0146] Next, refer to Fig.10 and 13, after the ultrasonic bonding process is completed, the vibration transmitter 740 of the ultrasonic device 700 is separated from the upper surface of the printed base film 310.

[0147] Then, the printed base film 310 and the lead wiring LE may rise back to the previous position. Due to ultrasonic bonding, the second coupling force F2 between the signal line PAD and the lead LE may be greater than the first coupling force F1 between the lead LE and the printed base film 310. In this way, the lead wiring LE may be peeled off from the printed base film 310.

[0148] In consideration of the above, according to an exemplary embodiment, the ultrasonic bonding process may be performed when the first curable pattern IRP2 is located between adjacent lead wirings LE, so that the lead LE may be prevented from being peeled off from the printed base film 310 .

[0149] Next, refer to Fig.13 and Fig.17 , a second curable resin UFR1 is applied between the first curable pattern IRP2 and the display substrate 101 .

[0150] The second curable resin UFR1 may be disposed between adjacent signal wiring PADs. The second curable resin UFR1 may extend to the end of the panel pad area P_PA of the display substrate 101. When viewed from the top, the second curable resin UFR1 may surround the longer side edge of the signal wiring PAD and the shorter side edge adjacent to the display area DA, but may not surround the lower shorter side edge of the signal wiring PAD.

[0151] The second curable resin UFR1 may contact a portion of the lower surface of each lead wiring LE facing the upper surface of the signal wiring PAD, and contact a portion of the side surface of each lead wiring LE. The second curable resin UFR1 may contact and overlap the first curable pattern IRP2 in the thickness direction. The second curable resin UFR1 may be provided between adjacent signal wirings PAD.

[0152] A portion of the second curable resin UFR1 may be in contact with the first curable pattern IRP2 disposed thereon, and another portion thereof may not be in contact with the first curable pattern IRP2.

[0153] Next, refer to Fig.18 , the first curable pattern IRP2 and the second curable resin UFR1 are cured to form the first curable pattern IRP and the second curable pattern UFR, respectively.

[0154] As in forming the first curable pattern IRP2, curing the first curable pattern IRP2 and the second curable resin UFR1 may be performed by using an ultrasonic laser.

[0155] The first curable pattern IRP may have a first average curing rate, and the second curable pattern UFR may have a second average curing rate. The first average curing rate may be greater than the second average curing rate.

[0156] When the printed base film 310 and the lead wiring LE rise after the ultrasonic bonding process is completed, the deformation rate of the printed base film 310 in the thickness direction in the portion where the lead wiring LE is not provided can be greater than the deformation rate of the printed base film 310 in the thickness direction in the portion where the lead wiring LE is provided. Thus, according to an exemplary embodiment, the first curable pattern IRP has a lower surface height from the printed base film 310 than the lead wiring LE and is spaced apart from the display substrate 101 provided thereunder, but as described above, the first curable pattern IRP includes a material having a higher curing rate than the second curable pattern UFR. Therefore, the deformation rate of the printed base film 310 in the portion where the lead wiring LE is not provided can be reduced. In this way, the edge of the lead wiring LE can be prevented from being peeled off from the printed base film 310 due to the larger deformation rate of the printed base film 310 in the portion where the lead wiring LE is not provided.

[0157] Fig.19 is a plan view of a display device according to still another exemplary embodiment. Fig. 20 is a cross-sectional view of a display device according to still another exemplary embodiment.

[0158] Reference Fig.19 and Fig. 20 , the display panel 100_1 of the display device 3 according to the illustrated exemplary embodiment may further include a bending area BA.

[0159] The display substrate of the display panel 100_1 may be made of an insulating material such as a polymer resin. The material of the polymer resin may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. The display substrate may be a flexible substrate that can be bent, folded, or curled, and may include polyimide (PI), but is not limited thereto.

[0160] The bending area BA may be formed between the pixel array and the panel pad area P_PA_1. The bending area BA may be located in the non-display area NA. The display panel 100_1 may be folded relative to a bending line, which is a reference line provided in the bending area BA. The bending line may be a straight line substantially parallel to the lower side (or upper side) of the display panel 100_1. Fig. 20As shown in FIG. 1 , the bending area BA of the display panel 100_1 may be bent downward in the third direction DR3 .

[0161] In some exemplary embodiments, the display area DA and the panel pad area P_PA_1 may be connected to each other without the bending area BA. More specifically, without the bending area BA in the display panel 100_1, the entire display area DA and the non-display area NA may be substantially flat.

[0162] In the panel pad area P_PA_1, the above reference Figure 3 The driver integrated circuit 900 may be attached to the plurality of signal wiring PADs. The main circuit board 500_1 of the display device 3 is connected to the display panel 100_1 through the panel pad area P_PA_2.

[0163] According to an exemplary embodiment, a chip on plastic (COP) or a chip on glass (COG) may be used as the driver integrated circuit 900. The driver integrated circuit 900 may include a plurality of protrusions connected to a plurality of signal wirings PAD, respectively. The protrusions may be formed of at least one of gold (Au), nickel (Ni), and tin (Sn).

[0164] According to an exemplary embodiment, the protrusions of the driver integrated circuit 900 may directly contact and bond with the corresponding signal wiring PAD without a layer or structure interposed therebetween. The signal wiring PAD and the protrusions of the driver integrated circuit 900 may be bonded to each other by ultrasonic bonding.

[0165] According to the exemplary embodiment, it is possible to prevent the lead from being peeled off from the printed base film of the printed circuit board.

[0166] Although some exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to these embodiments, but to the broader scope of the appended claims and to various obvious modifications and equivalent arrangements that will be apparent to those of ordinary skill in the art.

Claims

1. Display device, include: The display panel comprises a display substrate having a display area and a pad area around the display area, and a plurality of signal wirings arranged in the pad area of ​​the display substrate; a base film attached to the pad region of the display substrate; a plurality of lead wirings disposed on the base film and connected to the plurality of signal wirings; a first curable pattern disposed between adjacent lead wirings of the plurality of lead wirings; as well as a second curable pattern disposed between adjacent signal wirings among the plurality of signal wirings, wherein the surface height of the first curable pattern from the surface of the base film is less than the surface height of the lead wiring from the surface of the base film, The first curable pattern includes a curable resin having a first average curing rate, and the second curable pattern includes a curable resin having a second average curing rate that is less than the first average curing rate.

2. The display device according to claim 1, in, The first curable pattern is spaced apart from the display substrate.

3. The display device according to claim 2, in, The first curable pattern is in contact with at least a portion of a side surface of the lead wiring and the surface of the base film.

4. The display device according to claim 3, in, The first curable pattern is bonded to the at least a portion of the side surface of the lead wiring and the surface of the base film.

5. The display device according to claim 3, in, A first portion of the second curable pattern contacts the first curable pattern, and a second portion of the second curable pattern does not contact the first curable pattern, and the second curable pattern partially contacts the first curable pattern with a gap formed therebetween.

6. The display device according to claim 5, in: The first curable pattern exposes a lower end portion of a side surface of each of the plurality of lead wirings; as well as The second curable pattern contacts the exposed lower end portion of the side surface of each of the plurality of lead wirings.

7. The display device according to claim 6, in, The second curable pattern is in contact with a lower surface of each of the plurality of lead wirings facing an upper surface of a corresponding signal wiring of the plurality of signal wirings and is in contact with an upper surface of each of the plurality of signal wirings.

8. A method for manufacturing a display device, the method The following steps are involved: applying a first curing resin between adjacent lead wirings among the lead wirings provided on the base film, the surface height of the first curing resin being smaller than the surface height of the lead wirings; curing the applied first curable resin to form a first curable pattern; applying a second curable resin between adjacent signal wirings among signal wirings disposed on the display substrate, wherein a second average curing rate of the second curable resin is lower than a first average curing rate of the first curable resin; as well as The signal wiring is coupled to the lead wiring.

9. The method according to claim 8, in, The step of coupling the signal wiring with the lead wiring includes bringing the signal wiring into direct contact with the lead wiring.

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