Method of forming a vertical field effect transistor device

Abstract

A method for forming a vertical field-effect transistor device is provided. The method may include forming a first channel region and a second channel region on a substrate, forming a liner on the substrate and the first and second channel regions, forming a recess in the substrate between the first and second channel regions by removing a portion of the liner and a portion of the substrate, forming a bottom source / drain region in the recess of the substrate, forming a capping layer on the bottom source / drain region, removing the liner and the capping layer, forming spacers on the substrate and the bottom source / drain region, and forming a gate structure on side surfaces of the first and second channel regions.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 62 / 845,924, filed on May 10, 2019, in the USPTO, entitled “VFET FLAT BOTTOM SPACERFORMATION USING CAPPING LAYER ON EPI FILM,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to the field of electronic devices, and more particularly, to vertical field-effect transistor (VFET) devices. Background Art

[0004] Due to the high scalability of VFET devices, various structures and fabrication processes for VFET devices have been studied. The fabrication process for VFET devices may degrade performance by increasing the distance between the bottom source / drain region and the gate structure. Summary of the Invention

[0005] According to some embodiments of the present invention, a method of forming a VFET device may include: forming a first channel region and a second channel region on a substrate; forming a liner on the substrate and the first and second channel regions; forming a recess in the substrate between the first and second channel regions by removing a portion of the liner and a portion of the substrate; forming a bottom source / drain region in the recess of the substrate; forming a capping layer on the bottom source / drain region; removing the liner and the capping layer; forming a spacer on the substrate and the bottom source / drain region; and forming a gate structure on side surfaces of the first and second channel regions. The first and second channel regions may protrude from the substrate, and the spacer may extend between the gate structure and the substrate.

[0006] According to some embodiments of the present invention, a method of forming a VFET device may include: forming a first channel region and a second channel region; forming a liner on a substrate and side surfaces of the first and second channel regions; forming a recess in the substrate between the first and second channel regions by removing a portion of the liner and a portion of the substrate; and forming a bottom source / drain region in the recess of the substrate. The first and second channel regions may protrude from the substrate. The bottom source / drain region may include an upper surface exposed by the substrate. The method may further include removing the liner. Removing the liner may not change the profile of the upper surface of the bottom source / drain region and may expose the side surfaces of the first and second channel regions. The method may further include, after removing the liner, forming spacers on the substrate and the bottom source / drain region, and forming a gate structure on the side surfaces of the first and second channel regions. The spacer may extend between the gate structure and the substrate.

[0007] According to some embodiments of the present invention, a method of forming a VFET device may include: forming a first channel region and a second channel region; forming a bottom source / drain region in a substrate between the first channel region and the second channel region; forming a spacer on the substrate and the bottom source / drain region; and forming a gate structure on side surfaces of the first channel region and the second channel region. The first channel region and the second channel region may protrude from the substrate. The bottom source / drain region may include an upper surface exposed by the substrate, and the upper surface of the bottom source / drain region may not have a recess. The spacer may have a unitary structure and may contact the side surfaces of the first channel region and the second channel region. The spacer may extend between the gate structure and the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a flow chart illustrating a method of forming a VFET device according to some embodiments of the present inventive concept.

[0009] Figures 2 to 8 is a cross-sectional view illustrating a method of forming a VFET device according to some embodiments of the inventive concept.

[0010] Figures 9 to 14 is a cross-sectional view illustrating a method of forming a VFET device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0011] Example embodiments are described below with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the spirit and teachings of the present invention, and therefore the present disclosure should not be construed as limited to the example embodiments set forth herein. On the contrary, these example embodiments are provided to make this disclosure thorough and complete and to convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Throughout the text, the same reference numerals refer to the same elements.

[0012] Example embodiments of the present inventive concepts are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, example embodiments of the present inventive concepts should not be construed as limited to the particular shapes illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.

[0013] During the manufacturing process of the VFET device, the upper surface of the bottom source / drain region may be partially removed, and a recess may be formed in the upper surface of the bottom source / drain region. The recess in the upper surface of the bottom source / drain region may change (e.g., increase) the distance between the bottom source / drain region and the gate structure, thereby potentially degrading the performance of the VFET device.

[0014] Figure 1 is a flow chart illustrating a method of forming a VFET device according to some embodiments of the present inventive concept. Figures 2 to 8 is a cross-sectional view illustrating a method of forming a VFET device according to some embodiments of the inventive concept.

[0015] refer to Figures 1 to 3 , the method may include forming channel regions 12 protruding from the substrate 10 (e.g., from the upper surface 10_S of the substrate 10) (S110). Each of the channel regions 12 may protrude in a vertical direction that may be perpendicular to the upper surface 10_S of the substrate 10. In some embodiments, forming the channel regions 12 may include forming a mask layer 14 on the substrate 10, and etching the substrate 10 using the mask layer 14 as an etching mask to form the channel regions 12. Therefore, the channel regions 12 may be part of the substrate 10. In some embodiments, as Figure 2 As shown, after forming the channel region 12, the mask layer 14 may remain on the channel region 12. For example, the mask layer 14 may be a hard mask layer. In some embodiments, the mask layer 14 may be omitted. For example, forming the channel region 12 may include performing a selective epitaxial growth process using the substrate 10 as a seed layer without using the mask layer 14.

[0016] The substrate 10 may include one or more semiconductor materials, for example, Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP. In some embodiments, the substrate 10 may be a bulk substrate (e.g., a bulk silicon substrate) or a semiconductor on insulator (SOI) substrate.

[0017] refer to Figure 1 and Figure 2 , the method may include forming a protective layer 16 on the channel region 12 and the substrate 10 (S120). In some embodiments, the protective layer 16 may have a uniform thickness along the surface (e.g., side surface) of the channel region 12 and the upper surface 10_S of the substrate 10, but the present inventive concept is not limited thereto. In some embodiments, the protective layer 16 may have a first thickness on the side of the channel region 12 that is thicker than a second thickness of the protective layer 16 on the upper surface 10_S of the substrate 10. The protective layer 16 may include a material different from that of the substrate 10 and may have an etching selectivity relative to the substrate 10. For example, the protective layer 16 may include a silicon nitride layer and / or a silicon oxynitride layer.

[0018] It should be understood that protection layer 16 may be referred to as a liner or protective liner because protection layer 16 has a liner shape extending along the surface of channel region 12 and upper surface 10_S of substrate 10. In some embodiments, protection layer 16 may contact the surface of channel region 12 and upper surface 10_S of substrate 10.

[0019] refer to Figure 1 and Figure 3 , a portion of the protective layer 16 and a portion of the substrate 10 may be removed to form a recess 21 in the substrate 10 between the channel regions 12 (S130). Removing a portion of the protective layer 16 and a portion of the substrate 10 may be performed by one or more of various processes (including, for example, a dry etching process and / or a wet etching process). Although not shown, it should be understood that a mask layer may be formed to selectively remove a portion of the protective layer 16 and a portion of the substrate 10.

[0020] refer to Figure 1 and Figure 4 , the method may include forming a bottom source / drain region 22 in the recess 21 (S140), and forming a capping layer 23 on an upper surface 22_S of the bottom source / drain region 22 (S150). The substrate 10 may not cover the upper surface 22_S of the bottom source / drain region 22, and thus the upper surface 22_S of the bottom source / drain region 22 may be exposed by the substrate 10. The upper surface 22_S of the bottom source / drain region 22 may remain exposed until the capping layer 23 is formed thereon. In some embodiments, as Figure 4 As shown, the lower surface of the capping layer 23 may contact the upper surface 22_S of the bottom source / drain region 22. For example, the bottom source / drain region 22 may include a semiconductor material including a first dopant.

[0021] The capping layer 23 may include a material different from the protective layer 16 and may have an etch selectivity relative to the protective layer 16. Therefore, the capping layer 23 may cover and / or protect the upper surface 22_S of the bottom source / drain region 22 when the protective layer 16 is removed during subsequent processes.

[0022] For example, the capping layer 23 may include an undoped semiconductor layer (e.g., an undoped silicon layer) and / or a semiconductor layer including a second dopant (e.g., a silicon layer including phosphorus). It should be understood that the undoped semiconductor layer may not have dopants intentionally added thereto and may be substantially free of dopants. However, it should also be understood that an undoped semiconductor layer is not necessarily free of unintentionally added dopants. In some embodiments, the undoped semiconductor layer may include dopants from adjacent elements, for example, through diffusion of dopants.

[0023] When the capping layer 23 includes a doped semiconductor layer, the doping concentration of the semiconductor layer of the capping layer 23 may be lower than the doping concentration of the bottom source / drain region 22. In some embodiments, the doping concentration of the semiconductor layer of the capping layer 23 may be less than 15% of the doping concentration of the bottom source / drain region 22. For example, the doping concentration of the semiconductor layer of the capping layer 23 may be approximately 7% of the doping concentration of the bottom source / drain region 22. For example, the doping concentration of the semiconductor layer of the capping layer 23 may be approximately 1E20 atoms / cm3.

[0024] In some embodiments, the bottom source / drain region 22 may be formed by performing an epitaxial growth process (e.g., a selective epitaxial growth process) using the surface of the recess 21 as a seed layer. In some embodiments, the capping layer 23 may be formed by performing an epitaxial growth process (e.g., a selective epitaxial growth process) using the bottom source / drain region 22 as a seed layer.

[0025] In some embodiments, the bottom source / drain region 22 and the capping layer 23 can be formed in the same device and / or in the same chamber, and thus can be referred to as being formed in situ. In some embodiments, the capping layer 23 can be formed on the bottom source / drain region 22 without exposing the bottom source / drain region 22 to the outside of the device. In some embodiments, the capping layer 23 can be formed on the bottom source / drain region 22 immediately after the bottom source / drain region 22 is formed (e.g., within 10 seconds).

[0026] In some embodiments, as Figure 4As shown, the thickness of the capping layer 23 in the vertical direction can be uniform. Figure 4 The upper surface of the capping layer 23 is shown to protrude vertically beyond the upper surface of the portion of the protective layer 16 adjacent thereto that contacts the upper surface 10_S of the substrate 10, but the present invention is not limited thereto. In some embodiments, the upper surface of the capping layer 23 may be recessed toward the substrate 10 relative to the upper surface of the portion of the protective layer 16 adjacent to the capping layer 23.

[0027] refer to Figure 1 、 Figure 5 and Figure 6 , the method may include removing the protective layer 16 and the capping layer 23 (S160). Removing the protective layer 16 and the capping layer 23 may expose the side of the channel region 12. In some embodiments, as Figure 5 and Figure 6 As shown, by removing the protection layer 16 and the capping layer 23, the side of the channel region 12 can be completely exposed. Figure 6 As shown, only the upper portion of the capping layer 23 may be removed, and thus the lower portion 23' of the capping layer 23 may remain on the bottom source / drain region 22. In some embodiments, when the channel regions 12 are spaced about 40 nm or more apart from each other, only the upper portion of the capping layer 23 may be removed.

[0028] Removal of the protective layer 16 and the capping layer 23 may be performed by one or more of various processes, including, for example, a dry etching process and / or a wet etching process. In some embodiments, removal of the protective layer 16 and the capping layer 23 may not change the profile of the upper surface 22_S of the bottom source / drain region 22. For example, removal of the protective layer 16 and the capping layer 23 may not remove the bottom source / drain region 22. In some embodiments, as Figure 5 and Figure 6 As shown, removing the protection layer 16 and the capping layer 23 may not form a recess in the upper surface 22_S of the bottom source / drain region 22, and the upper surface 22_S of the bottom source / drain region 22 may remain flat. Therefore, the bottom source / drain region 22 may be aligned with the gate structure (e.g., Figure 7 and Figure 8 The gate structures 35 in the circuit are spaced at uniform distances and can be kept at a relatively close distance to the gate structures.

[0029] refer to Figure 1 、 Figure 7 and Figure 8 The method may include forming a spacer 32 on the substrate 10 and the bottom source / drain region 22 (S170), and forming a gate structure 35 and a top source / drain region 36 on the spacer 32 (S180). In some embodiments, as Figure 8As shown, the spacer 32 may be formed on the lower portion 23 ′ of the capping layer 23 .

[0030] In some embodiments, the spacer 32 may contact the lower portion 23' of the capping layer 23. The spacer 32 may extend between the substrate 10 and the gate structure 35, and thus may separate the gate structure 35 from the substrate 10. In some embodiments, as shown in FIG. Figure 7 and Figure 8 As shown, the spacer 32 may not include a portion protruding into the bottom source / drain region 22 , and a portion of the lower surface of the spacer 32 facing the bottom source / drain region 22 may be flat.

[0031] The spacers 32 may include insulating materials and may electrically isolate the gate structure 35 from the substrate 10 and the bottom source / drain regions 22. Figure 7 and Figure 8 As shown, the spacer 32 may contact the side surface of the channel region 12 (e.g., the lower portion of the side surface of the channel region 12) and may have a single structure. It should be understood that the term "single structure" refers to a structure formed by the same process and / or a structure having no interface between two layers formed by different processes.

[0032] The spacers 32 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. In some embodiments, the spacers 32 may be formed by performing a directional deposition process, such as, for example, a gas cluster ion beam (GCIB) deposition process or a high-density plasma chemical vapor deposition (HDPCVD) process. Therefore, in some embodiments, the spacers 32 may not be formed on the upper portion of the channel region 12 on which the gate structure 35 is formed.

[0033] Still refer to Figure 7 and Figure 8 The gate structure 35 may be formed on the spacer 32 and on the side of the channel region 12. The gate structure 35 may include a plurality of layers sequentially stacked on the side of the channel region 12, such as a gate insulator, a work function regulating layer, a diffusion barrier layer, an etch stop layer, and / or a conductive gate electrode. For example, the gate structure 35 may include a gate insulator 33 and a conductive gate electrode 34.

[0034] The method may include forming top source / drain regions 36 on channel region 12 by performing one or more of various processes. In some embodiments, top source / drain regions 36 may be formed by performing an epitaxial growth process (eg, a selective epitaxial growth process) using channel region 12 as a seed layer.

[0035] Figures 9 to 14 is a cross-sectional view illustrating a method of forming a VFET device according to some embodiments of the present inventive concept. For ease of explanation, the description will focus on differences from the above-described method of forming a VFET device according to some embodiments of the present inventive concept.

[0036] refer to Figure 1 and Figure 9 The method may include forming an expanded recess 21e below the channel region 12 (S130). The expanded recess 21e may expose the entire lower surface of the channel region 12. The expanded recess 21e may be formed by performing one or more of various processes, including, for example, a dry etching process and / or a wet etching process.

[0037] refer to Figure 1 and Figure 10 The method may include forming a bottom source / drain region 22 in the expanded recess 21 e ( S140 ), and forming a capping layer 23 on an upper surface 22_S of the bottom source / drain region 22 ( S150 ).

[0038] refer to Figure 1 、 Figure 11 and Figure 12 , the method may include removing the protective layer 16 and the capping layer 23 (S160). Removing the protective layer 16 and the capping layer 23 may expose the side of the channel region 12. In some embodiments, as Figure 11 and Figure 12 As shown, by removing the protection layer 16 and the capping layer 23, the side of the channel region 12 can be completely exposed. Figure 12 As shown, only the upper portion of the capping layer 23 may be removed, and thus a lower portion 23 ′ of the capping layer 23 may remain on the bottom source / drain region 22 .

[0039] In some embodiments, the protective layer 16 and the capping layer 23 may be removed without changing the profile of the upper surface 22 of the bottom source / drain region 22. For example, the protective layer 16 and the capping layer 23 may be removed without removing the bottom source / drain region 22. In some embodiments, as Figure 11 and Figure 12 As shown, removing the protection layer 16 and the capping layer 23 may not form a recess in the upper surface 22_S of the bottom source / drain region 22 , and the upper surface 22_S of the bottom source / drain region 22 may remain flat.

[0040] refer to Figure 1 、 Figure 13 and Figure 14The method may include forming a spacer 32 on the substrate 10 and the bottom source / drain region 22 (S170), and forming a gate structure 35 on the spacer 32 (S180). In some embodiments, as Figure 14 As shown, the spacer 32 may be formed on the lower portion 23 ′ of the capping layer 23 .

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. It should also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0042] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present inventive concept. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of stated features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups thereof.

[0043] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] It should be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teaching of the present invention, the first element can be called the second element.

[0045] It should also be noted that in some alternative implementations, the function / action marked in the flow chart frame of this paper may not occur according to the order marked in the flow chart.For example, depending on the function / action involved, the two blocks shown continuously can actually be performed substantially simultaneously, or these blocks can sometimes be performed in reverse order.In addition, the function of the given block of flow chart and / or block diagram can be divided into multiple blocks, and / or the function of two or more blocks of flow chart and / or block diagram can be at least partially integrated.Finally, without departing from the scope of the present invention, other blocks can be added / inserted between shown blocks, and / or block / operation can be omitted.

[0046] The above-disclosed subject matter is to be considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the inventive concept. Therefore, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

1. A method for forming a vertical field effect transistor device, the method comprising: forming a first channel region and a second channel region on a substrate, wherein the first channel region and the second channel region protrude from the substrate; forming a liner on the substrate and the first channel region and the second channel region; forming a recess in the substrate between the first channel region and the second channel region by removing a portion of the liner and a portion of the substrate; forming a bottom source / drain region in the recessed portion of the substrate; forming a capping layer on the bottom source / drain region; removing the liner and the capping layer; forming spacers on the substrate and the bottom source / drain region; as well as forming a gate structure on side surfaces of the first channel region and the second channel region, wherein the spacer extends between the gate structure and the substrate, and The capping layer includes an undoped semiconductor layer or a doped semiconductor layer, and the doping concentration of the doped semiconductor layer is less than 15% of the doping concentration of the bottom source / drain region.

2. The method according to claim 1, wherein Forming the capping layer includes performing an epitaxial growth process using the bottom source / drain region as a seed layer.

3. The method according to claim 1, wherein The capping layer includes a material different from that of the liner.

4. The method according to claim 1, wherein Removing the liner and the capping layer includes removing an upper portion of the capping layer and leaving a lower portion of the capping layer, and The forming of the spacer includes forming a portion of the spacer contacting the lower portion of the capping layer.

5. The method according to claim 1, wherein Removing the liner and the capping layer does not change the profile of the upper surface of the bottom source / drain region.

6. The method according to claim 1, wherein Forming the spacer includes forming the spacer contacting the side surfaces of the first and second channel regions.

7. The method according to claim 6, wherein: Forming the spacer includes forming the spacer to have a unitary structure.

8. The method according to claim 1, wherein Forming the spacers includes forming spacers that do not protrude into the bottom source / drain region.

9. The method according to claim 1, wherein forming the bottom source / drain region includes forming the bottom source / drain region including an upper surface exposed by the substrate, and Wherein, the upper surface of the bottom source / drain region has no recess.

10. A method of forming a vertical field effect transistor device, the method comprising: forming a first channel region and a second channel region, wherein the first channel region and the second channel region protrude from a substrate; forming a liner on the substrate and side surfaces of the first channel region and the second channel region; forming a recess in the substrate between the first channel region and the second channel region by removing a portion of the liner and a portion of the substrate; forming a bottom source / drain region in the recessed portion of the substrate, wherein the bottom source / drain region includes an upper surface exposed by the substrate; forming a capping layer in contact with the upper surface of the bottom source / drain region; removing the liner, wherein at least a portion of the capping layer is removed when the liner is removed, and removing the liner does not change a profile of the upper surface of the bottom source / drain region and exposes the side surfaces of the first channel region and the second channel region; After removing the liner, forming spacers on the substrate and the bottom source / drain region; and forming a gate structure on the side surfaces of the first channel region and the second channel region, wherein the spacer extends between the gate structure and the substrate, and The capping layer includes an undoped semiconductor layer or a doped semiconductor layer, and the doping concentration of the doped semiconductor layer is less than 15% of the doping concentration of the bottom source / drain region.

11. The method according to claim 10, wherein: Removing the liner does not form a recess in the upper surface of the bottom source / drain region.

12. The method according to claim 10, wherein: The spacer does not include a protruding portion that protrudes into the bottom source / drain region.

13. The method according to claim 10, wherein: The liner is removed to expose the upper surface of the bottom source / drain region.

14. The method according to claim 10, wherein: Removing the liner includes removing an upper portion of the capping layer and leaving a lower portion of the capping layer, and The forming of the spacer includes forming a portion of the spacer contacting the lower portion of the capping layer.

15. A method of forming a vertical field effect transistor device, the method comprising: forming a first channel region and a second channel region, wherein the first channel region and the second channel region protrude from a substrate; forming a bottom source / drain region in the substrate between the first channel region and the second channel region, wherein the bottom source / drain region includes an upper surface exposed by the substrate, and the upper surface of the bottom source / drain region has no recess; forming a spacer on the substrate and the bottom source / drain region, wherein the spacer has a single structure and contacts side surfaces of the first channel region and the second channel region; forming a capping layer on the bottom source / drain region before forming the spacer; as well as forming a gate structure on the side surfaces of the first channel region and the second channel region, wherein the spacer extends between the gate structure and the substrate, and The capping layer includes an undoped semiconductor layer or a doped semiconductor layer, and the doping concentration of the doped semiconductor layer is less than 15% of the doping concentration of the bottom source / drain region.

16. The method according to claim 15, wherein Forming the spacers includes forming spacers that do not protrude into the bottom source / drain region.

Images