Page buffer and storage device comprising the same

Abstract

The present disclosure provides a page buffer and a memory device including the same. Systems and methods including a page buffer to reduce threshold voltage distribution skew of memory cells and improve programming performance are described. The page buffer includes a first circuit element connected to a first terminal for supplying a first bit line voltage, a second circuit element connected to a second terminal for supplying a second bit line voltage, and a latch configured to control the first circuit element and the second circuit element.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a page buffer and a memory device including the same. BACKGROUND

[0002] Computers use various memory devices to store information. When used for main memory, memory devices operate at high speed to enable immediate access with reduced latency. In many cases, memory devices are located near processing units to further improve access speed.

[0003] Consumers demand smaller and higher capacity memory devices. Compared to two-dimensional designs, vertically stacked memory cells improve cell area efficiency, thereby reducing cell size. As a result, vertically stacked memory cells are increasingly used in various memory devices.

[0004] However, programming speeds of different cells within a memory device including vertically stacked memory cells can differ greatly based on lengths of wiring connected to each cell. Different programming speeds can interfere with efficient operation of the memory device. Therefore, there is a need in the art for a memory device that compensates for programming speed differences. SUMMARY

[0005] Example embodiments provide a memory device that can adjust a bit line voltage provided from a page buffer to reduce threshold voltage distribution skew of memory cells and improve programming performance.

[0006] According to an example embodiment, a page buffer configured to supply a bit line voltage to a bit line connected to a plurality of memory cells includes a first circuit element connected to a first terminal for supplying a first bit line voltage, a second circuit element connected to a second terminal for supplying a second bit line voltage lower than the first bit line voltage, and a latch configured to control the first circuit element and the second circuit element based on whether there is a selected memory cell among the plurality of memory cells, and configured to apply one of the first bit line voltage and the second bit line voltage to the bit line. When there is the selected memory cell among the plurality of memory cells, based on information of a channel connected to the bit line, a level of the second bit line voltage is set lower than a level of the first bit line voltage and higher than or equal to a level of a ground voltage.

[0007] According to one example embodiment, a storage device includes: a plurality of bit lines, including a first bit line and a second bit line; a storage cell array including a plurality of storage cell strings connected to the plurality of bit lines, the plurality of storage cell strings including a first storage cell string and a second storage cell string, the first storage cell string being connected to the first bit line and including a plurality of first storage cells, the second storage cell string being connected to a second bit line and including a plurality of second storage cells; and a page buffer configured to output a first bit line voltage to the first bit line during a programming operation on at least one of the plurality of first storage cells, and to output a second bit line voltage different from the first bit line voltage to the second bit line during a programming operation on at least one of the plurality of second storage cells. The thickness of a first gate insulating layer of the first storage cell string is less than the thickness of a second gate insulating layer of the second storage cell string, and the first bit line voltage is higher than the second bit line voltage.

[0008] According to one example embodiment, a memory device includes: a substrate; a plurality of word lines stacked on a top surface of the substrate; a plurality of word line cutting regions dividing the plurality of word lines into multiple regions and extending in a direction perpendicular to the top surface of the substrate; a first channel disposed in a first direction parallel to the top surface of the substrate at a first distance from the first word line cutting region among the plurality of word line cutting regions; a second channel disposed in the first direction at a second distance from the first word line cutting region less than the first distance; and a controller configured to supply a first bit line voltage to a bit line connected to the first channel in a programming operation of a first memory cell corresponding to the first channel, and to supply a second bit line voltage higher than the first bit line voltage to a bit line connected to the second channel in a programming operation of a second memory cell corresponding to the second channel.

[0009] According to one example embodiment, a memory device includes: a stacked structure disposed on a substrate, wherein the stacked structure includes a plurality of gate electrode layers alternating with a plurality of insulating layers; one or more channel structures penetrating the stacked structure, wherein the channel structures are disposed on an epitaxial layer connected to the substrate; and a word line dicing region dividing the stacked structure into a plurality of regions. The plurality of gate electrode layers include a ground select line, a serial select line, and a plurality of word lines disposed between the ground select line and the serial select line. The word lines and the channel structures adjacent to the word lines provide memory cells. As the distance from the word line dicing region increases, the thickness of each word line decreases, and the bit line voltage input to the bit line connected to the memory cell decreases.

[0010] According to another example embodiment, a method for programming a storage device includes: identifying location information of a selected storage cell; determining a voltage based on the location information, wherein the voltage is higher than ground and lower than a power supply voltage; and supplying the voltage to the selected storage cell. The method may further include: selecting a first mode of the storage device, wherein the voltage is determined based on the first mode; selecting a second mode of the storage device; and supplying ground voltage to the selected storage cell based on the second mode. The method may further include: determining that the selected storage cell does not exist among a plurality of storage cells; and supplying power supply voltage to a bit line based on the determination. Attached Figure Description

[0011] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a schematic block diagram of a storage device according to an example embodiment;

[0013] Figure 2 This is a schematic diagram of a storage cell array included in a storage device according to an example embodiment;

[0014] Figure 3 This is a schematic diagram illustrating the structure of a storage device according to an example embodiment;

[0015] Figures 4 to 15 A method for manufacturing a storage device according to an example embodiment is shown;

[0016] Figures 16 to 18 The programming speed of a storage device according to an example embodiment is shown;

[0017] Figures 19A to 19C A comparative example is shown to describe the operational results of the storage device. Figures 20A to 20C An example of the invention is shown for describing the operational results of a storage device according to an exemplary embodiment;

[0018] Figure 21 This is a circuit diagram of a page buffer according to an example implementation;

[0019] Figures 22A to 22C This illustrates a method of operating a page buffer according to an example embodiment;

[0020] Figure 23A and 23B This is a voltage timing diagram based on an example implementation;

[0021] Figure 24A and 24B The forced operation is shown according to an example implementation; and

[0022] Figure 25 This is a schematic block diagram of an electronic device including a storage device according to an example embodiment. Detailed Implementation

[0023] During the removal of the gate sacrificial layer, the gate insulation layer of the channel adjacent to the word line cleaving region has a small thickness, while the gate insulation layer of the channel farther from the word line cleaving region has a large thickness. Therefore, the programming speed of the channel adjacent to the word line cleaving region is relatively high, while the programming speed of the channel farther from the word line cleaving region is relatively low. During the programming operation of the memory cell, the page buffer provides different bit line voltages to the bit lines based on the distance between the channel and the word line cleaving region for each bit line. Therefore, the difference in programming speed can be compensated based on the distance between the word line cleaving region and the channel.

[0024] In the following description, exemplary embodiments will be described with reference to the accompanying drawings.

[0025] Figure 1 This is a schematic block diagram of a storage device according to an example embodiment.

[0026] Reference Figure 1 According to one example embodiment, the storage device 10 may include a storage cell array 20 and a storage controller 30. The storage cell array 20 may include a plurality of storage cells, at least some of which may be interconnected to provide a storage cell string. The storage cell array 20 may include a plurality of storage cell strings. The plurality of storage cell strings may be divided into a plurality of blocks. The storage controller 30 may include control logic 31, address decoder circuitry 32, page buffer circuitry 33, and input / output (I / O) circuitry 34.

[0027] In one example implementation, the address decoder circuit 32 can be connected to the memory cell MC (e.g., via word line WL, serial select line SSL, ground select line GSL, etc.) Figure 2 The storage cells MC1 to MCn are located in the memory. The page buffer circuit 33 can be connected to the storage cell MC via the bit line BL. In one example embodiment, the address decoder circuit 32 can select the storage cell MC when writing or reading data, and can receive address information for selecting the storage cell MC from the control logic 31.

[0028] Page buffer circuit 33 can write data to or read data from memory cell MC. Page buffer circuit 33 can write or read data on a page-by-page basis. Page buffer circuit 33 may include multiple page buffers, and each of the multiple page buffers may be connected to at least one bit line BL. Data to be written to or read from memory cell array 20 by page buffer circuit 33 can be input / output via I / O circuit 34. The operation of address decoder circuit 32, page buffer circuit 33, and I / O circuit 34 can be controlled by control logic 31.

[0029] According to one example implementation, the page buffer circuit 33 can supply a bit line voltage to the bit line corresponding to the memory cell to be programmed during a programming operation. In this case, the page buffer circuit 33 can determine the bit line voltage supplied to the bit line based on information about the channel connected to the bit line.

[0030] Figure 2 This is a schematic diagram of a storage cell array included in a storage device according to an example embodiment. (Refer to...) Figure 2 A memory cell array according to an example implementation may include multiple memory cells (MCs). The multiple memory cells (MCs) may be connected to multiple word lines (WLs) and multiple bit lines (BLs) for operation. As an example, each memory cell (MC) may be connected to a single word line (WL) and a single bit line (BL).

[0031] Some of the plurality of memory cells MC can be connected in series with each other to provide a single memory cell string MCS. In addition to the memory cells MC, the memory cell string MCS may also include a string select transistor SST and a ground select transistor GST. The string select transistor SST may be connected to one of the bit lines BL above the memory cells MC in the memory cell string MCS. The ground select transistor GST may be connected to the common source line CSL below the memory cells MC.

[0032] exist Figure 2 In the diagram, a single memory cell string (MCS) is shown as comprising a single ground select transistor (GST) and a single string select transistor (SST). However, the number of ground select transistors (GST) and the number of string select transistors (SST) can be varied. Additionally, dummy word lines (not shown) may be provided between the ground select transistor (GST) and the word line (WL) and between the string select transistor (SST) and the word line (WL).

[0033] According to one example implementation, the bit line BL can be connected to the page buffer circuit (e.g., Figure 1The page buffer circuit (33) can input voltage to bit line BL. The input voltage is used to perform programming, reading, erasing, and other operations on the memory cells MC. In one example embodiment, during a programming operation, the page buffer circuit can determine the magnitude of the voltage input to bit line BL. Bit line BL is connected to the memory cell string MCS. The memory cell string MCS includes the memory cells MC to be programmed. The magnitude of the voltage is determined based on the position of the memory cell string MCS.

[0034] Figure 3 This is a schematic diagram illustrating the structure of a storage device according to an example embodiment. Figure 3 It can be a perspective view showing a portion of the array of storage cells included in the storage device 10.

[0035] Reference Figure 3 According to one example embodiment, the storage device 100 may include a substrate 101, a plurality of channel structures CH perpendicular to the top surface of the substrate 101, and a plurality of dummy channel structures DCH. Figure 3 In the illustrated embodiment, the XY plane can be used to assume the vertical direction. Additionally, the storage device 100 may also include a plurality of gate electrode layers 130 (131 to 138) stacked on the substrate 101 adjacent to the channel structure CH. The plurality of gate electrode layers 130 may be stacked alternately with a plurality of insulating layers 140 (141 to 149). At least some of the plurality of gate electrode layers 130 may be divided into a plurality of gate insulating layers by an insulating layer 155.

[0036] Multiple gate electrode layers 130 can provide a ground select line 131, a serial select line 138, and multiple word lines 132 to 137. The ground select line 131 and the serial select line 138 can provide a ground select transistor (GST) and a serial select transistor (SST) together with the channel structure CH, respectively. The multiple word lines 132 to 137 can be disposed between the ground select line 131 and the serial select line 138, and can provide multiple memory cells MC1 to MCn together with the channel structure CH.

[0037] The plurality of gate electrode layers 130 can be divided into multiple gate electrode layers by a common source line 151 and spacers 109 on the side surface of the common source line 151. The common source line 151 can be formed of a conductive material such as metal, metal compound, polysilicon, etc. In addition, the common source line 151 can be electrically connected to a source region 103 formed in the substrate 101. The source region 103 can be provided as the source region of a ground selection transistor GST. The common source line 151 can be electrically insulated from the plurality of gate electrode layers 130 by the spacers 109.

[0038] Common source line 151 and spacer 109 can be provided in the word line cutting area.

[0039] Multiple channel structures CH and multiple dummy channel structures DCH can be arranged in a direction perpendicular to the top surface of the substrate 101 (in... Figure 3 In the illustrated example embodiment, the channel extends in the Z direction. Each channel structure CH may include a channel layer 110, a buried insulating layer 115, a drain region 113, and a gate insulating layer 160. The buried insulating layer 115 fills the interior space of the channel layer 110. The drain region 113 is provided above the channel layer 110, and the gate insulating layer 160 is provided between the channel layer 110 and the gate electrode layer 130. The gate insulating layer 160 may include a tunnel layer, a charge storage layer, a barrier layer, etc. Additionally, at least a portion of the gate insulating layer 160 is formed to surround the gate electrode layer 130. According to an example embodiment, without the buried insulating layer 115, the channel layer 110 may have a columnar shape, such as a cylindrical or prismatic shape. Furthermore, each channel structure CH may have a sloping side surface that narrows in a direction perpendicular to the substrate 101 based on the aspect ratio of the channel structure CH.

[0040] Multiple channel structures (CH) and multiple dummy channel structures (DCH) can be configured to be isolated from each other in the XY plane. The number and arrangement of the multiple channel structures (CH) and multiple dummy channel structures (DCH) can vary based on the example implementation. For example, the multiple channel structures (CH) and multiple dummy channel structures (DCH) can be arranged in a zigzag pattern in at least one direction.

[0041] exist Figure 3 In the diagram, multiple channel structures (CH) are shown symmetrically arranged. An insulating layer 155 is inserted between the symmetrically arranged channel structures (CH). Multiple dummy channel structures (DCH) are shown penetrating the insulating layer 155. However, the arrangement of the multiple channel structures (CH) and multiple dummy channel structures (DCH) is not limited to this. Each channel structure (CH) can be connected to a bit line, and two or more channel structures (CH) can be connected to a single bit line. As an example, in... Figure 3 In the embodiment shown, at least some of the multiple channel structures CH located at the same position in the X-axis direction can be connected to a single bit line.

[0042] The channel layer 110 can be electrically connected to the substrate 101 via the epitaxial layer 105 beneath it. The channel layer 110 may include a semiconductor material such as polycrystalline silicon or monocrystalline silicon. The semiconductor material may be undoped or may include P-type or N-type impurities. The epitaxial layer 105 may be a layer grown using a selective epitaxial growth (SEG) process. Figure 3 As shown, the epitaxial layer 105 can be formed at a predetermined depth into the substrate 101.

[0043] Multiple dummy channel structures (DCHs) can have a structure similar to a channel structure (CH). For example, multiple dummy channel structures (DCHs) may include a drain region 113, a channel layer 110, and a buried insulating layer 115, and may optionally include an epitaxial layer 111. Unlike a channel structure (CH), multiple dummy channel structures (DCHs) may not be connected to the bit lines above the gate structure. Therefore, control operations, such as programming operations, may not be performed in the memory cells MC1 to MCn provided by the dummy channel structures (DCHs).

[0044] According to one example implementation, during a programming operation performed on at least one memory cell MC, the page buffer can supply different bit line voltages to each channel. For example, different bit line voltages can be supplied to each channel based on the distance between the channel and a word line slicing region, which may include a common source line 151 and spacers 109.

[0045] Figures 4 to 15 A method for manufacturing a storage device according to an example embodiment is shown. Figure 5 It is along Figure 4 The cross-sectional view taken from line I-I'.

[0046] Reference Figure 4 and Figure 5 In the cell array group region C, a plurality of sacrificial layers 121 to 128 (120), a plurality of insulating layers 141 to 149 (140), and an interlayer insulating layer 170 may be formed on the substrate 101. The plurality of sacrificial layers 120 may comprise a material having a predetermined etch selectivity relative to the plurality of insulating layers 140. In one example embodiment, when the plurality of insulating layers 140 are formed of silicon oxide, the plurality of sacrificial layers 120 may be formed of silicon nitride. Therefore, in a subsequent process, the plurality of sacrificial layers 120 may be removed, while the plurality of insulating layers 140 may be retained. In different embodiments, the number and thickness of the plurality of sacrificial layers 120 and the plurality of insulating layers 140 may vary. Figure 5 In this design, multiple sacrificial layers 120 and multiple insulating layers 140 are shown to have substantially the same thickness. However, some sacrificial layers 120 or some insulating layers 140 may have different thicknesses from each other.

[0047] The interlayer insulation layer 170 may include insulating materials such as silicon oxide, and may include high-density plasma (HDP) oxide, tetraethyl orthosilicate (TEOS) oxide, etc.

[0048] Figure 7 It is along Figure 6 The cross-sectional view taken from line I-I'. (Refer to...) Figure 6 and Figure 7An insulating layer 155 can be formed from the top surface of the interlayer insulating layer 170. Multiple channel structures CH and multiple dummy channel structures DCH can also be formed.

[0049] Similar to interlayer insulating layer 170 and multiple insulating layers 140, isolation insulating layer 155 may include an insulating material such as silicon oxide. In one example embodiment, isolation insulating layer 155 may include a material that has etch selectivity relative to the multiple sacrificial layers 120.

[0050] The isolation insulating layer 155 can divide at least one sacrificial layer 128 into multiple regions. The sacrificial layer 128 divided by the isolation insulating layer 155 can be a layer that is replaced by the gate electrode layer of the string select transistor (SST) in a subsequent process.

[0051] The channel structure CH and the dummy channel structure DCH can penetrate multiple sacrificial layers 120, multiple insulating layers 140, and interlayer insulating layers 170. (Refer to...) Figure 6 The dummy channel structure DCH can be formed to penetrate the insulating layer 155. Alternatively, the dummy channel structure DCH can be located at another position where the insulating layer 155 is not formed. The number and location of the dummy channel structures DCH and the channel structures CH are not limited to... Figure 6 and Figure 7 Those shown in the image are not the only ones that can be changed in various ways.

[0052] Reference Figure 7 The channel structure CH may include a channel layer 110, a buried insulating layer 115, a drain region 113, an epitaxial layer 105, etc. The dummy channel structure DCH may have a structure similar to that of the channel structure CH. The gate insulating layer 160 may be disposed between multiple sacrificial layers 120 and the channel layer 110, and may extend between the channel layer 110 and the substrate 101.

[0053] The gate insulating layer 160 may include a tunneling layer, a charge storage layer, and a barrier layer sequentially stacked from the channel layer 110. The relative thicknesses of the aforementioned layers constituting the gate insulating layer 160 are not limited to those shown in the figure, but can be varied in various ways.

[0054] To form the dummy channel structure DCH and the channel structure CH, a via can be formed first. The via is formed to penetrate the interlayer insulating layer 170, multiple sacrificial layers 120, and multiple insulating layers 140. The via can be formed to penetrate the substrate 101 to a predetermined depth. Therefore, a portion of the substrate 101 can be exposed below the via through the via. Epitaxial layers 105 and 111 can be formed using a selective epitaxial growth process that uses the exposed portion of the substrate 101 as a seed.

[0055] After forming epitaxial layers 105 and 111, a barrier layer 166, a charge storage layer 164, and a tunneling layer 162 can be formed in the channel via using atomic layer deposition (ALD) or chemical vapor deposition (CVD). A channel layer 110 can then be formed on the inner side of the tunneling layer 162. The channel layer 110 can have a thickness of approximately 1 / 50 to 1 / 5 of the diameter of the channel via and can be formed from polycrystalline silicon with predetermined impurities, undoped polycrystalline silicon, etc. The channel layer 110 can have a hollow annular shape, and a buried insulating layer 115 can be formed within the channel layer 110. Optionally, before forming the buried insulating layer 115, hydrogen annealing can be further performed to anneal the structure in a gaseous atmosphere including hydrogen or deuterium. The channel layer 110 is a structure formed in a gaseous atmosphere using a hydrogen annealing process. Many crystal defects present in the channel layer 110 can be eliminated by hydrogen annealing. Next, a drain region 113 can be formed on the channel layer 110, and the drain region 113 is formed of a conductive material such as polysilicon.

[0056] Figure 9 It is along Figure 8 A sectional view taken along line I-I'. (Refer to...) Figure 8 and Figure 9 A vertical opening WC can be formed to divide the plurality of sacrificial layers 120 and the plurality of insulating layers 140 into a plurality of regions. The vertical opening WC can be formed in the shape of a trench extending in a first direction (X-axis direction). A portion of the substrate 101 can be exposed below the vertical opening WC. The vertical opening WC can be provided as a word line cut region WC.

[0057] refer to Figure 10 and Figure 11 Multiple sacrificial layers 120 exposed through the vertical opening WC can be removed by an etching process. For example, the multiple sacrificial layers 120 can be removed by an etchant such as phosphoric acid introduced through the vertical opening WC. During the removal of the multiple sacrificial layers 120, multiple insulating layers 140 can be retained. Horizontal openings 180 are formed in the regions where the multiple sacrificial layers 120 are removed. The multiple insulating layers 140 can be left undamaged by the multiple channel structures CH and the multiple dummy channel structures DCH.

[0058] To increase the capacity of the storage device 100, it is desirable to increase the number of gate electrode layers 130 stacked on the substrate 101. As the number of gate electrode layers 130 increases, it may become difficult to remove multiple sacrificial layers 120 in a single etching operation. Therefore, the number of etching processes used for multiple sacrificial layers 120 may be increased.

[0059] refer to Figure 10The enlarged view shows that the gate insulating layer 160 may include a tunneling layer 162, a charge storage layer 164, and a barrier layer 166. As the distance from the word line dicing region WC increases, some of the gate insulating layer 160 may be etched together with the sacrificial layer 120. When removing multiple sacrificial layers 120, a process of etching the gate insulating layer 160 and the sacrificial layer 120 together occurs.

[0060] Therefore, the thickness of the gate insulating layer 160 can vary from one another based on its distance from the word line cutting region WC. As an example, the thickness T1 of the gate insulating layer 160 closer to the word line cutting region WC can be less than the thickness T2 of the gate insulating layer 160 farther from the word line cutting region WC.

[0061] Reference Figure 11 The enlarged view shows that the thickness of the horizontal openings 180 in the areas where multiple sacrificial layers 120 are removed varies from one another based on the distance from the word line dicing region WC. As an example, as the distance from the word line dicing region WC decreases, the multiple sacrificial layers 120 can be over-etched. The thickness D1 of the horizontal openings 180 closer to the word line dicing region WC can be greater than the thickness D2 of the horizontal openings 180 farther from the word line dicing region WC.

[0062] Reference Figure 10 and Figure 11 An example embodiment in which the thicknesses of the gate insulating layers 160 differ from each other is described. Additionally, the thicknesses of the horizontal openings 180, which differ from each other based on their distance from the word line cutting region WC, are also described. However, the thicknesses of the gate insulating layers 160 and the horizontal openings 180 can vary simultaneously based on their distance from the word line cutting region WC.

[0063] Figures 13 to 15 It is along Figure 12 The cross-sectional view taken from line I-I'. (Refer to...) Figures 12 to 15 Multiple horizontal openings 180 can be filled with a conductive material to form multiple gate electrode layers 130. The multiple gate electrode layers 130 can provide a gate structure together with multiple insulating layers 140. A barrier layer 166b and gate electrode layers 130 can be sequentially formed in a region in which multiple sacrificial layers 120 have been removed. The barrier layer 166b can include a high-k dielectric and can include two or more layers. The term "high-k dielectric" can be understood as a dielectric material having a dielectric constant higher than that of silicon oxide.

[0064] The gate electrode layer 130 may comprise a metal, polysilicon, or a metal silicide material. The metal silicide material may be a silicide material of a metal selected from, for example, cobalt (Co), nickel (Ni), hafnium (Hf), platinum (Pt), tungsten (W), and titanium (Ti), or a combination thereof. When the gate electrode layer 130 is formed of a metal silicide material, the gate electrode layer 130 can be formed by performing a silicide process by filling the horizontal opening with silicon (Si) and forming an additional metal layer. In one example embodiment, the gate electrode layer 130 may comprise multiple metal layers, such as titanium (Ti), titanium nitride (TiN), tungsten (W), etc.

[0065] refer to Figure 13 The enlarged view shows the gate electrode layer 133, insulating layers 143 and 144, gate insulating layer 160, and channel structure CH included in region A1. The channel structure CH may include a buried insulating layer 115 and a channel layer 110. The channel layer 110 may have an annular shape, and the buried insulating layer 115 may be disposed within the channel layer 110. The gate insulating layer 160 has a structure including barrier layers 166a and 166b, a charge storage layer 164, and a tunneling layer 162, sequentially stacked from the gate electrode layer 133 to the channel layer 110.

[0066] The gate insulating layer 160 can be configured such that the barrier layer comprises two layers, namely 166a and 166b. These two layers are a first barrier layer 166a and a second barrier layer 166b surrounding the gate electrode layer 133. The first barrier layer 166a is similar to the channel layer 110 and extends in the vertical direction. However, the configuration of the gate insulating layer 160 is not limited to this.

[0067] The thickness T1 of the gate insulating layer 160 near the word line cutting region WC can be less than the thickness T2 of the gate insulating layer 160 away from the word line cutting region WC. The relative thicknesses of the aforementioned layers constituting the gate insulating layer 160 are not limited to the thicknesses shown in the figures, but can be varied in various ways.

[0068] The second barrier layer 166b may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), or a high-k dielectric. The high-k dielectric may be selected from aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), or zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), Hafnium silicon oxide (HfSi) x O y Lanthanum oxide (La₂O₃), lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x Oy ), Hafnium aluminum oxide (HfAl) x O y It is one of the groups consisting of praseodymium oxide (Pr2O3) and praseodymium oxide (Pr2O3).

[0069] The second barrier layer 166b may have a higher dielectric constant than the first barrier layer 166a. In this case, the first barrier layer 166a (also referred to as the low-k dielectric layer) may be positioned in contact with the charge storage layer 164. The second barrier layer 166b (also referred to as the high-k dielectric layer) may be formed of a material having a dielectric constant higher than that of the tunneling layer 162. Furthermore, the low-k dielectric layer may be formed of a material having a dielectric constant relatively lower than that of the high-k dielectric layer. The low-k dielectric layer is disposed on the side surface of the high-k dielectric layer, thereby allowing adjustment of the energy band (such as the barrier height) to improve the characteristics of the non-volatile memory device. For example, improving the erase characteristics of the non-volatile memory device.

[0070] The charge storage layer 164 can be a charge trapping layer or a floating gate conductive layer. When the charge storage layer 164 is a floating gate conductive layer, it can be formed by depositing polysilicon. For example, a low-pressure chemical vapor deposition (LPCVD) process can be used. When the charge storage layer 164 is a charge trapping layer, it can include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), hafnium oxide (HfO2), zirconium oxide (ZrO2), tantalum oxide (Ta2O3), titanium oxide (TiO2), or hafnium aluminum oxide (HfAl). x O y ), Hafnium tantalum oxide (HfTa) x O y ), Hafnium silicon oxide (HfSi) x O y ), aluminum nitride (Al) x N y ) and aluminum gallium nitride (AlGa x N y At least one of the following.

[0071] The tunneling layer 162 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon nitride oxide (SiON), hafnium oxide (HfO2), and hafnium silicon oxide (HfSi). x O y At least one of aluminum oxide (Al2O3) and zirconium oxide (ZrO2).

[0072] refer to Figure 14In the enlarged view, the thickness D1 of the gate electrode layer (also called the word line) 133 near the word line dicing region WC is greater than the thickness D2 of the word line 133 away from the word line dicing region WC. Alternatively, the gate length D1 near the word line dicing region WC can be greater than the gate length D2 away from the word line dicing region WC.

[0073] exist Figure 13 and Figure 14 In this context, the thickness of the gate insulating layer 160 or the thickness of the word line 133 is shown to vary based on the distance from the word line cutting region WC. Figure 15 The thickness of the gate insulating layer 160 and the thickness of the word line 133 are shown to vary simultaneously based on the distance from the word line cutting region WC.

[0074] In the storage device 100, the thickness of the gate insulating layer 160 and the thickness of the word line 133 vary based on the distance from the word line cutting region WC. Therefore, the plurality of storage cells MC1 to MCn can have characteristic differences based on their distance from the word line cutting region WC.

[0075] According to one example implementation, in the storage device 100, channels closer to the word line slicing region WC can have relatively higher programming speeds, while channels farther from the word line slicing region WC can have relatively lower programming speeds. Therefore, according to one example implementation, the page buffer can supply different bit line voltages to the bit lines based on information about the channels connected to each bit line to compensate for the characteristic differences among the multiple memory cells MC.

[0076] Figures 16 to 18 The programming speed of a storage device according to an example embodiment is shown.

[0077] First refer to Figure 16 The storage device includes multiple channels CH1 to CH4, and each of the multiple channels CH1 to CH4 can correspond to a string of memory cells. Each of the multiple channels CH1 to CH4 can be connected to a bit line. As an example, the first channel CH1 can be connected to the first bit line BL1, the second channel CH2 can be connected to the second bit line BL2, the third channel CH3 can be connected to the third bit line BL3, and the fourth channel CH4 can be connected to the fourth bit line BL4.

[0078] The SSL Cut region separates the string select lines from each other, and multiple channels CH1 to CH4 are located between the WL Cut region and the SSL Cut region. The distances between the multiple channels CH1 to CH4 and the WL Cut region can be different. For example, the first distance L1 between the WL Cut region and the first channel CH1 can be less than the second distance L2 between the WL Cut region and the second channel CH2. The third distance L3 between the WL Cut region and the third channel CH3 is less than the fourth distance L4 between the WL Cut region and the fourth channel CH4. The first difference between the thicknesses of the gate insulating layers included in a memory cell string commonly connected to one of the multiple bit lines BL1, BL2 is less than the second difference between the thicknesses of the gate insulating layers included in memory cell strings connected to different bit lines BL3, BL4.

[0079] In one example implementation, during programming operations on memory cells provided by multiple channels CH1 to CH4, voltages of different magnitudes can be input to bit lines respectively connected to the multiple channels CH1 to CH4, based on the distance from the word line cut region WL Cut. For example, in Figure 17 As described, by inputting voltages of different magnitudes to the bit lines, programming speed differences based on the distance from the word line cutting region WL Cut can be compensated. Different input voltages are provided to multiple channels CH1 to CH4 respectively.

[0080] Figure 17 It is shown Figure 16 A simplified diagram of a portion of the string of storage cells included in the storage device shown.

[0081] The first memory cell string MCS1 may include multiple memory cells MC11 to MC18 connected between the ground select transistor GST and the string select transistor SST. The second memory cell string MCS2 may include multiple memory cells MC21 to MC28 connected between the ground select transistor GST and the string select transistor SST. The third memory cell string MCS3 may include multiple memory cells MC31 to MC38 connected between the ground select transistor GST and the string select transistor SST. The fourth memory cell string MCS4 may include multiple memory cells MC41 to MC48 connected between the ground select transistor GST and the string select transistor SST. The first to fourth memory cell strings MCS1 to MCS4 may share the ground select transistor GST and the string select transistor SST.

[0082] Reference Figure 16 and Figure 17The first memory cell string MCS1 may include a first channel CH1 and may be connected to the first bit line BL1. The second memory cell string MCS2 may include a second channel CH2 and may be connected to the second bit line BL2. The third memory cell string MCS3 may include a third channel CH3 and may be connected to the third bit line BL3. The fourth memory cell string MCS4 may include a fourth channel CH4 and may be connected to the fourth bit line BL4.

[0083] Since the first to fourth memory cell strings MCS1 to MCS4 share a word line and are respectively connected to the first to fourth bit lines BL1 to BL4, the first to fourth memory cell strings MCS1 to MCS4 can be programmed independently.

[0084] In one example implementation, when the seventh memory cell MC37 of the third memory cell string MCS3 is selected as the memory cell to be programmed, a programming voltage is input to the word line connected to the seventh memory cell MC37. Alternatively, a first voltage may be input to the third bit line BL3.

[0085] In the operation of programming the seventh memory cell MC37 of the third memory cell string MCS3, a second voltage different from the first voltage can be input to the first bit line BL1. For example, the second voltage can be the power supply voltage VDD. The second voltage can be input to the first bit line BL1 to prevent the seventh memory cell MC17 of the first memory cell string MCS1, which shares a word line with the seventh memory cell MC37 of the third memory cell string MCS3, from being programmed. Similarly, the second voltage can be input to the second bit line BL2 and the fourth bit line BL4 to prevent the seventh memory cell MC27 of the second memory cell string MCS2 and the seventh memory cell MC47 of the fourth memory cell string MCS4 from being programmed.

[0086] As an example, the distances between the first to fourth memory cell strings MCS1 to MCS4 and the word line cut region WL Cut can be different from each other. In one example implementation, during programming operations, the magnitude of the first voltage input to each bit line BL1-BL4 can vary based on the distance from the word line cut region WL Cut.

[0087] As an example, the first voltage input to the third bit line BL3 during a programming operation of the third memory cell string MCS3, which is relatively close to the word line cut region WL Cut, can have a first magnitude. The first voltage input to the first bit line BL1 during a programming operation of the first memory cell string MCS1, which is relatively far from the word line cut region WLCut, can have a second magnitude. For example, the first magnitude can be greater than the second magnitude. In one example embodiment, the first magnitude can be greater than the ground voltage and less than the power supply voltage VDD. Additionally or alternatively, the second magnitude can be equal to the ground voltage. Similarly, the magnitude of the first voltage input to the fourth bit line BL4 can be greater than the magnitude of the first voltage input to the second bit line BL2.

[0088] Figure 18 This is a graph illustrating programming speed based on the distance between the memory cell string and the word line segmentation region. Figure 18 In the graph, the horizontal axis represents the distance between the storage cell string and the word line cutting area, and the vertical axis represents the programming speed.

[0089] refer to Figures 16 to 18 The programming speed of the third memory cell string (MCS3), which is closest to the word line slicing region, is the highest, while the programming speed of the second memory cell string (MCS2), which is furthest from the word line slicing region, is the lowest. This is due to the semiconductor process; the gate insulating layer surrounding the third memory cell string (MCS3) has the smallest thickness, while the word lines connecting to the second memory cell string (MCS2) have the largest thickness.

[0090] As a result, in order to compensate for differences in programming speed (based on the distance between the memory cell string and the word line cutting region), the page buffer can adjust the bit line voltage supplied to the bit lines to which each memory cell string is connected.

[0091] Figures 19A to 19C A comparative example is shown to describe the operational results of the storage device. Figures 20A to 20C An example of the invention is shown for describing the operational results of a storage device according to an exemplary embodiment. Reference will be made below. Figures 16 to 20C Describe it.

[0092] When Figure 19A When the power supply voltage VDD is supplied to the unselected bit line BL and the ground voltage 0V is supplied to the selected bit line BL, a skew may occur in the threshold voltage distribution between channels CH1 and CH4 based on the distance between the word line cut-off region and channels CH1 to CH4, such as... Figure 19B As shown. This is because a 0-volt ground voltage is applied equally to the selected bit lines, regardless of the programming speed of each channel, which varies based on the word line cut region and the distance between channels CH1 to CH4.

[0093] Therefore, asFigure 19C As shown, even when the programming voltage V PGM When applied equally to the selected word line WL, the threshold voltage V of the first and third channels CH1 and CH3 th There is also a voltage difference ΔV between them.

[0094] Return to Figure 19B The third channel CH3, closest to the word line cut-off area, has a relatively high programming speed, while the second channel CH2, furthest from the word line cut-off area, has a relatively low programming speed. Since the programming performance of the second channel CH2, furthest from the word line cut-off area, is determined, the programming speed of the channel with the low programming speed can be improved.

[0095] Therefore, such as Figure 20A As shown, the power supply voltage VDD can be supplied to the unselected bit line BL, and a voltage equal to or higher than the ground voltage of 0 volts and lower than the power supply voltage VDD can be supplied to the selected bit line BL.

[0096] Based on the distance between the channel connected to bit line BL and the word line cut-off region, the voltage supplied to the selected bit line BL can be determined to have any value greater than or equal to ground voltage (0 volts) and less than the supply voltage VDD. For example, a voltage with a first level LV1 can be supplied to bit line BL3 connected to a third channel CH3 relatively close to the word line cut-off region. A voltage with a second level LV2 can be supplied to bit line BL1 connected to a first channel CH1 relatively far from the word line cut-off region. The first level LV1 can be higher than the ground voltage level and lower than the supply voltage VDD level. The second level LV2 can be the ground voltage level.

[0097] Because different bit line voltages can be supplied to each channel CH1 to CH4 to compensate for the differences in programming speed among channels CH1 to CH4, such as Figure 20B As shown, the skewness in the threshold voltage distribution between CH1 and CH4 can be reduced.

[0098] Reference Figure 20C ,exist Figure 19C The threshold voltage V of the first channel CH1 and the third channel CH3 described in the figure th The voltage difference ΔV can correspond to the difference between the voltage supplied to bit line BL3 connected to the third channel CH3 and the voltage supplied to bit line BL1 connected to the first channel CH1.

[0099] According to one example implementation, the programming voltage V applied to the selected word line WL can be increased. PGMThe programming speed can be increased by adjusting the voltage level. As a result, the programming performance of the memory device can be improved. Furthermore, if the differences in programming speed between different memory cells are balanced (i.e., compensated) by providing different voltages to the bit lines of different memory cells, the programming performance can be improved.

[0100] Figure 21 This is a circuit diagram of a page buffer according to an example implementation. (Refer to...) Figure 21 The page buffer may include a first terminal TD1, a second terminal TD2, a latch LATCH, a PMOS transistor PM, an NMOS transistor NM, a switch SW, and an output terminal TD0.

[0101] PMOS transistor PM and NMOS transistor NM are connected in series between the first terminal TD1 and the second terminal TD2. Additionally, a latch is connected between the gates of PMOS transistor PM and NMOS transistor NM. Switch SW may have a first terminal commonly connected to the drain terminals of both PMOS transistor PM and NMOS transistor NM, a second terminal connected to the output terminal TD0, and a third terminal connected to BL_Control. Output terminal TD0 may be connected to the bit line BL. Switch SW can be turned on during programming.

[0102] The PMOS transistor PM has a source terminal connected to the second terminal TD2, and can receive a second bit line voltage V2 from the second terminal TD2, and can output the received second bit line voltage V2 to the bit line BL through the output terminal TD0.

[0103] The NMOS transistor NM has a source terminal connected to the first terminal TD1, and can receive the first line voltage V1 from the first terminal TD1, and can output the received first line voltage V1 to the bit line BL through the output terminal TD0.

[0104] The latch (LATCH) stores information about whether a selected memory cell exists among a plurality of memory cells. Based on the presence or absence of a selected memory cell, the latch (LATCH) controls the PMOS transistor (PM) and NMOS transistor (NM) to apply one of the first bit line voltage (V1) and the second bit line voltage (V2) to bit line BL.

[0105] For example, a first bit line voltage V1 can be supplied to the selected bit line BL, and a second bit line voltage V2 can be supplied to the unselected bit line BL. The first bit line voltage V1 can be equal to or higher than the ground voltage of 0 volts, and the second bit line voltage V2 can be the power supply voltage VDD. The first bit line voltage V1 can be determined based on the distance between the memory cell string connected to the bit line BL and the word line cut-off region.

[0106] The storage device can operate in either a first mode or a second mode. The first mode is in which the level of the first bit line voltage V1 can be determined based on information about the channels connected to the bit lines. The second mode is in which the level of the first bit line voltage V1 has a predetermined value when a selected memory cell exists among a plurality of memory cells connected to the bit lines. The channel information may include physical location information of the channel. The physical location information may include information about the distance between the word line cut-off region separating the multiple word lines and the channel.

[0107] For example, in the first mode, the level of the first line voltage V1 can be determined to be any value greater than 0 volts ground and less than the supply voltage VDD. This example depends on the distance between the channel connected to the bit line BL and the word line cut-off region. The first line voltage V1 can be determined based on the bit line address assigned to the bit line BL. In the second mode, the level of the first line voltage V1 can be determined to be the level of 0 volts ground.

[0108] Therefore, according to an example embodiment, a method for programming a storage device includes: identifying location information of a selected storage cell; determining a first line voltage V1 based on the location information, wherein the first line voltage V1 is higher than ground voltage and lower than power supply voltage VDD; and supplying the first line voltage V1 to the selected storage cell.

[0109] The method may further include: selecting a first mode of the storage device, wherein a first bit line voltage V1 is determined based on the first mode; selecting a second mode of the storage device; and supplying a second bit line voltage V2 (e.g., ground voltage) to the selected storage cell based on the second mode. The method may further include determining that the selected storage cell does not exist among a plurality of storage cells; and based on this determination, supplying a power supply voltage VDD to bit line BL.

[0110] In some cases, the first line voltage V1 is based on the distance between the memory cell string including the selected memory cell and the word line cut-off region. In some cases, the first line voltage V1 is configured to compensate for the gate insulation layer thickness of the channel of the selected memory cell, and the gate insulation layer thickness varies based on the distance between the channel and the word line cut-off region.

[0111] Figures 22A to 22C This illustrates a method of operating a page buffer according to an example implementation. In detail, Figures 22A to 22C The operation of a page buffer is illustrated, which can determine the bit line voltage of each channel differently during programming operations, taking into account the differences in the characteristics of memory cells.

[0112] Reference Figure 22AIn the first mode, when the latch LATCH contains information about the selected memory cell among multiple memory cells, the PMOS transistor PM can be turned off and the NMOS transistor NM can be turned on. Therefore, the page buffer can supply the first line voltage V1 to the bit line BL via the output terminal TD0. For example, the first line voltage V1 can be equal to or higher than the ground voltage of 0 volts.

[0113] The level of the first line voltage V1 can be determined based on the distance between the channel connected to the bit line BL and the word line cut-off region, and can be any value equal to or greater than the ground voltage of 0 volts and less than the supply voltage VDD. For example, the shorter the distance between the channel connected to the bit line BL and the word line cut-off region, the higher the level of the first line voltage V1.

[0114] Because the page buffer determines the bit line voltage supplied to the bit line connected to the channel based on the channel information, the page buffer can compensate for the characteristic differences of multiple memory cells.

[0115] Reference Figure 22B In the second mode, when the latch LATCH contains information about the selected memory cell among multiple memory cells, the PMOS transistor PM can be turned off, and the NMOS transistor NM can be turned on. Therefore, the page buffer can supply the first line voltage V1 to the bit line BL through the output terminal TD0. For example, the level of the first line voltage V1 can be determined to be the level of ground voltage 0 volts.

[0116] Reference Figure 22C In the first mode, when the latch LATCH includes information about the selected memory cell among multiple memory cells, the PMOS transistor PM can be turned on, and the NMOS transistor NM can be turned off. Therefore, the page buffer can supply the second bit line voltage V2 to the bit line BL through the output terminal TD0. For example, the second bit line voltage V2 can be the power supply voltage VDD.

[0117] Figure 23A and 23B This is a voltage timing diagram based on an example implementation. Figure 24A and 24B This illustrates a forced operation according to an example implementation. (Refer to...) Figure 23AWhen the memory device is in the second mode, during the bit line setup operation, the memory device controller can apply a ground voltage of 0 volts to the bit line (selected BL) connected to the memory cell to be programmed, and can apply the power supply voltage VDD to the bit line (unselected BL) connected to the memory cell to be disabled for programming. Typically, during the programming operation, the threshold voltage of the memory cell is controlled using Incremental Step Pulse Programming (ISPP). According to ISPP, voltages with regular intervals can be gradually increased and supplied to the word lines connected to the memory cells of the memory device to perform the programming operation of the memory cells.

[0118] Reference Figure 24A In the first verification operation for the first programming operation, when the threshold voltage of at least one memory cell is lower than the first verification voltage V r At this time, at least one memory cell may enter a fault state. Therefore, the memory cell in the fault state can be reprogrammed during the second programming operation.

[0119] Assuming that the voltage V is higher than the first verification voltage during the first programming operation. r The distribution of threshold voltages in the memory cells at the threshold voltage will be referred to as the target state, i.e., region C. Based on the second verification voltage V... f It has a voltage lower than the first verification voltage V r The memory cells with threshold voltage can be divided into memory cells in the region (region B) close to the target state (region C) and memory cells in the region (region A) far from the target state (region C).

[0120] Referring to 24B, when a memory cell in a faulty state is reprogrammed during a second programming operation, the bit line voltage supplied to the memory cell in the region (region B) closer to the target state (region C) may be higher than the bit line voltage supplied to the memory cell in the region (region A) farther from the target state (region C). Hereinafter, the memory cell in the region (region B) closer to the target state (region C) will be referred to as the forced cell.

[0121] Since the programming operations of memory cells in regions closer to the target state (region C) (region B) are performed more precisely than those in regions far from the target state (region C) (region A), the width of the threshold voltage distribution can be further reduced.

[0122] Return to Figure 23A After the information about the forced unit is transmitted to the latch, a forced voltage (e.g., 1 volt) that is higher than ground voltage (0 volts) and lower than power supply voltage VDD can be applied to the bit line corresponding to the forced unit during bit line forced operation.

[0123] When the memory device is in the first mode, a bit line voltage with any value greater than or equal to ground voltage 0 volts and less than the power supply voltage VDD can be applied to the bit line (selected BL) to which the memory cell to be programmed is connected. Additionally, as... Figure 23B As shown, during the bit line setting operation, the power supply voltage VDD can be applied to the bit line (unselected BL) to which the memory cell to be programmed is connected.

[0124] As described above, the bit line voltage to be supplied to the bit line to which the memory cell to be programmed is connected can be determined based on the distance between the channel connected to the bit line and the word line cleavage region. For example, a first bit line voltage (e.g., 0.5 volts) can be supplied to the bit line connected to the channel with the shortest distance from the word line cleavage region, and a second bit line voltage (e.g., 0 volts) can be supplied to the bit line connected to the channel with the longest distance from the word line cleavage region.

[0125] When a forced voltage is applied to the bit line corresponding to the forced cell during forced operation, the forced voltage can be determined to be a level that is higher than the first line voltage (e.g., 0.5 volts) supplied to the bit line connected to the channel with the shortest distance from the word line cut region and lower than the supply voltage level (e.g., 1 volt). However, the level of the forced voltage is not limited to this.

[0126] Figure 25 This is a schematic block diagram of an electronic device including a storage device according to an example embodiment.

[0127] according to Figure 25 An example embodiment of the electronic device shown (e.g., computer device 1000) may include a display 1010, a sensor unit 1020, a memory 1030, a processor 1040, a port 1050, etc. The computer device 1000 may also include wired / wireless communication devices, a power supply, etc. Figure 25 Among the components shown, port 1050 can be a device that allows computer device 1000 to communicate with video cards, sound cards, memory cards, USB devices, etc. Computer device 1000 can be broadly interpreted to include general-purpose desktop computers, laptop computers, smartphones, tablet PCs, smart wearable devices, etc.

[0128] The processor 1040 can execute operations, commands, tasks, etc. The processor 1040 can be a central processing unit (CPU), a microprocessor unit (MCU), a system-on-a-chip (SoC), etc., and can communicate with the display 1010, the sensor unit 1020, the memory 1030, and other devices connected to the port 1050 via the bus 1060.

[0129] The memory 1030 may be a storage medium configured to store data for the operation of the computer device 1000 or to store multimedia data. The memory 1030 may include volatile memory such as random access memory (RAM) or non-volatile memory such as flash memory. The memory 1030 may include at least one of a solid-state drive (SSD), a hard disk drive (HDD), and an optical disk drive (ODD) as a storage device.

[0130] The memory 1030 may include a phase-change memory device configured to use the resistance change of a phase-change material to read and / or erase data. Figure 25 In the example embodiment shown, the memory 1030 may include components according to the above references. Figures 1 to 24B Storage devices for various embodiments described.

[0131] As described above, according to the example implementation, a voltage determined differently based on the information of the channel connected to the bit line can be supplied from an existing terminal that is supplied with ground voltage. Therefore, the programming performance of the memory device can be improved without additional latches or additional data processing.

[0132] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

[0133] This application claims priority to Korean Patent Application No. 10-2019-0053189, filed with the Korean Intellectual Property Office on May 7, 2019, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A page buffer configured to supply bit line voltages to bit lines connected to a plurality of memory cells, the page buffer comprising: A first circuit element is connected to a first terminal for supplying the first line voltage; The second circuit element is connected to a second terminal for supplying a second bit line voltage that is lower than the first bit line voltage; and A latch is configured to control the first and second circuit elements based on whether a selected memory cell exists among the plurality of memory cells, and is configured to apply one of the first bit line voltage and the second bit line voltage to the bit line. When the selected memory cell exists among the plurality of memory cells, based on information about the channels connected to the bit lines, the level of the second bit line voltage is lower than the level of the first bit line voltage and higher than or equal to the level of the ground voltage. The second bit line voltage is determined based on the thickness of the gate insulating layer of the channel. The first bit voltage is supplied to the bit line connected to the channel relatively close to the word line cut-off region, and the second bit voltage is supplied to the bit line connected to the channel relatively far from the word line cut-off region.

2. The page buffer according to claim 1, wherein, The information about the trench includes the physical location information of the trench.

3. The page buffer according to claim 2, wherein, The physical location information is based on the distance between the word line cutting area, which divides multiple word lines into multiple regions, and the channel.

4. The page buffer according to claim 1, wherein, The second bit line voltage is determined based on the thickness of the word line connected to the selected memory cell.

5. The page buffer according to claim 1, wherein, The second bit line voltage is determined based on the bit line address assigned to the bit line.

6. The page buffer according to claim 1, wherein, The first circuit element includes a PMOS transistor, and the second circuit element includes an NMOS transistor. The first circuit element and the second circuit element are connected in series between the first terminal and the second terminal, and The latch is commonly connected between the gate of the PMOS transistor and the gate of the NMOS transistor.

7. A storage device, comprising: Multiple bit lines, including the first bit line and the second bit line; A storage cell array includes multiple storage cell strings connected to the multiple bit lines. The multiple storage cell strings include a first storage cell string and a second storage cell string. The first storage cell string is connected to the first bit line and includes multiple first storage cells. The second storage cell string is connected to the second bit line and includes multiple second storage cells. as well as A page buffer is configured to output a first bit line voltage to the first bit line during a first programming operation on at least one of the plurality of first memory cells, and to output a second bit line voltage different from the first bit line voltage to the second bit line during a second programming operation on at least one of the plurality of second memory cells. Wherein, the first gate insulating layer of the first memory cell string has a thickness smaller than that of the second gate insulating layer of the second memory cell string, and the first bit line voltage is higher than the second bit line voltage.

8. The storage device according to claim 7, wherein, The gate length of the first memory cell string is different from the gate length of the second memory cell string.

9. The storage device according to claim 8, wherein, The gate length of the first memory cell string is greater than the gate length of the second memory cell string.

10. The storage device according to claim 7, wherein, The first difference between the thicknesses of the gate insulating layers included in a memory cell string that is commonly connected to one of the multiple bit lines is less than the second difference between the thicknesses of the gate insulating layers included in memory cell strings that are connected to different bit lines.

11. The storage device according to claim 8, wherein, The first memory cell string includes at least one first string select transistor, and the second memory cell string includes at least one second string select transistor. The first string select transistor and the second string select transistor are connected to a single string select line.

12. The storage device according to claim 11, further comprising: Multiple word lines connected to the first memory cell and the second memory cell, The multiple character lines are divided into multiple regions by character line cutting areas, and The distance between the first storage cell string and the word line cutting region is less than the distance between the second storage cell string and the word line cutting region.

13. A storage device, comprising: substrate; Multiple word lines stacked on the top surface of the substrate; Multiple character line cutting areas divide the multiple character lines into multiple regions and extend in a direction perpendicular to the top surface of the substrate; The first channel is disposed in a first direction parallel to the top surface of the substrate at a first distance from the first character line cutting area among the plurality of character line cutting areas; The second channel is disposed in the first direction at a second distance from the first character line cutting area, which is less than the first distance; as well as The controller is configured to supply a first bit line voltage to a first bit line connected to the first channel during a programming operation of a first memory cell corresponding to the first channel, and to supply a second bit line voltage higher than the first bit line voltage to a second bit line connected to the second channel during a programming operation of a second memory cell corresponding to the second channel. The gate insulating layer disposed between the second channel and the plurality of word lines has a thickness smaller than that of the gate insulating layer disposed between the first channel and the plurality of word lines.

14. The storage device according to claim 13, wherein, The controller controls the first bit line voltage and the second bit line voltage by referring to the externally input bit line address.

15. The storage device according to claim 13, further comprising: A string selection line positioned above the multiple character lines; and The string selection line cutting area that separates the string selection lines from each other. The first channel and the second channel are disposed between the first character line cutting area and the string selection line cutting area.

16. The storage device according to claim 13, wherein, The word line connected to the second memory cell has a greater thickness than the word line connected to the first memory cell.

17. The storage device according to claim 13, wherein, As the distance from the word line cutting area increases, the thickness of each of the plurality of word lines decreases.

18. The storage device according to claim 13, wherein, The controller supplies the first bit line voltage based on the first bit line address assigned to the first bit line, and supplies the second bit line voltage based on the second bit line address assigned to the second bit line.

Images