Electronic devices and methods of manufacturing them

Abstract

An electronic device and a method of manufacturing the electronic device are provided. The electronic device includes a display unit and an input sensing unit. The display unit includes an insulating layer, signal lines, pads connected to the ends of the signal lines, and circuit elements. The insulating layer includes a first insulating layer that covers the circuit elements and exposes at least a portion of the circuit elements. The input sensing unit includes a first conductive layer, a second conductive layer, and a second insulating layer. The second conductive layer includes a sensing pattern, and the second insulating layer is located between the first conductive layer and the second conductive layer. The second insulating layer exposes at least a portion of the first conductive layer. An insulating layer between the ends of the signal lines and the pads is defined as a pad insulating layer. The maximum thickness of the pad insulating layer is greater than the sum of the thicknesses of the first insulating layer and the second insulating layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0055215, filed on May 10, 2019, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments generally relate to an electronic device and a method of manufacturing the same, and more specifically, to a display device including a pad (also called a solder pad) area and a method of manufacturing the same. Background Technology

[0004] Various display units have been developed for use in a wide range of multimedia electronic devices, such as televisions, mobile phones, tablets, navigation systems, and game consoles. Keyboards or mice are commonly used as input devices in electronic devices. Electronic devices may also include input sensing units (e.g., touch panels) as input devices. Furthermore, electronic devices may include a circuit substrate to control the operation of the display unit or input sensing unit. The display unit or input sensing unit can be connected to the motherboard via the circuit substrate.

[0005] The information disclosed in this section is only for understanding the background of the inventive concept and may therefore contain information that does not constitute prior art. Summary of the Invention

[0006] Some exemplary embodiments are capable of providing an electronic device configured to prevent or suppress failures in a pad connected to a circuit substrate.

[0007] Some exemplary embodiments can provide a method of manufacturing an electronic device configured to prevent or suppress failures in a pad connected to a circuit substrate.

[0008] Other aspects will be set forth in the detailed description below, and will be apparent in part from this disclosure, or may be learned by practice of the inventive concept.

[0009] According to an example embodiment, an electronic device includes a display unit and an input sensing unit. The display unit includes an insulating layer, a signal line, a pad connected to an end of the signal line, and a circuit element. The insulating layer includes a first insulating layer covering the circuit element and exposing at least a portion of the circuit element. The input sensing unit includes a first conductive layer, a second conductive layer including a sensing pattern, and a second insulating layer between the first conductive layer and the second conductive layer. The second insulating layer exposes at least a portion of the first conductive layer. The insulating layer between the end of the signal line and the pad is defined as a pad insulating layer. A maximum thickness of the pad insulating layer is greater than a sum of thicknesses of the first insulating layer and the second insulating layer.

[0010] According to an example embodiment, an electronic device includes a base substrate, a circuit element, a signal line, a first insulating layer, a display device layer, a first conductive layer, a second insulating layer, a second conductive layer, and a pad. The base substrate includes an active area and a peripheral area. The circuit element is on the active area. The signal line is connected to the circuit element. The first insulating layer covers the circuit element and the signal line. The first insulating layer exposes a portion of the circuit element and a portion of an end of the signal line. The display device layer includes a light emitting device on the active area. The display device layer is connected to the portion of the circuit element. The first conductive layer is on the display device layer. The second insulating layer covers the first conductive layer. The second insulating layer exposes a portion of the first conductive layer and a portion of the end of the signal line. The second conductive layer is on the second insulating layer, superposed with the first conductive layer, and connected to the first conductive layer. The pad is on the peripheral area, superposed with the end of the signal line, and bonded to the end of the signal line.

[0011] According to an example embodiment, a method of manufacturing an electronic device includes forming a circuit element on a base substrate; forming a signal line on the base substrate; forming a first insulating layer covering the circuit element and the signal line; forming a display device layer on the first insulating layer, the display device layer including a light emitting device; forming a first conductive layer on the display device layer; forming a second insulating layer covering the first insulating layer and the first conductive layer; forming a first contact hole penetrating the second insulating layer in a first area superposed with the first conductive layer; forming a second contact hole penetrating the first insulating layer and the second insulating layer in a second area superposed with an end of the signal line; forming a second conductive layer superposed with the first area; and forming a pad superposed with the second area.

[0012] The foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the subject matter claimed. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings, which are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the inventive concept.

[0014] FIG. 1A is a perspective view of an electronic device according to an exemplary embodiment.

[0015] FIG. 1B is a perspective view of an electronic device according to an exemplary embodiment. FIG. 1A is an exploded perspective view of an electronic device according to an exemplary embodiment.

[0016] FIG. 2 is a perspective view of an electronic device according to an exemplary embodiment. FIG. 1B is an exploded perspective view of an example of an electronic panel according to an exemplary embodiment.

[0017] FIG. 3 is a cross-sectional view of a portion of an electronic panel according to an exemplary embodiment, taken along section line I-I' of FIG. 2 .

[0018] FIG. 4 is a cross-sectional view of a portion of an electronic panel according to an exemplary embodiment, taken along section line II-II' of FIG. 2 .

[0019] FIG. 5A , FIG. 5B and FIG. 5C are cross-sectional views of a pad of FIG. 4 at several manufacturing stages according to various exemplary embodiments.

[0020] FIG. 6A is a cross-sectional view of a portion of an electronic panel according to an exemplary embodiment, taken along section line II-II' of FIG. 2 .

[0021] FIG. 6B is a magnified view of a pad region AR1 in FIG. 6A according to an exemplary embodiment.

[0022] FIG. 7A , FIG. 7B , FIG. 7C and FIG. 7D are cross-sectional views of several manufacturing stages in which the thickness of an insulating layer of FIG. 6B is reduced according to various exemplary embodiments.

[0023] FIG. 8A , FIG. 8B and FIG. 8C are cross-sectional views of several manufacturing stages in which FIG. 7A to FIG. 7D is made as described in connection with FIG. 6BCross-sectional view of a display unit at several manufacturing stages during a process to reduce the thickness of an insulating layer of the display unit. DETAILED DESCRIPTION

[0024] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments. As used herein, the terms "embodiment" and "exemplary embodiment" are used interchangeably, and are non-limiting examples of one or more of the inventive concepts disclosed herein. It will be apparent, however, that various exemplary embodiments can be practiced without these specific details, or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various exemplary embodiments. In addition, various exemplary embodiments can be different from one another but not necessarily mutually exclusive. For example, a particular feature or characteristic of an exemplary embodiment can be used in another exemplary embodiment or in a modification or permutation thereof without necessarily being mutually exclusive.

[0025] Unless otherwise specified, the exemplary embodiments shown are to be understood as providing exemplary features of different details of some exemplary embodiments. Thus, unless otherwise specified, various features, components, modules, layers, films, panels, regions, aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various figures shown can be additionally combined, separated, interchanged, and / or rearranged without departing from the inventive concepts.

[0026] The use of cross-hatching and / or shading in the drawings is generally provided to illustrate the boundaries, or edges, of elements of the drawings. As such, unless otherwise specified, the presence of cross-hatching or shading in a drawing generally does not mean or suggest any preference or requirement for particular materials, material properties, dimensions, proportions, commonality of the illustrated elements, and / or any other characteristic, attribute, property, etc. of the elements shown. In addition, in the drawings, the dimensions and relative dimensions of various elements can be exaggerated for clarity and / or descriptive purposes. As such, the dimensions and relative dimensions of the various elements and / or features can not be to scale. When the exemplary embodiments can be carried out in various ways, the specific sequences can be performed in different sequences without departing from the inventive concepts. For example, two sequentially described processes can be performed at about the same time or in the reverse order of the way they are described. Additionally, like reference numerals indicate like elements.

[0027] When an element, such as a layer, is referred to as being "on" another element, "connected to," or "bonded to" another element, the element may be directly on, directly connected to, or directly bonded to the other element, or there may be intermediate elements present. However, when an element is referred to as being "directly on" another element, "directly connected to," or "directly bonded to" another element, there are no intermediate elements present. Other terms and / or phrases used to describe relationships between elements should be interpreted in the same way, such as "between" versus "directly between," "adjacent" versus "directly adjacent," "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, and / or a fluid connection. Additionally, the DR1, DR2, and DR3 axes are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the DR1, DR2, and DR3 axes can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0028] Although the terms “first,” “second,” etc., may be used here to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element.

[0029] Spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein for descriptive purposes and thereby to describe the relationship of one element to another (other) element as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features would then be positioned “above” said other elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. Furthermore, the terms “comprising” and / or “including,” and variations thereof, when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and are thus used to interpret the inherent biases in measurements, calculated values, and / or provided values ​​that will be recognized by those skilled in the art.

[0031] Various exemplary embodiments are described herein with reference to sectional views, isometric views, perspective views, plan views, and / or exploded views, which are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances will be anticipated. Therefore, the exemplary embodiments disclosed herein should not be construed as limited to the shapes of the specific areas shown, but will include deviations in shape caused, for example, by manufacturing processes. For this purpose, the areas shown in the drawings may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and this is not intended to be limiting.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in general dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0033] As is customary in the art, exemplary embodiments are described and illustrated in the accompanying drawings according to functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.), which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the inventive concept, each block, unit, and / or module of some exemplary embodiments can be physically separated into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the inventive concept, blocks, units, and / or modules of some exemplary embodiments can be physically combined into more complex blocks, units, and / or modules.

[0034] In the following sections, various exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0035] FIG. 1A This is a perspective view of an electronic device illustrated according to an exemplary embodiment. FIG. 1B This is illustrated according to an exemplary embodiment. FIG. 1A An exploded perspective view of an electronic device.

[0036] Reference FIG. 1A The electronic device EA may include a front surface FS for displaying an image IM. The front surface FS may be defined as parallel to the plane containing the first direction DR1 and the second direction DR2. The front surface FS may include a transmissive region TA and a border region BZA adjacent to the transmissive region TA.

[0037] The electronic device EA can display an image IM on the transmission area TA. The image IM can be at least one of a still image and a moving image. FIG. 1A A clock and multiple icons are shown as an example of an image IM, but exemplary embodiments are not limited thereto. The transmissive region TA is shown as a rectangular shape with sides parallel to the first direction DR1 and the second direction DR2, and with rounded corners, but exemplary embodiments are not limited to this example. For example, the shape of the transmissive region TA can be varied.

[0038] The border region BZA may be configured to be adjacent to the transmissive region TA. The border region BZA may have a specific (or defined) color. The border region BZA may surround the transmissive region TA. However, the exemplary embodiment is not limited to this example, and in the exemplary embodiment, the border region BZA may be configured to be adjacent to one of the side regions of the transmissive region TA, or may be omitted.

[0039] The direction orthogonal to the front surface FS can correspond to the thickness direction DR3 of the electronic device EA (hereinafter, the third direction DR3). Based on the display direction of the image IM (e.g., the third direction DR3), the front (or top) surface and rear (or bottom) surface of each element or component can be distinguished from each other. For example, the front and rear surfaces of each of the various components can be opposite each other on the third direction DR3. The directions represented by the first direction DR1, the second direction DR2, and the third direction DR3 can be relative concepts and, in some exemplary embodiments, can be used to represent other directions.

[0040] An electronic device EA can sense external input TC provided by the user from the outside. External input TC can include various types of external input, such as input via a part of the user's body, light, heat, and / or pressure. Furthermore, the electronic device EA can sense input that is in contact with or near it. External input TC is shown as input via the user's hand to the front surface FS, but as mentioned above, external input TC can be provided in various forms. Additionally, the electronic device EA can sense external input TC that can be applied through the side or rear surface of the electronic device EA, depending on its structure.

[0041] Reference FIG. 1B An electronic device EA may include a window 100, an electronic panel 200, a circuit substrate 300, and a housing 400. The window 100 and the housing 400 may be combined with each other (or integrated with each other) to form the appearance of the electronic device EA.

[0042] Window 100 may be disposed on electronic panel 200 to cover the front surface IS of electronic panel 200. Window 100 may include an optically transparent insulating material. For example, window 100 may be formed of at least one of glass and plastic (or include at least one of glass and plastic). Window 100 may have a multilayer structure or a single-layer structure. For example, window 100 may have a stacked structure comprising multiple plastic films bonded to each other by an adhesive layer, or it may have a stacked structure comprising a glass substrate and plastic films bonded to each other by an adhesive layer.

[0043] Window 100 may include a front surface FS exposed to the outside. The front surface of the electronic device EA may be substantially defined by the front surface FS of window 100. For example, the transmissive region TA may be an optically transparent region. The transmissive region TA may have a shape corresponding to the effective region AA. For example, the transmissive region TA may completely overlap or at least partially overlap with the effective region AA of the front surface IS of the electronic panel 200. An image IM displayed on (or via) the effective region AA of the electronic panel 200 may be provided to the user through the transmissive region TA.

[0044] The border area BZA can define the shape of the transmissive area TA. The border area BZA can be adjacent to and surround the transmissive area TA. The border area BZA can have a predetermined color. When the window 100 is provided in the form of a glass substrate or a plastic substrate, the border area BZA can be formed by printing or depositing a color layer on the surface of the glass substrate or the plastic substrate, or by coloring the glass substrate or the plastic substrate. Compared to the transmissive area TA, the border area BZA can have a relatively low optical transmittance. The border area BZA can cover the peripheral area NAA of the electronic panel 200 and can prevent (or mitigate) the peripheral area NAA from being recognized by the user. However, the exemplary embodiments are not limited thereto; in the exemplary embodiments, the border area BZA can be omitted.

[0045] The electronic panel 200 can display an image IM and sense external input TC. According to an exemplary embodiment, the electronic device EA can provide an environment in which the electronic panel 200 is used not only to display an image IM but also to sense external input TC. Furthermore, according to some exemplary embodiments, it is possible to reduce the thickness of the electronic device EA and assemble the electronic device EA more efficiently. (Refer to...) FIG. 2 An exemplary structure of the electronic panel 200 is described in more detail below.

[0046] When viewed in a plan view (e.g., when viewed along (or from) a third party toward DR3), the electronic panel 200 may include an active area AA and a peripheral area NAA that are distinct from each other. The active area AA may be an area activated according to an electrical signal. In an exemplary embodiment, the active area AA may be an area for displaying an image IM and sensing an external input TC. However, the exemplary embodiment is not limited to this example; in an exemplary embodiment, the active area AA may be divided into an area for displaying the image IM and another area for sensing the external input TC.

[0047] The peripheral region NAA may be adjacent to the active region AA. For example, the peripheral region NAA may surround the boundary of the active region AA. However, the exemplary embodiments are not limited to this example; in the exemplary embodiments, the peripheral region NAA may be adjacent to a portion of the boundary of the active region AA. Various signal lines, pads, and / or electronic components for providing electrical signals to the active region AA may be disposed within the peripheral region NAA. The peripheral region NAA may be covered by the border region BZA and may not be recognizable by the user.

[0048] The circuit substrate 300 can be connected to the electronic panel 200. The circuit substrate 300 can be disposed on the peripheral area NAA of the electronic panel 200. The circuit substrate 300 can be bonded to the electronic panel 200 by means of a chip-on-panel (COP). However, the exemplary embodiment is not limited to this example. In the exemplary embodiment, the circuit substrate 300 can be connected to the electronic panel 200 by means of a flexible circuit substrate.

[0049] The circuit substrate 300 may include signal lines and electronic components; that is, the circuit substrate 300 may be an electronic circuit. The electronic components may be incorporated into the signal lines and may be electrically connected to the electronic panel 200. The electronic components may generate various electrical signals (e.g., electrical signals for generating an image IM and / or electrical signals for sensing an external input TC) and / or may process the sensed signals. As an example, the circuit substrate 300 may provide a data voltage to generate an image IM. As another example, the circuit substrate 300 may include multiple electronic components, each for each signal to be generated or processed.

[0050] The housing 400 may be disposed at least below the electronic panel 200. The housing 400 may comprise a material with relatively high rigidity compared to the electronic panel 200. For example, the housing 400 may comprise multiple frames and / or plates, each of which is formed of at least one of glass, plastic, and metal. The housing 400 may provide space for storing and / or supporting the electronic panel 200 and the circuit substrate 300, and may protect the electronic panel 200 and the circuit substrate 300 from external impacts.

[0051] FIG. 2 This is illustrated according to an exemplary embodiment. FIG. 1B An exploded perspective view of an example electronic panel.

[0052] Reference FIG. 2 The electronic panel 200 may include a display unit 210 and an input sensing unit 220. The display unit 210 may generate and display an image IM on (or via) an effective area AA. The display unit 210 may include a substrate SUB, multiple signal lines GL, DL, PL and RL, a pixel PX, and a pad PD.

[0053] The substrate SUB can have a planar shape corresponding to the planar shape of the electronic panel 200. The substrate SUB can be rigid, flexible, and / or tortuous, etc. As an example, the substrate SUB can be an insulating polymer film.

[0054] Signal lines GL, DL, PL, and RL can be disposed on the substrate SUB. Signal lines GL, DL, PL, and RL can include gate line GL, data line DL, power line PL, and routing line RL. Gate line GL, data line DL, and power line PL can be used to transmit different electrical signals.

[0055] Gate lines GL may extend along a first direction DR1. In an exemplary embodiment, multiple gate lines GL may be arranged to be spaced apart from each other along a second direction DR2, but for ease of illustration, in FIG. 2 The diagram exemplarily illustrates only one of multiple gate lines GL. The gate line GL can be used to transmit gate signals generated in a gate drive circuit (not shown) to a pixel PX.

[0056] Data lines DL can extend along a second direction DR2. Data lines DL can be electrically disconnected from gate lines GL. In an exemplary embodiment, multiple data lines DL can be arranged to be spaced apart from each other along a first direction DR1; however, for ease of illustration, ... FIG. 2 The example shows only one of multiple data lines DL. The data line DL can be used to transmit data signals to the pixel PX. Here, the data signal can be, for example... FIG. 1B The circuit substrate 300 is provided.

[0057] The power line PL can extend along the second direction DR2. The power line PL can be electrically disconnected from the gate line GL and the data line DL. In an exemplary embodiment, multiple power lines PL can be arranged to be spaced apart from each other along the first direction DR1, but for ease of illustration, in FIG. 2 The example shown is only one of multiple power lines PL. Power lines PL can be used to provide power signals to pixel(s) PX(s).

[0058] The routing line RL can be set in the peripheral area NAA. The routing line RL can connect the pad PD to the corresponding signal lines. Signal lines may include data lines DL, gate lines GL, lines connected to the gate drive circuit (not shown), and / or lines connected to the power line PL, etc. Exemplary embodiments are not limited to these examples. FIG. 2 In the example shown, in some exemplary embodiments, each of the routing lines RL can be connected to a corresponding one of the signal lines to form a single object.

[0059] Pixel PX can emit light that constitutes image IM in response to an electrical signal. In an exemplary embodiment, multiple pixels PX can be provided, but for ease of illustration, ... FIG. 2 The example shows only one of a plurality of pixels PX. In some exemplary embodiments, the circuit structure of the pixel PX may be varied, and the exemplary embodiments are not limited to the specific embodiment.

[0060] Pixel PX can receive data signals provided via data lines DL based on a gate signal provided via gate line GL. For this purpose, pixel PX may include a switching transistor. Pixel PX may include elements for storing charge, and the amount of charge stored in the charge storage element can be determined by the difference between the data signal and the electrical signal. For example, pixel PX may include a capacitor as a charge storage element. Pixel PX may include a light-emitting device configured to emit light, and the intensity of the light can be determined by the amount of charge stored in the capacitor. Furthermore, pixel PX may include a drive transistor that controls the current flowing through the light-emitting device based on the amount of charge. (See reference...) FIG. 3 An exemplary cross-sectional structure of pixel PX is described in more detail.

[0061] The pad PD can be disposed in the peripheral region NAA of the display unit 210, and can be disposed in a side region of the peripheral region NAA defined as a pad region. The pad PD can be connected to the circuit substrate 300. As an example, the pad PD and the circuit substrate 300 can be electrically connected to each other through conductive components (e.g., anisotropic conductive films). The display pad PDD and the sensing pad PDT can be disposed in a portion of the peripheral region NAA, in which case the display unit 210 and the input sensing unit 220 can be driven (e.g., simultaneously driven) through the circuit substrate 300. In this case, it is possible to efficiently assemble the electronic panel 200 and / or the electronic device EA and simplify the manufacturing process of the electronic panel 200 and / or the electronic device EA.

[0062] The pad PD may include a display pad PDD and a sensing pad PDT. The display pad PDD may provide electrical signals to the display unit 210. In an exemplary embodiment, the display pad PDD may include pads, each of which is connected to one of a data line DL, a power line PL, and a gate drive circuit (not shown). The sensing pad PDT may provide electrical signals to the input sensing unit 220. In an exemplary embodiment, the sensing pad PDT may be connected to the sensing terminal TP of the input sensing unit 220.

[0063] Pads (PDs) can be configured to have no differences in stacking structure and constituent materials, and can be formed using essentially the same process. In other words, display pads (PDDs) and sensing pads (PDTs) can have similar stacking and chemical structures, and can be formed using the same process. The process for forming pads (PDs) will be described in more detail below.

[0064] The input sensing unit 220 may be disposed on the display unit 210. The input sensing unit 220 may be configured to sense external input TC (e.g., FIG. 1A The input sensing unit 220 may include multiple sensing electrodes TE1 and TE2, multiple sensing lines TSL, and sensing terminals TP, as shown in the figure.

[0065] Sensing electrodes TE1 and TE2 can be disposed within the effective region AA. Sensing electrodes TE1 and TE2 may include a first sensing electrode TE1 and a second sensing electrode TE2 that receive corresponding electrical signals different from each other. The input sensing unit 220 can obtain information about the external input TC from the change in capacitance between the first sensing electrode TE1 and the second sensing electrode TE2.

[0066] The first sensing electrode TE1 may extend along the second direction DR2. In an exemplary embodiment, a plurality of first sensing electrodes TE1 may be arranged to be spaced apart from each other along the first direction DR1. The first sensing electrode TE1 may include a plurality of first sensing patterns SP1 and a plurality of first connecting patterns BP1 arranged along the second direction DR2. The first sensing patterns SP1 and the first connecting patterns BP1 may be arranged alternately along the second direction DR2. Each of the first connecting patterns BP1 may connect two adjacent patterns in the first sensing patterns SP1.

[0067] The second sensing electrode TE2 may extend along the first direction DR1. In an exemplary embodiment, a plurality of second sensing electrodes TE2 may be arranged to be spaced apart from each other along the second direction DR2. The second sensing electrode TE2 may include a plurality of second sensing patterns SP2 and a plurality of second connecting patterns BP2 arranged along the first direction DR1. The second sensing patterns SP2 and the second connecting patterns BP2 may be arranged alternately along the first direction DR1. Each of the second connecting patterns BP2 may connect two adjacent patterns in the second sensing patterns SP2.

[0068] In an exemplary embodiment, the first connection pattern BP1 and the second connection pattern BP2 may be disposed on different layers, while the first sensing pattern SP1 and the second sensing pattern SP2 may be disposed on the same layer. For example, the first connection pattern BP1 may be disposed on a different layer than the layer below the second connection pattern BP2, the first sensing pattern SP1, and the second sensing pattern SP2, while the second connection pattern BP2, the first sensing pattern SP1, and the second sensing pattern SP2 may be disposed on the same layer. However, the exemplary embodiment is not limited to this example. In an exemplary embodiment, the first connection pattern BP1 may be disposed on the same layer as the layer below the first sensing pattern SP1 and the second sensing pattern SP2, or the first sensing electrode TE1 and the second sensing electrode TE2 may be disposed on different layers.

[0069] Sensing lines TSL and sensing terminals TP can be disposed in the peripheral area NAA. Sensing terminals TP can be connected to sensing lines TSL. Sensing terminals TP can be connected to sensing pads PDT. Sensing lines TSL may include a first sensing line SL1 and a second sensing line SL2. The first sensing line SL1 can be used to transmit an externally supplied electrical signal to a first sensing electrode TE1. The second sensing line SL2 can be used to transmit an externally supplied electrical signal to a second sensing electrode TE2. For example, the electrical signal may be generated by a touch event.

[0070] FIG. 3 It is shown along according to an exemplary embodiment. FIG. 2 A cross-sectional view of a portion of the electronic panel, taken by section line I-I'. FIG. 3 It can be shown in relation to FIG. 2 A cross-sectional view of the display unit 210 and the input sensing unit 220 in the area corresponding to pixel PX. However, FIG. 3 The cross-sectional view shows an example structure and cross-sectional shape of pixel PX, and can vary depending on the selected location of the cross-sectional view. For example, the location of contact holes, the connection structure between patterns, and the arrangement of insulating layers can be changed depending on the selected location of the cross-sectional view.

[0071] Reference FIG. 3The display unit 210 may include a substrate SUB, a circuit element layer, a display device layer, and a TFE encapsulation layer. The circuit element layer includes various circuit elements for driving light-emitting devices, and the display device layer includes the light-emitting devices. The substrate SUB may include an insulating material. For example, the substrate SUB may include a flexible material such as polyimide (PI). In some exemplary embodiments, the substrate SUB may include a rigid material such as glass or plastic. In other cases, the substrate SUB may be a single-layer structure or a multi-layer structure. A multi-layer structure of the substrate SUB may include layers whose material is different from the material of at least one other layer in the multi-layer structure.

[0072] The circuit element layer may include multiple insulating layers 211, 212, 213, 214, and 215, semiconductor patterns SP-1 and SP-2, conductive patterns GT1-1, GT1-2, and GT2, and connection patterns E1-1, E1-2, and E2. The insulating layers 211, 212, 213, 214, and 215, the semiconductor patterns SP-1 and SP-2, the conductive patterns GT1-1, GT1-2, and GT2, and the connection patterns E1-1, E1-2, and E2 can be used to form multiple transistors and / or multiple capacitors included in the aforementioned pixel PX. Although not shown, the circuit element layer may also include a buffer layer disposed on the substrate SUB. The buffer layer may include at least one inorganic layer and may increase the adhesion strength between the substrate SUB and the semiconductor patterns SP-1 and SP-2.

[0073] Semiconductor patterns SP-1 and SP-2 can be disposed on a substrate SUB and a buffer layer (not shown). Semiconductor patterns SP-1 and SP-2 can include at least one of polycrystalline silicon, amorphous silicon, and metal oxide, but exemplary embodiments are not limited to this example. Semiconductor patterns SP-1 and SP-2 can be arranged in a specific regularity throughout the entire pixel PX. Semiconductor patterns SP-1 and SP-2 can include doped regions and undoped regions. Doped regions can be doped with n-type dopant or p-type dopant. As an example, a p-type transistor can include doped regions doped with p-type dopant.

[0074] Doped regions can have higher conductivity than undoped regions, and therefore can be used as electrodes or signal lines. In an exemplary embodiment, the undoped region can be used as the active region or channel region of a transistor. In other words, semiconductor patterns SP-1 and SP-2 may include portions serving as active regions of a transistor, another portion serving as source or drain electrodes of a transistor, and another portion serving as connection electrodes or connection signal lines.

[0075] The first insulating layer 211 can be disposed on the substrate SUB, the buffer layer (not shown), and the semiconductor patterns SP-1 and SP-2. The first insulating layer 211 can be associated with multiple pixels PX (e.g., see...). FIG. 2 The layers are stacked together and can cover semiconductor patterns SP-1 and SP-2. The first insulating layer 211 can be an inorganic layer and / or an organic layer and can have a single-layer structure or a multilayer structure. As an example, the first insulating layer 211 can be a single-layer silicon oxide layer. However, the exemplary embodiments are not limited to this example. In the exemplary embodiments, the first insulating layer 211 can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, zirconium oxide, and hafnium oxide.

[0076] First conductive patterns GT1-1 and GT1-2 may be disposed on the first insulating layer 211. The first conductive patterns GT1-1 and GT1-2 may be portions of a metal pattern. In an exemplary embodiment, the first conductive patterns GT1-1 and GT1-2 may have, for example, a three-layer structure of titanium / aluminum / titanium, but the exemplary embodiment is not limited to this example. The first conductive patterns GT1-1 and GT1-2 may be stacked with semiconductor patterns SP-1 and SP-2, respectively. The first conductive patterns GT1-1 and GT1-2 may be used as gates to control the current flowing through semiconductor patterns SP-1 and SP-2. The first conductive patterns GT1-1 and GT1-2 may be used as doping masks in a process of doping semiconductor patterns SP-1 and SP-2 with dopants.

[0077] The second insulating layer 212 can be disposed on the first insulating layer 211 and the first conductive patterns GT1-1 and GT1-2. The second insulating layer 212 can be associated with multiple pixels PX (e.g., see...). FIG. 2 The two insulating layers are stacked together and can cover the first conductive patterns GT1-1 and GT1-2. The second insulating layer 212 can be an inorganic layer and / or an organic layer and can have a single-layer structure or a multi-layer structure. As an example, the second insulating layer 212 can be a single-layer silicon nitride layer, but the exemplary embodiments are not limited to this example.

[0078] The second conductive pattern GT2 can be disposed on the second insulating layer 212. The second conductive pattern GT2 can be superimposed on at least one of the first conductive patterns GT1-1 and GT1-2 (e.g., the first conductive pattern GT1-1) to form a reference. FIG. 2 The capacitor described. In this case, the second insulating layer 212 can be used as the dielectric material of the capacitor, and the first conductive pattern GT1-1 and the second conductive pattern GT2 can be used as the electrodes of the capacitor. The second conductive pattern GT2 can be part of a metal pattern. As an example, the second conductive pattern GT2 can have a three-layer structure such as titanium / aluminum / titanium, but the exemplary embodiment is not limited to this example.

[0079] The third insulating layer 213 can be disposed on the second insulating layer 212 and the second conductive pattern GT2. The third insulating layer 213 can be associated with multiple pixels PX (e.g., see...). FIG. 2 The third insulating layer 213 can be stacked together and may cover the second conductive pattern GT2. The third insulating layer 213 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. As an example, the third insulating layer 213 may include a silicon oxide layer and a silicon nitride layer, but the exemplary embodiments are not limited to this example.

[0080] Intermediate connection patterns E1-1 and E1-2 can penetrate at least one of the first insulating layer 211, the second insulating layer 212, and the third insulating layer 213, and can be connected to at least one of the semiconductor patterns SP-1 and SP-2 or at least one of the conductive patterns GT1-1, GT1-2, and GT2. Contact holes can be formed to penetrate at least one of the first insulating layer 211, the second insulating layer 212, and the third insulating layer 213, and each of the intermediate connection patterns E1-1 and E1-2 can be connected to a corresponding semiconductor pattern or conductive pattern through a corresponding contact hole in the contact hole. For example, one of the intermediate connection patterns E1-1 and E1-2 (e.g., intermediate connection pattern E1-1) can be connected to the first conductive pattern GT1-1 to transmit a gate signal to the gate. For example, the other of the intermediate connection patterns E1-1 and E1-2 (e.g., intermediate connection pattern E1-2) can be connected to the drain or source of the semiconductor pattern SP-2 and can be used to transmit electrical signals (e.g., current) supplied to or output from the transistor to other electronic devices. In an exemplary embodiment, the intermediate connecting patterns E1-1 and E1-2 may have a three-layer structure, for example, titanium / aluminum / titanium, but the exemplary embodiment is not limited to this example.

[0081] The fourth insulating layer 214 can be disposed on the third insulating layer 213 and the intermediate connecting patterns E1-1 and E1-2. The fourth insulating layer 214 can be associated with multiple pixels PX (e.g., see...). FIG. 2 They are stacked together and can cover the intermediate connecting patterns E1-1 and E1-2. The fourth insulating layer 214 can be an organic layer. The fourth insulating layer 214 can be configured to have a flat top surface.

[0082] The upper connection pattern E2 can penetrate the fourth insulating layer 214 and can be connected to at least one of the intermediate connection patterns E1-1 and E1-2 (e.g., intermediate connection pattern E1-2). Contact holes can be formed to penetrate the fourth insulating layer 214. For example, the upper connection pattern E2 can be connected to the intermediate connection pattern E1-2 to provide current to the light-emitting device. As an example, the upper connection pattern E2 can have a three-layer structure, such as titanium / aluminum / titanium, but the exemplary embodiments are not limited to this example.

[0083] The fifth insulating layer 215 can be disposed on the fourth insulating layer 214 and the upper connecting pattern E2. The fifth insulating layer 215 can be associated with multiple pixels PX (e.g., see...). FIG. 2 The layers are stacked and can cover the upper connection pattern E2. The fifth insulating layer 215 can be an organic layer. The fifth insulating layer 215 can be configured to have a flat top surface. Contact holes can be formed in the fifth insulating layer 215, through which the upper connection pattern E2 can transmit electrical signals to the display device layer.

[0084] The display device layer may include a first electrode AE, an emissive layer EML, a second electrode CE, and a pixel defining layer PDL. The first electrode AE, the emissive layer EML, and the second electrode CE define the light-emitting device. Although not shown, a hole control layer may be disposed between the first electrode AE ​​and the emissive layer EML, and an electronic control layer may be disposed between the second electrode CE and the emissive layer EML.

[0085] The first electrode AE ​​can be disposed on the fifth insulating layer 215 and the upper connecting pattern E2. The first electrode AE ​​can penetrate the fifth insulating layer 215 and can be connected to the upper connecting pattern E2. The first electrode AE ​​can be used as the anode electrode of the light-emitting device. The first electrode AE ​​can receive electrical signals from the upper connecting pattern E2.

[0086] A pixel defining layer (PDL) may be disposed on the fifth insulating layer 215 and the first electrode AE. The pixel defining layer (PDL) may have an opening superimposed on the light-emitting region. This opening may be defined to expose a portion of the first electrode AE.

[0087] The emissive layer EML can be disposed in an opening defined in the pixel-defining layer PDL and can be disposed on the first electrode AE. The emissive layer EML can include at least one of organic light-emitting materials, quantum dots, and quantum rods, but exemplary embodiments are not limited to this example. The emissive layer EML can include a light-emitting material. For example, the emissive layer EML can be formed of at least one material selected from light-emitting materials that emit at least one of red, green, and blue light. The emissive layer EML can emit light based on the potential difference between the first electrode AE ​​and the second electrode CE.

[0088] The second electrode CE can be disposed on the light-emitting layer EML and the pixel-defining layer PDL. The second electrode CE may include a transmissive conductive material or a transmissive-reflective conductive material that allows easy emission of light. The second electrode CE can be associated with multiple pixels PX (e.g., see...). FIG. 2 They are stacked together.

[0089] The encapsulation layer TFE can be disposed on the second electrode CE to cover the display device layer. The encapsulation layer TFE can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure. The encapsulation layer TFE can provide a flat top surface.

[0090] The input sensing unit 220 may include insulating layers 221 and 222 and conductive layers T1 and T2. The input sensing unit 220 may be disposed on the display unit 210.

[0091] The sixth insulating layer 221 may be disposed on the encapsulation layer TFE of the display unit 210. The sixth insulating layer 221 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. As an example, the sixth insulating layer 221 may be a single-layer silicon nitride layer, but the exemplary embodiments are not limited to this example.

[0092] The first conductive layer T1 may be disposed on the sixth insulating layer 221. For example, the first conductive layer T1 may include FIG. 2 The first conductive layer T1 can be connected to the second conductive layer T2 via a contact hole. The first conductive layer T1 may comprise at least two layers of transparent conductive material (e.g., at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), poly(3,4-ethylenedioxythiophene) (PEDOT), metal nanowires, and graphene) and / or a metal layer (e.g., at least one of molybdenum, silver, titanium, copper, and aluminum, or alloys thereof). As an example, the first conductive layer T1 may have a three-layer structure, for example, titanium / aluminum / titanium.

[0093] A seventh insulating layer 222 may be disposed on the sixth insulating layer 221 and the first conductive layer T1. The seventh insulating layer 222 may cover the first conductive layer T1. The seventh insulating layer 222 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. As an example, the seventh insulating layer 222 may be a single-layer silicon nitride layer, but the exemplary embodiments are not limited to this example.

[0094] The second conductive layer T2 can be disposed on the seventh insulating layer 222. The second conductive layer T2 can penetrate the seventh insulating layer 222 and can be connected to the first conductive layer T1. The second conductive layer T2 may include FIG. 4 The first connection pattern BP1 and the second connection pattern BP2, the first sensing pattern SP1 and the second sensing pattern SP2. The second conductive layer T2 may include at least two layers of transparent conductive layer (e.g., at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), poly(3,4-ethylenedioxythiophene) (PEDOT), metal nanowires and graphene) and / or metal layer (e.g., at least one of molybdenum, silver, titanium, copper and aluminum or alloys thereof). As an example, the second conductive layer T2 may have, for example, a three-layer structure of titanium / aluminum / titanium.

[0095] FIG. 2It is shown along according to an exemplary embodiment. FIG. 4 A cross-sectional view of a portion of the electronic panel, taken by section line II-II'. For example, FIG. 2 It can be shown with FIG. 4 A cross-sectional view of the area corresponding to the pad PD.

[0096] Reference FIG. 2 In the region corresponding to the pad PD, FIG. 4 The electronic panel 200 may include a substrate SUB, multiple insulating layers 211, 212, 213, 221 and 222, signal lines GT and pad conductive patterns TT.

[0097] Insulating layers 211, 212, 213, 221 and 222 can be stacked on the substrate SUB. FIG. 3 Each of the insulating layers in the middle is used with FIG. 3 The corresponding layer in the attached diagram is identified. In other words, it can be formed using... FIG. 4 The first insulating layer 211, the second insulating layer 212, the third insulating layer 213, the sixth insulating layer 221, and the seventh insulating layer 222 are formed by the corresponding layer process. FIG. 3 Each of the insulating layers 211, 212, 213, 221, and 222 is shown below. In the following text, in order to... FIG. 3 The description in the text will remain consistent and will be combined. FIG. 3 The reference numerals in the accompanying drawings are used to define the name of each element in the insulating layer. For example, the reference numerals will be used with... FIG. 4 The terms corresponding to the figure labels are used to describe FIG. 4 The diagram shows five insulating layers, instead of describing them using the terms "first insulating layer to fifth insulating layer". FIG. 3 The five insulating layers are shown in the image.

[0098] The first insulating layer 211 can be disposed on the substrate SUB. When formed... FIG. 3 When the first insulating layer 211 covers the semiconductor patterns SP-1 and SP-2, the first insulating layer 211 can be with FIG. 3 The first insulating layer 211 of the display unit 210 is formed together with the first insulating layer 211. Therefore, the first insulating layer 211 may include the first insulating layer 211 formed together with the first insulating layer 211 of the display unit 210. FIG. 3 The material of the first insulating layer 211 corresponds to the material, and can have the same as the material of the first insulating layer 211. FIG. 3 The thickness of the first insulating layer 211 is basically the same.

[0099] The signal line GT can be disposed on the first insulating layer 211. When the first conductive patterns GT1-1 and GT1-2 are formed, the signal line GT can be connected to the corresponding... FIG. 3 The first conductive patterns GT1-1 and GT1-2 of the gate are formed together. Therefore, the signal line GT may include... FIG. 3The material corresponding to the first conductive patterns GT1-1 and GT1-2, and can have the same material as FIG. 3 The first conductive patterns GT1-1 and GT1-2 have essentially the same thickness.

[0100] The second insulating layer 212 can be disposed on the signal line GT and the first insulating layer 211. The second insulating layer 212 can cover the signal line GT. When formed FIG. 3 When the second insulating layer 212 covers the first conductive patterns GT1-1 and GT1-2, the second insulating layer 212 can be with FIG. 3 The second insulating layer 212 is formed together with the second insulating layer 212. Therefore, the second insulating layer 212 may include the second insulating layer 212 with the second insulating layer 212. FIG. 3 The material of the second insulating layer 212 corresponds to the material of the second insulating layer, and may have the same material as the second insulating layer 212. FIG. 3 The thickness of the second insulating layer 212 is basically the same.

[0101] The third insulating layer 213 can be disposed on the second insulating layer 212. When formed FIG. 3 When the third insulating layer 213 covers the second conductive pattern GT2, the third insulating layer 213 can be with FIG. 3 The third insulating layer 213 is formed together with the third insulating layer 213. Therefore, the third insulating layer 213 may include the third insulating layer 213 with the third insulating layer 213. FIG. 3 The material of the third insulating layer 213 corresponds to the material, and can have the same as FIG. 3 The thickness of the third insulating layer 213 is substantially the same as that shown in the figures. Contrary to what is shown in the figures, one of the second insulating layer 212 and the third insulating layer 213 may not be present in the relevant area.

[0102] The second insulating layer 212 and the third insulating layer 213 can cover the signal line GT and prevent the signal line GT from being exposed to the outside until the manufacturing is completed. FIG. 3 The manufacturing process of the display unit 210. When the signal line GT is exposed to the outside, it may react with the etching solution used in the etching process of manufacturing the display unit 210 and may generate metal particles. In this case, a short circuit may form in the pad area. For example, if the signal line GT contains aluminum, silver contained in the etching solution used in the process of manufacturing the display device layer may be reduced by the aluminum. If silver particles are formed near the signal line GT by such a reduction process, a short circuit may form between the conductive pattern and / or the signal line. According to an exemplary embodiment, the second insulating layer 212 and the third insulating layer 213 may cover the signal line GT, in which case such a chemical reaction can be prevented.

[0103] Pad PD may not include FIG. 3 The conductive patterns corresponding to the connection patterns E1-1, E1-2, and E2. Return to reference. FIG. 3The fourth insulating layer 214 and the fifth insulating layer 215 can be configured to cover the connection patterns E1-1, E1-2, and E2. Since the fourth insulating layer 214 and the fifth insulating layer 215 are much thicker than the first insulating layer 211, the second insulating layer 212, and the third insulating layer 213, the fourth insulating layer 214 and the fifth insulating layer 215 may not be disposed on the third insulating layer 213 in the region corresponding to the pad PD. Therefore, if the conductive patterns corresponding to the connection patterns E1-1, E1-2, and E2 are formed at the ends of the signal lines GT, the conductive patterns may be exposed to the outside during the manufacturing process of the display device layer, which can lead to quality degradation of the pad PD.

[0104] The sixth insulating layer 221 can be disposed on the third insulating layer 213. When in FIG. 3 When a sixth insulating layer 221 is formed on the display unit 210, the sixth insulating layer 221 can interact with... FIG. 3 The sixth insulating layer 221 is formed together with the input sensing unit 220. In other words, the sixth insulating layer 221 can be generated during the manufacturing process of the input sensing unit 220. Therefore, the sixth insulating layer 221 may include the sixth insulating layer 221 with the input sensing unit 220. FIG. 3 The material of the sixth insulating layer 221 corresponds to the material, and can have the same as FIG. 3 The thickness of the sixth insulating layer 221 is basically the same.

[0105] The seventh insulating layer 222 can be disposed on the sixth insulating layer 221. When formed... FIG. 3 When the seventh insulating layer 222 covers the first conductive layer T1, the seventh insulating layer 222 can interact with... FIG. 3 The seventh insulating layer 222 is formed together with the seventh insulating layer 222. In other words, the seventh insulating layer 222 can be produced during the manufacturing process of the input sensing unit 220. Therefore, the seventh insulating layer 222 can include the seventh insulating layer 222 with the seventh insulating layer 222. FIG. 3 The material corresponding to the seventh insulating layer 222, and can have the same material as FIG. 3 The thickness of the seventh insulating layer 222 is basically the same.

[0106] The conductive pattern TT can penetrate the second insulating layer 212, the third insulating layer 213, the sixth insulating layer 221 and the seventh insulating layer 222 and can be connected to the end of the signal line GT. FIG. 3 Each of the pads PD may include a pad conductive pattern TT. Contact holes may be formed to penetrate a corresponding insulating layer, and the contact holes may be formed during the... FIG. 3 The contact holes are used to connect the first conductive layer T1 and the second conductive layer T2 to each other. FIG. 3 The contact holes are formed together. Furthermore, when formed... FIG. 3 When the second conductive layer T2 is applied, the pad conductive pattern TT can be... FIG. 3The second conductive layer T2 is formed together with it. Therefore, the pad conductive pattern TT can include, together with, the second conductive layer T2. FIG. 4 The material of the second conductive layer T2 corresponds to the material of the pad. Furthermore, the conductive pattern of the pad can be exposed to the outside during the manufacturing process of the input sensing unit 220.

[0107] The conductive pattern TT pad can be electrically connected to FIG. 6A The circuit substrate 300 can be bonded to the electronic panel 200 in a chip-on-panel (COP) manner. In this case, the organic layer surrounding the pad PD or the pad conductive pattern TT may not be present. For example, when forming FIG. 3 When the fifth insulating layer 215 is applied, the organic layer can interact with... FIG. 3 The fifth insulating layer 215 is formed together. When the circuit substrate 300 is bonded to the electronic panel 200 via a pad PD, the pressure applied to the pad PD may be higher compared to the case formed by chip-on-film (COF). Such pressure may cause the organic layer surrounding the pad PD to lift. Therefore, the organic layer may not surround the pad PD.

[0108] FIG. 4 , FIG. 4 and FIG. 3 These are examples illustrating several manufacturing stages according to various exemplary embodiments. FIG. 3 A cross-sectional view of the pad.

[0109] Reference FIG. 6B A first insulating layer 211 can be disposed on the substrate SUB. The first insulating layer 211 can be coupled with... FIG. 2 The first insulating layer 211 corresponds to and can be with FIG. 3 The first insulating layer 211 is formed together with it. A signal line GT can be disposed on the first insulating layer 211. When formed... FIG. 7A When the first conductive patterns GT1-1 and GT1-2 are used, the signal line GT can be connected to... FIG. 7B The first conductive patterns GT1-1 and GT1-2 are formed together.

[0110] Subsequently, a second insulating layer 212 and a third insulating layer 213 can be provided on the signal line GT to cover the signal line GT. The second insulating layer 212 can be combined with... FIG. 7C The second insulating layer 212 corresponds to and can be with FIG. 7D The second insulating layer 212 is formed together with the third insulating layer 213. FIG. 6B The third insulating layer 213 corresponds to and can be with FIG. 6AThe third insulating layer 213 is formed together with it. The end of the signal line GT may not be exposed to the outside until the process of manufacturing the display unit 210 is completed after the third insulating layer 213 is formed. Therefore, it is possible to prevent the characteristics of the pad PD from being degraded by the etching solution during the process of manufacturing the display device layer.

[0111] Reference FIG. 4 A sixth insulating layer 221 and a seventh insulating layer 222 can be disposed on the third insulating layer 213. The sixth insulating layer 221 and the seventh insulating layer 222 can be formed during the manufacturing process of the input sensing unit 220. The sixth insulating layer 221 can be... FIG. 7A The sixth insulating layer 221 corresponds to and can be with FIG. 3 The sixth insulating layer 221 is formed together. The seventh insulating layer 222 can be formed together with... FIG. 7B The seventh insulating layer 222 corresponds to and can be with FIG. 7C Together with the seventh insulating layer 222, it is formed.

[0112] Reference FIG. 7B To form the conductive pattern TT on the pad, contact holes CH can be formed to penetrate the insulating layer. Contact holes can be formed to... FIG. 7D Contact holes CH are formed during the process of connecting the first conductive layer T1 and the second conductive layer T2. A mask can be used to etch the second insulating layer 212, the third insulating layer 213, the sixth insulating layer 221, and the seventh insulating layer 222 in a specific area. Afterward, the pad conductive pattern TT can be bonded to the end of the signal line GT.

[0113] The maximum thickness of the insulating layer (hereinafter referred to as the pad insulating layer) disposed between the end of the signal line GT and the pad conductive pattern TT can be determined by the previously described process. The maximum thickness of the pad insulating layer can be greater than the sum of the thickness of a single insulating layer (e.g., a second insulating layer 212 or a third insulating layer 213) and the thickness of a contact hole, the single insulating layer being used to form or cover circuit elements (e.g., transistors or capacitors) constituting the display unit 210, the contact hole being used to connect the first conductive layer T1 and the second conductive layer T2 of the input sensing unit 220. This is because at least one insulating layer is used before forming the display device layer, and the thickness of the insulating layer prior to forming the contact hole affects the thickness of the pad insulating layer in the manufacturing process of the input sensing unit 220.

[0114] FIG. 3 It is shown along according to an exemplary embodiment. FIG. 8A A cross-sectional view of a portion of the electronic panel, taken by section line II-II'. FIG. 8B This is according to an exemplary embodiment. FIG. 8C A magnified view of the pad region AR1 in the image. For example, FIG. 7A to FIG. 7D and FIG. 6BIt can be shown with FIG. 8A to FIG. 8C A cross-sectional view of the area corresponding to the pad PD.

[0115] Reference FIG. 2 In the region corresponding to the pad PD, FIG. 8A The electronic panel 200 may include a substrate SUB, multiple insulating layers 211, 213, 221, and 222, the end of a signal line GT, and a conductive pattern TT. The insulating layers 211, 213, 221, and 222 may be disposed and stacked on the substrate SUB. A first insulating layer 211 may be disposed on the substrate SUB. The first insulating layer 211 may be connected to... FIG. 7A The display unit 210 is formed in a first insulating layer 211 covering semiconductor patterns SP-1 and SP-2.

[0116] The signal line GT can be disposed on the first insulating layer 211. As an example, when a second conductive pattern GT2 is formed to form... FIG. 8B When using a capacitor, the signal line GT can be formed together with the second conductive pattern GT2. In other words, it is combined with... FIG. 7B Compared to the exemplary embodiments described, when forming FIG. 8C When the second conductive pattern GT2 is used instead of the first conductive patterns GT1-1 and GT1-2, the signal line GT can be formed together with the second conductive pattern GT2. In this case, FIG. 3 The second insulating layer 212 may not be provided on the pad area or may be provided between the first insulating layer 211 and the signal line GT.

[0117] The third insulating layer 213 can be disposed on the signal line GT and the first insulating layer 211. The third insulating layer 213 can cover the signal line GT. The third insulating layer 213 can be... FIG. 8B The formation corresponds to the third insulating layer 213 covering the second conductive pattern GT2. The third insulating layer 213 can cover the end of the signal line GT and can prevent the end of the signal line GT from being exposed to the outside until the manufacturing is completed. FIG. 7C The process of the display unit 210.

[0118] The sixth insulating layer 221 can be disposed on the third insulating layer 213. The sixth insulating layer 221 can be... FIG. 7D The seventh insulating layer 222 can be disposed on the sixth insulating layer 221, corresponding to the sixth insulating layer 221 disposed on the display unit 210. The seventh insulating layer 222 can be... ​ The seventh insulating layer 222 used to cover the first conductive layer T1 corresponds to it.

[0119] The conductive pattern TT can penetrate the third insulating layer 213, the sixth insulating layer 221, and the seventh insulating layer 222 and can be connected to the end of the signal line GT. Contact holes can be formed to penetrate the corresponding insulating layers 213, 221, and 222, and these contact holes can be formed... ​ The contact holes are used to connect the first conductive layer T1 and the second conductive layer T2 to each other. ​ The contact holes are formed together. Furthermore, when formed... ​ When the second conductive layer T2 is applied, the pad conductive pattern TT can be... ​ The second conductive layer T2 is formed together.

[0120] and combination ​ Compared to the exemplary embodiments described, in ​ In the pad, the thickness of the pad insulating layer between the end of the signal line GT and the pad conductive pattern TT can be reduced. This is because the second insulating layer 212 is not included in the pad insulating layer. In this case, the gate (e.g., formed before forming the signal line GT) can be thinned. ​ The first conductive patterns GT1-1 and GT1-2 can be electrically connected to the signal line GT due to bridges, etc.

[0121] As an example, in ​ and ​ In the middle, the thickness of the second insulating layer 212 can be approximately The thickness of the third insulating layer 213 can be approximately The thickness of the sixth insulating layer 221 can be approximately The thickness of the seventh insulating layer 222 can be approximately in this case, ​ The pad insulation layer can have Or a greater thickness, therefore, contact holes may be required. Or even greater thickness. To reduce the thickness of the pad insulation layer during the process of forming contact holes, when forming... ​ When the second conductive pattern GT2 is applied, the signal line GT can be connected to... ​ The second conductive pattern GT2 is formed together, and the second insulating layer 212 may not be included in the pad insulating layer.

[0122] Reference ​ This shows the pad region AR1 corresponding to a single pad. Within the region corresponding to pad region AR1, ​ The electronic panel 200 may include a first insulating layer 211, a third insulating layer 213, a sixth insulating layer 221, a seventh insulating layer 222, the end of the signal line GT, and a pad conductive pattern TT.

[0123] When the third insulating layer 213 is formed, the third insulating layer 213 may initially have a first thickness D1. In an exemplary embodiment, the first thickness D1 may be approximately To reduce the thickness of the pad insulation layer during the process of forming the contact hole, the thickness of the third insulation layer 213 disposed on the end of the signal line GT can be reduced before forming the sixth insulation layer 221. For example, the thickness of the third insulation layer 213 can be reduced to a second thickness D2 that is smaller than the first thickness D1. When forming for... ​ When etching the contact holes of the intermediate connecting patterns E1-1 and E1-2, the third insulating layer 213 can be etched. However, the third insulating layer 213 can be etched only partially to prevent the end of the signal line GT from being exposed to the outside. For example, the third insulating layer 213 can be etched to have approximately The second thickness D2.

[0124] In cases where a portion of the third insulating layer 213 is thinner than another portion of the third insulating layer 213, and the overall thickness of the sixth insulating layer 221 and the seventh insulating layer 222 remains substantially unchanged, it can be explained (or considered) that said portion of the third insulating layer 213 is pre-etched. Furthermore, in cases where a stepped structure is formed due to changes in the thickness of the pad insulating layer, it can be explained that a portion of the third insulating layer 213 is pre-etched. Since only a portion of the end of the signal line GT is pre-etched, the maximum thickness of the pad insulating layer can be maintained.

[0125] ​ , ​ , ​ and ​ The reduction is shown according to various exemplary embodiments. ​ Cross-sectional views of several manufacturing stages of the insulation layer thickness. Methods for reducing insulation layer thickness can be applied not only to... ​ The pad structure, and can be applied to ​ The pad structure.

[0126] Reference ​ A signal line GT can be disposed on the first insulating layer 211. A third insulating layer 213 can be formed on the signal line GT to cover the signal line GT. The third insulating layer 213 can have a first thickness D1 (e.g., approximately...). The third insulating layer 213 can be with ​ The third insulating layer 213 corresponds to this. In order to etch the third insulating layer 213, a photoresist PR can be coated on the third insulating layer 213.

[0127] Reference ​A halftone mask HM can be applied to the photoresist PR. The halftone mask HM can be used to expose a portion of the photoresist PR to light in the area where the signal line GT overlaps with the third insulating layer 213. The halftone mask HM can be configured to reduce the amount of light incident on the exposed area. As a result, the amount of light incident on the pad region AR1 can be less than the amount of light incident on the display unit 210. The exposed area of ​​the photoresist PR can be removed during the development step. In this case, a portion of the photoresist PR can be retained due to the halftone mask HM.

[0128] Reference ​ A dry etching process can be performed on the pad region AR1. This can partially remove the photoresist PR in the pad region. ​ The area exposed to light can be etched, and a portion of the third insulating layer 213 can be etched. As a result, in the area where the third insulating layer 213 overlaps with the end of the signal line GT, the thickness of the third insulating layer 213 can be reduced to the second thickness D2.

[0129] Reference ​ This can remove the remaining areas of the photoresist PR. Afterwards, it can be manufactured... ​ The input sensing unit 220 is fabricated by providing a sixth insulating layer 221 and a seventh insulating layer 222 on the pad region AR1. This can reduce the thickness of the layers etched in the contact hole process to form the pad conductive pattern TT.

[0130] ​ , ​ and ​ This is illustrated according to various exemplary embodiments in the context of combination. ​ The described reduction ​ A cross-sectional view of the display unit during several manufacturing stages, showing the thickness of the insulating layer. ​ sectional view and along ​ The sectional view corresponding to the section line I-I' is taken.

[0131] Reference ​ Semiconductor patterns SP-1 and SP-2, conductive patterns GT1-1, GT1-2 and GT2, and a first insulating layer 211, a second insulating layer 212, and a third insulating layer 213 can be formed on a substrate SUB. A photoresist PR can be coated on the third insulating layer 213. The photoresist PR can be combined with... ​ The photoresist PR corresponds to this.

[0132] Reference ​A full-tone mask FM can be placed on (e.g., on top of) a photoresist PR. The full-tone mask FM can be used to expose a portion of the photoresist PR to light. Under the same conditions (e.g., the same amount of incident light), the full-tone mask FM can be configured to allow a greater amount of light to pass through it compared to a half-tone mask HM. In an exemplary embodiment, the full-tone mask FM can be combined with... ​ The halftone mask HM is provided together. It can remove the exposed areas of the photoresist PR during the development step.

[0133] Reference ​ Dry etching can be performed to form contact holes. ​ The connection patterns E1-1, E1-2, and E2 will be set in the contact holes. The photoresist PR can be removed in... ​ The area exposed to light can be etched, and the third insulating layer 213 in the corresponding area can be etched. Therefore, the semiconductor pattern SP-2 and the conductive pattern GT1-1 can be exposed to the outside and then electrically connected to the connection patterns E1-1, E1-2, and E2. This can be combined with... ​ and ​ The dry etching process is performed together with the etching of the third insulating layer 213.

[0134] According to an exemplary embodiment, during the process of manufacturing the display device layer, the ends of the signal lines may not be exposed to the outside. Therefore, it is possible to prevent the silver-containing etching solution used in the process of manufacturing the display device layer from being reduced in the pad region, thereby reducing the pad failure rate. Furthermore, according to an exemplary embodiment, pads can be formed during the process of manufacturing the display unit and the input sensing unit, and failures occurring in the electronic device where the circuit substrate is directly bonded to the panel can be prevented or suppressed.

[0135] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the broader scope of the appended claims and the various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. An electronic device comprising: a display unit; and an input sensing unit on the display unit, wherein: the display unit includes an insulating layer, a signal line, a circuit element, and a pad connected to an end portion of the signal line; and the insulating layer includes a first insulating layer covering the circuit element, the first insulating layer exposing at least a portion of the circuit element, wherein the input sensing unit includes a first conductive layer, a second conductive layer including a sensing pattern, and a second insulating layer between the first conductive layer and the second conductive layer, the second insulating layer exposing at least a portion of the first conductive layer, wherein: an insulating layer between the end portion of the signal line and the pad is defined as a pad insulating layer; and a maximum thickness of the pad insulating layer is greater than a sum of a thickness of the first insulating layer and a thickness of the second insulating layer, and wherein: the pad insulating layer includes a first portion, which is stacked with the end portion of the signal line and the pad, the first portion having the maximum thickness; and a second portion, which is stacked with the end portion of the signal line and the pad, the second portion having a thickness smaller than the maximum thickness; a contact hole is defined in the second portion; and the pad is bonded to the end portion of the signal line through the contact hole. 2.The electronic device of claim 1, wherein: the circuit element includes a transistor; and a thickness of the signal line corresponds to a thickness of a gate of the transistor. 3.The electronic device of claim 1, wherein: the circuit element includes a capacitor; and a thickness of the signal line corresponds to a thickness of an electrode of the capacitor. 4.The electronic device of claim 1, wherein: the circuit element includes a capacitor; the insulating layer further includes a third insulating layer between a first conductive pattern and a second conductive pattern of the capacitor; and the pad insulating layer includes the first insulating layer, the second insulating layer, and the third insulating layer. 5.The electronic device of claim 1, wherein: a contact hole is defined in the pad insulating layer; and the pad is bonded to the end portion of the signal line through the contact hole. 6.The electronic device of claim 1, wherein: the input sensing unit further includes a third insulating layer between the display unit and the first conductive layer; and the pad insulating layer includes the first insulating layer, the second insulating layer, and the third insulating layer. 7.The electronic device of claim 1, further comprising: an electronic circuit on the pad and bonded to the pad. 8.An electronic device comprising: a base substrate including an active area and a peripheral area; a circuit element on the active area; a signal line connected to the circuit element; a first insulating layer covering the circuit element and the signal line, the first insulating layer exposing a portion of the circuit element and a portion of an end portion of the signal line; a display device layer including a light emitting device on the active area, the display device layer connected to the portion of the circuit element; a first conductive layer over the display element layer; a second insulating layer covering the first conductive layer, the second insulating layer exposing a portion of the first conductive layer and a portion of the end portion of the signal line; a second conductive layer over the second insulating layer, stacked with the first conductive layer, and connected to the first conductive layer; and a pad over the peripheral region, stacked with the end portion of the signal line, and bonded to the end portion of the signal line, wherein: an insulating layer between the end portion of the signal line and the pad is defined as a pad insulating layer; and, a maximum thickness of the pad insulating layer is greater than a sum of a thickness of the first insulating layer and a thickness of the second insulating layer, and wherein: the pad insulating layer includes: a first portion stacked with the end portion of the signal line and the pad, the first portion having the maximum thickness; and a second portion stacked with the end portion of the signal line and the pad, the second portion having a thickness smaller than the maximum thickness; a contact hole is defined in the second portion; and the pad is bonded to the end portion of the signal line through the contact hole.

9. A method of manufacturing an electronic device, the method comprising: forming a circuit element on a base substrate; forming a signal line on the base substrate; forming a first insulating layer covering the circuit element and the signal line; forming a display element layer over the first insulating layer, the display element layer including a light emitting device; forming a first conductive layer over the display element layer; forming a second insulating layer covering the first insulating layer and the first conductive layer; forming a first contact hole in a first region stacked with the first conductive layer, the first contact hole penetrating the second insulating layer; forming a second contact hole in a second region stacked with an end portion of the signal line, the second contact hole penetrating the first insulating layer and the second insulating layer; forming a second conductive layer stacked with the first region; and forming a pad stacked with the second region, wherein, after forming the first insulating layer and before forming the display element layer, in the second region, the first insulating layer is partially etched so that the first insulating layer is thinned. ​

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