power supply circuit

Abstract

This invention relates to the field of power supply technology, specifically a power supply circuit. The invention provides an induction heating power supply circuit with good performance. The invention includes a main processor, an FPGA, a main power circuit, a current acquisition section, a first RS485 bus monitoring section, a second RS485 bus monitoring section, and a drive circuit. The drive circuit's control signal input port is connected to the main processor's control signal output port; its signal transmission port is connected to the FPGA's signal transmission port; and its control signal output port is connected to the main power circuit's control signal input port. The signal transmission port of the current acquisition section is connected to the FPGA's signal transmission port.

Description

Technical Field

[0001] This invention belongs to the field of power supply technology, and in particular relates to a power supply circuit. Background Technology

[0002] Induction heating power supplies offer the highest efficiency and fastest heating speed for metal materials, while also being energy-efficient and environmentally friendly. They are widely used in various industries for hot processing, heat treatment, hot assembly, welding, and smelting of metal materials. However, current induction heating power supplies are generally three-phase powered, which is inconvenient in some situations; further improvements are needed in their structure and functionality. Summary of the Invention

[0003] The present invention addresses the above-mentioned problems by providing an induction heating power supply circuit with good performance.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: the present invention includes a main processor, an FPGA, a power main circuit, a current acquisition section, an RS485 bus first monitoring section, an RS485 bus second monitoring section, and a driving circuit. The driving circuit is characterized in that its control signal input port is connected to the control signal output port of the main processor, its signal transmission port is connected to the signal transmission port of the FPGA, and its control signal output port is connected to the control signal input port of the power main circuit.

[0005] The signal transmission port of the current acquisition section is connected to the signal transmission port of the FPGA.

[0006] The signal input port of the first listening section of the RS485 bus is connected to the signal output port of the driver circuit.

[0007] The signal input port of the second monitoring section of the RS485 bus is connected to the signal output port of the driver circuit.

[0008] The power input terminal of the main power circuit is connected to single-phase mains power.

[0009] As a preferred embodiment, the main processor of this invention adopts an STM32H743IIT6 ARM processor U5. Pins 158, 148, 135, 126, 113, 102, 90, 71, 61, 22, and 14 of U5 are grounded, and pins 172, 159, 149, 136, 127, 114, 103, 91, 82, 72, 62, 49, 36, 23, and 15 of U5 are connected to +3.3V.

[0010] Pin 1 of the MPM-20-12 chip U55 is connected to pin 2 of the UU9.8 common mode inductor L5. Pin 1 of L5 is connected to one end of the rheostat R299 and one end of the fuse F1. The other end of F1 is connected to L. The other end of R299 is connected to N and pin 3 of L5. Pin 4 of L5 is connected to pin 2 of U55. Pin 3 of U55 is connected to one end of capacitor C203, the positive terminal of capacitor C204, and +12V. The other end of C203 is connected to pin 4 of U55, the negative terminal of C204, and GND.

[0011] One end of resistor R2 is connected to U5_BOOT0, and the other end of R2 is connected to GND;

[0012] Pin 1 of SP3485 chip U60 is connected to U5_PA3, pins 2 and 3 of U60 are connected to U5_PA1, pin 4 of U60 is connected to U5_PA2, pins 5 to 8 of U60 are connected to GND, A, B, and +3.3V respectively, resistor R290 is connected to B and GND respectively, and resistor R291 is connected to A and +3.3V respectively.

[0013] Pin 1 of SP3485 chip U64 is connected to U5_PA10, pins 2 and 3 of U64 are connected to U5_PA8, pin 4 of U64 is connected to U5_PA92, pins 5, 6, 7, and 8 of U64 are connected to GND, A, B, and +3.3V respectively, resistor R292 is connected to B and GND respectively, and resistor R293 is connected to A and +3.3V respectively.

[0014] Pin 1 of SP3485 chip U63 is connected to U5_PA10, pins 2 and 3 of U63 are connected to U5_PA8, pin 4 of U63 is connected to U5_PA9, pins 5, 6, 7, and 8 of U63 are connected to GND, A, B, and +3.3V respectively, resistor R294 is connected to B and GND respectively, and resistor R295 is connected to A and +3.3V respectively.

[0015] Capacitors C85 and C69 to C82 are connected in parallel between +3.3V and GND;

[0016] +3.3V is connected to RESET, one end of capacitor C84, and one end of switch SW1 through resistor R24. The other end of C84 is connected to GND and the other end of SW1.

[0017] Pin 1 of the SD8942 / A6166 chip U19 is connected to pin 6 of U19 and one end of inductor L3 via capacitor C19. The other end of L3 is connected to +5V and one end of resistor R206. The other end of R206 is connected to one end of resistor R205 and pin 3 of U19. The other end of R205 is connected to GND and pin 2 of U19. Pin 4 of U19 is connected to pin 5 of U19, +12V, one end of capacitor C22, one end of capacitor C23, and one end of capacitor C24 via resistor R204. The other end of C22 is connected to the other end of C23, the other end of C24, and GND.

[0018] Pin 1 of the 4-pin connector P3 is connected to GND. Pin 3 of P3 is connected to U5_JTMS and one end of resistor R19. The other end of R19 is connected to +3.3V. Pin 2 of P3 is connected to U5_JTCK and one end of resistor R22. The other end of R22 is connected to GND. Pin 1 of P3 is connected to GND.

[0019] Pin 4 of crystal oscillator Y1 is connected to GND. Pin 1 of Y1 is connected to U5_OSC_OUT and one end of capacitor C67. The other end of C67 is connected to GND, pin 2 of Y1, and one end of capacitor C68. The other end of C68 is connected to pin 3 of Y1 and U5_OSC_IN.

[0020] One end of crystal oscillator Y2 is connected to one end of capacitor C66 and U5_OSC32_IN respectively. The other end of C66 is connected to GND and one end of capacitor C83 respectively. The other end of C83 is connected to the other end of Y2 and U5_OSC32_OUT respectively.

[0021] As another preferred embodiment, pin 171 of U5 in this invention is connected to pin 37 of U5, one end of capacitor C43, one end of capacitor C44, and GND through resistor R5. The other end of C43 is connected to pin 39 of U5, the other end of C44, and one end of resistor R4. The other end of R4 is connected to +3.3V.

[0022] Pin 125 of U5 is connected to GND and one end of capacitor C39 via capacitor C41. The other end of C39 is connected to pin 81 of U5.

[0023] Pin 38 of U5 is connected to +3.3V and one end of capacitor C40, while the other end of C40 is connected to GND.

[0024] Pin 6 of U5 is connected to +3.3V and one end of capacitor C36. The other end of C36 is connected to GND and one end of resistor R8. The other end of R8 is connected to pin 48 of U5.

[0025] Connect pin 166 of U5 to U5_BOOT0;

[0026] Connect pin 31 of U5 to RESET.

[0027] As another preferred embodiment, the FPGA of the present invention uses the EP4CE10F17C8 chip U22 with pins H7-10, J7-10, B2, B15, C5, C12, D7, D10, E4, and E13 connected to GND, and pins G4, G13, K4, K13, M4, M13, N7, N10, P5, P12, R2, R15, E2, H16, and H15 connected to GND.

[0028] The Vin pin of VR1 of the HT7550-1 chip is connected to capacitors C31, C32, C53, and +5V. The other end of C31 is connected to GND, the other end of C32, the other end of C53, the GND pin of VR1, one end of capacitors C33-38, one end of capacitor C42, and one end of capacitors C45-49. The other end of capacitor C33 is connected to the Vout pin of VR1, the other end of C34-38, the other end of capacitor C42, the other end of capacitors C45-49, and +3.3V.

[0029] The Vin pin of VR2 of the HT7550-1 chip is connected to one end of capacitor C50, one end of capacitor C51, one end of capacitor C55, and +3.3V. The other end of C50 is connected to GND, the other end of capacitor C51, the other end of capacitor C55, the GND pin of VR2, the negative terminal of capacitor C52, and one end of capacitor C56. The positive terminal of C52 is connected to the Vout pin of VR2, the other end of C56, and +1.2V.

[0030] The Vin pin of VR3 of the HT7550-1 chip is connected to one end of capacitors C61-63 and +5V. The other end of C61-63 is connected to GND, the GND pin of VR3, the negative terminal of capacitor C65, one end of capacitor C86, one end of capacitor C88, one end of capacitor C89, and one end of capacitor C93. The positive terminal of C65 is connected to the Vout pin of VR3, the other end of capacitor C86, the other end of capacitor C88, the other end of capacitor C89, the other end of capacitor C93, and +2.5V.

[0031] Pin 1 of SP3485 chip U65 is connected to B4, pins 2 and 3 of U65 are connected to D5, and pin 4 of U65 is connected to D6. Pins 5, 6, 7, and 8 of U65 are connected to GND, A, B, and +3.3V respectively. Resistor R275 is connected to B and GND respectively, and resistor R2765 is connected to A and +3.3V respectively.

[0032] As another preferred embodiment, in this invention, pin L5 of U22 is connected to +2.5V, pin N4 of U22 is connected to +1.2V, pin F12 of U22 is connected to +2.5V, pin D13 of U22 is connected to +1.2V, and pins E12 and M5 of U22 are connected to GND.

[0033] Pin H4 of U22 is connected to +2.5V, one end of resistor R131, and pin H12 of U22 via resistor R121. Pin H3 of U22 is connected to GND via resistor R128, and the other end of R131 is connected to pin J5 of U22.

[0034] Pin H13 of U22 is connected to pin G12 of U22, GND, and one end of resistor R241. The other end of R241 is connected to pin J3 of U22.

[0035] Pin H14 of U22 is connected to +3.3V through resistor R252, pin H5 of U22 is connected to +3.3V through resistor R253, and pin F4 of U22 is connected to +3.3V through resistor R254.

[0036] For the JTAG-10 FPGA interface, pins 2 and 10 of JTAG1 are connected to GND, and pin 4 of JTAG1 is connected to +2.5V.

[0037] Pins E3, G3, K3, M3, P4, P7, T1, P10, P13, T16, K14, M14, E14, G14, A16, C10, C13, A1, C4, and C7 of U22 are connected to +3.3V, and pins G6 to G10, H6, H11, and K7 of U22 are connected to +1.2V.

[0038] Connect pin 2 of crystal oscillator XTAL1 to GND, pin 3 of XTAL1 to CLK_1, and pin 4 of XTAL1 to +3.3V.

[0039] Pins 6, 5, 2, and 8 of the M25P16 chip U30 are connected to EPCS_CLK, EPCS_ASDO, EPCS_DATA0, and +3.3V respectively. Pin 4 of U30 is connected to GND, pins 3 and 7 of U30 are connected to +3.3V, and pin 1 of U30 is connected to EPCS_CS.

[0040] As another preferred embodiment, the power main circuit of the present invention includes an air switch K1. One end of K1 is connected to the mains power, and the other end of K1 is connected to the primary side of transformer T1. One end of the first secondary side of T1 is connected to the cathode of diode D1, the drain of IGBT Q2, and Q2_D. The anode of D1 is connected to the source of IGBT Q1 and Q1_S. The gate of Q1 is connected to Q1_B. The drain of Q1 is connected to Q1_D, the cathode of diode D2, and pin 1 of common mode inductor L2. The anode of D2 is connected to the source of Q2 and Q2_S. The gate of Q2 is connected to Q2_B. Pin 3 of L2 is connected to the other end of the first secondary side of T1.

[0041] Pin 2 of L2 is connected to the anode of diode D5 and the cathode of diode D7, respectively. The cathode of D5 is connected to the cathode of diode D6 and one end of inductor L1, respectively. The other end of L1 is connected to one end of capacitor C6 and the collector of NPN transistor Q3, respectively. The base of Q3 is connected to Q3_B, and the emitter of Q3 is connected to Q3_S, one end of capacitors C1-C4, the drain of IGBT Q4, and the drain of IGBT Q5, respectively. The other ends of C1-C4 are connected to one end of capacitors C9-C12, the source of Q4, Q4_S, the drain of IGBT Q6, and one end of the primary winding of main transformer T2, respectively. The other end of the primary winding of T2 is connected to one end of capacitors C7, C8, C13, C14, and C5, respectively. The other ends of capacitors C7, C8, C13, C14, and C5 are connected to Q5_S, the source of Q5, and the IGBT, respectively. The drain of Q7 is connected to the source of Q7, which is connected to PGND, the source of Q6, the other end of capacitors C9-C12, the other end of C6, the anode of D7, and the anode of diode D8. The cathode of D8 is connected to pin 4 of L2 and the anode of D6.

[0042] One end of the first secondary side of T2 is connected to one end of capacitors C110 to C115 respectively. The other end of C110 to C115 is connected to pin 1 of the two-pin connector P8. Pin 2 of P8 is connected to the other end of the first secondary side of T2 through the primary side of current transformer T3.

[0043] As another preferred embodiment, the current acquisition section of the present invention includes an adjustable reference source control circuit, a linear drive circuit, a voltage reference array, and a voltage comparator array. The output port of the adjustable reference source control circuit is connected to the input port of the voltage reference array. The output terminal of the voltage reference array is connected to the input terminal of the voltage comparator array and the FPGA, respectively. The output port of the linear drive circuit is connected to the input terminal of the voltage comparator array.

[0044] As another preferred embodiment, the adjustable reference source control circuit of the present invention includes an AD / DC_POW chip U44. Pin 1 of U44 is connected to the mains power L, pin 2 of U44 is connected to the mains power N, and pin 3 of U44 is connected to +15VA, one end of capacitor C126, the positive terminal of capacitor C127, one end of resistor R307, and the collector of NPN transistor Q17. The other end of R307 is connected to the base of Q17 and the collector of the output terminal of optocoupler OP3. The emitter of the output terminal of optocoupler OP3 is connected to the other end of capacitor C126, the negative terminal of capacitor C127, pin 4 of U44, one end of resistor R309, and GND. The emitter of Q17 is connected to the other end of resistor R309 and VRE_1 through resistor R308.

[0045] The anode of the OP3 input terminal is connected to one end of resistor R305 and one end of resistor R306. The other end of R305 is connected to the positive terminal of capacitor C123, one end of capacitor C122, and +15VA. The other end of C122 is connected to GND, the negative terminal of C123, pin 2 of TL431 chip U46, pin 3 of X9C103 chip U45, pin 4 of U45, one end of capacitor C124, and one end of capacitor C125. The other ends of C124 and C125 are connected to pin 8 of U45 and +3.3V. Pins 7, 2, and 1 of U45 are connected to J12, J14, and J15 respectively. Pin 5 of U45 is connected to pin 1 of U46 and the other end of R306. Pin 3 of U46 is connected to the cathode of the OP3 input terminal.

[0046] As another preferred embodiment, the voltage reference array of the present invention includes a resistor R10, one end of which is connected to VRE_1, and the other end of which is connected in sequence to resistors R15-R17, R25, R30-R32, R37, R42-R44, R49, R54-R56, R61, R66, R67, R68, R73, R78-80, R85, R90-92, R97, R102-104, R109, R110, R115, R116, R122, R123, R129, R130, R136, R137, R142, R143, and R144. 8. R149, R154, R155, R160, R161, R166, R167, R172, R173, R178, R179, R184, R185, R190, R191, R196, R197, R202, and R203 are connected to pin 5 of the X9C103 chip U18. Pin 3 of U18 is connected to GND, V, RE_1, pin 4 of U18, one end of capacitor C20, and one end of capacitor C21. The other end of C20 is connected to +3.3V, pin 8 of U18, and the other end of C21. Pins 7, 2, and 1 of U18 are connected to L6, K6, and J6 respectively.

[0047] As another preferred embodiment, the voltage comparator array of the present invention includes MAX9140 chips U1, U2, U3, U4, U5, U6, U7, U8, U9, U10, U11, U12, U13, U14, U15, U16, and U17. Pins 4 of U1 to U17 are respectively connected to the positive terminal of capacitor C17, one end of capacitor C18, and +5V. Pins 11 of U1 to U17 are respectively connected to the negative terminal of capacitor C17, the other end of capacitor C18, and GND.

[0048] Pins 3, 5, 12, and 10 of U1 to U17 are connected to ADC0; pin 9 of U1 to U17 is connected to V15 and V30 to V16 respectively; pin 13 of U1 to U17 is connected to V31 and V14 to V0 respectively; pin 6 of U1 to U17 is connected to V47 to V32 respectively; and pin 2 of U1 to U17 is connected to V63 to V48 respectively.

[0049] Pins 8 of U1 to U17 are connected to K2, F3, D2, D1, G5, F2, F1, G2, G1, G16, G15, F13, F16, F15, B16, and F14 respectively through 1K resistors. Pins 8 of U1 to U17 are connected to GND through 2K resistors respectively.

[0050] Pins 14 of U1 to U17 are connected to C2, K1, L2, L1, L3, N2, N1, K5, L4, R1, P2, P1, D4, E5, F5, and B1 respectively through 1K resistors. C2, K1, L2, L1, L3, N2, N1, K5, L4, R1, P2, P1, D4, E5, F5, and B1 are connected to GND through 2K resistors respectively.

[0051] Pins 7 of U1 to U17 are connected to D16, D15, G11, C16, C15, R9, T9, K9, L9, M9, N9, R10, T10, R11, T11, and R12 respectively through 1K resistors. Pins D16, D15, G11, C16, C15, R9, T9, K9, L9, M9, N9, R10, T10, R11, T11, and R12 are connected to GND through 2K resistors respectively.

[0052] Pin 1 of U1 to U17 is connected to T12, K10, L10, P9, P11, R13, T13, M10, N11, T14, T15, R14, P14, L11, M11, and N12 respectively through a 1K resistor. T12, K10, L10, P9, P11, R13, T13, M10, N11, T14, T15, R14, P14, L11, M11, and N12 are connected to GND through a 2K resistor.

[0053] As another preferred embodiment, the linear drive circuit of the present invention includes a MOSFET-N transistor Q21. The drain of Q21 is connected to the cathode of ADC0, the cathode of Zener diode ZD2, and the cathode of diode D9, respectively. The source of Q21 is connected to GND, the cathode of ZD2, one end of capacitor C16, and one end of the secondary side of current transformer T3, respectively. The other end of the secondary side of T3 is connected to one end of capacitor C15 and the anode of D9, respectively. The other end of C15 is connected to the other end of C16 and FG, respectively.

[0054] +15VA is connected to one end of capacitor C121, the positive terminal of capacitor C120, and one end of resistor R304. The other end of R304 is connected to one end of resistor R303 and the anode of the input terminal of optocoupler OP2. The cathode of the input terminal of optocoupler OP2 is connected to pin 3 of TL431 chip U43. Pin 2 of U43 is connected to GND, the other end of capacitor C121, the negative terminal of capacitor C120, pin 3 of X9C103 chip U42, pin 4 of U42, one end of capacitor C99, and one end of capacitor C98. Pin 1 of U43 is connected to the other end of resistor R303 and pin 5 of U42. Pins 1, 2, and 7 of U42 are connected to J13, J2, and J1 respectively. Pin 8 of U42 is connected to the other end of capacitor C99 and the other end of capacitor C98.

[0055] Connect L to pin 1 of AD / DC_POW chip U41. Connect pin 2 of U41 to N. Connect pin 3 of U41 to +15VA, one end of capacitor C97, the positive terminal of capacitor C96, one end of resistor R302, and the collector of NPN transistor Q16. Connect the other end of R302 to the base of Q16 and the collector of the output terminal of OP2. Connect the emitter of the output terminal of OP2 to pin 4 of U41, the other end of C97, the negative terminal of C96, one end of resistor R300, and GND. Connect the other end of R300 to Q21_G and one end of resistor R301. Connect the other end of resistor R301 to the emitter of Q16.

[0056] As another preferred embodiment, the driving circuit of the present invention includes KP103 chips U21, U28, U36, and U38. Pin 4 of U21 is connected to +15V, pin 5 of U21 is connected to GND, pin 2 of U21 is connected to one end of resistor R214 and one end of capacitor C26, and the other end of C26 is connected to the other end of R214 and +15V. Pin 3 of U21 is connected to the collector of S8050 transistor Q9, and the base of Q9 is connected to one end of resistor R222 and one end of resistor R223, the other end of R222 is connected to A3, and the other end of R223 is connected to GND and the emitter of Q9. Pin 13 of U21 is connected to an optocoupler through resistor R224. The cathode of the input terminal of U26 is connected to pin 18 of U21. The emitter of the output terminal of U26 is connected to A8, and the collector of the output terminal of U26 is connected to +3.3V. Pin 17 of U21 is connected to one end of resistor R213, one end of bidirectional Zener diode ZD4, and Q4_S. Pins 16 and 15 of U21 are connected to one end of resistor R212. The other end of R212 is connected to the other end of R213, the other end of ZD4, and Q4_B. Pin 12 of U21 is connected to the anode of diode D11 through Zener diode, and the cathode of D11 is connected to Q3_S.

[0057] Pin 4 of U28 is connected to +15V, pin 5 is connected to GND, pin 2 is connected to one end of resistor R233 and one end of capacitor C57, the other end of C57 is connected to the other end of R233 and +15V, pin 3 of U28 is connected to the collector of S8050 transistor Q12, the base of Q12 is connected to one end of resistor R238 and one end of resistor R239, the other end of R238 is connected to B3, the other end of R239 is connected to GND and the emitter of Q12, pin 13 of U28 is connected to optocoupler U through resistor R240. The cathode of U32 input terminal is connected to pin 18 of U28. The emitter of U32 output terminal is connected to B8, and the collector of U32 output terminal is connected to +3.3V. Pin 17 of U28 is connected to one end of resistor R232, one end of bidirectional Zener diode ZD6, and Q5_S. Pins 16 and 15 of U28 are connected to one end of resistor R230. The other end of R230 is connected to the other end of R232, the other end of ZD6, and Q5_B. Pin 12 of U28 is connected to the anode of diode D13 through Zener diode, and the cathode of D13 is connected to Q3_S.

[0058] Pin 4 of U36 is connected to +15V, pin 5 is connected to GND, pin 2 is connected to one end of resistor R246 and one end of capacitor C64, the other end of C64 is connected to the other end of R246 and +15V, pin 3 of U36 is connected to the collector of S8050 transistor Q13, the base of Q13 is connected to one end of resistor R248 and one end of resistor R247, the other end of R247 is connected to C3, the other end of R248 is connected to GND and the emitter of Q13, pin 13 of U36 is connected to optocoupler U through resistor R249. The cathode of U37 input terminal is connected to pin 18 of U36. The emitter of U37 output terminal is connected to C8, and the collector of U37 output terminal is connected to +3.3V. Pin 17 of U36 is connected to one end of resistor R245, one end of bidirectional Zener diode ZD7, and PGND. Pins 16 and 15 of U36 are connected to one end of resistor R244. The other end of R244 is connected to the other end of R245, the other end of ZD7, and Q6_B. Pin 12 of U36 is connected to the anode of diode D14 through Zener diode, and the cathode of D14 is connected to Q4_S.

[0059] Pin 4 of U38 is connected to +15V, pin 5 is connected to GND, pin 2 is connected to one end of resistor R261 and one end of capacitor C87, the other end of C87 is connected to the other end of R261 and +15V, pin 3 of U38 is connected to the collector of S8050 transistor Q14, the base of Q14 is connected to one end of resistor R265 and one end of resistor R266, the other end of R265 is connected to D3, the other end of R266 is connected to GND and the emitter of Q14, pin 13 of U38 is connected to optocoupler U through resistor R267. The cathode of U40 input terminal is connected to pin 18 of U38. The emitter of U40 output terminal is connected to D8, and the collector of U40 output terminal is connected to +3.3V. Pin 17 of U38 is connected to one end of resistor R260, one end of bidirectional Zener diode ZD8, and PGND. Pins 16 and 15 of U38 are connected to one end of resistor R259. The other end of R259 is connected to the other end of R260, the other end of ZD8, and Q7_B. Pin 12 of U38 is connected to the anode of diode D15 through Zener diode, and the cathode of D15 is connected to Q5_S.

[0060] As another preferred embodiment, the driving circuit of the present invention includes KP103 chips U20 and U27. Pin 4 of U20 is connected to +15V, pin 5 of U20 is connected to GND, pin 2 of U20 is connected to one end of resistor R211 and one end of capacitor C25, and the other end of C25 is connected to the other end of R211 and +15V. Pin 3 of U20 is connected to the collector of S8050 transistor Q8. The base of Q8 is connected to one end of resistor R217 and one end of resistor R218, the other end of R217 is connected to U33_PA6, and the other end of R218 is connected to GND and the emitter of Q8. Pin 13 of U20 is connected to the cathode of the input terminal of optocoupler U25 through resistor R219. The anode of the input terminal of U25 is connected to pin 18 of U20. The emitter of the output terminal of U25 is connected to U33_PA7. The collector of the output terminal of U25 is connected to +3.3V. Pin 17 of U20 is connected to one end of resistor R210, one end of bidirectional Zener diode ZD3, and Q2_S. Pins 16 and 15 of U20 are connected to one end of resistor R209. The other end of R209 is connected to the other end of R210, the other end of ZD3, and Q2_B. Pin 12 of U20 is connected to the anode of diode D10 through Zener diode. The cathode of D10 is connected to Q2_D.

[0061] Pin 4 of U27 is connected to +15V, pin 5 is connected to GND, pin 2 is connected to one end of resistor R229 and one end of capacitor C54, the other end of C54 is connected to the other end of R229 and +15V, pin 3 of U27 is connected to the collector of S8050 transistor Q11, the base of Q11 is connected to one end of resistor R234 and one end of resistor R235, the other end of R234 is connected to U33_PA4, the other end of R235 is connected to GND and the emitter of Q11, pin 13 of U27 is connected to optocoupler U through resistor R236. The cathode of U31 input terminal is connected to pin 18 of U27. The emitter of U31 output terminal is connected to U33_PA5. The collector of U31 output terminal is connected to +3.3V. Pin 17 of U27 is connected to one end of resistor R228, one end of bidirectional Zener diode ZD5, and Q1_S. Pins 16 and 15 of U27 are connected to one end of resistor R225. The other end of R225 is connected to the other end of R228, the other end of ZD5, and Q1_B. Pin 12 of U27 is connected to the anode of diode D12 through Zener diode. The cathode of D12 is connected to Q1_D.

[0062] Pin 12 of STM32F030F4 chip U33 is connected to U33_PA6, pin 13 of STM32F030F4 chip U33 is connected to U33_PA7, pin 10 of STM32F030F4 chip U33 is connected to U33_PA4, and pin 11 of STM32F030F4 chip U33 is connected to U33_PA5;

[0063] Pin 1 of U33 is connected to GND through resistor R250. Pin 1 of the four-pin connector P5 is connected to +3.3V and one end of capacitor C90. The other end of C90 is connected to GND and pin 4 of P5. Pins 2 and 3 of P5 are connected to pins 19 and 20 of U33 respectively.

[0064] Capacitors C100 to C104 are connected in parallel between +3.3V and GND.

[0065] As another preferred embodiment, the driving circuit of the present invention includes an X9C103 chip U24. Pin 5 of U24 is connected to one end of resistor R208 and pin 1 of TL431 chip U23. The other end of R208 is connected to one end of resistor R207 and the anode of the input terminal of optocoupler OP1. The cathode of the input terminal of OP1 is connected to pin 3 of U23. Pin 2 of U23 is connected to GND, the negative terminal of capacitor C27 and capacitor C28, pin 3 of U24, pin 2 of U23, pin 4 of U24, one end of capacitor C29, and one end of capacitor C30. Pin 8 of U24 is connected to +3.3V, the other end of capacitor C29, and the other end of capacitor C30. Pins 1, 2, and 7 of U24 are connected to U34_PA4, U34_PA5, and U34_PA6 respectively. +15V is connected to the other end of C27, the other end of C28, and the other end of R207.

[0066] Pin 1 of the AD / DC_POW chip U29 is connected to the AC power L, pin 2 of U29 is connected to the AC power N, pin 3 of U29 is connected to +15V, one end of capacitor C59, the positive terminal of capacitor C60, one end of resistor R231, and the collector of NPN transistor Q10. The other end of R231 is connected to the base of Q10 and the collector of the output terminal of OP1. The emitter of the output terminal of OP1 is connected to pin 4 of U29, the other end of C59, the negative terminal of C60, one end of resistor R237, and Q3_S. The other end of R237 is connected to Q3_B and one end of resistor R226. The other end of R226 is connected to the emitter of Q10.

[0067] Pins 10, 11, and 12 of the STM32F030F4 chip U34 are connected to U34_PA4, U34_PA5, and U34_PA6 respectively. Pin 1 of U34 is connected to GND through resistor R251. The four corner connectors are plugged into pin 1 of P6 and connected to +3.3V and one end of capacitor C91 respectively. The other end of C91 is connected to pin 4 of P6 and GND respectively. Pins 2 and 3 of P6 are connected to U34_TMS and U34_TCK respectively.

[0068] Capacitors C105 to C109 are connected in parallel between +3.3V and GND.

[0069] As another preferred embodiment, the present invention further includes an input AC zero-crossing capture circuit, which includes a second secondary side of transformer T1. One end of the second secondary side of T1 is connected to the anode of the input terminal of optocoupler U49 through diode D3 and resistor R1 in sequence. The cathode of the input terminal of U49 is connected to the center tap of the second secondary side of T1 and the cathode of the input terminal of optocoupler U50 in sequence. The anode of the input terminal of U50 is connected to the other end of the second secondary side of T1 through resistor R255 and diode D4 in sequence.

[0070] The collector of the output terminal of U49 is connected to +3.3V, the emitter of the output terminal of U49 is connected to U33_PB1, the emitter of the output terminal of U50 is connected to U33_PB2, and the collector of the output terminal of U50 is connected to +3.3V.

[0071] As another preferred embodiment, the first listening section of the RS485 bus in this invention includes an SP3485 chip U39. Pin 1 of U39 is connected to U33_PA3, pins 2 and 3 of U39 are connected to U33_PA1, pin 4 of U39 is connected to U33_PA2, pins 5 to 8 of U39 are connected to GND, A, B, and +3.3V respectively, two ends of resistor R263 are connected to B and GND respectively, and two ends of resistor R264 are connected to A and +3.3V respectively.

[0072] As another preferred embodiment, the second monitoring section of the RS485 bus in this invention includes an SP3485 chip U35, pin 1 of U35 is connected to U34_PA3, pins 2 and 3 of U35 are connected to U34_PA1, pin 4 of U35 is connected to U34_PA2, and pins 5, 6, 7 and 8 of U35 are respectively connected to GND, A, B and +3.3V;

[0073] Resistor R242 is connected to B and GND respectively, and resistor R243 is connected to A and +3.3V respectively.

[0074] As another preferred embodiment, the present invention also includes a voltage sensor circuit, which includes an HBV10A3.3 chip VP1. Pin 1 of VP1 is connected to Q3_S in sequence through resistors R216 and R215. Pin 2 of VP1 is connected to PGND in sequence through resistors R221 and R220. Pins 4, 5, and 6 of VP1 are connected to U43_PA7, GND, and +3.3V respectively.

[0075] One end of resistor R227 is connected to one end of U34_PA7 and one end of capacitor C58, and the other end of R227 is connected to GND and the other end of C58.

[0076] The beneficial effects of this invention.

[0077] This invention is a single-phase power supply circuit for induction heating; at the same time, through the cooperation of various parts, the performance and functionality of the induction heating power supply are improved. Attached Figure Description

[0078] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. The scope of protection of the present invention is not limited to the following description.

[0079] Figure 1 , 2 This is the schematic diagram of the power main circuit of the present invention.

[0080] Figures 3-10 Figure 17 is a schematic diagram of the first monitoring part of the RS485 bus, the second monitoring part of the RS485 bus, the voltage sensor circuit, and the driving circuit of the present invention.

[0081] Figures 11-13 This is the schematic diagram of the main processor circuit of this invention.

[0082] Figures 14-16 This is a schematic diagram of the current acquisition circuit of this invention.

[0083] Figures 18-23 This is the FPGA circuit schematic diagram of the present invention. Detailed Implementation

[0084] As shown in the figure, the present invention includes a main processor, an FPGA, a power main circuit, a current acquisition section, an RS485 bus first monitoring section, an RS485 bus second monitoring section, and a driving circuit. The control signal input port of the driving circuit is connected to the control signal output port of the main processor, the signal transmission port of the driving circuit is connected to the signal transmission port of the FPGA, and the control signal output port of the driving circuit is connected to the control signal input port of the power main circuit.

[0085] The signal transmission port of the current acquisition section is connected to the signal transmission port of the FPGA.

[0086] The signal input port of the first listening section of the RS485 bus is connected to the signal output port of the driver circuit.

[0087] The signal input port of the second monitoring section of the RS485 bus is connected to the signal output port of the driver circuit.

[0088] The power input terminal of the main power circuit is connected to single-phase mains power.

[0089] The main processor uses an STM32H743IIT6 ARM processor U5. Pins 158, 148, 135, 126, 113, 102, 90, 71, 61, 22, and 14 of U5 are grounded, and pins 172, 159, 149, 136, 127, 114, 103, 91, 82, 72, 62, 49, 36, 23, and 15 of U5 are connected to +3.3V.

[0090] Pin 1 of the MPM-20-12 chip U55 is connected to pin 2 of the UU9.8 common mode inductor L5. Pin 1 of L5 is connected to one end of the rheostat R299 and one end of the fuse F1. The other end of F1 is connected to L. The other end of R299 is connected to N and pin 3 of L5. Pin 4 of L5 is connected to pin 2 of U55. Pin 3 of U55 is connected to one end of capacitor C203, the positive terminal of capacitor C204, and +12V. The other end of C203 is connected to pin 4 of U55, the negative terminal of C204, and GND.

[0091] One end of resistor R2 is connected to U5_BOOT0, and the other end of R2 is connected to GND;

[0092] Pin 1 of SP3485 chip U60 is connected to U5_PA3, pins 2 and 3 of U60 are connected to U5_PA1, pin 4 of U60 is connected to U5_PA2, pins 5 to 8 of U60 are connected to GND, A, B (A and B are internal RS485 buses used to connect FPGA and processor; the main processor U5 controls other microprocessors and FPGA to work together via RS485), and +3.3V respectively. Resistor R290 is connected to B and GND respectively, and resistor R291 is connected to A and +3.3V respectively.

[0093] Pin 1 of SP3485 chip U64 is connected to U5_PA10, pins 2 and 3 of U64 are connected to U5_PA8, pin 4 of U64 is connected to U5_PA92, and pins 5, 6, 7, and 8 of U64 are connected to GND, A, B, and +3.3V respectively. Resistor R292 is connected to B and GND respectively, and resistor R293 is connected to A and +3.3V respectively. Thermocouples are used to measure the temperature of the workpiece to be processed. Based on the thermocouple feedback value, when the temperature is too high, U33 is controlled through the RS485 internal bus to control the conduction time of Q1 and Q2, thereby reducing the input voltage and thus reducing the overall heating power and reducing the temperature rise of the workpiece, and vice versa.

[0094] Pin 1 of SP3485 chip U63 is connected to U5_PA10, pins 2 and 3 of U63 are connected to U5_PA8, pin 4 of U63 is connected to U5_PA9, pins 5, 6, 7, and 8 of U63 are connected to GND, A, B, and +3.3V respectively, resistor R294 is connected to B and GND respectively, and resistor R295 is connected to A and +3.3V respectively.

[0095] Capacitors C85 and C69 to C82 are connected in parallel between +3.3V and GND;

[0096] +3.3V is connected to RESET, one end of capacitor C84, and one end of switch SW1 through resistor R24. The other end of C84 is connected to GND and the other end of SW1.

[0097] Pin 1 of the SD8942 / A6166 chip U19 is connected to pin 6 of U19 and one end of inductor L3 via capacitor C19. The other end of L3 is connected to +5V and one end of resistor R206. The other end of R206 is connected to one end of resistor R205 and pin 3 of U19. The other end of R205 is connected to GND and pin 2 of U19. Pin 4 of U19 is connected to pin 5 of U19, +12V, one end of capacitor C22, one end of capacitor C23, and one end of capacitor C24 via resistor R204. The other end of C22 is connected to the other end of C23, the other end of C24, and GND.

[0098] Pin 1 of the 4-pin connector P3 is connected to GND. Pin 3 of P3 is connected to U5_JTMS and one end of resistor R19. The other end of R19 is connected to +3.3V. Pin 2 of P3 is connected to U5_JTCK and one end of resistor R22. The other end of R22 is connected to GND. Pin 1 of P3 is connected to GND.

[0099] Pin 4 of crystal oscillator Y1 is connected to GND. Pin 1 of Y1 is connected to U5_OSC_OUT and one end of capacitor C67. The other end of C67 is connected to GND, pin 2 of Y1, and one end of capacitor C68. The other end of C68 is connected to pin 3 of Y1 and U5_OSC_IN.

[0100] One end of crystal oscillator Y2 is connected to one end of capacitor C66 and U5_OSC32_IN respectively. The other end of C66 is connected to GND and one end of capacitor C83 respectively. The other end of C83 is connected to the other end of Y2 and U5_OSC32_OUT respectively.

[0101] Pin 171 of U5 is connected to pin 37 of U5, one end of capacitor C43, one end of capacitor C44, and GND through resistor R5. The other end of C43 is connected to pin 39 of U5, the other end of C44, and one end of resistor R4. The other end of R4 is connected to +3.3V.

[0102] Pin 125 of U5 is connected to GND and one end of capacitor C39 via capacitor C41. The other end of C39 is connected to pin 81 of U5.

[0103] Pin 38 of U5 is connected to +3.3V and one end of capacitor C40, while the other end of C40 is connected to GND.

[0104] Pin 6 of U5 is connected to +3.3V and one end of capacitor C36. The other end of C36 is connected to GND and one end of resistor R8. The other end of R8 is connected to pin 48 of U5.

[0105] Connect pin 166 of U5 to U5_BOOT0;

[0106] Connect pin 31 of U5 to RESET.

[0107] The FPGA uses the EP4CE10F17C8 chip U22. Pins H7-10, J7-10, B2, B15, C5, C12, D7, D10, E4, and E13 are connected to GND, and pins G4, G13, K4, K13, M4, M13, N7, N10, P5, P12, R2, R15, E2, H16, and H15 of U22 are connected to GND.

[0108] The Vin pin of VR1 of the HT7550-1 chip is connected to capacitors C31, C32, C53, and +5V. The other end of C31 is connected to GND, the other end of C32, the other end of C53, the GND pin of VR1, one end of capacitors C33-38, one end of capacitor C42, and one end of capacitors C45-49. The other end of capacitor C33 is connected to the Vout pin of VR1, the other end of C34-38, the other end of capacitor C42, the other end of capacitors C45-49, and +3.3V.

[0109] The Vin pin of VR2 of the HT7550-1 chip is connected to one end of capacitor C50, one end of capacitor C51, one end of capacitor C55, and +3.3V. The other end of C50 is connected to GND, the other end of capacitor C51, the other end of capacitor C55, the GND pin of VR2, the negative terminal of capacitor C52, and one end of capacitor C56. The positive terminal of C52 is connected to the Vout pin of VR2, the other end of C56, and +1.2V.

[0110] The Vin pin of VR3 of the HT7550-1 chip is connected to one end of capacitors C61-63 and +5V. The other end of C61-63 is connected to GND, the GND pin of VR3, the negative terminal of capacitor C65, one end of capacitor C86, one end of capacitor C88, one end of capacitor C89, and one end of capacitor C93. The positive terminal of C65 is connected to the Vout pin of VR3, the other end of capacitor C86, the other end of capacitor C88, the other end of capacitor C89, the other end of capacitor C93, and +2.5V.

[0111] Pin 1 of SP3485 chip U65 is connected to B4, pins 2 and 3 of U65 are connected to D5, and pin 4 of U65 is connected to D6. Pins 5, 6, 7, and 8 of U65 are connected to GND, A, B, and +3.3V respectively. Resistor R275 is connected to B and GND respectively, and resistor R2765 is connected to A and +3.3V respectively.

[0112] Connect U22's L5 pin to +2.5V, U22's N4 pin to +1.2V, U22's F12 pin to +2.5V, U22's D13 pin to +1.2V, and U22's E12 and M5 pins to GND.

[0113] Pin H4 of U22 is connected to +2.5V, one end of resistor R131, and pin H12 of U22 via resistor R121. Pin H3 of U22 is connected to GND via resistor R128, and the other end of R131 is connected to pin J5 of U22.

[0114] Pin H13 of U22 is connected to pin G12 of U22, GND, and one end of resistor R241. The other end of R241 is connected to pin J3 of U22.

[0115] Pin H14 of U22 is connected to +3.3V through resistor R252, pin H5 of U22 is connected to +3.3V through resistor R253, and pin F4 of U22 is connected to +3.3V through resistor R254.

[0116] For the JTAG-10 FPGA interface, pins 2 and 10 of JTAG1 are connected to GND, and pin 4 of JTAG1 is connected to +2.5V.

[0117] Pins E3, G3, K3, M3, P4, P7, T1, P10, P13, T16, K14, M14, E14, G14, A16, C10, C13, A1, C4, and C7 of U22 are connected to +3.3V, and pins G6 to G10, H6, H11, and K7 of U22 are connected to +1.2V.

[0118] Connect pin 2 of crystal oscillator XTAL1 to GND, pin 3 of XTAL1 to CLK_1, and pin 4 of XTAL1 to +3.3V.

[0119] Pins 6, 5, 2, and 8 of the M25P16 chip U30 are connected to EPCS_CLK, EPCS_ASDO, EPCS_DATA0, and +3.3V respectively. Pin 4 of U30 is connected to GND, pins 3 and 7 of U30 are connected to +3.3V, and pin 1 of U30 is connected to EPCS_CS.

[0120] The main power circuit includes an air switch K1. One end of K1 is connected to the mains power, and the other end of K1 is connected to the primary side of transformer T1. One end of the first secondary side of T1 is connected to the cathode of diode D1, the drain of IGBT Q2, and Q2_D. The anode of D1 is connected to the source of IGBT Q1 and Q1_S. The gate of Q1 is connected to Q1_B. The drain of Q1 is connected to Q1_D, the cathode of diode D2, and pin 1 of common mode inductor L2. The anode of D2 is connected to the source of Q2 and Q2_S. The gate of Q2 is connected to Q2_B. Pin 3 of L2 is connected to the other end of the first secondary side of T1.

[0121] Pin 2 of L2 is connected to the anode of diode D5 and the cathode of diode D7, respectively. The cathode of D5 is connected to the cathode of diode D6 and one end of inductor L1, respectively. The other end of L1 is connected to one end of capacitor C6 and the collector of NPN transistor Q3, respectively. The base of Q3 is connected to Q3_B, and the emitter of Q3 is connected to Q3_S, one end of capacitors C1-C4, the drain of IGBT Q4, and the drain of IGBT Q5, respectively. The other ends of C1-C4 are connected to one end of capacitors C9-C12, the source of Q4, Q4_S, the drain of IGBT Q6, and one end of the primary winding of main transformer T2, respectively. The other end of the primary winding of T2 is connected to one end of capacitors C7, C8, C13, C14, and C5, respectively. The other ends of capacitors C7, C8, C13, C14, and C5 are connected to Q5_S, the source of Q5, and the IGBT, respectively. The drain of Q7 is connected to the source of Q7, which is connected to PGND, the source of Q6, the other end of capacitors C9-C12, the other end of C6, the anode of D7, and the anode of diode D8. The cathode of D8 is connected to pin 4 of L2 and the anode of D6.

[0122] One end of the first secondary side of T2 is connected to one end of capacitors C110 to C115 respectively. The other end of C110 to C115 is connected to pin 1 of the two-pin connector P8. Pin 2 of P8 is connected to the other end of the first secondary side of T2 through the primary side of current transformer T3.

[0123] Q4, Q5, Q6, and Q7 can use the FZ800R33KF2C model IGBT.

[0124] The circuit consisting of D1, Q1, D2, Q2 and U33 in the figure forms a step-down power control circuit, which can flexibly turn on at the zero-crossing point of each AC cycle and turn off before reaching or approaching 90°. It can also turn on again after exceeding 90° and before 180°, which greatly reduces the current impact on the highest potential point of the power grid and greatly improves the power factor of the equipment.

[0125] As shown in the figure, the T1B winding is 35T and the T1A winding is 165T, which boosts the single-phase 220V AC power to 1100V.

[0126] The circuit has a large-capacity filter capacitor at its input. Due to the capacitor's characteristics, it is nearly short-circuited at power-on, resulting in a huge current surge to the front-end rectifier bridge, potentially even causing it to break down. In this invention, a high-power NPN transistor Q3 is installed between the rectifier bridge and the input filter capacitor. Before power-on, the transistor operates in the cutoff region; at this time, the rectifier bridge current is 0. After the system powers on, the microprocessor detects the voltage across the capacitor.

[0127] Upon initial power-up, all microprocessors are powered by AC220V to DC15V, and all microprocessors start operating before the main circuit. Once the U5 system successfully completes its self-test, it communicates with other slave microprocessors on the RS485 bus to acquire data. After other microprocessors have started, they send data to the U34 microprocessor, initiating the main circuit startup state. The U34, through the VP1 voltage sensor, detects that the voltage across Q3_S to PGND is below 30V (the voltage across Q3_S to PGND is the voltage across the filter capacitors C1, C2, C3, C4, C9, C10, C11, and C12). It determines that surge protection is necessary and controls Q3 to operate in the amplification region (Q3 is connected in series with the filter capacitor group). In the amplification region, Q3's IB current limits the charging current to the capacitor group, thus preventing surge damage to the front-end circuit.

[0128] The control function for the IB current is:

[0129] if(VP1<(220*1.414) / 0.75){IB = 0.67mA}else{IB = 1.5A};

[0130] The driver circuit controls transistor Q3 to slowly transition from the cutoff region to the amplification region. Because the transistor operates in the amplification region, the rectifier bridge current is always limited to a safe range. After the filter capacitor voltage slowly rises to 75% of its rated voltage, the surge protector transistor Q3 enters the amplification region, completing the surge protection function. Because its surge protection operation is very brief, and the H-bridge resonant circuit (Q4-Q7) does not operate while the surge protection is in progress, its heat dissipation device experiences no temperature rise. Therefore, the high-power transistor Q3 shares the same heatsink as the H-bridge IGBT, eliminating the need to increase the original heatsink size.

[0131] The current acquisition section includes an adjustable reference source control circuit, a linear drive circuit, a voltage reference array, and a voltage comparator array. The output port of the adjustable reference source control circuit is connected to the input port of the voltage reference array. The output of the voltage reference array is connected to the input of the voltage comparator array and the FPGA, respectively. The output port of the linear drive circuit is connected to the input of the voltage comparator array.

[0132] The adjustable reference source control circuit includes an AD / DC_POW chip U44. Pin 1 of U44 is connected to the mains power L, pin 2 of U44 is connected to the mains power N, and pin 3 of U44 is connected to +15VA, one end of capacitor C126, the positive terminal of capacitor C127, one end of resistor R307, and the collector of NPN transistor Q17. The other end of R307 is connected to the base of Q17 and the collector of the output terminal of optocoupler OP3. The emitter of the output terminal of optocoupler OP3 is connected to the other end of capacitor C126, the negative terminal of capacitor C127, pin 4 of U44, one end of resistor R309, and GND. The emitter of Q17 is connected to the other end of resistor R309 and VRE_1 through resistor R308.

[0133] The anode of the OP3 input terminal is connected to one end of resistor R305 and one end of resistor R306. The other end of R305 is connected to the positive terminal of capacitor C123, one end of capacitor C122, and +15VA. The other end of C122 is connected to GND, the negative terminal of C123, pin 2 of TL431 chip U46, pin 3 of X9C103 chip U45, pin 4 of U45, one end of capacitor C124, and one end of capacitor C125. The other ends of C124 and C125 are connected to pin 8 of U45 and +3.3V. Pins 7, 2, and 1 of U45 are connected to J12, J14, and J15 respectively. Pin 5 of U45 is connected to pin 1 of U46 and the other end of R306. Pin 3 of U46 is connected to the cathode of the OP3 input terminal.

[0134] The voltage reference array includes resistor R10, one end of which is connected to VRE_1, and the other end of which is connected in sequence to resistors R15-R17, R25, R30-R32, R37, R42-R44, R49, R54-R56, R61, R66, R67, R68, R73, R78-80, R85, R90-92, R97, R102-104, R109, R110, R115, R116, R122, R123, R129, R130, R136, R137, R142, R143, R148, and R149. R154, R155, R160, R161, R166, R167, R172, R173, R178, R179, R184, R185, R190, R191, R196, R197, R202, and R203 are connected to pin 5 of the X9C103 chip U18. Pin 3 of U18 is connected to GND, V, RE_1, pin 4 of U18, one end of capacitor C20, and one end of capacitor C21. The other end of C20 is connected to +3.3V, pin 8 of U18, and the other end of C21. Pins 7, 2, and 1 of U18 are connected to L6, K6, and J6 respectively.

[0135] The voltage comparator array includes MAX9140 chips U1, U2, U3, U4, U5, U6, U7, U8, U9, U10, U11, U12, U13, U14, U15, U16, and U17. Pins 4 of U1 to U17 are connected to the positive terminal of capacitor C17, one end of capacitor C18, and +5V, respectively. Pin 11 of U1 to U17 is connected to the negative terminal of capacitor C17, the other end of capacitor C18, and GND, respectively.

[0136] Pins 3, 5, 12, and 10 of U1 to U17 are connected to ADC0; pin 9 of U1 to U17 is connected to V15 and V30 to V16 respectively; pin 13 of U1 to U17 is connected to V31 and V14 to V0 respectively; pin 6 of U1 to U17 is connected to V47 to V32 respectively; and pin 2 of U1 to U17 is connected to V63 to V48 respectively.

[0137] Pins 8 of U1 to U17 are connected to K2, F3, D2, D1, G5, F2, F1, G2, G1, G16, G15, F13, F16, F15, B16, and F14 respectively through 1K resistors. Pins 8 of U1 to U17 are connected to GND through 2K resistors respectively.

[0138] Pins 14 of U1 to U17 are connected to C2, K1, L2, L1, L3, N2, N1, K5, L4, R1, P2, P1, D4, E5, F5, and B1 respectively through 1K resistors. C2, K1, L2, L1, L3, N2, N1, K5, L4, R1, P2, P1, D4, E5, F5, and B1 are connected to GND through 2K resistors respectively.

[0139] Pins 7 of U1 to U17 are connected to D16, D15, G11, C16, C15, R9, T9, K9, L9, M9, N9, R10, T10, R11, T11, and R12 respectively through 1K resistors. Pins D16, D15, G11, C16, C15, R9, T9, K9, L9, M9, N9, R10, T10, R11, T11, and R12 are connected to GND through 2K resistors respectively.

[0140] Pin 1 of U1 to U17 is connected to T12, K10, L10, P9, P11, R13, T13, M10, N11, T14, T15, R14, P14, L11, M11, and N12 respectively through a 1K resistor. T12, K10, L10, P9, P11, R13, T13, M10, N11, T14, T15, R14, P14, L11, M11, and N12 are connected to GND through a 2K resistor.

[0141] The linear drive circuit includes a MOSFET-N transistor Q21. The drain of Q21 is connected to ADC0, the cathode of Zener diode ZD2, and the cathode of diode D9. The source of Q21 is connected to GND, the cathode of ZD2, one end of capacitor C16, and one end of the secondary side of current transformer T3. The other end of the secondary side of T3 is connected to one end of capacitor C15 and the anode of D9. The other end of C15 is connected to the other end of C16 and FG.

[0142] +15VA is connected to one end of capacitor C121, the positive terminal of capacitor C120, and one end of resistor R304. The other end of R304 is connected to one end of resistor R303 and the anode of the input terminal of optocoupler OP2. The cathode of the input terminal of optocoupler OP2 is connected to pin 3 of TL431 chip U43. Pin 2 of U43 is connected to GND, the other end of capacitor C121, the negative terminal of capacitor C120, pin 3 of X9C103 chip U42, pin 4 of U42, one end of capacitor C99, and one end of capacitor C98. Pin 1 of U43 is connected to the other end of resistor R303 and pin 5 of U42. Pins 1, 2, and 7 of U42 are connected to J13, J2, and J1 respectively. Pin 8 of U42 is connected to the other end of capacitor C99 and the other end of capacitor C98.

[0143] Connect L to pin 1 of AD / DC_POW chip U41. Connect pin 2 of U41 to N. Connect pin 3 of U41 to +15VA, one end of capacitor C97, the positive terminal of capacitor C96, one end of resistor R302, and the collector of NPN transistor Q16. Connect the other end of R302 to the base of Q16 and the collector of the output terminal of OP2. Connect the emitter of the output terminal of OP2 to pin 4 of U41, the other end of C97, the negative terminal of C96, one end of resistor R300, and GND. Connect the other end of R300 to Q21_G and one end of resistor R301. Connect the other end of resistor R301 to the emitter of Q16.

[0144] The output current, which is the induction heating load current, is acquired using a T3A electromagnetic inductance current sensor. This invention achieves high-speed acquisition of the output current through a reference array circuit, a voltage comparator array circuit, a low-level variable reference voltage circuit, and an FPGA circuit. The high-speed conversion rate of the electromagnetic inductance current sensor circuit proportionally converts the output current into a voltage signal, and the complete restoration of the actual current waveform and true RMS current value is then provided to the main processor U5.

[0145] After U5 boots normally, configure its peripherals. Connect to the RS485 internal bus via U63, establish a communication connection with microprocessor U33 via U39 to obtain U33's boot status. Establish a communication connection with microprocessor U34 via U35 to obtain U34's boot status. Obtain the boot status of U22 Field Programmable Gate Array (FPGA) via U65.

[0146] U5 controls U33 to enter 50% voltage regulation mode via the internal RS485 bus, and controls U34 to start surge protection. U5 communicates with U34 to confirm the end of surge protection startup. U5 establishes communication with U65 and U22 (FPGA) via the internal RS485 bus, and outputs four H-bridge drive signals through U22; drives the H-bridge circuit (Q4, Q5, Q6, Q7) through the isolated IGBT driver chips U21, U28, U36, and U38; and performs frequency sweep. After receiving the information that U22 has completed the frequency sweep via the internal RS485 bus, U5 controls U33 to enter 100% voltage regulation mode via the RS485 bus for full power output.

[0147] During the control cycle, U5 obtains the temperature value measured by the external thermocouple via U64; and controls the output power by adjusting the voltage value of the self-tuning PID control U33 to ensure that the temperature of the heated workpiece conforms to the set constant temperature. U22 fine-tunes the operating frequency of the H-bridge to ensure that the entire machine always operates at the resonant point with the heated workpiece. If a suitable resonant point is not found during the fine-tuning process (e.g., the workpiece reaches the Curie temperature), U22 will re-sweep from the lowest frequency supported by the equipment to the highest frequency to find a new resonant point and continue operating at the new resonant point.

[0148] The current acquisition section of this invention includes a 64-bit voltage divider circuit consisting of 63 voltage divider resistors and one digitally adjustable resistor; and a voltage comparator array consisting of 64 ultra-high-speed voltage comparators.

[0149] In this invention, Q21 operates in the variable resistance region as a current-to-voltage circuit. Using the electromagnetic inductance current sensor T3, and applying the formula N1:N2=V1:V2=1 / A1:1 / A2, the output current at terminal T3B of the inductance current sensor is 1 / 5000 of that at terminal T3A. According to Ohm's law U=I*R, since Q21 operates in the variable resistance region controlled by U22, its resistance value can be dynamically changed. The current at T3B is moderate and within the sensitive range of its downstream sampling array.

[0150] The current is collected, passes through a current transformer, is rectified by a resistor converter, and then converted into a voltage signal at the output terminal.

[0151] A current signal, proportionally scaled down to the output current, is obtained through a current transformer. This current signal is converted into a voltage signal by a Q21 MOSFET operating in the variable resistance region. The voltage signal is then applied to the non-inverting input of a 64-bit voltage comparator via a voltage reference array consisting of a bottom-level variable reference source and 63-bit voltage divider resistors. The comparator's output is connected to an FPGA. The resistance of Q21 in the variable resistance region is controlled by the FPGA through a linear drive circuit, and the resistance of the bottom-level reference source in the voltage divider array is driven by the FPGA.

[0152] In a mutual inductance current sensor, the voltage value of VER_1 is proportionally increased by its resistance to ground; that is, the higher the resistance, the higher the voltage, and vice versa. When the measured current is large, the equivalent resistance of the variable resistor in the Q21 field-effect transistor can be reduced to within the sensitive range of the downstream acquisition circuit by adjusting the Q21 field-effect transistor. Similarly, if the measured current is small, the equivalent resistance of the variable resistor region in the Q21 field-effect transistor can be increased to within the sensitive range of the downstream acquisition circuit by adjusting the Q21 field-effect transistor to obtain the best acquisition accuracy. The function of the bottom variable reference of the resistor divider array is to adjust the voltage reference of the bottom layer to the minimum value of the required measurement range when high-precision measurement is required for a certain range of the current value. This serves as the threshold for starting the detection range, and the remaining range is used as the 63-bit high-resolution detection range. For example, when measuring a 50A high-frequency current, the measurement range can be determined to be between 45A and 55A by adjusting the bottom variable reference and the inverting input reference of the voltage comparator array, thereby improving the accuracy of the detected current value.

[0153] The driver circuit includes KP103 chips U21, U28, U36, and U38. Pin 4 of U21 is connected to +15V, pin 5 is connected to GND, and pin 2 is connected to one end of resistor R214 and one end of capacitor C26. The other end of C26 is connected to the other end of R214 and +15V. Pin 3 of U21 is connected to the collector of S8050 transistor Q9. The base of Q9 is connected to one end of resistor R222 and one end of resistor R223. The other end of R222 is connected to A3, and the other end of R223 is connected to GND and the emitter of Q9. Pin 13 of U21 is connected to an optocoupler through resistor R224. The cathode of the input terminal of U26 is connected to pin 18 of U21. The emitter of the output terminal of U26 is connected to A8, and the collector of the output terminal of U26 is connected to +3.3V. Pin 17 of U21 is connected to one end of resistor R213, one end of bidirectional Zener diode ZD4, and Q4_S. Pins 16 and 15 of U21 are connected to one end of resistor R212. The other end of R212 is connected to the other end of R213, the other end of ZD4, and Q4_B. Pin 12 of U21 is connected to the anode of diode D11 through Zener diode, and the cathode of D11 is connected to Q3_S.

[0154] Pin 4 of U28 is connected to +15V, pin 5 is connected to GND, pin 2 is connected to one end of resistor R233 and one end of capacitor C57, the other end of C57 is connected to the other end of R233 and +15V, pin 3 of U28 is connected to the collector of S8050 transistor Q12, the base of Q12 is connected to one end of resistor R238 and one end of resistor R239, the other end of R238 is connected to B3, the other end of R239 is connected to GND and the emitter of Q12, pin 13 of U28 is connected to optocoupler U through resistor R240. The cathode of U32 input terminal is connected to pin 18 of U28. The emitter of U32 output terminal is connected to B8, and the collector of U32 output terminal is connected to +3.3V. Pin 17 of U28 is connected to one end of resistor R232, one end of bidirectional Zener diode ZD6, and Q5_S. Pins 16 and 15 of U28 are connected to one end of resistor R230. The other end of R230 is connected to the other end of R232, the other end of ZD6, and Q5_B. Pin 12 of U28 is connected to the anode of diode D13 through Zener diode, and the cathode of D13 is connected to Q3_S.

[0155] Pin 4 of U36 is connected to +15V, pin 5 is connected to GND, pin 2 is connected to one end of resistor R246 and one end of capacitor C64, the other end of C64 is connected to the other end of R246 and +15V, pin 3 of U36 is connected to the collector of S8050 transistor Q13, the base of Q13 is connected to one end of resistor R248 and one end of resistor R247, the other end of R247 is connected to C3, the other end of R248 is connected to GND and the emitter of Q13, pin 13 of U36 is connected to optocoupler U through resistor R249. The cathode of U37 input terminal is connected to pin 18 of U36. The emitter of U37 output terminal is connected to C8, and the collector of U37 output terminal is connected to +3.3V. Pin 17 of U36 is connected to one end of resistor R245, one end of bidirectional Zener diode ZD7, and PGND. Pins 16 and 15 of U36 are connected to one end of resistor R244. The other end of R244 is connected to the other end of R245, the other end of ZD7, and Q6_B. Pin 12 of U36 is connected to the anode of diode D14 through Zener diode, and the cathode of D14 is connected to Q4_S.

[0156] Pin 4 of U38 is connected to +15V, pin 5 is connected to GND, pin 2 is connected to one end of resistor R261 and one end of capacitor C87, the other end of C87 is connected to the other end of R261 and +15V, pin 3 of U38 is connected to the collector of S8050 transistor Q14, the base of Q14 is connected to one end of resistor R265 and one end of resistor R266, the other end of R265 is connected to D3, the other end of R266 is connected to GND and the emitter of Q14, pin 13 of U38 is connected to optocoupler U through resistor R267. The cathode of U40 input terminal is connected to pin 18 of U38. The emitter of U40 output terminal is connected to D8, and the collector of U40 output terminal is connected to +3.3V. Pin 17 of U38 is connected to one end of resistor R260, one end of bidirectional Zener diode ZD8, and PGND. Pins 16 and 15 of U38 are connected to one end of resistor R259. The other end of R259 is connected to the other end of R260, the other end of ZD8, and Q7_B. Pin 12 of U38 is connected to the anode of diode D15 through Zener diode, and the cathode of D15 is connected to Q5_S.

[0157] U21, U28, U36, and U38 are used to drive IGBTs Q4 to Q7. The PMM signal or high / low level signal output from the microprocessor U22 or FPGA is converted into a positive 15V and negative 9V (high level corresponds to +15V to turn on the IGBT, low level corresponds to -9V to turn off the IGBT) with a current of at least 9A, providing driving power, and is connected to the IGBT controller for on / off control. The KP103 features rapid IGBT turn-off protection when the IGBT crosses zero.

[0158] The overcurrent signal of Q1 is fed back to the microprocessor U33_PA7 through pins 18 and 13 of U27 via U31.

[0159] The overcurrent signal of Q2 is fed back to the microprocessor U33_PA5 through pins 18 and 13 of U20 and U25.

[0160] The overcurrent signal of Q4 is fed back to the microprocessor U22_A8 through pins 18 and 13 of U21 via U26.

[0161] The overcurrent signal of Q5 is fed back to the microprocessor U22_B8 through pins 18 and 13 of U28 via U32.

[0162] The overcurrent signal of Q6 is fed back to the microprocessor U22_C8 through pins 18 and 13 of U36 and U37.

[0163] The overcurrent signal of Q7 is fed back to the microprocessor U22_D8 through pins 18 and 13 of U38 and U40.

[0164] The USART3 (synchronous and asynchronous serial communication) port of the U5 main processor circuit is connected to U63. U63 is connected to the internal RS485 bus of the whole machine. U5 is connected to the RS485 bus in the host mode of the internal RS485 bus.

[0165] The FPGA (U22) has an internal NIOS_II soft core and an asynchronous serial communication soft core built in software. It is connected to U65 through PIO B4, D5, and D6, and then connected to the internal RS485 bus of the whole machine through U65. U22 is connected to the RS485 bus as an internal RS485 slave mode.

[0166] The U22 FPGA uses a high-speed H-bridge drive signal module built with FPGA hardware units written in VerilogHDL.

[0167] The driving circuit includes KP103 chips U20 and U27. Pin 4 of U20 is connected to +15V, pin 5 of U20 is connected to GND, pin 2 of U20 is connected to one end of resistor R211 and one end of capacitor C25, and the other end of C25 is connected to the other end of R211 and +15V. Pin 3 of U20 is connected to the collector of S8050 transistor Q8. The base of Q8 is connected to one end of resistor R217 and one end of resistor R218, and the other end of R217 is connected to U33_PA6. The other end of R218 is connected to GND and the emitter of Q8. Pin 13 of U20 is connected to... Resistor R219 is connected to the cathode of the input terminal of optocoupler U25. The anode of the input terminal of U25 is connected to pin 18 of U20. The emitter of the output terminal of U25 is connected to U33_PA7. The collector of the output terminal of U25 is connected to +3.3V. Pin 17 of U20 is connected to one end of resistor R210, one end of bidirectional Zener diode ZD3, and Q2_S. Pins 16 and 15 of U20 are connected to one end of resistor R209. The other end of R209 is connected to the other end of R210, the other end of ZD3, and Q2_B. Pin 12 of U20 is connected to the anode of diode D10 through Zener diode. The cathode of D10 is connected to Q2_D.

[0168] Pin 4 of U27 is connected to +15V, pin 5 is connected to GND, pin 2 is connected to one end of resistor R229 and one end of capacitor C54, the other end of C54 is connected to the other end of R229 and +15V, pin 3 of U27 is connected to the collector of S8050 transistor Q11, the base of Q11 is connected to one end of resistor R234 and one end of resistor R235, the other end of R234 is connected to U33_PA4, the other end of R235 is connected to GND and the emitter of Q11, pin 13 of U27 is connected to optocoupler U through resistor R236. The cathode of U31 input terminal is connected to pin 18 of U27. The emitter of U31 output terminal is connected to U33_PA5. The collector of U31 output terminal is connected to +3.3V. Pin 17 of U27 is connected to one end of resistor R228, one end of bidirectional Zener diode ZD5, and Q1_S. Pins 16 and 15 of U27 are connected to one end of resistor R225. The other end of R225 is connected to the other end of R228, the other end of ZD5, and Q1_B. Pin 12 of U27 is connected to the anode of diode D12 through Zener diode. The cathode of D12 is connected to Q1_D.

[0169] Pin 12 of STM32F030F4 chip U33 is connected to U33_PA6, pin 13 of STM32F030F4 chip U33 is connected to U33_PA7, pin 10 of STM32F030F4 chip U33 is connected to U33_PA4, and pin 11 of STM32F030F4 chip U33 is connected to U33_PA5;

[0170] Pin 1 of U33 is connected to GND through resistor R250. Pin 1 of the four-pin connector P5 is connected to +3.3V and one end of capacitor C90. The other end of C90 is connected to GND and pin 4 of P5. Pins 2 and 3 of P5 are connected to pins 19 and 20 of U33 respectively.

[0171] Capacitors C100 to C104 are connected in parallel between +3.3V and GND.

[0172] The input unidirectional AC sine wave is divided into two half-axis, positive and negative, resulting in two peaked waves. Q2 is switched on and off on the positive half-axis, and Q1 is switched on and off on the negative half-axis. Taking the positive half-cycle power adjustment of Q2 as an example, the control principle for the negative half-cycle is the same as that for the positive half-axis Q1, except that the control cycle is on the negative half-axis of the input AC current.

[0173] The microprocessor uses its internal timer T1 interrupt, with the timer overflow interrupt time set to 1 / 100 of each half-cycle. A bidirectional counter, with a maximum count of 50, is used. The counter decrements from 50 at the zero-crossing point of the positive half-cycle, reaching its maximum value of 0 at the end of the positive half-cycle, and then increments again to 50 at the end of the positive half-cycle. A voltage adjustment value of 0-50 is designed, where 0 represents the highest voltage and 50 represents the lowest. Each time T1 interrupts, the counter changes and is compared with the voltage adjustment value. If the adjustment value is greater than the count value, transistor Q2 is turned off; otherwise, Q2 is turned on. It is then turned back on at the zero-crossing point of the next positive half-cycle.

[0174] According to the RS485 communication command of U5, when maximum power output is required, Q2 and Q1 are turned on until they are turned on in each half cycle, and the back-end rectifier and filter circuit receives the complete swirl waveform, with the highest voltage amplitude.

[0175] The driving circuit includes an X9C103 chip U24. Pin 5 of U24 is connected to one end of resistor R208 and pin 1 of TL431 chip U23. The other end of R208 is connected to one end of resistor R207 and the anode of the input terminal of optocoupler OP1. The cathode of the input terminal of OP1 is connected to pin 3 of U23. Pin 2 of U23 is connected to GND, the negative terminal of capacitor C27 and capacitor C28, pin 3 of U24, pin 2 of U23, pin 4 of U24, one end of capacitor C29, and one end of capacitor C30. Pin 8 of U24 is connected to +3.3V, the other end of capacitor C29, and the other end of capacitor C30. Pins 1, 2, and 7 of U24 are connected to U34_PA4, U34_PA5, and U34_PA6 respectively. +15V is connected to the other end of C27, the other end of C28, and the other end of R207.

[0176] Pin 1 of the AD / DC_POW chip U29 is connected to the AC power L, pin 2 of U29 is connected to the AC power N, pin 3 of U29 is connected to +15V, one end of capacitor C59, the positive terminal of capacitor C60, one end of resistor R231, and the collector of NPN transistor Q10. The other end of R231 is connected to the base of Q10 and the collector of the output terminal of OP1. The emitter of the output terminal of OP1 is connected to pin 4 of U29, the other end of C59, the negative terminal of C60, one end of resistor R237, and Q3_S. The other end of R237 is connected to Q3_B and one end of resistor R226. The other end of R226 is connected to the emitter of Q10.

[0177] Pins 10, 11, and 12 of the STM32F030F4 chip U34 are connected to U34_PA4, U34_PA5, and U34_PA6 respectively. Pin 1 of U34 is connected to GND through resistor R251. The four corner connectors are plugged into pin 1 of P6 and connected to +3.3V and one end of capacitor C91 respectively. The other end of C91 is connected to pin 4 of P6 and GND respectively. Pins 2 and 3 of P6 are connected to U34_TMS and U34_TCK respectively.

[0178] Capacitors C105 to C109 are connected in parallel between +3.3V and GND.

[0179] U34 is connected to pins 1, 2, and 7 of U24 via pins 10, 11, and 12 respectively. U24 is an X9C103 digital variable resistor chip. Its function is to change the resistance between pins 5 and 3 by controlling pins 1, 2, and 7. U24 is also a TL431 2.5V reference chip. Its function is to maintain the voltage between pins 1 and 2 at 2.5V. When the voltage is higher than 2.5V, the chip decreases the resistance between pins 3 and 2; when the voltage at pin 2 is lower than 2.5V, it increases the resistance between pins 3 and 2. This circuit, combined with an optocoupler, forms an isolated voltage sampling feedback circuit.

[0180] The microprocessor U34 controls the resistance values ​​of pins 5 and 3 of U24 through three GPIO pins.

[0181] A resistor voltage divider circuit is formed by resistor R208 and pins 5 and 3 of U24.

[0182] U23 and the primary side of OP1 form a series circuit. The current in the primary side of OP1 is limited by R207 and U23; the resistance value of R207 is fixed.

[0183] Based on the characteristics of the U23 chip TL431 mentioned above, by changing the voltage divider between pins 1 and 2, the current of OP1 can be controlled, thereby changing the conduction depth of the phototransistor on the secondary side of OP1.

[0184] U29 is an AD220V to DC15V power converter. This 15V power supply passes through Q10 and R226 to the base (B) of Q3. The IB current of Q10 is controlled by the secondary side of OP1. When the conduction depth of the OP1 secondary side is large, the IB current of Q10 decreases, and vice versa. The decrease in the IB current of Q10 causes Q10 to enter the amplification region, thereby controlling the IB current of Q3 and its operating state. This allows the U34 microprocessor to control Q3 to operate in the linear region (amplification region), providing surge protection for the device.

[0185] It also includes an input AC zero-crossing capture circuit (U33 acquires the input AC zero-crossing capture signal; controls Q1 and Q2 to realize the step-down power regulation function. U5 communicates with U33 via RS485 and transmits the control value to U33).

[0186] The input AC zero-crossing capture circuit includes the second secondary side of transformer T1. One end of the second secondary side of T1 is connected to the anode of the input terminal of optocoupler U49 through diode D3 and resistor R1 in sequence. The cathode of the input terminal of U49 is connected to the center tap of the second secondary side of T1 and the cathode of the input terminal of optocoupler U50 in sequence. The anode of the input terminal of U50 is connected to the other end of the second secondary side of T1 through resistor R255 and diode D4 in sequence.

[0187] The collector of the output terminal of U49 is connected to +3.3V, the emitter of the output terminal of U49 is connected to U33_PB1, the emitter of the output terminal of U50 is connected to U33_PB2, and the collector of the output terminal of U50 is connected to +3.3V.

[0188] The first listening section of the RS485 bus includes an SP3485 chip U39. Pin 1 of U39 is connected to U33_PA3, pins 2 and 3 of U39 are connected to U33_PA1, pin 4 of U39 is connected to U33_PA2, and pins 5 to 8 of U39 are connected to GND, A, B, and +3.3V respectively. The two ends of resistor R263 are connected to B and GND respectively, and the two ends of resistor R264 are connected to A and +3.3V respectively.

[0189] The microprocessor (U33) and RS485 communication bus circuit act as an RS485 slave, constantly monitoring message data on the RS485 bus. It controls the on / off duration of IGBTs Q1 and Q2 based on commands sent from the RS485 master to the local unit. The U33 program configures an internal timer TIM1, which generates a timer overflow interrupt every 100µs and disables the timer (configured but not started). Configure external falling edge interrupt pins PB1 and PB2. PB1 is externally connected to the secondary side of the input AC zero-crossing protection circuit U49, and PB2 is connected to U50. The T1C and D windings are a set of step-down auxiliary windings of the AC input main transformer, and this winding has a center tap. According to their same-name terminal relationship, when the AC input goes from the positive half-cycle (the same-name terminal is high level) to zero, it passes through diode D3 to U49. On the secondary side of U49 (at PB1), a rectangular wave can be obtained, and its falling edge is the zero-crossing point of its negative half-cycle; the conduction start time of Q1. Conversely, the conduction start time of Q2 is also determined by the zero-crossing capture circuit of Q2 (the zero-crossing capture circuit of Q2 is D4 and U50). The falling edge of U49 on its secondary side triggers the falling edge external interrupt service function PB1 of the microprocessor circuit U33. Within this function, Q1 is first turned on, and the global counter COUN1 is set to 0. The TIM1 timer is enabled, generating a TIM1 overflow interrupt every 100µs. Each time this service function is entered, the value of COUN1 is compared with the on-time value sent by the host on the RS485 bus. When the value of COUN1 equals the value of Q1, Q1 is immediately turned off, and the TIM1 timer is disabled. At the end of the second half-cycle, a falling edge will be generated on the secondary side of U50. At this time, the falling edge interrupt service function is input to PB2, and the on-time of Q2 is controlled accordingly through the COUN1 counter, with the implementation principle being the same as that of Q1.

[0190] The second monitoring section of the RS485 bus includes an SP3485 chip U35. Pin 1 of U35 is connected to U34_PA3, pins 2 and 3 of U35 are connected to U34_PA1, pin 4 of U35 is connected to U34_PA2, and pins 5, 6, 7, and 8 of U35 are connected to GND, A, B, and +3.3V respectively.

[0191] Resistor R242 is connected to B and GND respectively, and resistor R243 is connected to A and +3.3V respectively.

[0192] The microprocessor (U34) and RS485 communication bus circuit, acting as an RS485 slave, constantly monitor the message data on the RS485 bus. Based on the commands sent from the RS485 master to the local unit, it controls the IB current of transistor Q3 to operate in the amplification region or saturation region. Initially, when the entire unit is powered on, Q3, not receiving commands from the master on the RS485 communication bus, is controlled by the microprocessor to operate in the cutoff region, and no current flows through Q3. When the master controller U5 enters startup mode, it commands the microprocessor's minimum circuit (U34) to enter startup mode via the RS485 communication bus. The microprocessor then controls the IB current of Q3 to slowly move it from the cutoff region to the amplification region, and constantly monitors the voltage between Q3_S and PGND through VP1. When the voltage reaches 2 / 3 (*220*1.414), Q3 enters the saturation region and enters normal operating mode. U24, U29, U23, OP1, and peripheral circuits constitute a digitally controllable linear drive circuit. This circuit can be controlled by the microprocessor U34 via 3-bit GPIO to adjust the resistance between pins 5 and 3 of U24. When the resistance between pins 5 and 3 of U24 changes, the reference voltage at pin 1 of U23 changes, causing a change in the resistance between pins 3 and 2 of U23. This, in turn, changes the light output power on the primary side of OP1, affecting the IB of Q10 on the secondary side; thus changing the IB current of Q3. The controller U34 operates within the load's operating range and zone.

[0193] It also includes a voltage sensor circuit, which includes the HBV10A3.3 chip VP1. Pin 1 of VP1 is connected to Q3_S through resistors R216 and R215 in sequence. Pin 2 of VP1 is connected to PGND through resistors R221 and R220 in sequence. Pins 4, 5, and 6 of VP1 are connected to U43_PA7, GND, and +3.3V respectively.

[0194] One end of resistor R227 is connected to one end of U34_PA7 and one end of capacitor C58, and the other end of R227 is connected to GND and the other end of C58.

[0195] Voltage sensor VP1 collects the voltage (main energy storage filter capacitor voltage) across Q3_S and PGND. This voltage is used for: input surge protection, equipment output power calculation, and step-down control.

[0196] It is understood that the above specific description of the present invention is only for illustrating the present invention and is not limited to the technical solutions described in the embodiments of the present invention. Those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention to achieve the same technical effect; as long as the use needs are met, they are all within the protection scope of the present invention.

Claims

1. A power supply circuit comprising a main processor, an FPGA, a power main circuit, a current collection part, a first RS485 bus listening part, a second RS485 bus listening part and a driving circuit, characterized in that The control signal input port of the drive circuit is connected to the control signal output port of the main processor, the signal transmission port of the drive circuit is connected to the signal transmission port of the FPGA, and the control signal output port of the drive circuit is connected to the control signal input port of the power main circuit. The signal transmission port of the current acquisition section is connected to the signal transmission port of the FPGA. The signal input port of the first listening section of the RS485 bus is connected to the signal output port of the driver circuit. The signal input port of the second monitoring section of the RS485 bus is connected to the signal output port of the driver circuit. The power input terminal of the main power circuit is connected to single-phase mains power; The driver circuit includes KP103 chips U21, U28, U36, and U38. Pin 4 of U21 is connected to +15V, pin 5 of U21 is connected to GND, pin 2 of U21 is connected to one end of resistor R214 and one end of capacitor C26, and the other end of C26 is connected to the other end of R214 and +15V. Pin 3 of U21 is connected to the collector of S8050 transistor Q9, and the base of Q9 is connected to one end of resistor R222 and one end of resistor R223, the other end of R222 is connected to A3, and the other end of R223 is connected to GND and the emitter of Q9. Pin 13 of U21... Pin 17 of U21 is connected to one end of resistor R213, one end of bidirectional Zener diode ZD4, and Q4_S. Pins 16 and 15 of U21 are connected to one end of resistor R212. The other end of R212 is connected to the other end of R213, the other end of ZD4, and Q4_B. Pin 12 of U21 is connected to the anode of diode D11 through Zener diode. The cathode of D11 is connected to Q3_S. Pin 4 of U28 is connected to +15V, pin 5 is connected to GND, pin 2 is connected to one end of resistor R233 and one end of capacitor C57, the other end of C57 is connected to the other end of R233 and +15V, pin 3 of U28 is connected to the collector of S8050 transistor Q12, the base of Q12 is connected to one end of resistor R238 and one end of resistor R239, the other end of R238 is connected to B3, the other end of R239 is connected to GND and the emitter of Q12, pin 13 of U28 is connected to optocoupler U through resistor R240. The cathode of U32 input terminal is connected to pin 18 of U28. The emitter of U32 output terminal is connected to B8, and the collector of U32 output terminal is connected to +3.3V. Pin 17 of U28 is connected to one end of resistor R232, one end of bidirectional Zener diode ZD6, and Q5_S. Pins 16 and 15 of U28 are connected to one end of resistor R230. The other end of R230 is connected to the other end of R232, the other end of ZD6, and Q5_B. Pin 12 of U28 is connected to the anode of diode D13 through Zener diode, and the cathode of D13 is connected to Q3_S. Pin 4 of U36 is connected to +15V, pin 5 is connected to GND, pin 2 is connected to one end of resistor R246 and one end of capacitor C64, the other end of C64 is connected to the other end of R246 and +15V, pin 3 of U36 is connected to the collector of S8050 transistor Q13, the base of Q13 is connected to one end of resistor R248 and one end of resistor R247, the other end of R247 is connected to C3, the other end of R248 is connected to GND and the emitter of Q13, pin 13 of U36 is connected to optocoupler U through resistor R249. The cathode of U37 input terminal is connected to pin 18 of U36. The emitter of U37 output terminal is connected to C8, and the collector of U37 output terminal is connected to +3.3V. Pin 17 of U36 is connected to one end of resistor R245, one end of bidirectional Zener diode ZD7, and PGND. Pins 16 and 15 of U36 are connected to one end of resistor R244. The other end of R244 is connected to the other end of R245, the other end of ZD7, and Q6_B. Pin 12 of U36 is connected to the anode of diode D14 through Zener diode, and the cathode of D14 is connected to Q4_S. Pin 4 of U38 is connected to +15V, pin 5 is connected to GND, pin 2 is connected to one end of resistor R261 and one end of capacitor C87, the other end of C87 is connected to the other end of R261 and +15V, pin 3 of U38 is connected to the collector of S8050 transistor Q14, the base of Q14 is connected to one end of resistor R265 and one end of resistor R266, the other end of R265 is connected to D3, the other end of R266 is connected to GND and the emitter of Q14, pin 13 of U38 is connected to optocoupler U through resistor R267. The cathode of U40 input terminal is connected to pin 18 of U38. The emitter of U40 output terminal is connected to D8. The collector of U40 output terminal is connected to +3.3V. Pin 17 of U38 is connected to one end of resistor R260, one end of bidirectional Zener diode ZD8, and PGND. Pins 16 and 15 of U38 are connected to one end of resistor R259. The other end of R259 is connected to the other end of R260, the other end of ZD8, and Q7_B. Pin 12 of U38 is connected to the anode of diode D15 through Zener diode. The cathode of D15 is connected to Q5_S. The main power circuit includes an air switch K1. One end of K1 is connected to the mains power, and the other end of K1 is connected to the primary side of transformer T1. One end of the first secondary side of T1 is connected to the cathode of diode D1, the drain of IGBT Q2, and Q2_D. The anode of D1 is connected to the source of IGBT Q1 and Q1_S. The gate of Q1 is connected to Q1_B. The drain of Q1 is connected to Q1_D, the cathode of diode D2, and pin 1 of common mode inductor L2. The anode of D2 is connected to the source of Q2 and Q2_S. The gate of Q2 is connected to Q2_B. Pin 3 of L2 is connected to the other end of the first secondary side of T1. D1, Q1, D2, Q2 and U33 form a step-down power regulation circuit, which turns on at the zero crossing point of each AC cycle, turns off before reaching or approaching 90°, and turns on again after exceeding 90° and before 180°. The current acquisition section includes an adjustable reference source control circuit, a linear drive circuit, a voltage reference array, and a voltage comparator array. The output port of the adjustable reference source control circuit is connected to the input port of the voltage reference array. The output of the voltage reference array is connected to the input of the voltage comparator array and the FPGA, respectively. The output port of the linear drive circuit is connected to the input of the voltage comparator array. The adjustable reference source control circuit includes an AD / DC_POW chip U44. Pin 1 of U44 is connected to the mains power L, pin 2 of U44 is connected to the mains power N, and pin 3 of U44 is connected to +15VA, one end of capacitor C126, the positive terminal of capacitor C127, one end of resistor R307, and the collector of NPN transistor Q17. The other end of R307 is connected to the base of Q17 and the collector of the output terminal of optocoupler OP3. The emitter of the output terminal of optocoupler OP3 is connected to the other end of capacitor C126, the negative terminal of capacitor C127, pin 4 of U44, one end of resistor R309, and GND. The emitter of Q17 is connected to the other end of resistor R309 and VRE_1 through resistor R308. The anode of the OP3 input terminal is connected to one end of resistor R305 and one end of resistor R306. The other end of R305 is connected to the positive terminal of capacitor C123, one end of capacitor C122, and +15VA. The other end of C122 is connected to GND, the negative terminal of C123, pin 2 of TL431 chip U46, pin 3 and pin 4 of X9C103 chip U45, one end of capacitor C124, and one end of capacitor C125. The other ends of C124 and C125 are connected to pin 8 of U45 and +3.3V. Pins 7, 2, and 1 of U45 are connected to J12, J14, and J15 respectively. Pin 5 of U45 is connected to pin 1 of U46 and the other end of R306. Pin 3 of U46 is connected to the cathode of the OP3 input terminal. The voltage reference array includes resistor R10, one end of which is connected to VRE_1, and the other end of which is connected in sequence to resistors R15-R17, R25, R30-R32, R37, R42-R44, R49, R54-R56, R61, R66, R67, R68, R73, R78-80, R85, R90-92, R97, R102-104, R109, R110, R115, R116, R122, R123, R129, R130, R136, R137, R142, R143, R148, and R149. R154, R155, R160, R161, R166, R167, R172, R173, R178, R179, R184, R185, R190, R191, R196, R197, R202, and R203 are connected to pin 5 of the X9C103 chip U18. Pin 3 of U18 is connected to GND, V, RE_1, pin 4 of U18, one end of capacitor C20, and one end of capacitor C21. The other end of C20 is connected to +3.3V, pin 8 of U18, and the other end of C21. Pins 7, 2, and 1 of U18 are connected to L6, K6, and J6 respectively. The linear drive circuit includes a MOSFET-N transistor Q21. The drain of Q21 is connected to ADC0, the cathode of Zener diode ZD2, and the cathode of diode D9. The source of Q21 is connected to GND, the cathode of ZD2, one end of capacitor C16, and one end of the secondary side of current transformer T3. The other end of the secondary side of T3 is connected to one end of capacitor C15 and the anode of D9. The other end of C15 is connected to the other end of C16 and FG. +15VA is connected to one end of capacitor C121, the positive terminal of capacitor C120, and one end of resistor R304. The other end of R304 is connected to one end of resistor R303 and the anode of the input terminal of optocoupler OP2. The cathode of the input terminal of optocoupler OP2 is connected to pin 3 of TL431 chip U43. Pin 2 of U43 is connected to GND, the other end of capacitor C121, the negative terminal of capacitor C120, pin 3 of X9C103 chip U42, pin 4 of U42, one end of capacitor C99, and one end of capacitor C98. Pin 1 of U43 is connected to the other end of resistor R303 and pin 5 of U42. Pins 1, 2, and 7 of U42 are connected to J13, J2, and J1 respectively. Pin 8 of U42 is connected to the other end of capacitor C99 and the other end of capacitor C98. Connect L to pin 1 of AD / DC_POW chip U41, pin 2 of U41 to N, pin 3 of U41 to +15VA, one end of capacitor C97, the positive terminal of capacitor C96, one end of resistor R302, and the collector of NPN transistor Q16. The other end of R302 is connected to the base of Q16 and the collector of the output terminal of OP2. The emitter of the output terminal of OP2 is connected to pin 4 of U41, the other end of C97, the negative terminal of C96, one end of resistor R300, and GND. The other end of R300 is connected to Q21_G and one end of resistor R301. The other end of resistor R301 is connected to the emitter of Q16. The current acquisition section consists of a 64-bit voltage divider circuit composed of 63 voltage divider resistors and one digitally adjustable resistor; and a voltage comparator array composed of 64 ultra-high-speed voltage comparators. MOSFET-N tube Q21 works in variable resistance area as current-voltage conversion circuit, through T3 electromagnetic mutual inductance type current sensor, through formula N1:N2=V1:V2=1 / A1:1 / A2, the output current of mutual inductance type current sensor T3B is 1 / 5000 of T3A end, according to Ohm's law U=I R, Q21 works in variable resistance area through U22 control, the resistance value of Q21 can dynamically change; the current of T3B is moderate in the sensitive interval of the rear end sampling array; The voltage conversion result of the mutual inductance current sensor shows that the voltage value of VER_1 increases proportionally with its resistance to ground; that is, the greater the resistance, the higher the voltage, and vice versa. Optimal acquisition accuracy can be obtained by adjusting the equivalent resistance of the variable resistor in the Q21 field-effect transistor to bring it within the sensitive range of the downstream acquisition circuit, or by increasing the equivalent resistance of the variable resistor region in the Q21 field-effect transistor to bring it within the sensitive range of the downstream acquisition circuit. When high-precision measurement is required for a certain range of the current value to be measured, the underlying voltage reference is adjusted to the minimum value of the required measurement range as the threshold for starting the detection range, and the remaining range is used as the 63-bit high-resolution detection range. When measuring a 50A high-frequency current, the measurement range is determined to be between 45A and 55A by adjusting the underlying variable reference and the inverting input reference of the voltage comparator array. The power supply circuit also includes an input AC zero-crossing capture circuit, which includes the second secondary side of transformer T1. One end of the second secondary side of T1 is connected to the anode of the input terminal of optocoupler U49 via diode D3 and resistor R1. The cathode of the input terminal of U49 is connected to the center tap of the second secondary side of T1 and the cathode of the input terminal of optocoupler U50. The anode of the input terminal of U50 is connected to the other end of the second secondary side of T1 via resistor R255 and diode D4. The collector of the output terminal of U49 is connected to +3.3V, the emitter of the output terminal of U49 is connected to U33_PB1, the emitter of the output terminal of U50 is connected to U33_PB2, and the collector of the output terminal of U50 is connected to +3.3V. The power supply circuit also includes a voltage sensor circuit, which includes an HBV10A3.3 chip VP1. Pin 1 of VP1 is connected to Q3_S through resistors R216 and R215 in sequence. Pin 2 of VP1 is connected to PGND through resistors R221 and R220 in sequence. Pins 4, 5, and 6 of VP1 are connected to U43_PA7, GND, and +3.3V respectively. One end of resistor R227 is connected to U34_PA7 and one end of capacitor C58 respectively. The other end of R227 is connected to GND and the other end of C58 respectively.

2. The power supply circuit according to claim 1, characterized in that, The driving circuit includes KP103 chips U20 and U27. Pin 4 of U20 is connected to +15V, pin 5 of U20 is connected to GND, pin 2 of U20 is connected to one end of resistor R211 and one end of capacitor C25, and the other end of C25 is connected to the other end of R211 and +15V. Pin 3 of U20 is connected to the collector of S8050 transistor Q8. The base of Q8 is connected to one end of resistor R217 and one end of resistor R218, and the other end of R217 is connected to U33_PA6. The other end of R218 is connected to GND and the emitter of Q8. Pin 13 of U20 is connected to... Resistor R219 is connected to the cathode of the input terminal of optocoupler U25. The anode of the input terminal of U25 is connected to pin 18 of U20. The emitter of the output terminal of U25 is connected to U33_PA7. The collector of the output terminal of U25 is connected to +3.3V. Pin 17 of U20 is connected to one end of resistor R210, one end of bidirectional Zener diode ZD3, and Q2_S. Pins 16 and 15 of U20 are connected to one end of resistor R209. The other end of R209 is connected to the other end of R210, the other end of ZD3, and Q2_B. Pin 12 of U20 is connected to the anode of diode D10 through Zener diode. The cathode of D10 is connected to Q2_D. Pin 4 of U27 is connected to +15V, pin 5 is connected to GND, pin 2 is connected to one end of resistor R229 and one end of capacitor C54, the other end of C54 is connected to the other end of R229 and +15V, pin 3 of U27 is connected to the collector of S8050 transistor Q11, the base of Q11 is connected to one end of resistor R234 and one end of resistor R235, the other end of R234 is connected to U33_PA4, the other end of R235 is connected to GND and the emitter of Q11, pin 13 of U27 is connected to optocoupler U through resistor R236. The cathode of U31 input terminal is connected to pin 18 of U27. The emitter of U31 output terminal is connected to U33_PA5. The collector of U31 output terminal is connected to +3.3V. Pin 17 of U27 is connected to one end of resistor R228, one end of bidirectional Zener diode ZD5, and Q1_S. Pins 16 and 15 of U27 are connected to one end of resistor R225. The other end of R225 is connected to the other end of R228, the other end of ZD5, and Q1_B. Pin 12 of U27 is connected to the anode of diode D12 through Zener diode. The cathode of D12 is connected to Q1_D. Pin 12 of STM32F030F4 chip U33 is connected to U33_PA6, pin 13 of STM32F030F4 chip U33 is connected to U33_PA7, pin 10 of STM32F030F4 chip U33 is connected to U33_PA4, and pin 11 of STM32F030F4 chip U33 is connected to U33_PA5. Pin 1 of U33 is connected to GND through resistor R250. Pin 1 of the four-pin connector P5 is connected to +3.3V and one end of capacitor C90. The other end of C90 is connected to GND and pin 4 of P5. Pins 2 and 3 of P5 are connected to pins 19 and 20 of U33 respectively. Capacitors C100 to C104 are connected in parallel between +3.3V and GND.

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