A wafer-level chip packaging structure and a preparation method thereof

Abstract

The present invention provides a wafer-level chip packaging structure and a preparation method. The wafer-level chip packaging structure includes: a substrate; a redistribution layer formed on the substrate, the redistribution layer having a dicing slot area; a packaging layer formed on the redistribution layer; and a groove formed in the packaging layer, the groove being located on the dicing slot area. The wafer-level chip packaging structure and the preparation method of the present invention can release the stress inside the packaging structure, reduce the warpage of the wafer, increase the process stability, improve the yield, and increase the output.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor packaging, and particularly relates to a wafer-level chip packaging structure and a preparation method thereof. Background Art

[0002] Wafer Level Chip Scale Packaging (WLCSP), that is, the wafer-level chip packaging method, is different from the traditional chip packaging method (first cutting and then packaging and testing, and the volume after packaging is at least 20% larger than the original chip). This latest technology first performs packaging and testing on the entire wafer, and then cuts it into individual IC particles. Therefore, the volume after packaging is the same as the original size of the IC die. The packaging method of WLCSP not only significantly reduces the size of the memory module, but also meets the high-density requirement of the mobile device for the body space. On the other hand, in terms of performance, it also improves the speed and stability of data transmission.

[0003] The wafer-level chip scale packaging technology integrates thin-film passive device technology and large-area manufacturing technology capabilities, which not only provides a cost-saving solution, but also provides a form factor that conforms to the existing surface mount assembly process. The chip scale packaging technology not only provides a performance improvement roadmap, but also reduces the size of the integrated passive devices. However, the wafer-level chip packaging method often causes large warping of the packaging structure, resulting in difficult process operations.

[0004] Based on the above, the purpose of the present invention is to provide a wafer-level chip packaging structure and a preparation method thereof to solve the warping problem of wafer-level chip packaging. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a wafer-level chip packaging structure and a preparation method thereof to solve the warping problem of wafer-level chip packaging.

[0006] To achieve the above object and other related objects, the present invention provides a preparation method of a wafer-level chip packaging structure, including the steps of:

[0007] Provide a wafer-level chip packaging structure to be processed, the wafer-level chip packaging structure to be processed includes: a substrate, a redistribution layer, and a packaging layer. The redistribution layer is formed on the substrate, the packaging layer is formed on the redistribution layer, the wafer-level chip packaging structure to be processed has a dicing slot area, and the wafer-level chip packaging structure to be processed has warping.

[0008] Form a groove on the packaging layer, the groove is located on the dicing slot area, and the groove reduces the stress inside the wafer-level chip packaging structure to be processed to obtain a flattened wafer-level chip packaging structure.

[0009] Optionally, the groove is located within the dicing slot area.

[0010] Optionally, the groove penetrates through the encapsulation layer.

[0011] Optionally, the groove does not penetrate through the encapsulation layer, and the ratio of the depth of the groove to the thickness of the encapsulation layer is between 1 / 2 and 4 / 5.

[0012] Optionally, the method for forming the groove includes one of a mechanical method, a laser grooving method, and a chemical etching method.

[0013] Optionally, an annealing treatment is further included after forming the groove.

[0014] Optionally, the heating temperature of the annealing treatment does not exceed 200°C.

[0015] Optionally, the annealing treatment includes a cooling step, and the cooling method includes natural cooling.

[0016] Optionally, a protective layer is further included, which is formed within the groove and on the upper surface of the encapsulation layer, and the protective layer covers the corner regions of the groove.

[0017] Optionally, the material of the protective layer includes epoxy resin.

[0018] The present invention further provides a wafer-level chip packaging structure, including:

[0019] A substrate;

[0020] A redistribution layer formed on the substrate, and the redistribution layer has a dicing slot area;

[0021] An encapsulation layer formed on the redistribution layer;

[0022] A groove formed in the encapsulation layer, and the groove is located above the dicing slot area.

[0023] Optionally, the groove is located within the dicing slot area.

[0024] Optionally, the groove penetrates through the encapsulation layer.

[0025] Optionally, the groove does not penetrate through the encapsulation layer, and the ratio of the depth of the groove to the thickness of the encapsulation layer is between 1 / 2 and 4 / 5.

[0026] Optionally, a protective layer is further included, which is formed within the groove and on the upper surface of the encapsulation layer, and the protective layer covers the corner regions of the groove.

[0027] Optionally, the material of the protective layer includes epoxy resin.

[0028] As described above, the present invention provides a wafer-level chip packaging structure and a preparation method thereof, and the present invention has the following effects:

[0029] The wafer-level chip packaging structure and the preparation method thereof of the present invention can release the stress inside the packaging structure, reduce the warpage of the wafer, increase the process stability, improve the yield, and increase the output.

[0030] Further, after forming the groove, an annealing treatment is included, which can release more stress inside the packaging structure, make the wafer-level chip packaging structure flatter, and improve the processability. Forming a protective layer in the groove and on the upper surface of the encapsulation layer can effectively protect the integrity of the encapsulation layer, avoid the phenomenon of corner peeling and chipping in subsequent processes, and enable the subsequent process operations to proceed smoothly. The groove is located in the dicing saw region, and the groove does not exceed the dicing saw region to avoid damaging the effective encapsulation layer. The depth of the groove accounts for a proportion between 1 / 2 and 4 / 5 of the thickness of the encapsulation layer, which can not only achieve the effect of reducing warpage but also avoid damaging the redistribution layer during the grooving process. Description of the Drawings

[0031] Figures 1 to 4 It shows a schematic structural diagram presented by each step of the preparation method of the wafer-level chip packaging structure of the present invention.

[0032] Figure 5 It shows a flowchart of the preparation method of the wafer-level chip packaging structure of the present invention.

[0033] Figure 2 It shows a cross-sectional view presented by the groove in the wafer-level chip packaging structure of the present invention.

[0034] Figure 3 It shows a top view presented by the groove in the wafer-level chip packaging structure of the present invention.

[0035] Description of Component Labels

[0036] 101 Substrate

[0037] 102 Redistribution layer

[0038] 103 Metal layer

[0039] 104 Dielectric layer

[0040] 105 Encapsulation layer

[0041] 106 Dicing saw region

[0042] 107 Groove

[0043] 108 Protective layer

[0044] Steps S01 to S04 Specific embodiments

[0045] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] Please refer to Figures 1 to 5 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0047] As Figures 1 to 5 shown, this embodiment provides a method for preparing a wafer-level chip packaging structure, including the steps:

[0048] As Figure 1 shown, perform step 1) S01, provide a wafer-level chip packaging structure to be processed, the wafer-level chip packaging structure to be processed includes: a substrate 101, a redistribution layer 102, and a packaging layer 105. The redistribution layer 102 is formed on the substrate 101, and the packaging layer 105 is formed on the redistribution layer 102. The wafer-level chip packaging structure to be processed has a dicing slot area 106, and the wafer-level chip packaging structure to be processed has warpage.

[0049] The redistribution layer 102 includes a patterned dielectric layer 104 and a patterned metal wiring layer. The number of layers of the dielectric layer 104 includes at least 1 layer, and the number of layers of the metal wiring layer includes at least 1 layer; forming the redistribution layer 102 includes the steps: forming the dielectric layer 104 on the surface of the separation layer by chemical vapor deposition process or physical vapor deposition process, and etching the dielectric layer 104 to form a patterned dielectric layer 104; forming a metal layer 103 on the surface of the patterned dielectric layer 104 by chemical vapor deposition process, evaporation process, sputtering process, electroplating process, or electroless plating process, and etching the metal layer 103 to form a patterned metal wiring layer; the material of the dielectric layer 104 includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

[0050] The method for encapsulating the chip with the encapsulation layer 105 includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, and spin coating, and the material of the encapsulation layer 105 includes one of polyimide, silicone rubber, and epoxy resin.

[0051] As Figures 2 to 3 shown, step 2) S02 is performed to form a groove 107 on the encapsulation layer 105. The groove 107 is located in the dicing slot area 106. The groove 107 reduces the stress inside the wafer-level chip packaging structure to obtain a planarized wafer-level chip packaging structure.

[0052] As an example, the groove 107 is located within the dicing slot area 106.

[0053] In one embodiment, the groove 107 penetrates through the encapsulation layer 105. In another embodiment, the groove 107 does not penetrate through the encapsulation layer 105, and the ratio of the depth of the groove 107 to the thickness of the encapsulation layer 105 is between 1 / 2 and 4 / 5. For example, the ratio of the depth of the groove 107 to the thickness of the encapsulation layer 105 can be 1 / 2, 2 / 3, or 4 / 5. The ratio of the depth of the groove 107 to the thickness of the encapsulation layer 105 being between 1 / 2 and 4 / 5 can not only reduce the warpage but also avoid damaging the redistribution layer 102 during the grooving process.

[0054] As an example, the method for forming the groove 107 includes a mechanical method, a laser grooving method, and a chemical etching method.

[0055] Forming the groove 107 on the encapsulation layer 105 can release the stress inside the packaging structure, reduce the warpage of the wafer, increase the process stability, improve the yield, and increase the output.

[0056] Generally, the warpage of the packaging structure is between 0.5 mm and 10 mm, which belongs to high warpage; the warpage of the packaging structure after adopting this method does not exceed 1 mm, which belongs to low warpage.

[0057] The groove 107 is located in the dicing slot area 106 and does not exceed the dicing slot area 106 to avoid damaging the effective encapsulation layer 105.

[0058] Step 3) S03: Anneal the wafer-level chip packaging structure.

[0059] As an example, the heating temperature of the annealing treatment does not exceed 200°C. For example, the heating temperature of the annealing treatment can be 100°C, 150°C, or 200°C, and the cooling method of the annealing treatment includes natural cooling. Performing the annealing treatment after forming the groove 107 can release more stress inside the encapsulation structure, make the wafer-level chip packaging structure flatter, and improve the process capabilities.

[0060] As Figure 4 shown, perform step 4) S04 to form a protective layer 108 in the groove 107 and on the upper surface of the encapsulation layer 105, and the protective layer 108 covers the corner regions of the groove 107.

[0061] As an example, the material of the protective layer 108 includes epoxy resin. Forming the protective layer 108 in the groove 107 and on the upper surface of the encapsulation layer 105 can effectively protect the integrity of the encapsulation layer 105, avoid corner peeling and chipping phenomena in subsequent processes, and enable the subsequent process operations to proceed smoothly.

[0062] As shown in Figure 4 the figure, this embodiment also provides a wafer-level chip packaging structure, including: a substrate 101, a redistribution layer 102, an encapsulation layer 105, a groove 107, and a protective layer 108.

[0063] The redistribution layer 102 is formed on the substrate 101, and the redistribution layer 102 has a dicing saw groove area 106.

[0064] The redistribution layer 102 includes a patterned dielectric layer 104 and a patterned metal wiring layer. The number of layers of the dielectric layer 104 includes at least 1 layer, and the number of layers of the metal wiring layer includes at least 1 layer; the material of the dielectric layer 104 includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

[0065] The encapsulation layer 105 is formed on the redistribution layer 102. The material of the encapsulation layer 105 includes one of polyimide, silica gel, and epoxy resin.

[0066] The groove 107 is formed in the encapsulation layer 105, and the groove 107 is located on the dicing saw groove area 106.

[0067] As an example, the groove 107 is located within the dicing saw groove area 106.

[0068] In one embodiment, the groove 107 penetrates through the encapsulation layer 105. In another embodiment, the groove 107 does not penetrate through the encapsulation layer 105, and the ratio of the depth of the groove 107 to the thickness of the encapsulation layer 105 is between 1 / 2 and 4 / 5. For example, the ratio of the depth of the groove 107 to the thickness of the encapsulation layer 105 can be 1 / 2, 2 / 3, or 4 / 5. When the ratio of the depth of the groove 107 to the thickness of the encapsulation layer 105 is between 1 / 2 and 4 / 5, it can not only reduce the warpage but also avoid damaging the redistribution layer 102 during the grooving process.

[0069] Forming the groove 107 on the encapsulation layer 105 can release the stress inside the encapsulation structure, reduce the warpage of the wafer, increase the process stability, improve the yield, and increase the output.

[0070] The groove 107 is located in the dicing slot area 106, and the groove 107 does not exceed the dicing slot area 106 to avoid damaging the effective encapsulation layer 105.

[0071] The protective layer 108 is formed in the groove 107 and on the upper surface of the encapsulation layer 105, and the protective layer 108 covers the corner areas of the groove 107.

[0072] As an example, the material of the protective layer 108 includes epoxy resin. Forming the protective layer 108 in the groove 107 and on the upper surface of the encapsulation layer 105 can effectively protect the integrity of the encapsulation layer 105, avoid corner peeling and chipping during subsequent processes, and enable the subsequent process operations to proceed smoothly.

[0073] In summary, the present invention provides a wafer-level chip packaging structure and a manufacturing method, having the following effects:

[0074] The wafer-level chip packaging structure and the manufacturing method of the present invention can release the stress inside the encapsulation structure, reduce the warpage of the wafer, increase the process stability, improve the yield, and increase the output.

[0075] Furthermore, after forming the groove 107, an annealing process is included, which can release more stress inside the encapsulation structure, make the wafer-level chip encapsulation structure flatter, and improve the processability. A protective layer 108 is formed inside the groove 107 and on the upper surface of the encapsulation layer 105, which can effectively protect the integrity of the encapsulation layer 105, avoid corner peeling and chipping during subsequent processes, and enable subsequent process operations to proceed smoothly. The groove 107 is located in the dicing groove area 106, and the groove 107 does not exceed the dicing groove area 106 to avoid damaging the effective encapsulation layer 105. The ratio of the depth of the groove 107 to the thickness of the encapsulation layer 105 is between 1 / 2 and 4 / 5, which can not only reduce the warpage but also avoid damaging the rewiring layer 102 during the grooving process. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0076] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a wafer-level chip packaging structure, characterized in that, Including the steps of: Providing a wafer-level chip package structure to be processed, the wafer-level chip package structure to be processed includes: a substrate, a redistribution layer, and a package layer. The redistribution layer is formed on the substrate, the package layer is formed on the redistribution layer, the wafer-level chip package structure to be processed has a dicing slot area, and the wafer-level chip package structure to be processed has warpage; Forming a groove on the package layer, the groove is located on the dicing slot area, the groove does not penetrate through the package layer, and the ratio of the depth of the groove to the thickness of the package layer is between 1 / 2 and 4 / 5. The groove reduces the stress inside the wafer-level chip package structure to be processed to obtain a planarized wafer-level chip package structure; Forming a protective layer in the groove and on the upper surface of the package layer, and the protective layer also covers the corner area of the groove.

2. The method for manufacturing a wafer-level chip packaging structure according to claim 1, wherein: The groove is located within the dicing slot area.

3. The method for manufacturing the wafer-level chip packaging structure according to claim 1, wherein: The groove penetrates through the package layer.

4. The manufacturing method of the wafer-level chip packaging structure according to claim 1, characterized in that: The method for forming the groove includes one of a mechanical method, a laser grooving method, and a chemical etching method.

5. The manufacturing method of the wafer-level chip packaging structure according to claim 1, wherein: After forming the groove, an annealing treatment is further included.

6. The method for manufacturing a wafer-level chip packaging structure according to claim 5, wherein: The heating temperature of the annealing treatment does not exceed 200°C.

7. The method for manufacturing a wafer-level chip packaging structure according to claim 5, wherein: The annealing treatment includes a cooling step, and the cooling method includes natural cooling.

8. The manufacturing method of the wafer-level chip packaging structure according to claim 1, characterized in that: The material of the protective layer includes epoxy resin.

9. A wafer-level chip packaging structure, characterized in that, Including: A substrate; A redistribution layer formed on the substrate, and the redistribution layer has a dicing slot area; A package layer formed on the redistribution layer; A groove formed in the package layer, the groove is located on the dicing slot area, the groove does not penetrate through the package layer, and the ratio of the depth of the groove to the thickness of the package layer is between 1 / 2 and 4 / 5 A protective layer formed in the groove and on the upper surface of the package layer, and the protective layer covers the corner area of the groove.

10. The wafer-level chip packaging structure according to claim 9, wherein: The groove is located within the dicing slot area.

11. The wafer-level chip packaging structure according to claim 9, wherein: The groove penetrates through the package layer.

12. The wafer-level chip packaging structure according to claim 9, wherein: The material of the protective layer includes epoxy resin.

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