Semiconductor device and semiconductor device packaging structure

Abstract

The present invention discloses a semiconductor element and a packaging structure of the semiconductor element. The semiconductor element includes a substrate, a semiconductor structure and a conductive reflective structure. The substrate has a first side and a second side opposite to the first side. The semiconductor structure is located on the first side of the substrate. The conductive reflective structure is located on the second side of the substrate. The conductive reflective structure includes a metal oxide structure and a metal structure. The metal oxide structure is located between the metal structure and the substrate. The metal oxide structure directly contacts the surface of the second side.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and in particular to semiconductor devices such as light emitting diodes. Background Art

[0002] Semiconductor components are widely used, and the development and research of related materials are also ongoing. For example, III-V semiconductor materials containing group III and group V elements can be applied to various optoelectronic semiconductor components such as light emitting diodes (LEDs), laser diodes (LDs), solar cells, etc., and can be used in lighting, medical treatment, display, communication, sensing, power supply systems and other fields. Among them, light emitting diodes, as one of the semiconductor components, have the advantages of low power consumption and long life, so they are widely used in various fields. With the development of science and technology, there are still many technical research and development needs for semiconductor components. Summary of the invention

[0003] The present invention provides a semiconductor element, which includes: a substrate having a first side and a second side opposite to the first side; a semiconductor structure located on the first side of the substrate and including a first semiconductor layer, a second semiconductor layer and an active area located between the first semiconductor layer and the second semiconductor layer; and a conductive reflective structure located on the second side of the substrate and including a metal oxide structure and a metal structure, the metal oxide structure being located between the metal structure and the substrate, the metal structure including a first metal layer and a second metal layer, the first metal layer being located between the second metal layer and the metal oxide structure; a contact layer located between the substrate and the metal oxide structure and connected to the second side of the substrate; and a dielectric material layer located between the substrate and the metal oxide structure and connected to the second side of the substrate, and the dielectric material layer is separated from the contact layer by a distance; wherein the first metal layer has a first width, the second metal layer has a second width greater than the first width, and the active area has a third width less than the first width.

[0004] In one embodiment, the metal oxide structure includes a first metal oxide layer and a second metal oxide layer.

[0005] In one embodiment, the first metal oxide layer includes a first conductive material, and the second metal oxide layer includes a second conductive material different from the first conductive material.

[0006] In one embodiment, the first conductive material and the second conductive material have at least one same metal element.

[0007] In one embodiment, the second metal oxide layer is located between the first metal oxide layer and the first metal layer, and the first metal layer and the first metal oxide layer are not in direct contact.

[0008] In one embodiment, the second metal layer directly contacts the metal oxide structure.

[0009] In one embodiment, the first metal layer covers a portion of the metal oxide structure.

[0010] In one embodiment, the dielectric material layer has a first region and a second region, the first region overlaps with the active region, and the second region does not overlap with the active region.

[0011] In one embodiment, the semiconductor device further includes a first electrode located on the semiconductor structure and electrically connected to the semiconductor structure.

[0012] In one embodiment, the semiconductor device further includes a protection layer, and the protection layer covers the semiconductor structure.

[0013] In one embodiment, the metal oxide structure is located between the dielectric material layer and the contact layer.

[0014] In one embodiment, the substrate may include gallium arsenide, indium phosphide, silicon carbide, gallium phosphide, zinc oxide, gallium nitride, aluminum nitride, germanium, or silicon.

[0015] In one embodiment, the first metal layer has a side wall, and the second metal layer covers the side wall.

[0016] In one embodiment, the substrate comprises indium phosphide or gallium phosphide.

[0017] In one embodiment, the conductor element is a vertical semiconductor light emitting element.

[0018] In one embodiment, the semiconductor device is a light emitting device and emits radiation having a peak wavelength between 800 nm and 2000 nm.

[0019] In one embodiment, the contact layer includes a semiconductor material.

[0020] In one embodiment, in a top view, the contact layer is distributed in a two-dimensional dot pattern.

[0021] In one embodiment, the metal oxide structure has a fourth width greater than the first width.

[0022] The present invention provides a semiconductor element, comprising: a substrate having a first side, a second side opposite to the first side, and a first side edge; a semiconductor structure located on the first side of the substrate; and a conductive reflective structure located on the second side of the substrate and comprising a surface of a metal structure directly contacting the second side, wherein the metal structure comprises a plurality of unit patterns, each unit pattern comprising a first figure and a second figure different from the first figure; wherein the semiconductor structure has a first width, the substrate has a second width greater than the first width, and one of the plurality of unit patterns has a second side edge, an imaginary line extending from the second side edge in a horizontal direction has an angle θ with the first side edge, and 0°<θ<90°.

[0023] In one embodiment, the second graphic is located in the first graphic and is surrounded by the first graphic.

[0024] In one embodiment, the second shape and the first shape respectively include an ellipse, a circle, a triangle, a rectangle or a polygon.

[0025] In one embodiment, the second shape is a circle and the first shape is a rectangle.

[0026] In one embodiment, the area of ​​the region defined by the outline of each unit pattern is A0, the sum of the areas of the first figure and the second figure in each unit pattern is A1, and 20%≤(A1 / A0)×100%≤75%.

[0027] In one embodiment, the substrate comprises indium phosphide.

[0028] In one embodiment, the semiconductor device is a light emitting device and emits radiation having a peak wavelength between 800 nm and 2000 nm.

[0029] In one embodiment, the ratio of the area of ​​the metal structure to the area of ​​the surface of the second side of the substrate is in the range of 20% to 80%.

[0030] In one embodiment, each unit pattern is divided into a first area, a second area, a third area and a fourth area. The patterns of the first area and the third area are symmetrical relative to the center point of each unit pattern, and the patterns of the second area and the fourth area are symmetrical relative to the center point of each unit pattern.

[0031] In one embodiment, the semiconductor device further includes a protection layer covering the sidewalls of the semiconductor structure.

[0032] In one embodiment, the semiconductor structure has a roughened upper surface.

[0033] In one embodiment, the semiconductor element further includes a first electrode located on the semiconductor structure and including a main electrode and an extended electrode. The protection layer covers the extended electrode but does not cover the main electrode.

[0034] In one embodiment, the substrate has a thickness greater than or equal to 60 μm and less than or equal to 250 μm.

[0035] In one embodiment, the semiconductor device further includes a contact layer located between the conductive reflective structure and the substrate and covering at least a portion of the substrate.

[0036] The present invention provides a semiconductor device packaging structure, which includes a carrier, a semiconductor device located on the carrier, and a packaging material layer covering the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1A A top view of the structure of a semiconductor device according to an embodiment of the present invention;

[0038] Figure 1B for Figure 1A A schematic diagram of the cross-sectional structure of a semiconductor element along line AA';

[0039] Figure 1C is a schematic cross-sectional structural diagram of a semiconductor element according to an embodiment of the present invention;

[0040] Figure 1D is a schematic cross-sectional structural diagram of a semiconductor element according to an embodiment of the present invention;

[0041] Figure 1E is a schematic cross-sectional structural diagram of a semiconductor element according to an embodiment of the present invention;

[0042] Figure 1F is a schematic cross-sectional structural diagram of a semiconductor element according to an embodiment of the present invention;

[0043] Figure 1G is a schematic cross-sectional structural diagram of a semiconductor element according to an embodiment of the present invention;

[0044] Figure 1H is a schematic cross-sectional structural diagram of a semiconductor element according to an embodiment of the present invention;

[0045] Fig. 1I is a schematic cross-sectional structural diagram of a semiconductor element according to an embodiment of the present invention;

[0046] Figure 1J is a schematic cross-sectional structural diagram of a semiconductor element according to an embodiment of the present invention;

[0047] Figure 2A A top view of the structure of a semiconductor device according to an embodiment of the present invention;

[0048] Figure 2B for Figure 2A A schematic diagram of the cross-sectional structure of a semiconductor element along line BB';

[0049] Figure 3 is a schematic cross-sectional structural diagram of a semiconductor element according to an embodiment of the present invention;

[0050] Figure 4A is a schematic cross-sectional structural diagram of a semiconductor element according to an embodiment of the present invention;

[0051] Figure 4B A schematic diagram of a patterned metal structure according to an embodiment of the present invention;

[0052] Figure 4C for Figure 4B An enlarged view of a unit pattern in ;

[0053] Figure 4D is a schematic diagram of a patterned metal structure according to an embodiment of the present invention;

[0054] Figure 5 is a schematic cross-sectional structural diagram of a semiconductor element according to an embodiment of the present invention;

[0055] Figure 6 is a schematic cross-sectional structural diagram of a semiconductor element according to an embodiment of the present invention;

[0056] Figure 7 FIG. 4 is a schematic diagram of a packaging structure of a semiconductor element according to an embodiment of the present invention.

[0057] Explanation of symbols

[0058] 10, 20, 30, 40, 50, 60, 70, 80, 90, 90a, 90b, 90c, 90d, 90e: semiconductor components

[0059] 100: Base

[0060] 100a: First side

[0061] 100b: Second side

[0062] 102: Semiconductor structure

[0063] 102a: first semiconductor layer

[0064] 102b: Second semiconductor layer

[0065] 102c: Semiconductor Structure

[0066] 104: Conductive reflective structure

[0067] 106: Metal Oxide Structure

[0068] 106a: First metal oxide layer

[0069] 106b: Second metal oxide layer

[0070] 108: Metal Structure

[0071] 108a: First metal layer

[0072] 108b: Second metal layer

[0073] 110: First electrode

[0074] 111: Second electrode

[0075] 110a: Main electrode

[0076] 110b: Extended electrode

[0077] 112: Contact layer

[0078] 114, 114', 114": dielectric material layer

[0079] 116, 116': Protective layer

[0080] 120: Unit pattern

[0081] 120a: District 1

[0082] 120b: Second District

[0083] 120c: Third District

[0084] 120d: District 4

[0085] 122: First Graphic

[0086] 124: Second Graphic

[0087] 126: Overlay

[0088] 600: Packaging structure

[0089] 61: Package substrate

[0090] 62: Through hole

[0091] 63: Carrier

[0092] 63a: Part I

[0093] 63b: Part 2

[0094] 65: Bonding line

[0095] 66: Contact structure

[0096] 66a: First contact pad

[0097] 66b: Second contact pad

[0098] 68: Packaging material layer

[0099] A-A’, B-B’: Lines

[0100] C: Center point

[0101] C1, C2, S0: Imaginary lines

[0102] a, L0, L1: Lengths

[0103] b, W0, W1: Widths

[0104] W: Line width

[0105] R1: Major axis length

[0106] R2: Minor axis length

[0107] S, S1, S2, S3, S4: Sides

[0108] θ: Angle Detailed implementation manners

[0109] The following embodiments will illustrate the concept of the present invention with the accompanying drawings. In the drawings or the description, similar or identical components will be described using similar or identical reference numerals. And unless otherwise specified, the shapes or dimensions of the components in the drawings are only illustrative and are not actually limited thereto. It should be particularly noted that the components not shown or described in the drawings may be in forms known to those skilled in the art.

[0110] Unless otherwise specified, the general formula InGaAs represents In z1 Ga 1-z1 As, where 0 < z1 < 1; the general formula InAlAs represents In z2 Al 1-z2 As, where 0 < z2 < 1; InGaAsP represents In z3 Ga 1-z3 As z4 P 1-z4 , where 0 < z3 < 1, 0 < z4 < 1; AlGaInAs represents (Al z5 Ga (1-z5) ) z6 In 1-z6 As, where 0 < z5 < 1, 0 < z6 < 1; the general formula AlGaInP represents (Al z7 Ga (1-z7) ) z8 In 1-z8P, where 0 < z7 < 1 and 0 < z8 < 1. The composition and dopants of each layer included in the semiconductor device of the present disclosure can be analyzed by any suitable method, such as a secondary ion mass spectrometer (SIMS), and the thickness of each layer can also be analyzed by any suitable method, such as a transmission electron microscope ( transmission electron microscopy , TEM) or a scanning electron microscope (SEM). In addition, each dopant mentioned in the present disclosure can be intentionally added or unintentionally added. Intentional addition is, for example, by in-situ doping during epitaxial growth and / or by implanting with P-type or N-type dopants after epitaxial growth. Unintentional addition is, for example, due to what is generated during the manufacturing process.

[0111] Those of ordinary skill in the art should understand that other components can be added based on the embodiments described below. For example, in the case where it is not specifically stated, a similar description of "the first layer (or structure) is located on the second layer (or structure)" can include an embodiment where the first layer (or structure) is in direct contact with the second layer (or structure), and can also include an embodiment where there are other structures between the first layer (or structure) and the second layer (or structure) and they are not in direct contact with each other. In addition, it should be understood that the up-and-down positional relationship of each layer (or structure) and the like may change depending on the viewing direction. Furthermore, in the present disclosure, the statement that a layer or structure "substantially consists of X" means that the main component of the above layer or structure is X, but does not exclude the above layer or structure from including dopants or inevitable impurities.

[0112] Figure 1A is a top view of the structure of a semiconductor device 10 according to an embodiment of the present invention. Figure 1B is Figure 1A a schematic cross-sectional structure diagram of the semiconductor device 10 along line A-A'.

[0113] The semiconductor device 10 of the present invention may be a semiconductor light emitting device, such as a light emitting diode (LED) or a laser diode (LD), or a detection device, such as a photodiode (PD). In some embodiments, the semiconductor device 10 is a vertical semiconductor light emitting device. The semiconductor device 10 may include a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multiple quantum wells (MQW) structure. The semiconductor device 10 of the present embodiment includes a substrate 100, a semiconductor structure 102, a conductive reflective structure 104, and a first electrode 110. The substrate 100 has a first side 100a and a second side 100b opposite to the first side 100a. The semiconductor structure 102 is located on the first side 100a of the substrate 100, and the conductive reflective structure 104 is located on the second side 100b of the substrate 100. In the present embodiment, the semiconductor device 10 is rectangular and has a length a and a width b. In one embodiment, the length a and width b of the semiconductor element 10 may be substantially equal. In some embodiments, the length a and width b may be greater than or equal to 100 μm and less than or equal to 500 μm, such as 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, or 450 μm.

[0114] The substrate 100 may be a conductive substrate, including gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (GaP), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), germanium (Ge) or silicon (Si). The substrate 100 may include a dopant and have a doping concentration. The dopant may be a non-metallic element (such as carbon (C), sulfur (S), silicon (Si), etc.) or a metallic element (such as iron (Fe), zinc (Zn), etc.). The doping concentration in the substrate 100 may fall within 5×10 17 / cm 3 Up to 5×10 18 / cm 3 In the range of 3×10 18 / cm 3 Less than, preferably 2.5×10 18 / cm 3 Below or 2×10 18 / cm 3In some embodiments, when the doping concentration of the substrate 100 is 1×10 18 / cm 3 In some embodiments, when the doping concentration of the substrate 100 is within 3×10 18 / cm 3 Within the following range, the semiconductor device can have better light-emitting efficiency. The substrate 100 can be a growth substrate or a support substrate. Specifically, the semiconductor structure 102 can be obtained by epitaxial growth, and the substrate 100 is, for example, a growth substrate for growing the semiconductor structure 102, or the substrate 100 can be a support substrate bonded to the semiconductor structure 102 using a bonding layer after the growth substrate is removed.

[0115] When the semiconductor element 10 is a light emitting element, the semiconductor structure 102 can emit a radiation. The radiation can be non-coherent light or coherent light. The radiation is preferably red light or infrared light, such as near infrared light (NIR). When the radiation is near infrared light, it can have a peak wavelength between 800nm ​​and 2000nm, such as 810nm, 850nm, 910nm, 940nm, 1050nm, 1070nm, 1100nm, 1200nm, 1300nm, 1400nm, 1450nm, 1550nm, 1600nm, 1650nm, 1700nm, etc. The substrate 10 can be transparent, semi-transparent or opaque to the radiation. When the radiation emitted by the semiconductor element 10 is greater than 1000nm, the substrate 10 preferably has a transmittance greater than 30% or an absorptivity less than 30% to the radiation. In some embodiments, the substrate 100 may have a thickness greater than or equal to 60 μm and less than or equal to 250 μm, for example, 100 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 200 μm, or 230 μm.

[0116] The semiconductor structure 102 includes a first semiconductor layer 102a, a second semiconductor layer 102b, and an active region 102c located between the first semiconductor layer 102a and the second semiconductor layer 102b. The semiconductor structure 102 may have a first width, and the substrate 100 may have a second width greater than the first width. The first semiconductor layer 102a and the second semiconductor layer 102b are respectively located on both sides of the active region 102c and are adjacent to the semiconductor structure region 102c. The first semiconductor layer 102a and the second semiconductor layer 102b have opposite conductivity types to provide electrons and holes or holes and electrons. For example, the conductivity type of the first semiconductor layer 102a is n-type, and the conductivity type of the second semiconductor layer 102b is p-type; or the conductivity type of the first semiconductor layer 102a is p-type, and the conductivity type of the second semiconductor layer 102b is n-type. The materials of the first semiconductor layer 102a and the second semiconductor layer 102b may include aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P) or indium (In), and preferably do not include nitrogen (N). Preferably, the materials of the first semiconductor layer 102a and the second semiconductor layer 102b respectively include at least two selected from the group consisting of aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P) and indium (In). Specifically, the first semiconductor layer 102a and the second semiconductor layer 102b may respectively include binary, ternary or quaternary III-V semiconductor materials such as InP, GaAs, InGaAs or InAlAs. Preferably, the first semiconductor layer 102a and the second semiconductor layer 102b are substantially composed of binary, ternary or quaternary III-V semiconductor materials (such as InP, GaAs, InGaAs or InAlAs). In one embodiment, the first semiconductor layer 102a and the second semiconductor layer 102b are composed of the same material, for example, the first semiconductor layer 102a and the second semiconductor layer 102b both include InP, GaAs, InGaAs or InAlAs. In addition, the conductivity type of the first semiconductor layer 102a and the second semiconductor layer 102b can be adjusted by adding different dopants, such as magnesium (Mg), zinc (Zn), carbon (C), silicon (Si) or tellurium (Te). In one embodiment, the dopant in the first semiconductor layer 102a includes silicon (Si), and the dopant in the second semiconductor layer 102b includes zinc (Zn). The active region 102c may include a III-V semiconductor material, preferably aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P) or indium (In), and preferably does not include nitrogen (N). For example, the active region 102c may include a quaternary III-V semiconductor material such as InGaAsP or AlGaInAs. Preferably, the active region 102 c is substantially composed of a quaternary III-V semiconductor material, such as substantially composed of InGaAsP or AlGaInAs.

[0117] The conductive reflective structure 104 may include a metal oxide structure 106 and a metal structure 108. The conductive reflective structure 104 may reflect radiation emitted by the active region 102c so as to emit the radiation out of the semiconductor device 10 in the direction of the first semiconductor layer 102a. In this embodiment, the metal oxide structure 106 directly contacts the surface of the second side 100b of the substrate 100. Figure 1B As shown, the metal oxide structure 106 can completely cover the surface of the second side 100b of the substrate 100. The metal oxide structure 106 can be composed of a single layer or multiple layers. Preferably, the radiation emitted by the active region 102c has a transmittance of more than 80% to the metal oxide structure 106, and more preferably a transmittance of more than 90%. The metal oxide structure 106 can be composed of a single layer or multiple layers, preferably composed of two or three layers of materials. In addition, the metal oxide structure 106 is conductive and can be electrically connected to the metal structure 108 and the substrate 100. The material of the metal oxide structure 106 can include metal oxides, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO). Preferably, the metal oxide structure 106 is substantially composed of metal oxide (such as ITO, InO, SnO, CTO, ATO, AZO, ZTO, GZO, IWO, ZnO or IZO). In some embodiments, the metal oxide structure 106 is advantageous for improving current distribution in the semiconductor device.

[0118] The metal structure 108 may be composed of a single layer or multiple layers, and the metal structure 108 may be electrically connected to an external power source. The material of the metal structure 108 may include a metal or an alloy. When the metal structure 108 is composed of multiple layers, the material of each layer may include different metals or alloys, preferably, the material of each layer is substantially composed of different metals or alloys. In some embodiments, the metal structure 108 is composed of more than 3 layers of metal or alloy layers. The metal or alloy may be selected from the group consisting of In, Sn, Al, Au, Pt, Zn, Ag, Ti, Pb, Ge, Cu, Ni, W, Pt, AuBe, AuGe, AuZn, PbSn, GeAuNi. In one embodiment, the metal structure 108 includes at least one of Ag, Ti, Pt, and Au. Preferably, the metal structure 108 is substantially composed of a metal or alloy (e.g., In, Sn, Al, Au, Pt, Zn, Ag, Ti, Pb, Ge, Cu, Ni, W, Pt, AuBe, AuGe, AuZn, PbSn, or GeAuNi). In one embodiment, the metal structure 108 includes at least one reflective layer (e.g., an Ag or Au layer) adjacent to the metal oxide structure 106, and the reflective layer can be used to reflect the radiation emitted by the active region 102c. In one embodiment, the metal structure 108 includes a metal layer of at least two of Ag, Ti, Pt, and Au, such as Ag / Ti, Ti / Pt / Au, Ag / Ti / Pt / Au, Ag / Ti / Pt / Ti / Pt / Au, Au / Ti / Pt / Au, or Au / Ti / Pt / Ti / Pt / Au. In one embodiment, it is preferred that the metal structure 108 consists essentially of Ag / Ti / Pt / Au, Ag / Ti / Pt / Ti / Pt / Au, Au / Ti / Pt / Au or Au / Ti / Pt / Ti / Pt / Au.

[0119] In some embodiments, the conductive reflective structure 104 can be used as an electrode to be electrically connected to an external power source. That is, the conductive reflective structure 104 has the functions of reflecting the radiation emitted by the active area 102c and conducting current. In addition, in the semiconductor device 10, the metal structure 108 can be completely or partially covered on the lower surface of the substrate 100 or the lower surface of the metal oxide structure 106. In some embodiments, the conductive reflective structure 104 can also only include the metal structure 108 without including the metal oxide structure 106, and the metal structure 108 can directly contact the surface of the second side 100b of the substrate 100.

[0120] The first electrode 110 is located on the semiconductor structure 102 and is used to electrically connect to an external power source and the active region 102c. The first electrode 110 includes a main electrode 110a and an extended electrode 110b. Figure 1AAs shown, the first electrode 110 of the semiconductor element may include a main electrode 110a and a plurality of extended electrodes 110b. The number of the extended electrodes 110b is, for example, four or more. In this embodiment, the main electrode 110a is circular, and each extended electrode 110b is T-shaped. Figure 1A In the embodiment, the main electrode 110a is located at the center of the semiconductor element 10, and a plurality of extension electrodes 110b surround the outside of the main electrode 110a and are respectively connected to the main electrode 110a. The main electrode 110a may have a width (its diameter when the main electrode 110a is circular) falling within the range of 50 μm to 150 μm. The extension electrode 110b may have a width falling within the range of 1 μm to 10 μm. The width of the extension electrode 110b is preferably less than 1 / 10 of the width of the main electrode 110a. The material of the first electrode 110 may include metal oxides, metals or alloys. The metal oxide includes, for example, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO). Examples of the metal include germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), nickel (Ni), copper (Cu), etc. The alloy may include at least two selected from the group consisting of the above metals, such as germanium gold nickel (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu), zinc gold (ZnAu), etc.

[0121] Figure 1CSchematic diagram of the cross-sectional structure of a semiconductor device 20 according to an embodiment of the present invention. In the present embodiment, the metal oxide structure 106 includes a first metal oxide layer 106a and a second metal oxide layer 106b, and the metal structure 108 is a single layer. The first metal oxide layer 106a is adjacent to the substrate 100 and directly contacts the surface of the second side 100b of the substrate 100. The second metal oxide layer 106b is adjacent to the first metal oxide layer 106a and is in contact with the metal structure 108. The thickness of the second metal oxide layer 106b may be greater than or less than the first metal oxide layer 106a. The materials of the first metal oxide layer 106a and the second metal oxide layer 106b may be the same or different. The first metal oxide layer 106a includes a first conductive material, and the second metal oxide layer 106b includes a second conductive material. In one embodiment, the resistivity of the first metal oxide layer 106a is less than the resistivity of the second metal oxide layer 106b. The first metal oxide layer 106a and the second metal oxide layer 106b may include metal oxides, respectively. The metal oxide is selected from the group consisting of indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), and indium zinc oxide (IZO). In one embodiment, the first metal oxide layer 106a and the second metal oxide layer 106b have at least one same metal element, such as indium (In). In one embodiment, the first metal oxide layer 106a includes indium tin oxide (ITO), and the second metal oxide layer 106b includes indium zinc oxide (IZO).

[0122] The positions, relative relationships, material compositions, and structural variation examples of other layers or structures in this embodiment have been fully described in the previous embodiments and will not be repeated here.

[0123] Figure 1DSchematic diagram of the cross-sectional structure of a semiconductor device 30 according to an embodiment of the present invention. In this embodiment, the metal oxide structure 106 of this embodiment is a single layer, and the metal structure 108 is a multi-layer structure, including a first metal layer 108a and a second metal layer 108b. The materials of the first metal layer 108a and the second metal layer 108b can be the same or different. The first metal layer 108a and the second metal layer 108b can be substantially composed of metals or alloys, respectively. The metal or alloy can be selected from the group consisting of In, Sn, Al, Au, Pt, Zn, Ag, Ti, Pb, Ge, Cu, Ni, W, Pt, AuBe, AuGe, AuZn, PbSn, GeAuNi. In one embodiment, one of the first metal layer 108a or the second metal layer 108b can be patterned. For example, the patterned first metal layer 108a may be located at the center of the substrate 100 and partially cover the metal oxide structure 106, and the second metal layer 108b may cover the first metal layer 108a and be in contact with the metal oxide structure 106. In other words, the first metal layer 108a has a width that is smaller than the width of the second metal layer 108b and / or the metal oxide structure 106. Thus, the first metal layer 108a can be prevented from being damaged (e.g., oxidized) by direct contact with the external environment (e.g., air), thereby reducing the reflection effect. The positions, relative relationships, material compositions, and other contents and structural variations of other layers or structures in this embodiment have been fully described in the previous embodiments and will not be repeated here.

[0124] Figure 1E FIG. 4 is a cross-sectional view of a semiconductor device 40 according to an embodiment of the present invention. In this embodiment, the metal oxide structure 106 and the metal structure 108 each include multiple layers. Figure 1E As shown, the metal oxide structure 106 includes a first metal oxide layer 106a and a second metal oxide layer 106b, and the metal structure 108 includes a first metal layer 108a and a second metal layer 108b. The materials and structural changes of the first metal oxide layer 106a, the second metal oxide layer 106b, the first metal layer 108a and the second metal layer 108b can refer to the description of the above embodiments.

[0125] Figure 1F , Figure 1G 1H and 1H are schematic cross-sectional structural diagrams of semiconductor device 50, semiconductor device 60 and semiconductor device 70 according to the embodiments of the present invention respectively.

[0126] exist Figure 1FIn the embodiment, a contact layer 112 is further included between the conductive reflective structure 104 and the substrate 100. In some embodiments, the contact layer 112 can be used to further improve the electrical connection characteristics between the metal oxide structure 106 and the substrate 100, such as reducing the resistivity. The material and structural changes of the conductive reflective structure 104 can refer to the description of the above embodiments. The material of the contact layer 112 can include semiconductor materials, metals or alloys. Semiconductor materials can include compound semiconductors such as binary III-V semiconductor materials (GaAs, GaP, etc.), or elemental semiconductors such as silicon (Si). The metal or alloy can be selected from the group consisting of In, Sn, Al, Au, Pt, Zn, Ag, Ti, Pb, Ge, Cu, Ni, W, Pt, AuBe, AuGe, AuZn, PbSn, GeAuNi. In some embodiments, when the conductive reflective structure 104 includes a metal oxide containing indium (such as indium tin oxide (ITO)), the contact layer 112 can include a conductive semiconductor material such as silicon (Si).

[0127] In one embodiment, the contact layer 112 may completely cover the surface of the second side 100b of the substrate 100. Figure 1F In one embodiment, the contact layer 112 may be patterned and cover a portion of the surface of the second side 100b of the substrate 100, for example Figure 1G According to one embodiment, in a top view, the contact layer 112 may be distributed in a two-dimensional dot shape.

[0128] In one embodiment, the metal oxide structure 106 and the substrate 100 may include a dielectric material layer 114 in addition to the contact layer 112. Figure 1H As shown, the patterned contact layer 112 and the dielectric material layer 114 are both in direct contact with the substrate 100. In this embodiment, on the surface of the second side 100b of the substrate 100, the contact layer 112 and the dielectric material layer 114 are separated by a distance. The metal oxide structure 106 in the conductive reflective structure 104 conformally covers the contact layer 112 and the dielectric material layer 114. The material of the dielectric material layer 114 can be SiO2, MgF2, SiN x , Al2O3 or a combination thereof. The first metal layer 108a may be a patterned metal layer, located in the center of the conductive reflective structure 104 and partially covering the metal oxide structure 106, and the second metal layer 108b may cover the first metal layer 108a and be in contact with the metal oxide structure 106. The positions, relative relationships, material compositions, and structural variations of other layers or structures in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

[0129] Fig. 1I FIG. 8 is a schematic cross-sectional view of a semiconductor element 80 according to another embodiment of the present invention. Fig. 1IAs shown, in this embodiment, there is no contact layer 112 between the metal oxide structure 106 and the substrate 100. The dielectric material layer 114' may partially cover the surface of the second side 100b of the substrate 100. In this embodiment, the dielectric material layer 114' is a patterned layer. The material of the dielectric material layer 114' may be SiO2, MgF2, SiN x , Al2O3 or a combination thereof. Fig. 1I As shown, the patterned dielectric material layer 114' can directly contact the substrate 100. The first metal oxide layer 106a can conformally cover the dielectric material layer 114' and the substrate 100. The second metal oxide layer 106b can cover the first metal oxide layer 106a. When the semiconductor device 80 is actuated, the portion of the first metal oxide layer 106a that is in direct contact with the substrate 100 is a conductive area and can form a current path. In some embodiments, by forming a patterned dielectric material layer 114', the current distribution and light uniformity of the semiconductor device 80 can be further improved. The positions, relative relationships, material compositions, and other contents and structural variations of other layers or structures in this embodiment have been fully described in the previous embodiments and will not be repeated here.

[0130] Figure 1J FIG. 1 is a schematic cross-sectional view of a semiconductor device 90 according to an embodiment of the present invention. In this embodiment, the semiconductor device 90 does not have a metal oxide structure 106, and includes a dielectric material layer 114 between the metal structure 108 and the substrate 100. The metal structure 108 includes a first metal layer 108a and a second metal layer 108b. Figure 1J As shown, the dielectric material layer 114" partially covers the surface of the second side 100b of the substrate 100, for example, covers the surface of the substrate 100 near the edge of the semiconductor element 90. The first metal layer 108a can cover the dielectric material layer 114" and directly contact the substrate 100. The material of the dielectric material layer 114" can be SiO2, MgF2, SiN x , Al2O3 or a combination thereof. The materials and structural changes of the first metal layer 108a and the second metal layer 108b can refer to the description of the aforementioned embodiments. The positions, relative relationships, material compositions, and structural changes of other layers or structures in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

[0131] Figure 2A FIG. 1 is a top view of a semiconductor device 90 a according to an embodiment of the present invention. Figure 2B for Figure 2A A schematic cross-sectional structure diagram of a semiconductor element 90a along line BB'.

[0132] The semiconductor device 90a of the present embodiment further includes a protection layer 116, which at least covers the sidewalls of the semiconductor structure 102. Figure 2B As shown, the protective layer 116 of this embodiment covers a part of the upper surface of the substrate 100, the sidewalls of the semiconductor structure 102, and a part of the upper surface of the semiconductor structure 102. The material of the protective layer 116 may include nitrides or oxides of silicon (Si), such as SiO2, SiN x . The thickness of the protective layer 116 can be within to range (for example to obtain better protection effect. In addition, as shown in the top view of Figure 2A and the cross-sectional view of Figure 2B , the contact part between the protective layer 116 and the substrate 100 may have a width d1, and the protective layer 116 may have a width d2. Preferably, the width d1 and the width d2 satisfy 1 < d2 / d1 ≤ 3. For example, d2 / d1 is 1.2, 1.5, 1.8, 2, 2.5, 2.8. In some embodiments, by providing the protective layer 116, the semiconductor structure 102 can be prevented from being damaged, the brightness decay can be delayed, and the service life of the semiconductor element can be improved. The conductive reflective structure 104 in this embodiment can be the one described in any embodiment of the present invention. The positions, relative relationships, material compositions, etc. of other layers or structures in this embodiment and the structural variation examples have been described in detail in the previous embodiments and will not be repeated here.

[0133] Figure 3 is a schematic cross-sectional structure diagram of a semiconductor element 90b according to an embodiment of the present invention. This embodiment provides another implementation aspect of the protective layer. As Figure 3 shown, the protective layer 116' of this embodiment covers a part of the substrate 100, the sidewalls of the semiconductor structure 102, and the upper surface of the semiconductor structure 102. In this embodiment, the semiconductor structure 102 has a roughened upper surface, and the protective layer 116' conformally covers the roughened upper surface and can contact the first electrode 110. In one embodiment, the protective layer 116' may cover a part of the upper surface of the main electrode 110a in the first electrode 110, for example, less than 20% or less than 10% of the upper surface area of the main electrode 110a. In one embodiment, the protective layer 116' covers a part of the upper surface of the main electrode 110a and the extension electrode 110b in the first electrode 110. In one embodiment, the protective layer 116' only covers the extension electrode 110b and does not cover the upper surface of the main electrode 110a. The material of the protective layer 116' may include nitrides or oxides of silicon (Si), such as SiO2, SiN x . The thickness of the protective layer can be within to range (for example

[0134]

[0135] The conductive reflective structure 104 in this embodiment can be any of the embodiments of the present invention. The positions, relative relationships, material compositions, and structural variations of other layers or structures in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

[0136] Figure 4A FIG. 9 is a schematic cross-sectional view of a semiconductor element 90c according to an embodiment of the present invention. Figure 4A As shown, the conductive reflective structure 104 of this embodiment includes a metal oxide structure 106 and a patterned metal structure 108. In another embodiment, the conductive reflective structure 104 may not include the metal oxide structure 106, and the metal structure 108 is directly formed on the substrate 100. As known from the above, the patterned metal structure 108 can be covered on the metal oxide structure 106 or the substrate 100 and directly contact the metal oxide structure 106 or the substrate 100. The patterned metal structure 108 can be composed of a single metal layer or multiple metal layers. The material of the metal layer can include metal or alloy. The material and structural changes of the metal layer can refer to the description of the above embodiments.

[0137] Figure 4B 1 is a schematic diagram of a patterned metal structure according to an embodiment of the present invention. The patterned metal structure 108 may include a plurality of unit patterns 120. Each unit pattern 120 may include a first graphic 122 and / or a second graphic 124. The first graphic 122 and the second graphic 124 may be selected from a group consisting of an ellipse, a circle, a triangle, a rectangle or a polygon. Figure 4B As shown, each unit pattern 120 may be composed of a plurality of squares (first pattern 122) and / or a plurality of circles (second pattern 124). A plurality of unit patterns 120 may be repeatedly arranged to form a Figure 4B The pattern shown. Figure 4B Only four unit patterns 120 are shown. In one embodiment, the ratio of the area of ​​the patterned metal structure 108 to the area of ​​a surface of the substrate 100 (such as the surface of the second side 100b) may be in the range of 20% to 80%, such as 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%. Figure 4B The figure is only for illustration. A person skilled in the art should understand that in fact, depending on the size of the semiconductor device, the number of unit patterns 120 in the patterned metal structure 108 may also vary, and the pattern located at the edge of the semiconductor device may be cut in the subsequent device manufacturing process, leaving only a portion of the unit pattern 120.

[0138] Figure 4C for Figure 4B An enlarged view of a unit pattern 120 in FIG. Figure 4C As shown, the outline of the unit pattern 120 is rectangular, and it has a length L0 and a width W0. The length L0 and the width W0 may be in the range of 120nm to 200nm, for example, 140nm, 160nm, 180nm. The unit pattern 120 can be divided into a first area 120a, a second area 120b, a third area 120c and a fourth area 120d by an imaginary line C1 and an imaginary line C2 of the center point C of the unit pattern 120. The imaginary line C1 and the imaginary line C2 are perpendicular to each other and intersect at the center point C. The patterns of the first area 120a and the third area 120c may be symmetrical to each other, and the patterns of the second area 120b and the fourth area 120d may be symmetrical to each other. In the present embodiment, the patterns of the first area 120a and the third area 120c are symmetrical to each other relative to the center point C, and the patterns of the second area 120b and the fourth area 120d are symmetrical to each other relative to the center point C. The patterns of the first area 120a and the second area 120b are different. In this embodiment, the first area 120a, the second area 120b, the third area 120c and the fourth area 120d are connected to each other, and the first area 120a, the second area 120b, the third area 120c and the fourth area 120d respectively have the first graphic 122. Figure 4C As shown, the first graphic 122 may be a hollow rectangle with a line width W. The line width W may be in the range of 1 nm to 10 nm, for example, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm. The first graphic 122 may have a length L1 and a width W1. The length L1 and the width W1 may be in the range of 50 nm to 100 nm, for example, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm.

[0139] The first region 120a and the third region 120c each further include a second graphic 124, which is located in the first graphic 122 and surrounded by the first graphic 122. The second graphic 124 is, for example, an ellipse, a circle, a triangle, a rectangle or a polygon. In the present embodiment, the second graphic 124 is different from the first graphic 122 and is non-rectangular. When the second graphic 124 is an ellipse, the length of its major axis is R1 and the length of its minor axis is R2, and R1>R2. When the second graphic 124 is a circle, R1 is equal to R2. R1 and R2 may be in the range of 20nm to 60nm, for example, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm. In one embodiment, the unit pattern 120 has a square outline, that is, the length L0 is equal to the width W0. In one embodiment, the outlines of the first graphics 122 in the first area 120a, the second area 120b, the third area 120c and the fourth area 120d are all square (i.e., the length L1 is equal to the width W1), and the second graphics 124 are circular (i.e., R1=R2). Figure 4CAs shown, in this embodiment, the second region 120 b and the fourth region 120 d only have the first pattern 122 but not the second pattern 124 .

[0140] In one embodiment, the area defined by the outline of the unit pattern 120 is A0 (eg Figure 4C The area of ​​the unit pattern 120 shown is obtained by multiplying the length L0 by the width W0), and the total area of ​​all the first graphics 122 and the second graphics 124 in the unit pattern 120 is A1 (as shown in FIG. Figure 4C When the area of ​​the shaded area is the sum of the areas of the shaded areas shown in the figure), it is preferably in accordance with the following conditions: 20% ≤ (A1 / A0) × 100% ≤ 75%. For example, (A1 / A0) × 100% is 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%. In this way, the photoelectric properties of the semiconductor element can be further improved, for example, the forward voltage (vf) value of the semiconductor element can be reduced by taking into account both the luminous intensity and the contact characteristics.

[0141] In some embodiments, when 20%≤(A1 / A0)×100%≤75%, a forward voltage value vf of the semiconductor element at a current of 50mA may be in the range of 0.8V to 0.95V, such as 0.85V, 0.9V, and the luminous power of the semiconductor element may be at least in the range of 2 to 4mW, such as 2.5mW, 2.8mW, 3mW, 3.2mW, 3.5mW, etc.

[0142] Figure 4D FIG. 1 is a schematic diagram of a patterned metal structure 108 according to an embodiment of the present invention.

[0143] Please refer to Figure 4D , which may be a bottom view of a semiconductor device 90c according to an embodiment of the present invention. The outermost dotted frame represents the outline of the substrate 100 in the semiconductor device 90c, which is composed of a plurality of side edges of the substrate 100. The substrate 100 of this embodiment includes side edge S1, side edge S2, side edge S3, and side edge S4. Figure 4D As shown, the patterned metal structure 108 may include a pattern formed by repeatedly arranging a plurality of unit patterns 120. One of the unit patterns 120 has a side S, and an imaginary line S0 may be obtained by extending from the side S in a horizontal direction. Among the plurality of side edges of the substrate 100, the side edge S3 is closest to the side edge S. Figure 4DAs shown, the side S3 and the imaginary line S0 may have an angle θ, and preferably 0°<θ<90°, such as 10°, 15°, 20°, 25°, 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85°. Thus, in the manufacturing process of the semiconductor device, the possibility of damaging the metal structure 108 during the cutting process can be reduced.

[0144] Figure 4D The figure is only for illustration, and a person skilled in the art should understand that in fact, depending on the size of the semiconductor element, the number of unit patterns 120 in the patterned metal structure 108 is also different, and the pattern located at the edge of the semiconductor element may only leave a part of the unit pattern 120 due to cutting. The positions, relative relationships, material compositions, and structural variations of other layers or structures in this embodiment have been fully described in the previous embodiments, and will not be repeated here.

[0145] Figure 5 FIG. 1 is a schematic cross-sectional view of a semiconductor device 90d according to an embodiment of the present invention. The semiconductor device 90d according to the present embodiment further includes a covering layer 126 for protecting the metal oxide structure 106 and / or the metal structure 108. Figure 5 As shown, the cover layer 126 may cover the sidewalls and a portion of the upper surface of the substrate 100, and the sidewalls of the conductive reflective structure 104. In some embodiments, the material of the cover layer 126 may include silicon (Si) nitride or oxide, such as SiO2, SiN x etc. In some embodiments, the material of the capping layer 126 may include metal oxides, such as aluminum oxides (such as Al2O3). In some embodiments, the capping layer 126 may be formed by, for example, atomic layer deposition (ALD). In some embodiments, when the metal structure 108 includes a metal element with high activity, such as silver (Ag), the presence of the capping layer 126 may improve the accelerated degradation of the metal structure 108 due to environmental factors (such as high temperature, high humidity, etc.), thereby improving the reliability of the semiconductor device. The conductive reflective structure 104 in this embodiment may be that described in any embodiment of the present invention. The positions, relative relationships, material compositions, and other contents and structural variations of other layers or structures in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

[0146] Figure 6Schematic diagram of the cross-sectional structure of a semiconductor device 90e according to an embodiment of the present invention. The semiconductor device 90e according to the present embodiment includes a substrate 100, a semiconductor structure 102, a conductive reflective structure 104, a first electrode 110, and a second electrode 111. The substrate 100 has a first side 100a and a second side 100b opposite to the first side 100a. The semiconductor device 90e according to the present embodiment is a horizontal device, including a first electrode 110 and a second electrode 111 located on the same side (such as the first side 100a) of the substrate 100. The first electrode 110 and the second electrode 111 can be used to electrically connect to an external power source and the semiconductor structure 102.

[0147] The semiconductor structure 102 is located on the first side 100a of the substrate 100 and includes a first semiconductor layer 102a, a second semiconductor layer 102b, and a semiconductor structure 102c located between the first semiconductor layer 102a and the second semiconductor layer 102b. The first electrode 110 is located on the first semiconductor layer 102a, and the second electrode 111 is located on the second semiconductor layer 102b. The substrate 100 may be a conductive substrate including the aforementioned conductive material, or may be a non-conductive substrate including an insulating material, such as sapphire. The conductive reflective structure 104 in this embodiment may be that described in any embodiment of the present invention. The positions, relative relationships, material compositions, etc. of each layer or structure in this embodiment and the structural variation examples have been described in detail in the previous embodiments and will not be repeated here.

[0148] Figure 7 FIG. 4 is a schematic diagram of a packaging structure of a semiconductor element according to an embodiment of the present invention.

[0149] Please refer to Figure 7 , the packaging structure 600 includes a semiconductor element 60, a packaging substrate 61, a carrier 63, a bonding wire 65, a contact structure 66 and a packaging material layer 68. The packaging substrate 61 may include a ceramic or glass material. The packaging substrate 61 has a plurality of through holes 62. The through holes 62 may be filled with a conductive material such as a metal to facilitate conduction and / or heat dissipation. The carrier 63 is located on the surface of one side of the packaging substrate 61 and also includes a conductive material such as a metal. The contact structure 66 is located on the surface of the other side of the packaging substrate 61. In the present embodiment, the contact structure 66 includes a first contact pad 66a and a second contact pad 66b, and the first contact pad 66a and the second contact pad 66b may be electrically connected to the carrier 63 through the through hole 62. In one embodiment, the contact structure 66 may further include a thermal pad (not shown), for example, located between the first contact pad 66a and the second contact pad 66b.

[0150] The semiconductor element 60 is located on the carrier 63. In this embodiment, the semiconductor element 60 is taken as an example, but in fact it can be the semiconductor element described in any embodiment of the present invention. In this embodiment, the carrier 63 includes a first portion 63a and a second portion 63b, and the semiconductor element 60 is electrically connected to the second portion 63b of the carrier 63 through a bonding wire 65. The material of the bonding wire 65 can include a metal, such as gold, silver, copper, aluminum, or an alloy containing at least any of the above elements. The packaging material layer 68 covers the semiconductor element 60 and has the effect of protecting the semiconductor element 60. Specifically, the packaging material layer 68 can include a resin material such as epoxy resin, silicone resin, etc. The packaging material layer 68 can also include a plurality of wavelength conversion particles (not shown) to convert the first light emitted by the semiconductor element 60 into a second light. The wavelength of the second light is greater than the wavelength of the first light.

[0151] Based on the above, according to the embodiments of the present invention, a semiconductor element can be provided, which has good optoelectronic properties, such as further improvement in luminous efficiency, wavelength stability and element reliability, etc. The semiconductor element of the present invention can be applied to products in the fields of lighting, medical treatment, display, communication, sensing, power supply system, etc., such as lamps, monitors, mobile phones, tablet computers, car dashboards, televisions, computers, wearable devices (such as watches, bracelets, necklaces, etc.), traffic signs, outdoor displays, medical equipment, etc.

[0152] Although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the relevant technical field should understand that slight modifications or changes can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the definition of the attached claims. In addition, the contents of the above embodiments can be combined or replaced with each other under appropriate circumstances, and are not limited to the specific embodiments described. For example, the relevant parameters of a specific component disclosed in one embodiment or the connection relationship between a specific component and other components can also be applied to other embodiments, and all fall within the scope of protection of the present invention.

Claims

1. A semiconductor element, characterized in that: The semiconductor component includes: a substrate having a first side and a second side opposite to the first side; A semiconductor structure is located on the first side of the substrate and includes a first semiconductor layer, a second semiconductor layer, and an active region between the first semiconductor layer and the second semiconductor layer; and A conductive reflective structure, located on the second side of the substrate, and comprising a metal oxide structure and a metal structure, wherein the metal oxide structure is located between the metal structure and the substrate, the metal structure comprises a first metal layer and a second metal layer, and the first metal layer is located between the second metal layer and the metal oxide structure; a contact layer located between the substrate and the metal oxide structure and connected to the second side of the substrate; and A dielectric material layer is located between the substrate and the metal oxide structure and is in contact with the second side of the substrate, and the dielectric material layer is separated from the contact layer by a distance; The first metal layer has a first width, the second metal layer has a second width greater than the first width, and the active area has a third width less than the first width. 2 . The semiconductor device as claimed in claim 1 , wherein the metal oxide structure comprises a first metal oxide layer and a second metal oxide layer. 3 . The semiconductor device as claimed in claim 2 , wherein the first metal oxide layer comprises a first conductive material, and the second metal oxide layer comprises a second conductive material different from the first conductive material. 4 . The semiconductor device as claimed in claim 3 , wherein the first conductive material and the second conductive material have at least one same metal element. 5 . The semiconductor device as claimed in claim 2 , wherein the second metal oxide layer is located between the first metal oxide layer and the first metal layer, and the first metal layer and the first metal oxide layer are not in direct contact. The semiconductor device as claimed in claim 1 , wherein the second metal layer directly contacts the metal oxide structure. 7 . The semiconductor device as claimed in claim 1 , wherein the first metal layer covers a portion of the metal oxide structure. 8 . The semiconductor device as claimed in claim 1 , wherein the dielectric material layer comprises a first region and a second region, the first region overlaps with the active region, and the second region does not overlap with the active region. 9 . The semiconductor device as claimed in claim 1 , further comprising a first electrode located on the semiconductor structure and electrically connected to the semiconductor structure. 10 . The semiconductor device as claimed in claim 1 , further comprising a protection layer covering the semiconductor structure. 11 . The semiconductor device as claimed in claim 1 , wherein the metal oxide structure is located between the dielectric material layer and the contact layer. 12 . The semiconductor device as claimed in claim 1 , wherein the substrate comprises gallium arsenide, indium phosphide, silicon carbide, gallium phosphide, zinc oxide, gallium nitride, aluminum nitride, germanium or silicon. 13 . The semiconductor device as claimed in claim 1 , wherein the first metal layer has a sidewall, and the second metal layer covers the sidewall.

14. The semiconductor device according to claim 1, wherein The substrate comprises indium phosphide or gallium phosphide.

15. The semiconductor device according to claim 1, wherein The semiconductor element is a vertical semiconductor light emitting element.

16. The semiconductor device according to claim 1, wherein The semiconductor element is a light emitting element and emits radiation having a peak wavelength between 800nm ​​and 2000nm.

17. The semiconductor device according to claim 1, wherein: The contact layer includes a semiconductor material.

18. The semiconductor device according to claim 1, wherein In a top view, the contact layer is distributed in a two-dimensional dot pattern.

19. The semiconductor device according to claim 1, wherein: The metal oxide structure has a fourth width greater than the first width.

20. A semiconductor device, characterized in that: The semiconductor component includes: A substrate having a first side, a second side opposite to the first side, and a first side edge; a semiconductor structure disposed on the first side of the substrate; and A conductive reflective structure is located on the second side of the substrate and includes a metal structure directly contacting a surface of the second side, the metal structure includes a plurality of unit patterns, each unit pattern includes a first pattern and a second pattern different from the first pattern; The semiconductor structure has a first width, the substrate has a second width greater than the first width, and one of the multiple unit patterns has a second side, an imaginary line extending from the second side in a horizontal direction has an angle θ with the first side, and 0°<θ<90°.

21. The semiconductor device according to claim 20, wherein: The second graphic is located in the first graphic and is surrounded by the first graphic.

22. The semiconductor device according to claim 20, wherein: The second shape and the first shape respectively include an ellipse, a circle, a triangle, a rectangle or a polygon.

23. The semiconductor device according to claim 22, wherein: The second figure is circular and the first figure is rectangular.

24. The semiconductor device according to claim 20, wherein: The area of ​​the region defined by the outline of each unit pattern is A0, the sum of the areas of the first figure and the second figure in each unit pattern is A1, and 20%≤(A1 / A0)×100%≤75%.

25. The semiconductor device according to claim 20, wherein: The substrate includes indium phosphide.

26. The semiconductor device according to claim 20, wherein: The semiconductor element is a light emitting element and emits radiation having a peak wavelength between 800nm ​​and 2000nm.

27. The semiconductor device according to claim 20, wherein: The ratio of the area of ​​the metal structure to the area of ​​the surface of the second side of the substrate is in the range of 20% to 80%.

28. The semiconductor device according to claim 20, wherein: Each unit pattern is divided into a first area, a second area, a third area and a fourth area. The patterns of the first area and the third area are symmetrical relative to the center point of each unit pattern. The patterns of the second area and the fourth area are symmetrical relative to the center point of each unit pattern.

29. The semiconductor device as claimed in claim 20, further comprising a protection layer covering a sidewall of the semiconductor structure.

30. The semiconductor device as claimed in claim 20, wherein the semiconductor structure has a roughened upper surface. 31 . The semiconductor device as claimed in claim 29 , further comprising a first electrode, located on the semiconductor structure and comprising a main electrode and an extended electrode, wherein the protection layer covers the extended electrode but does not cover the main electrode. 32 . The semiconductor device as claimed in claim 20 , wherein the substrate has a thickness greater than or equal to 60 μm and less than or equal to 250 μm. 33 . The semiconductor device as claimed in claim 20 , further comprising a contact layer located between the conductive reflective structure and the substrate and covering at least a portion of the substrate.

34. A semiconductor device packaging structure, characterized in that: The semiconductor device packaging structure includes: Carrier; A semiconductor device as claimed in any one of claims 1 to 33, located on the carrier; and The packaging material layer covers the semiconductor element.

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