Temperature correction circuit and method of operating a power amplifier

Abstract

A temperature correction circuit and method for maintaining a transistor of a power amplifier in a linear operating region of the transistor. The temperature correction circuit includes a first current source circuit operable to provide a first correction current proportional to the absolute temperature of a semiconductor die including the transistor. The temperature correction circuit also includes a second current source circuit operable to provide a second correction current proportional to a change in temperature of a portion of the semiconductor die in which the transistor is located during operation of the transistor. The temperature correction circuit further includes a third current source circuit operable to provide a gain selection current. The temperature correction circuit also includes circuitry for generating a reference current from the first and second correction currents and the gain current. The temperature correction circuit further includes an output for providing the reference current to the transistor.

Description

Technical Field

[0001] The present invention relates to a temperature correction circuit for maintaining a transistor of a power amplifier in a linear operating region. The present invention also relates to a method of operating a power amplifier. Background Art

[0002] Traditionally, the static error vector magnitude (EVM) calculation of a power amplifier is based on amplitude-to-amplitude modulation (AM / AM) and amplitude-to-phase modulation (AM / PM) distortion and is primarily related to the P out / (I cq 2 .R1) is proportional, where P out is the output power of the power amplifier, I cq is the quiescent current of the power amplifier, and R1 is the load impedance.

[0003] However, this type of calculation does not capture the dynamic thermal behavior of the PA, which can be an important consideration, especially in time-division duplex (TDD) systems and flip-chip packaging.

[0004] Dynamic Error Vector Magnitude (DEVM) is directly dependent on the power gain variation. In bipolar PAs over a wide temperature range, stabilization of the power gain becomes critical when targeting low DEVM levels. Summary of the Invention

[0005] Various aspects of the present disclosure are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate, and not just where explicitly set out in the claims.

[0006] According to one aspect of the present disclosure, there is provided a temperature correction circuit for maintaining a transistor of a power amplifier in a linear operating region of the transistor, the temperature correction circuit comprising:

[0007] a first current source circuit operable to provide a first correction current proportional to an absolute static temperature of a semiconductor die including the transistor;

[0008] a second current source circuit operable to provide a second correction current proportional to a change in temperature of a portion of the semiconductor die in which the transistor is located during operation of the transistor;

[0009] a third current source circuit operable to provide a gain selection current;

[0010] circuitry for generating a reference current from the first and second correction currents and the gain current; and

[0011] An output for providing the reference current to the transistor.

[0012] According to another aspect of the present disclosure, a method of operating a power amplifier is provided, the method comprising:

[0013] Provides gain selection current;

[0014] providing a first correction current proportional to the absolute temperature of a semiconductor die including a transistor of the power amplifier;

[0015] providing a second correction current proportional to a change in temperature of a portion of the semiconductor die in which the transistor is located during operation of the transistor;

[0016] generating a reference current from the first and second correction currents and the gain current; and

[0017] The reference current is provided to the transistor to maintain the transistor in a linear operating region.

[0018] The temperature correction circuit and method according to embodiments of the present disclosure can allow the operation of a power amplifier to be corrected for both static and dynamic temperature variations. This can be achieved using a single reference current.

[0019] The circuitry for generating a reference current may include a static temperature subcircuit configured to use the first correction current and the gain select current to generate a contribution to the reference current associated with the absolute static temperature of the die.

[0020] The circuitry for generating a reference current may include a dynamic temperature subcircuit configured to use the first correction current and the second current to generate a contribution to the reference current associated with the temperature change of the portion of the semiconductor die in which the transistor is located.

[0021] Providing a static temperature subcircuit and a dynamic temperature subcircuit separately may allow generating the static and dynamic contributions to the reference current separately in such a way that the dynamic correction does not affect the static correction, and vice versa.

[0022] The dynamic temperature subcircuit may include:

[0023] circuitry for generating, from the second correction current, the contribution to the reference current associated with the temperature variation of the portion of the semiconductor die in which the transistor is located; and

[0024] Circuitry is provided for removing a static portion from the contribution using the first correction current.

[0025] The static temperature subcircuit may include one or more programmable current mirrors for generating the contribution to the reference current associated with the absolute static temperature of the die.

[0026] The dynamic temperature subcircuit may include one or more programmable current mirrors for generating the contribution to the reference current associated with the temperature variation of the portion of the semiconductor die in which the transistor is located.

[0027] The temperature correction circuit may be configured to use one or more code words for controlling the current mirror to produce the contribution to the reference current.These control codes may be provided by digital circuitry of the temperature correction circuit.

[0028] The reference current may be suitable for biasing the transistor of the power amplifier.

[0029] The temperature correction circuit may be configured to determine the gain selection current according to a gain mode of the power amplifier.

[0030] The first current source circuit may include a current mirror, a current source operable to output a current based on a bandgap voltage reference, and a pair of cross-coupled transistors located at a temperature of the die.

[0031] The first current source circuit may include:

[0032] A first transistor pair comprising:

[0033] a first transistor having a first current terminal, a second current terminal, and a control terminal; and

[0034] a second transistor having a first current terminal, a second current terminal, and a control terminal; and

[0035] A second transistor pair comprising:

[0036] a first transistor having a first current terminal, a second current terminal, and a control terminal; and

[0037] a second transistor having a first current terminal, a second current terminal, and a control terminal; and

[0038] in:

[0039] the pair of cross-coupled transistors of the first current source circuit comprising the second transistor pair;

[0040] the control terminal of the first transistor of the first transistor pair is coupled to the control terminal of the second transistor of the first transistor pair,

[0041] the current source being coupled to the first control terminal of the first transistor of the first transistor pair and the control terminals of the first transistor and the second transistor of the first transistor pair,

[0042] the second current terminal of the first transistor of the first transistor pair is coupled to the first current terminal of the first transistor of the second transistor pair,

[0043] the second current terminal of the second transistor of the first transistor pair being coupled to the first current terminal of the second transistor of the second transistor pair,

[0044] the control terminal of the first transistor of the second transistor pair is coupled to the first current terminal of the second transistor of the second transistor pair,

[0045] the control terminal of the second transistor of the second transistor pair is coupled to the first current terminal of the first transistor of the second transistor pair,

[0046] The second current terminal of the first transistor of the second transistor pair is coupled to ground, and

[0047] The second current terminal of the second transistor of the second transistor pair is coupled to ground through a resistor.

[0048] The second current source circuit may include a current mirror, a current source operable to output a current based on a bandgap voltage reference, and a pair of cross-coupled transistors located at a temperature of a junction of the transistor of the power amplifier.

[0049] The first current source circuit may include:

[0050] A first transistor pair comprising:

[0051] a first transistor having a first current terminal, a second current terminal, and a control terminal; and

[0052] a second transistor having a first current terminal, a second current terminal, and a control terminal; and

[0053] A second transistor pair comprising:

[0054] a first transistor having a first current terminal, a second current terminal, and a control terminal; and

[0055] a second transistor having a first current terminal, a second current terminal, and a control terminal; and

[0056] in:

[0057] the pair of cross-coupled transistors of the second current source circuit comprising the second transistor pair;

[0058] the control terminal of the first transistor of the first transistor pair is coupled to the control terminal of the second transistor of the first transistor pair,

[0059] the current source being coupled to the first current terminal of the first transistor of the first transistor pair and the control terminals of the first transistor and the second transistor of the first transistor pair,

[0060] the second current terminal of the first transistor of the first transistor pair is coupled to the first current terminal of the first transistor of the second transistor pair,

[0061] the second current terminal of the second transistor of the first transistor pair being coupled to the first current terminal of the second transistor of the second transistor pair,

[0062] the control terminal of the first transistor of the second transistor pair is coupled to the first current terminal of the second transistor of the second transistor pair,

[0063] the control terminal of the second transistor of the second transistor pair is coupled to the first current terminal of the first transistor of the second transistor pair,

[0064] The second current terminal of the first transistor of the second transistor pair is coupled to ground, and

[0065] The second current terminal of the second transistor of the second transistor pair is coupled to ground through a resistor.

[0066] The power amplifier may be a radio frequency (RF) power amplifier.

[0067] The power amplifier may be coupled to the output of the temperature correction circuit for providing the reference current to the transistor of the power amplifier.

[0068] For purposes of this disclosure, "radio frequency" (RF) refers to frequencies generally in the range of, but not limited to, 0.5 GHz < f < 100 GHz. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Embodiments of the present disclosure will hereinafter be described, by way of example only, with reference to the accompanying drawings, in which like reference numerals refer to like elements, and in which:

[0070] Figure 1 shows a block diagram of an RF front end according to one embodiment of the present disclosure;

[0071] Figure 2shows a circuit according to one embodiment of the present disclosure;

[0072] Figure 3 shows the output of a current mirror according to one embodiment of the present disclosure;

[0073] Figure 4 shows the output of a current mirror according to one embodiment of the present disclosure;

[0074] Figure 5 shows a circuit according to one embodiment of the present disclosure; and

[0075] Figure 6 A circuit according to one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0076] Embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0077] Figure 1 A block diagram of a radio frequency front end 10 (hereinafter referred to as “front end” or “RFFE”) according to one embodiment of the present disclosure is shown.

[0078] The RFFE 10 includes an antenna 16 that can be used to transmit and receive radio frequency signals. A switch 14 can be provided to route the transmitted and received signals within the RFFE 10. Figure 1 As shown, the switch 14 may be configured to connect the antenna 16 to the transmit path (Tx) of the RFFE 10. Alternatively, the switch 14 may be configured to connect the antenna to the receive path (Rx) of the RFFE 10. The receive path may include a low noise amplifier 28 for amplifying received RF signals.

[0079] The features in the transmission path of RFFE 10 will now be described.

[0080] The RFFE 10 includes a power amplifier 4. The power amplifier 4 may include a transistor, for example, a bipolar junction transistor for field effect transistor for amplifying an input signal to be transmitted by the antenna 16. The power amplifier 4 may be powered by a power supply voltage V cc Power is supplied. Inductor 6 provides an RF choke that isolates DC from the RF signal and resonates with the output capacitance of the transistor in power amplifier 4 to provide a resistive load at the collector of the transistor. The transmit path also includes a coupler 12 for coupling the amplified signal to antenna 16. Coupler 12 may include an inductor. The transmit path may further include capacitor 26, input impedance matching network 2, and output impedance matching network 8.

[0081] According to an embodiment of the present disclosure, a reference current I ref To control the operation of the power amplifier. refIt can be used to bias the transistors of the power amplifier 4 to keep the transistors in the linear operating region. Specifically, the reference current I ref It can be used to correct for static and dynamic temperature effects in the power amplifier 4.

[0082] RFFE 10 includes a circuit for generating a reference current I ref The circuit system may include a plurality of current mirrors 18 that can receive and process a plurality of input currents to generate I ref The output of the current mirror can be coupled to the power amplifier 4 to provide a reference current I to the power amplifier 4. ref .

[0083] The current mirror 18 is used to generate the reference current I ref The input current includes the first correction current I ptat , the first correction current I ptat is proportional to the absolute static temperature of the semiconductor die including the transistor. Accordingly, the first correction current I ptat This allows the quiescent temperature of the transistor to be taken into account with the reference current I ref The first correction current I ptat It can be generated by the first current source 20.

[0084] During operation of the transistors of the power amplifier 4, the temperature of a portion of the semiconductor die near the transistors may vary. Typically, operating the transistors heats up this portion of the semiconductor die, and conversely, when the transistors operate less or stop operating, this portion of the semiconductor die may cool down again. To account for these temperature variations, the input current also includes a second correction current I ptdt The second correction current I ptdt is proportional to the temperature change of the portion of the semiconductor die where the transistor is located. Accordingly, the second correction current I ptdt This allows temperature variations of the portion of the semiconductor die close to the transistor to be taken into account in the reference current I ref The second correction current I ptdt It can be generated by the second current source 22.

[0085] The input current also includes a gain selection current I0. The gain selection current I0 can be selected according to the operating mode of the power amplifier 4 (e.g., the required gain level). The gain selection current I0 can be generated by the third current source 24. The gain selection current I0 itself can be used to adjust the first and second correction currents I ptat , I ptdt Generation.

[0086] Figure 2The method for generating a reference current I according to one embodiment of the present disclosure is shown in more detail. ref The circuit system 300 includes a plurality of sub-circuits. Specifically, the circuit system 300 includes a static temperature sub-circuit 40 and a dynamic temperature sub-circuit 50. Each sub-circuit 40, 50 and its other sub-circuit systems can generate a reference current I ref corresponding contribution.

[0087] The static temperature subcircuit 40 is configured to use the first correction current I ptat and gain selection current I0 to generate a reference current I associated with the absolute static temperature of the semiconductor die containing the transistors of the power amplifier 4. ref The static temperature subcircuit 40 includes a first subcircuit 42 and a second subcircuit 44 .

[0088] The dynamic temperature subcircuit 50 is configured to use the first correction current I ptat and the second current I ptdt to produce a contribution to the reference current associated with temperature variations in the portion of the semiconductor die in which the transistors of the power amplifier 4 are located.

[0089] The dynamic temperature sub-circuit 50 in this embodiment includes a circuit for obtaining the second correction current I ptdt The circuitry 52 generates a contribution to the reference current associated with temperature variations in the portion of the semiconductor die where the transistors of the power amplifier 4 are located. The dynamic temperature subcircuit 50 in this embodiment also includes circuitry for generating a contribution to the reference current generated from the dynamic temperature subcircuit 50. ref The circuit system 54 removes the static part of the contribution. The circuit system 54 uses the first correction current I ptat to perform this correction.

[0090] like Figure 2 As shown, the output of the circuit system 300 (represented by node 302) is used to provide a reference current I to the power amplifier 4. ref Note that node 302 is connected to the ref The outputs of the static temperature subcircuit 40 and the dynamic temperature subcircuit 50. In this embodiment, I ref is provided to the input of a current mirror 30 comprising a pair of transistors 32, 34. The emitter of each transistor 32, 34 is connected to the power amplifier supply voltage V cc The collector of transistor 32 is coupled to node 302 to receive I ref The bases of each transistor 32, 34 are coupled together and are additionally coupled to a node 302 (the base receiving I ref / β, where β is the PNP current gain). The output of the current mirror 30 is provided to a replica transistor at 200. The replica transistor here represents a diode mounted transistor that forms the final current mirror with the power cell to achieve good collector current control. In this way, the collector current reflects I ref .

[0091] The reference current I will now be described. ref The mathematical principles of its generation.

[0092] Reference current I ref It can be expressed as:

[0093] I ref =AT die +B+α.[T PA -T die ]

[0094] Where A, B and α are constants, T die is the absolute static temperature of the semiconductor die in which the transistors of the power amplifier 4 are provided, T PA is the temperature to which the temperature of the portion of the semiconductor die where the transistors of the power amplifier 4 are located changes during transistor operation (correspondingly, the associated temperature change of the power amplifier is given by (T PA -T die ) is given. Note that the junction temperature of the transistor can be considered to be essentially equal to T PA As will be described in more detail below, Figure 2 The various parts of the circuit system 300 (particularly the static temperature subcircuit 40, the dynamic temperature subcircuit 50 and its subcircuit system) can be assigned to generate the same I shown above. ref The various parts of the expression correspond to the contributions of the tasks.

[0095] The first reference current I ptat It can be expressed as:

[0096] I ptat =aT die +b.

[0097] Where a and b are constants. Note that I ptat The absolute static temperature T of the power amplifier die Proportional.

[0098] The second reference current I ptdt It can be expressed as:

[0099] I ptdt =a.(T die +dtT die )+b.

[0100] where dtT die =T PA -T die , and corresponds to the temperature variation of the portion of the semiconductor die where the transistors of the power amplifier 4 are located during transistor operation, as described above. Note that I ptdt Proportional to the above temperature changes, but also includes the temperature corresponding to the absolute static temperature T die contribution.

[0101] The gain selection circuit I0 can be expressed as:

[0102] I0=b.

[0103] Note that b appears in the I shown above ptat and I ptdt Accordingly, according to the operation mode of the power amplifier 4, the first and second correction currents I ptdt , I ptat are at least partially determined by the gain selection current 10. In some embodiments, the gain selection current 10 can be approximately 50 μA.

[0104] Figure 2 The circuit can use the control code to control the multiple current mirrors provided in the static temperature subcircuit 40 and the dynamic temperature subcircuit 50 to generate the reference current I ref In this embodiment, the first sub-circuit 42, the second sub-circuit 44, and the circuit system 52 may include a current mirror, wherein the current mirror includes a plurality of field effect transistors (e.g., NMOS or PMOS) connected in parallel, whose gates are connected to receive corresponding bits of the control code for the current mirror. In this embodiment, the circuit system 54 may include a current mirror, wherein the current mirror includes a plurality of field effect transistors (e.g., NMOS or PMOS) connected in parallel, whose gates are connected to receive corresponding bits of the control code for the current mirror.

[0105] The control codes may be generated by the digital circuitry of circuitry 300 and provided to the current mirrors. In one exemplary embodiment, a 0V or 2.5V value may be provided to each control code depending on the targeted calibration or gain selection. These voltages may be applied to the gates of the NMOS or PMOS transistors of the current mirrors to control the current flowing within the bias circuitry.

[0106] exist Figure 2 middle:

[0107] Sx is used to generate AT die +B's current mirror ratio in the quiescent temperature subcircuit 40;

[0108] Sy is used to generate α[TPA -T die ] the ratio of the current mirror in the dynamic temperature subcircuit 50;

[0109] X is a control code for controlling the current mirror in the static temperature subcircuit 40 (more specifically, in the first subcircuit 42 described below) to select T corresponding to the value of the constant A. die Slope (for static error vector magnitude (EVM) temperature correction);

[0110] · is a control code for controlling a current mirror in the static temperature subcircuit 40 (more specifically, in the second subcircuit 44 described below) to process the current mirror of the current I0;

[0111] Y is the control code used to control the current mirror in the dynamic temperature subcircuit 50 (more specifically, in the circuit system 52 described below) to select dtT corresponding to the value of the constant a die Slope (for dynamic error vector magnitude (EVM) temperature correction);

[0112] · is control code for controlling a current mirror in the dynamic temperature subcircuit 50 (more specifically, in the circuitry 54 described below) to subtract the static portion from the contribution produced by the dynamic temperature subcircuit 50; and

[0113] Z is a control code for controlling the current mirror in the static temperature subcircuit 40 (more specifically, in the second subcircuit 44 described below) to select I corresponding to the value of the constant B. ref level.

[0114] Think back:

[0115] I ref =AT die +B+α.[T PA -T die ]

[0116] We will now describe Figure 2 It is used to generate the reference current I ref The various contributions of the various parts of the circuit to the operation. In this regard, note that the reference current can also be written as: I ref =AT die +α.dtT die +B.

[0117] exist Figure 2 The static temperature subcircuit 40 allows the generation of a ref Contribution of A.Tdie+B. Specifically, Figure 2As shown, the first sub-circuit 42 includes a first reference current I ptat Generate contribution AT die The second subcircuit 44 includes a current mirror that uses the gain selection current I0 to produce a contribution B. The outputs of the first subcircuit 42 and the second subcircuit 44 of the static temperature subcircuit 40 are summed at the output of the static temperature subcircuit 40 presented at node 302.

[0118] The first reference current I ptat Can be Figure 2 I shown ptat The current source is generated from the bandgap voltage. The first subcircuit 42 of the static temperature subcircuit 40 uses Figure 2 The current mirror S shown x To control and amplify the first reference current I ptat The circuit system 300 may be operable to use the code word X to control the current mirror S in the first sub-circuit 42. x . Current mirror S x The output (corresponding to the first reference current I ptat , by the current mirror S x The relationship between the change of static temperature T0 and the Figure 3 Shown in. Figure 3 Each slope 82, 84, 86, 88 in corresponds to a different value of the constant A.

[0119] The second subcircuit 44 of the static temperature subcircuit 40 uses a current mirror S x and current mirror S z To control and amplify the gain selection current I0. The circuit system 300 may be operable to use the code word To control the current mirror S in the second sub-circuit 44 x And use code word Z to control the current mirror S z , thereby generating a contribution B from the gain selection current I0. Note that the control code Z in this embodiment is dedicated to the gain selection current (for the multi-mode power amplifier 4 operable at different gain levels).

[0120] The second sub-circuit 44 is used to Figure 3 Each of the slopes 82, 84, 86, 88 shown returns to the same level, thereby reducing the AT generated by the first sub-circuit 42. die Corrected to B when generated by the second sub-circuit 44. Corresponding to AT die +B correction slopes 92, 94, 96, 98 are Figure 4 As described herein, the output of the static temperature subcircuit 40 is related to the static temperature of the die (T die) and allows compensation for errors (error vector magnitude (EVM)) associated with the slow thermal constants and static temperature of the die containing the transistors of power amplifier 4. Static temperature subcircuit 40 can accordingly compensate for ambient temperature variations of the die, as opposed to the typically faster temperature variations caused by the operation of the transistors of power amplifier 4 in the vicinity of the transistors.

[0121] As mentioned above, the dynamic temperature sub-circuit 50 in this embodiment includes a circuit for adjusting the second correction current I ptdt Circuitry 52 for generating a contribution to the reference current associated with temperature variations of the portion of the semiconductor die in which the transistors of the power amplifier 4 are located during transistor operation, and circuitry for generating a contribution to the reference current generated by the dynamic temperature subcircuit 50. ref Specifically, the circuit system 52 includes a current mirror S y , the current mirror S y Control and amplify the second reference current I ptdt To produce the corresponding αT PA I ref The circuit system 300 may be operable to use the code word Y to control the contribution of the second reference current I ptdt Producing αT PA The current mirror S in the circuit system 52 y .

[0122] Circuitry 54 includes a (eg, PMOS) current mirror S y , the current mirror S y Control and amplify the first reference current I ptat To produce the corresponding -αT die I ref This makes the expression

[0123] I ptdt =a.(T die +dtT die )+b

[0124] T die The circuit system 300 may be operable to use the code word To control the first reference current I ptat Producing -αT die The current mirror S in the circuit system 54 y .

[0125] The outputs of circuitry 52 and circuitry 54 of dynamic temperature sub-circuit 50 are summed at the output of dynamic temperature sub-circuit 50 , which is presented at node 302 .

[0126] In summary, the reference current I ref The above expression, that is,

[0127] I ref =AT die +α.dtT die +B

[0128] According to the above operation of the circuit system 300, a, b, X, Y, Z, S x 、S y 、S y , Tdie and dtT die Rewritten as:

[0129] I ref =ZS z b-XS x b+XS x (aT die +b)+YS y [a.(T die +dtT die )+b]-YS y (aT die +b)

[0130] in:

[0131] B=ZS z b,

[0132] A=XS x a, and

[0133] α=YS y a.

[0134] As mentioned above, the I ptat and I ptdt The expression includes b (where b is equal to the gain selection current I0), so I ptat and I ptdt Determined at least in part by the gain select current I0. Figure 5 The method for generating the first reference current I from the gain selection current I0 is shown. ptat circuit. Figure 6 The method for generating the second reference current I from the gain selection current I0 is shown. ptdt circuit.

[0135] Figure 5 The circuit includes a current mirror formed by transistors 64 and 66. Figure 5 The circuit further includes a current source 62 operable to output a current based on the bandgap voltage reference. Figure 5The circuit further includes a pair of cross-coupled transistors 72, 74 (eg, NPN bipolar transistors). Figure 5 Each transistor in the circuit includes a first current terminal, a second current terminal, and a control terminal. The current terminals may be, for example, a collector and an emitter of a bipolar junction transistor, and the control terminal may be a base.

[0136] The control terminal of transistor 64 is coupled to the control terminal of transistor 66. Current source 62 is coupled to a first current terminal (e.g., collector) of transistor 64 and to the control terminals of transistors 64 and 66. A second current terminal (e.g., emitter) of transistor 64 is coupled to a first current terminal (e.g., collector) of transistor 72. A second current terminal (e.g., emitter) of transistor 66 is coupled to a first current terminal (e.g., collector) of second transistor 74. The control terminal of transistor 72 is coupled to a first current terminal (e.g., collector) of transistor 74. The control terminal of transistor 74 is coupled to a first current terminal (e.g., collector) of transistor 72. A second current terminal (e.g., emitter) of transistor 72 is coupled to a reference potential, typically ground. A second current terminal (e.g., emitter) of transistor 74 is coupled to a reference potential (typically ground) via resistor 76.

[0137] Figure 6 The circuit shown in Figure 5 The circuit shown in is essentially the same (note that Figure 6 Features 162, 164, 166, 170, 172, 174, 176, and 178 correspond to Figure 5 Features 62, 64, 66, 70, 72, 74, 76, 78). However, Figure 5 A pair of transistors 72, 74 (highlighted in box 70) connected cross-connected in the middle maintain the die temperature T die (e.g., by placing transistors 72, 74 in separate locations on the semiconductor die that are not located near the die where they are susceptible to heating during operation of the transistors), but Figure 6 A pair of cross-connected transistors 172, 174 (highlighted in box 170) are maintained at a temperature T of the portion of the semiconductor die where the transistors of the power amplifier 4 are located. PA , the temperature T PA It can be the junction temperature of the transistors of the power amplifier 4. The transistors 72 and 74 are placed at T die Make Figure 5 The circuit acts as a first reference current I for outputting (at node 78) ptat The transistors 172 and 174 are placed on the T PA Make Figure 6The circuit tracks temperature changes near the transistor of the power amplifier 4 during transistor operation, thereby serving as a second reference current I for outputting (at node 178) ptdt current source.

[0138] Accordingly, a temperature correction circuit and method for maintaining a transistor of a power amplifier in a linear operating region of the transistor has been described herein. The temperature correction circuit includes a first current source circuit operable to provide a first correction current proportional to the absolute temperature of a semiconductor die including the transistor. The temperature correction circuit also includes a second current source circuit operable to provide a second correction current proportional to a change in temperature of a portion of the semiconductor die in which the transistor is located during operation of the transistor. The temperature correction circuit further includes a third current source circuit operable to provide a gain selection current. The temperature correction circuit also includes circuitry for generating a reference current from the first and second correction currents and the gain current. The temperature correction circuit further includes an output for providing the reference current to the transistor.

[0139] Although specific embodiments of the present disclosure have been described, it will be appreciated that numerous modifications / additions and / or substitutions may be made within the scope of the appended claims.

Claims

1. A temperature correction circuit for maintaining a transistor of a power amplifier in a linear operating region of the transistor, characterized in that The temperature correction circuit comprises: a first current source circuit operable to provide a first correction current proportional to an absolute static temperature of a semiconductor die including the transistor; a second current source circuit operable to provide a second correction current proportional to a change in temperature of a portion of the semiconductor die in which the transistor is located during operation of the transistor; a third current source circuit operable to provide a gain selection current; circuitry for generating a reference current from the first and second correction currents and the gain current; and An output for providing the reference current to the transistor.

2. The temperature correction circuit according to claim 1, wherein: The circuitry for generating a reference current includes a static temperature subcircuit configured to use the first correction current and the gain select current to generate a contribution to the reference current associated with the absolute static temperature of the die.

3. The temperature correction circuit according to claim 1 or 2, characterized in that: The circuitry for generating a reference current includes a dynamic temperature subcircuit configured to use the first correction current and the second correction current to generate a contribution to the reference current associated with the temperature change of the portion of the semiconductor die in which the transistor is located.

4. The temperature correction circuit according to claim 3, wherein: The dynamic temperature subcircuit comprises: circuitry for generating, from the second correction current, the contribution to the reference current associated with the temperature variation of the portion of the semiconductor die in which the transistor is located; and Circuitry is provided for removing a static portion from the contribution using the first correction current.

5. The temperature correction circuit according to claim 3, wherein: said static temperature subcircuit comprising one or more programmable current mirrors for generating said contribution to said reference current associated with said absolute static temperature of said die; and / or The dynamic temperature subcircuit includes one or more programmable current mirrors for generating the contribution to the reference current associated with the temperature variation of the portion of the semiconductor die in which the transistor is located.

6. The temperature correction circuit according to claim 5, wherein: The temperature correction circuit is configured to use one or more code words for controlling the current mirror to produce the contribution to the reference current.

7. The temperature correction circuit according to claim 1 or 2, characterized in that: The reference current is used to bias the transistor of the power amplifier.

8. The temperature correction circuit according to claim 1 or 2, characterized in that: The temperature correction circuit is configured to determine the gain selection current according to a gain mode of the power amplifier.

9. The temperature correction circuit according to claim 1 or 2, characterized in that: The first current source circuit includes a current mirror, a current source operable to output a current based on a bandgap voltage reference, and a pair of cross-coupled transistors located at a temperature of the die.

10. A method of operating a power amplifier, characterized in that The method comprises: Provides gain selection current; providing a first correction current proportional to the absolute temperature of a semiconductor die including a transistor of the power amplifier; providing a second correction current proportional to a change in temperature of a portion of the semiconductor die in which the transistor is located during operation of the transistor; generating a reference current from the first and second correction currents and the gain current; and The reference current is provided to the transistor to maintain the transistor in a linear operating region.

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