Semiconductor Memory Device and Method of Operating the Semiconductor Memory Device

Abstract

Provided are a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input / output (I / O) gating circuit, and a control logic circuit. The memory cell array includes a data area and a parity area. The I / O gating circuit is connected to the ECC engine and the memory cell array. The control logic circuit generates control signals by decoding commands received from a memory controller. The ECC engine is configured to generate first parity data based on first write data associated with a first command. The control logic circuit is further configured to adjust a first write timing to write the first parity data into the parity area based on a reception timing of a second command following the first command and a reference time interval.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2019 - 0059967, filed on May 22, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Devices and methods consistent with example embodiments of the inventive concept relate to memories, and more particularly, to semiconductor memory devices and methods of operating semiconductor memory devices. Background Art

[0004] Semiconductor memory devices can be classified into non - volatile memory devices such as flash memory devices or volatile memory devices such as dynamic random access memories (DRAMs). The high - speed operation and cost - efficiency of DRAMs enable DRAMs to be used for system memories. In order to obtain higher yields from their manufacturing processes, the dimensions of manufacturing processes associated with semiconductor memory devices have been shrinking. Accordingly, bit errors in memory cells in DRAMs have been increasing. Thus, there is a need to improve the integration of semiconductor memory devices. Summary of the Invention

[0005] According to an example embodiment of the inventive concept, a semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input / output (I / O) gating circuit, and a control logic circuit. The memory cell array includes a data region and a parity region. The I / O gating circuit is connected to the ECC engine and the memory cell array. The control logic circuit is configured to generate control signals by decoding commands received from a memory controller. The ECC engine is configured to generate first parity data based on first write data associated with a first command. The control logic circuit is further configured to adjust a first write timing for writing the first parity data into the parity region based on a reception timing of a second command following the first command and a reference time interval.

[0006] According to an exemplary embodiment of the inventive concept, a semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input / output (I / O) gating circuit, a control logic circuit, an address first-in first-out (FIFO) buffer, and a parity FIFO buffer. The memory cell array includes a data region and a parity region. The I / O gating circuit is connected to the ECC engine and the memory cell array. The control logic circuit is configured to generate control signals by decoding commands received from the memory controller. The address FIFO buffer is configured to store column addresses for accessing the parity region. The parity FIFO buffer is configured to store first parity data. The ECC engine is configured to generate the first parity data based on first write data associated with the first command. The control logic circuit is further configured to control the I / O gating circuit, the address FIFO buffer, and the parity FIFO buffer such that: based on the same column address, the first write data is written to the data region at a first time, and the first parity data is written to the parity region at a second time following the first time.

[0007] According to an exemplary embodiment of the inventive concept, a method of operating a semiconductor memory device is provided. The semiconductor memory device includes: a memory cell array including a data region and a parity region, an error correction code (ECC) engine, and a control logic circuit controlling the ECC engine. In the method, the control logic circuit receives a first command and a first address from a memory controller. While generating first parity data based on write data associated with the first command, the ECC engine writes the write data to a target page of the data region, and based on a reception timing of a second command from the memory controller, the control logic circuit adjusts a first write timing to write the first parity data to the parity region.

[0008] According to an exemplary embodiment of the inventive concept, a semiconductor memory device is provided, including: a memory cell array including a data region and a parity region; an error correction code (ECC) engine configured to write write data associated with a first command to a target page of the data region and generate first parity data based on the write data; and a control logic circuit configured to receive the first command from a memory controller and write the first parity data to the parity region in response to a reception timing of a second command from the memory controller.

[0009] Accordingly, the semiconductor memory device may adjust the write timing of the parity data based on the reception timing of the first command and the reception timing of the second command. In addition, the semiconductor memory device may include the generation of the parity data in the background operation of the semiconductor memory device, such that the writing of the write data is not affected by the generation of the parity data. Accordingly, the semiconductor memory device may separate the write timing of the write data and the write timing of the write parity data, and may improve the performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Exemplary, non-limiting embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 is a block diagram showing a storage system according to some exemplary embodiments of the inventive concept.

[0012] Figure 2 is a block diagram showing a Figure 1 semiconductor memory device in

[0013] Figure 3 shows a Figure 2 first bank array in the semiconductor memory device of

[0014] Figure 4 shows a Figure 2 bank array and an ECC engine shown in the semiconductor memory device of

[0015] Figure 5 shows a part of the Figure 3 semiconductor memory device during a write operation and a read operation of

[0016] Figure 6 is a block diagram showing an Figure 5 example of an ECC engine in an exemplary embodiment of the inventive concept.

[0017] Figure 7 is a block diagram showing an Figure 5 example of a command monitor in an exemplary embodiment of the inventive concept.

[0018] Figure 8 and Figure 9 show main data and a data mask signal according to an exemplary embodiment of the inventive concept.

[0019] Figure 10 shows an Figure 6 example of a flag generator in an exemplary embodiment of the inventive concept.

[0020] Figure 11is a timing diagram showing an example operation of a semiconductor memory device according to an exemplary embodiment of the inventive concept. Figure 5

[0021] Figure 12 Shows that Figure 5 the semiconductor memory device performs a normal write operation.

[0022] Figure 13 Shows that according to an exemplary embodiment of the inventive concept Figure 5 the semiconductor memory device performs a masked write operation.

[0023] Figure 14 is a flowchart showing a method of operating a semiconductor memory device according to an exemplary embodiment of the inventive concept.

[0024] Figure 15 Shows Figure 14 a flowchart of generating first parity data while writing write data into a data area in

[0025] Figure 16 Shows Figure 14 a flowchart of the execution of a read - modify operation in

[0026] Figure 17 is a block diagram showing a semiconductor memory device according to an exemplary embodiment of the inventive concept.

[0027] Figure 18 is a cross - sectional view of a 3D chip structure of a semiconductor memory device according to an exemplary embodiment of the inventive concept employing Figure 17

[0028] Figure 19 is a view showing a semiconductor package including a stacked memory device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0029] Hereinafter, various exemplary embodiments of the inventive concept will be described more fully with reference to the accompanying drawings showing exemplary embodiments. Throughout the specification, like reference numerals denote like elements. Thus, even if the same or similar reference numerals are not mentioned or described in the corresponding drawings, these reference numerals can be described with reference to other drawings. In addition, elements not denoted by reference numerals can be described with reference to other drawings.

[0030] Figure 1 is a block diagram showing a storage system according to some exemplary embodiments of the inventive concept.

[0031] Referring to Figure 1 ​, the storage system 20 may include a storage controller 100 (e.g., an external storage controller) and at least one semiconductor storage device 200.

[0032] The storage controller 100 may control the overall operation of the storage system 20. In some embodiments, the storage controller 100 may control the overall data exchange between an external host and the semiconductor storage device 200. For example, the storage controller 100 may write data into the semiconductor storage device 200 and / or read data from the semiconductor storage device 200 in response to a request from the host. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] In addition, the storage controller 100 may issue operation commands to the semiconductor storage device 200 to control the semiconductor storage device 200.

[0034] In some example embodiments, the semiconductor storage device 200 may be a storage device including a plurality of dynamic storage cells, such as, for example, a dynamic random access memory (DRAM), a double data rate 4 (DDR4) synchronous DRAM (SDRAM), or a low power DDR4 (LPDDR4) SDRAM, but the inventive concept is not limited thereto.

[0035] The storage controller 100 may send a clock signal CLK, a command CMD, an address (signal) ADDR, and a data mask signal DM to the semiconductor storage device 200, and may exchange main data MD with the semiconductor storage device 200. The data mask signal DM may indicate whether the main data MD is masked. That is, the data mask signal DM may indicate whether the size of the main data MD is less than the size of a word of the semiconductor storage device 200.

[0036] The semiconductor storage device 200 may include a memory cell array (MCA) 300 that stores main data MD, an error correction code (ECC) engine 400, and / or control logic circuitry 210.

[0037] In a mask write operation, the ECC engine 400 may perform a read-modify operation by: receiving data and parity data from a sub-page of a target page in the memory cell array 300 as read data and read parity data, correcting at least one error bit in the read data based on the read parity data to generate corrected data, and generating first parity data based on the corrected data and first write data. It will be understood that although terms such as first, second, third, etc. may be used herein to describe various elements, the elements should not be limited by these terms; rather, these terms are only used to distinguish one element from another. Thus, without departing from the scope of the inventive concept, the first element discussed may be referred to as the second element.

[0038] The control logic circuit 210 may control the ECC engine 400 such that the ECC engine 400 performs a read-modify operation independent of (e.g., independent of) the write operation of the main data MD. The control logic circuit 210 may control the ECC engine to perform a read-modify operation by including the read-modify operation in the background operation of the semiconductor memory device 200.

[0039] Figure 2 is a block diagram of a Figure 1 semiconductor memory device according to an exemplary embodiment of the inventive concept.

[0040] Referring to Figure 2 , the semiconductor memory device 200 may include a control logic circuit 210, an address register 220, a bank control logic 230, a refresh counter 245, a row address multiplexer (RA MUX) 240, a column address (CA) latch 250, a row decoder 260, a column decoder 270, a memory cell array 300, a sense amplifier unit 285, an input / output (I / O) strobe circuit 290, an ECC engine 400, and a data I / O buffer 295.

[0041] The memory cell array 300 may include a first bank array 310a to an s-th bank array 310s. Here, s is an integer greater than 1. For example, when the semiconductor memory device 200 is a DDR4 SDRAM, s may be sixteen, and when the semiconductor memory device 200 is an LPDDR4 SDRAM, s may be eight. However, the inventive concept herein is not limited thereto. Hereinafter, for the purpose of discussion, it is assumed that the semiconductor memory device 200 is a DDR4 SDRAM and s is sixteen. However, it will be understood that the example of s being sixteen is not intended to limit the embodiments of the inventive concept.

[0042] The row decoder 260 may include a first bank row decoder 260a to an s-th (e.g., sixteenth) bank row decoder 260s respectively coupled to the first bank array 310a to the s-th (e.g., sixteenth) bank array 310s. The column decoder 270 may include a first bank column decoder 270a to an s-th (e.g., sixteenth) bank column decoder 270s respectively coupled to the first bank array 310a to the sixteenth bank array 310s. And the sense amplifier unit 285 may include a first bank sense amplifier 285a to an s-th (e.g., sixteenth) bank sense amplifier 285s respectively coupled to the first bank array 310a to the sixteenth bank array 310s. The first bank array 310a to the sixteenth bank array 310s, the first bank row decoder 260a to the sixteenth bank row decoder 260s, the first bank column decoder 270a to the sixteenth bank column decoder 270s, and the first bank sense amplifier 285a to the sixteenth bank sense amplifier 285s may form the first bank to the sixteenth bank. Each of the first bank array 310a to the sixteenth bank array 310s may include a plurality of memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BTL.

[0043] The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100. The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230, may provide the received row address ROW_ADDR to the row address multiplexer 240, and may provide the received column address COL_ADDR to the column address latch 250.

[0044] The bank control logic 230 may generate bank control signals in response to the bank address BANK_ADDR. One bank row decoder corresponding to the bank address BANK_ADDR among the first bank row decoder 260a to the sixteenth bank row decoder 260s may be activated in response to the bank control signals, and one bank column decoder corresponding to the bank address BANK_ADDR among the first bank column decoder 270a to the sixteenth bank column decoder 270s may be activated in response to the bank control signals.

[0045] The row address multiplexer 240 can receive the row address ROW_ADDR from the address register 220 and can receive the refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 can selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 can be applied to the first bank row decoder 260a to the sixteenth bank row decoder 260s.

[0046] Among the first bank row decoder 260a to the sixteenth bank row decoder 260s, the activated (i.e., activated by the bank control logic 230) bank row decoder can decode the row address RA output from the row address multiplexer 240 and can activate the word line corresponding to the row address RA. For example, the activated bank row decoder can apply the word line drive voltage to the word line corresponding to the row address RA.

[0047] The column address latch 250 can receive the column address COL_ADDR from the address register 220 and can temporarily store the received column address COL_ADDR. In some example embodiments, in burst mode, the column address latch 250 can generate a column address incremented from the received column address COL_ADDR. The column address latch 250 can apply the temporarily stored or generated column address to the first bank column decoder 270a to the sixteenth bank column decoder 270s.

[0048] Among the first bank column decoder 270a to the sixteenth bank column decoder 270s, the activated bank column decoder can activate the sense amplifier corresponding to the bank address BANK_ADDR and / or the column address COL_ADDR through the I / O strobe circuit 290. The I / O strobe circuit 290 can include a circuit for strobbing input / output data, and can also include a read data latch for storing the data output from the first bank array 310a to the sixteenth bank array 310s, and a write driver for writing data to the first bank array 310a to the sixteenth bank array 310s.

[0049] The codeword CW read from one of the first to sixteenth memory bank arrays 310a to 310s can be sensed by a sense amplifier coupled to the one memory bank array from which data is to be read, and can be stored in a read data latch. After the ECC engine 400 performs ECC decoding on the codeword CW, the codeword CW stored in the read data latch can be provided to the memory controller 100 through the data I / O buffer 295. The main data MD to be written into one of the first to sixteenth memory bank arrays 310a to 310s can be provided from the memory controller 100 to the data I / O buffer 295, can be provided to the ECC engine 400, can generate parity data based on the main data MD, and the main data MD and the parity data can be written into a memory bank array by a driver.

[0050] The data I / O buffer 295 can, based on the clock signal CLK, in a write operation of the semiconductor memory device 200, provide the main data MD from the memory controller 100 to the ECC engine 400, and / or can, in a read operation of the semiconductor memory device 200, provide the main data MD from the ECC engine 400 to the memory controller 100. The data I / O buffer 295 can also provide a data mask signal DM indicating a masked write operation to the ECC engine 400.

[0051] In a masked write operation, the ECC engine 400 can perform a read-modify operation by: receiving data and parity data as read data and read parity data from a subpage of a target page in the memory cell array 300, correcting at least one error bit in the read data based on the read parity data to generate corrected data, and generating first parity data based on the corrected data and first write data. Additionally, the ECC engine 400 can generate first parity data based on the main data MD in a normal write operation.

[0052] Additionally, in a read operation, the ECC engine 400 can receive the codeword CW read from one memory bank array from the I / O strobe circuit 290. The ECC engine 400 can perform ECC decoding on the main data MD based on the parity data to correct at least one error bit in the main data, and can provide the corrected data to the data I / O buffer 295.

[0053] The control logic circuit 210 can control the operation of the semiconductor memory device 200. For example, the control logic circuit 210 can generate control signals for the semiconductor memory device 200 to perform write operations and / or read operations. The control logic circuit 210 can include a command decoder 211 and a mode register 212. The command decoder 211 decodes the command CMD received from the memory controller 100, and the mode register 212 sets the operation mode of the semiconductor memory device 200.

[0054] For example, the command decoder 211 can generate control signals corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc. The control logic circuit 210 can generate a first control signal CTL1 for controlling the I / O strobe circuit 290 and / or a second control signal CTL2 for controlling the ECC engine 400.

[0055] Figure 3 shows Figure 2 an example of the first bank array 310a in the semiconductor memory device 200.

[0056] Referring to Figure 3 , the first bank array 310a can include a plurality of word lines WL1 - WLm (where m is a natural number greater than 2), a plurality of bit lines BTL1 - BTLn (where n is a natural number greater than 2), and a plurality of memory cells MC disposed at the intersections between the word lines WL1 - WLm and the bit lines BTL1 - BTLn. Each memory cell MC can include an access (cell) transistor coupled to one of the word lines WL1 - WLm and one of the bit lines BTL1 - BTLn, and a storage (cell) capacitor coupled to the cell transistor.

[0057] Figure 4 shows Figure 2 the first bank array 310a and the ECC engine 400 shown in the semiconductor memory device.

[0058] In Figure 4 , for convenience, the first bank array 310a is shown, however, the details discussed herein related to the first bank array 310a can be applied to other banks in the bank arrays 310a - 310s.

[0059] Referring to Figure 4, the first memory bank array 310a may be divided into pages, where each page includes sub - pages and parity data associated with the respective sub - pages. For example, the size of each page of the first memory bank array 310a may be 8Kb, and the size of each sub - page of the page may be 64b, but the inventive concept is not limited thereto. 8b of parity data may be stored for each sub - page. Thus, in this example, the first memory bank array 310a may include 128 sub - pages and 1024 parity bits associated with a given page of the first memory bank array 310a. Data from each sub - page having a size of 64b and the corresponding parity data having a size of 8b may be sequentially read and provided to the ECC engine 400. Figure 4 The page and sub - page sizes are merely examples and are not intended to limit the inventive concept.

[0060] Figure 5 Shows a part of the semiconductor memory device 200 during write and read operations Figure 3 of.

[0061] In Figure 5 , the control logic circuit 210, the first memory bank array 310a, the I / O strobe circuit 290, the ECC engine 400, the parity first - in - first - out (FIFO) buffer 281, and the address FIFO buffer (which may also be referred to as a column address FIFO buffer) 283, the first sub - column decoder (SCD1) 271, and the second sub - column decoder (SCD2) 272 are shown.

[0062] Referring to Figure 5 , the first memory bank array 310a may include a data region DCR and a parity region PCR. The data region DCR may include a plurality of first memory blocks MB0 - MB7, i.e., 311 - 313, and the parity region PCR may include at least a second memory block EDB, i.e., 314. Figure 5 The number of the first memory blocks 311 - 313 and the number of the second memory blocks 314 shown are provided as examples and are not intended to limit the inventive concept. The first memory blocks 311 - 313 may be memory blocks that determine the storage capacity of the semiconductor memory device 200. The second memory block 314 may be used for ECC and / or redundancy repair.

[0063] In each of the first memory blocks 311 - 313, a plurality of first memory cells may be arranged in rows and columns. In the second memory block 314, a plurality of second memory cells may be arranged in rows and columns.

[0064] The I / O strobe circuit 290 may include a plurality of switch circuits (MUX) 291a - 291d respectively connected to the first memory blocks 311 - 313 and the second memory block 314. The I / O strobe circuit 290 may further include an I / O read amplifier (IOSA) 292a and a write driver (WRDRV) 292b connected to the data region DCR through the switch circuits 291a - 291c, and an I / O read amplifier 293a and a write driver 293b connected to the parity region PCR through the switch circuit 291d. In the semiconductor memory device 200, bit lines corresponding to data of a burst length (BL) may be accessed simultaneously to support the BL representing the maximum number of accessible column positions. For example, the BL may be set to 8.

[0065] The ECC engine 400 may be connected to the switch circuits 291a - 291d through a first data line GIO and a second data line EDBIO.

[0066] The control logic circuit 210 may decode the command CMD to generate a first control signal CTL1 for controlling the switch circuits 291a - 291d and a second control signal CTL2 for controlling the ECC engine 400. The control logic circuit 210 may provide a third control signal CTL3 to the address FIFO buffer 283 and the first sub - column decoder 271, and may provide a fourth control signal CTL4 to the parity FIFO buffer 281 and the address FIFO buffer 283.

[0067] The control logic circuit 210 may include a command monitor 213 that monitors the reception timing of the first command CMD and the reception timing of the second command CMD received from the memory controller 100.

[0068] When the first command CMD is a (normal) write command (e.g., an unmasked write command), the control logic circuit 210 may provide the first control signal CTL1 to the I / O strobe circuit 290 such that the write data MD (first write data) is written into a target page in the data region DCR, and may provide the second control signal CTL2 to the ECC engine 400. The ECC engine 400 may perform ECC encoding on the write data MD based on the second control signal CTL2 to generate write parity data WPRT, and may store the write parity data WPRT in the parity FIFO buffer 281. In some embodiments, the ECC engine 400 may provide the write data MD as write data WMD to the I / O strobe circuit 290 to write it into the data region DCR.

[0069] The control logic circuit 210 can adjust a first write timing for writing parity data to be written (WPRT) to the parity region PCR based on whether a second command CMD is received after the first command CMD within a reference time interval.

[0070] For example, in response to the control logic circuit 210 receiving the second command CMD before the expiration of the reference time interval, the control logic circuit 210 can control the I / O strobe circuit 290, the address FIFO buffer 283, and / or the parity FIFO buffer 281 such that the parity data to be written (first parity data) WPRT is written to the parity region PCR at a second timing when the write data WMD (second write data) received in association with and / or via the second command CMD is written to the data region DCR.

[0071] For example, in response to the control logic circuit 210 receiving the second command CMD after the expiration of the reference time interval, the control logic circuit 210 can control the I / O strobe circuit 290, the address FIFO buffer 283, and / or the parity FIFO buffer 281 such that the parity data to be written WPRT is written to the parity region PCR in response to an internal write command that is generated by the control logic circuit 210 at a second timing at the end of the reference time interval.

[0072] For example, in response to the first command (e.g., the first write command) specifying a masked write operation, the control logic circuit 210 can control the I / O strobe circuit 290 and the ECC engine 400 to perform a read - modify operation such that: the I / O strobe circuit 290 selects a sub - page of a target page corresponding to the target address received in association with and / or via the first command to read data and parity data from the sub - page; the data and parity data are provided as read data RMD and read parity data RPRT to the ECC engine 400; the ECC engine 400 corrects at least one error bit in the read data RMD based on the read parity data RPRT to generate corrected data, generates first parity data based on the corrected data and the first write data, and stores the first parity data in the parity FIFO buffer 281.

[0073] For example, in response to the first command (e.g., the first write command) specifying a masked write operation, the ECC engine 400 can, under the control of the control logic circuit 210, perform ECC encoding on the write data MD to generate first parity data and store the first parity data in the parity FIFO buffer 281.

[0074] For example, in response to a first command specifying a read operation, the I / O strobe circuit 290 may read data and parity data from a sub-page under the control of the control logic circuit 210, and provide the data and parity data as read data RMD and read parity data RPRT to the ECC engine 400. The ECC engine 400 may correct at least one error bit in the read data RMD based on the read parity data RPRT to generate corrected data C_MD, and may provide the corrected data C_MD to the data I / O buffer 295.

[0075] The first sub-column decoder 271 may decode the column address CADDR, and may activate the column select signal CSL in response to a third control signal CTL3 to access the data region DCR.

[0076] The parity FIFO buffer 281 may store the write parity data WPRT, and provide the delayed write parity data WPRT_D to the write driver 293b in response to a fourth control signal CTL4. The parity FIFO buffer 281 may provide the delayed write parity data WPRT_D to the write driver 293b at the write timing, or at the timing when an internal write command is generated in response to the fourth control signal CTL4, for writing the second write data MD.

[0077] The address FIFO buffer 283 may store the column address CADDR, and provide the delayed column address CADDR_D to the second sub-column decoder 272 in response to at least one of the third control signal CTL3 and the fourth control signal CTL4. The address FIFO buffer 283 may provide the delayed column address CADDR_D to the second sub-column decoder 272 at the write timing, or at the timing when an internal write command is generated in response to the fourth control signal CTL4, for writing the second write data MD.

[0078] The second sub-column decoder 272 may decode the delayed column address CADDR_D and activate the parity column select signal PCSL to access the parity region PCR.

[0079] In some embodiments, the first sub-column decoder 271 and the second sub-column decoder 272 may be included in Figure 2 the bank column decoder 270a in

[0080] Figure 6 is a block diagram showing an example of the Figure 5 ECC engine 400 in an example embodiment according to the inventive concept.

[0081] In Figure 6For ease of explanation, a data I / O buffer 295 is included in the illustration.

[0082] Referring Figure 6 , the ECC engine 400 may include a parity generator 410, an ECC decoder 430, and a flag generator 470.

[0083] The ECC decoder 430 may include a syndrome generation circuit 440, a syndrome decoder 450, and a data corrector 460. The syndrome generation circuit 440 may include a check bit generator 441 and a syndrome generator 443.

[0084] In some embodiments, the syndrome generation circuit 440 may be connected to the memory cell array 300 (e.g., the first bank array 310a) through the I / O strobe circuit 290, the syndrome decoder 450 may be connected to the syndrome generation circuit 440, and the data corrector 460 may be connected to the syndrome decoder 450.

[0085] The flag generator 470 may receive a data mask signal DM, may output a flag signal FL having a first logic level (e.g., high level) when the data mask signal DM designates a masked write operation, and may output a flag signal FL having a second logic level (e.g., low level) when the data mask signal DM designates a normal (e.g., non-masked) write operation. The flag generator 470 may provide the flag signal FL to the parity generator 410 and / or the ECC decoder 430.

[0086] The parity generator 410 may generate write parity data WPRT based on the flag signal FL using write data WMD, or may combine the write data WMD and the corrected data C_MD to generate the write parity data WPRT. In some embodiments, the write data WMD may be associated with the data MD provided to the ECC engine 400 by the data I / O buffer 295. For example, in some embodiments, when the command CMD is a write command, the write data WMD may correspond to the data MD.

[0087] The parity generator 410 may generate write parity data WPRT by performing ECC encoding on the write data WMD based on the flag signal FL, or may generate the write parity data WPRT by combining the write data WMD and the corrected data C_MD and performing ECC encoding on the combined data.

[0088] The check bit generator 441 may generate check bits CHB based on read data RMD. The syndrome generator 443 may generate syndrome data SDR by performing a bit-by-bit comparison of the read parity data RPRT with the corresponding bits of the check bits CHB.

[0089] The syndrome decoder 450 may decode the syndrome data SDR to generate an error position signal EPS indicating the position of at least one error bit in the read data RMD.

[0090] The data corrector 460 may receive the error position signal EPS and the read data RMD, correct at least one error bit in the read data RMD, and provide the corrected data C_MD to the parity generator 410 and the data I / O buffer 295.

[0091] In a mask write operation, the data corrector 460 may provide the corrected data C_MD to the parity generator 410, and in a read operation, the data corrector 460 may provide the corrected data C_MD to the parity generator 410 and the data I / O buffer 295.

[0092] Figure 7 is a block diagram showing an example of the command monitor 213 in Figure 5 an example embodiment according to the inventive concept.

[0093] Referring to Figure 7 , the command monitor 213 may include a timer 214, an interval comparator 215, and a register 216. The register 216 may store a time interval corresponding to a reference time interval RINT and / or the number of trigger times of the clock signal CLK during the reference time interval RINT.

[0094] The timer 214 may receive a command CMD (e.g., a first command and / or a second command), generate an interval signal INS having a predetermined pulse width when the command CMD is received, and provide the interval signal INS to the interval comparator 215.

[0095] The interval comparator 215 may start a counting operation of counting the clock signal CLK at a time point when the interval signal INS corresponding to the first command CMD is applied, and may output a determination signal DS having a first pulse width in response to the second command CMD being applied before the reference time interval RINT expires.

[0096] The interval comparator 215 may output a determination signal DS having a second pulse width at a time point when the reference time interval RINT ends in response to the reference time interval RINT expiring without receiving the second command CMD, or in response to the second command being applied after the reference time interval RINT expires.

[0097] In addition, when the interval comparator 215 outputs a determination signal DS, the interval comparator 215 may apply a reset signal RST to the timer 214 to reset the timer 214.

[0098] Figure 8 and Figure 9 illustrates master data and data mask signals according to an exemplary embodiment of the inventive concept.

[0099] Referring to Figure 8 and Figure 9 , the master data MD may include a plurality of unit data UN1-UNr (r is a natural number greater than 2), and each unit data UN1-UNr may include a plurality of data bits. The data mask signal DM may include a plurality of mask bits DMB1-DMBr corresponding to the unit data UN1-UNr.

[0100] Each mask bit DMB1-DMBr may indicate whether to write the corresponding unit data in the unit data UN1-UNr. The mask bit having a first logic level among the mask bits DMB1-DMBr indicates that the corresponding unit data is masked.

[0101] As Figure 8 shown, when at least one of the mask bits DMB1-DMBr has a first logic level (e.g., "H"), a masked write operation may be performed on the master data MD. As Figure 9 shown, if all the mask bits DMB1-DMBr have a second logic level (e.g., "L"), a normal (e.g., non-masked) write operation may be performed on the master data MD.

[0102] Figure 10 illustrates an example of a Figure 6 flag generator in accordance with an exemplary embodiment of the inventive concept.

[0103] Referring to Figure 10 , the flag generator 470 may include an "OR" gate 471, and the "OR" gate 471 performs an "OR" operation on the mask bits DMB1-DMBr to output a flag signal FL.

[0104] When at least one of the mask bits DMB1-DMBr has a first logic level (e.g., "H"), the flag signal FL has a first logic level and designates a masked write operation.

[0105] When all the mask bits DMB1-DMBr have a second logic level (e.g., "L"), the flag signal FL has a second logic level and designates a normal (e.g., non-masked) write operation.

[0106] Figure 11 is an illustration of an exemplary embodiment according to the inventive concept.Figure 5 Timing diagram of an example operation of a semiconductor memory device.

[0107] Referring to Figures 5 to 7 and Figure 11 When the internal command ICMD generated by the control logic circuit 210 in response to a write command from the memory controller 100 specifies a write operation WR, if a time interval tWRITE has elapsed since the write operation WR was specified, the write column selection signal WCSL can be activated, and if the write column selection signal WCSL is activated, the write data WMD can be written into the target page in the data area DCR.

[0108] Here, the time interval tWRITE can represent such a time interval: starting when the write operation WR is started and ending before the write data WMD is written. That is, the time interval tWRITE can represent an asynchronous delay corresponding to the time interval: starting when the internal write command is generated and ending when the write data WMD is written into the target page in the data area DCR.

[0109] In particular, when a time interval corresponding to the sum of the write wait time and half of the burst length has elapsed since the control logic circuit 210 received the write command from the memory controller 100, a write signal specifying the write operation WR can be generated inside the semiconductor memory device 200.

[0110] A command CMD specifying a masked write operation MWR can be provided from the memory controller 100 after a column access delay time tCCD_L has elapsed since the write operation WR was specified. Assume that the column access delay time tCCD_L is less than the reference time interval RINT. In response to the internal command ICMD specifying the masked write operation MWR, the internal read column selection signal iRCSL for reading data and parity data from the sub-page of the target page can be activated, and the data and parity data from the sub-page can be provided to the ECC engine 400 as read data and read parity data.

[0111] If a time interval tWRITE has elapsed since the time point when the masked write operation WMR was specified, the masked write column selection signal M_WCSL can be activated, and when the masked write column selection signal M_WCSL is activated, the unmasked write data unM_WMD can be written into the target page in the data area DCR.

[0112] The write column select signal WCSL of the parity check region PCR can be activated at the time point when the mask write column select signal M_WCSL is activated. The write parity data WPRT is generated based on the write data WMD before the write column select signal WCSL of the parity check region PCR is activated, and the write parity data WPRT can be written into the corresponding region of the parity check region PCR in response to the activated write column select signal WCSL.

[0113] Since the ECC engine 400 has not received a new command during the time interval tPRTGEN (also shown as INT1) since the mask write operation MWR is specified, the ECC engine 400 can combine the unmasked write data unM_WMD and the read data to generate parity data MPRT corresponding to the combined data.

[0114] Since the control logic circuit 210 has not received a new command during the time interval corresponding to the sum of the first time interval INT1 and the second time interval INT2 since the mask write operation MWR is specified, the control logic circuit 210 can generate an internal write command iWR at the time point when the time interval tPRTGEN ends, and can activate the internal write column select signal iWCSL associated with the parity check region PCR in response to the internal write command iWR.

[0115] Here, the first time interval INT1 corresponds to the time interval tPRTGEN, during which the ECC engine 400 generates the first parity data based on the first write data; the second time interval INT2 corresponds to the interval from the first time point to the second time point. At the first time point, the first write data WMD received by and / or associated with the first command is written into the target page of the data region DCR. At the second time point, the first write data WMD can be read from the target page of the data region DCR. The reference time interval RINT can be equal to or greater than the sum of the first time interval INT1 and the second time interval INT2. The second time interval INT2 corresponds to the time interval starting when the write column select signal WCSL is activated and ending exactly before the internal read column select signal iRCSL is activated.

[0116] When the internal write column select signal iWCSL is activated, the parity data MPRT corresponding to the combined data can be written into the corresponding position of the parity check region PCR. Here, the time interval tPRTGEN corresponds to the time interval during which the ECC engine 400 generates the parity data MPRT based on the combined data.

[0117] After generating the internal write command iWR, a command-specified read operation RD or precharge operation PRE from the memory controller 100 can be responded to.

[0118] Figure 12 shows that Figure 5 the semiconductor memory device 200 performs a normal (unmasked) write operation.

[0119] Referring to Figure 5 , Figures 8 to 10 and Figure 12 , when the flag signal FL has a second logic level and designates a normal write operation, the parity generator 410 can generate 8-bit write parity data WPRT based on 64-bit write data MD as indicated by reference flag 512, and the ECC engine 400 can write the 64-bit write data MD into the target page of the data region DCR in the first bank array 310a as indicated by reference flag 511, and then the ECC engine 400 can write the 8-bit write parity data WPRT into the corresponding position in the parity region PCR in the first bank array 310a as indicated by reference flag 513.

[0120] Figure 13 shows that Figure 5 the semiconductor memory device 200 performs a masked write operation.

[0121] Referring to Figure 5 , Figures 8 to 10 and Figure 13 , when the flag signal FL has a first logic level and designates a masked write operation, the I / O strobe circuit 290 can perform a read operation as indicated by reference flag 533, and can read data 521 and first parity data PRT1 from the sub-pages of the target page in the first bank array 310a as indicated by reference flags 531 and 532 respectively, and supply the data 521 and the first parity data PRT1 to the ECC decoder 430.

[0122] The ECC decoder 430 can perform ECC decoding on the data 521 based on the first parity data PRT1 as indicated by reference flag 534, and can supply the corrected data 521' to the parity generator 410.

[0123] The parity generator 410 can merge (e.g., modify) the masked write data M_MD and the corrected data 521' to generate second parity data PRT2 as indicated by reference flag 535. The I / O strobe circuit 290 can write the second parity data PRT2 into the corresponding position in the parity region PCR in the first bank array 310a after writing the masked write data M_MD into the target storage location in the first bank array 310a as indicated by reference flag 536.

[0124] In Figure 13In this case, the data 521 may include 64 bits and may include an error bit ER, and the corrected data 521' may include 64 bits. The first parity data PRT1 may include 8 bits, and the second parity data PRT2 may include 8 bits.

[0125] Figure 14 is a flowchart showing a method of operating a semiconductor memory device 200 according to an exemplary embodiment of the inventive concept.

[0126] Referring to Figures 2 to 14 , a method of operating a semiconductor memory device 200 is provided. The semiconductor memory device 200 includes: a memory cell array 300 including a data region and a parity region; an ECC engine 400; and a control logic circuit 210 that controls the ECC engine 400.

[0127] In this method, in operation S100, the control logic circuit 210 may receive a first command and a first address from an external memory controller 100.

[0128] In operation S200, the control logic circuit 210 may control the ECC engine 400 and the I / O gating circuit 290 such that while the I / O gating circuit 290 writes main data (e.g., write data) associated with and / or received through the first command to a target page in the data region, the ECC engine 400 generates first parity data based on the main data.

[0129] In operation S300, the control logic circuit 210 may adjust a first write timing to write the first parity data to the parity region based on the reception timing of a second command from the memory controller 100.

[0130] Figure 15 is a flowchart showing Figure 14 the operation of generating first parity data while writing write data to the data region in

[0131] Referring to Figures 2 to 15 , to generate first parity data while writing main data (e.g., write data) to the data region in operation S200, the control logic circuit 210 determines whether the first command specifies a masked write operation in operation S210.

[0132] When the first command specifies a normal (e.g., non-masked operation) write operation (No in S210), in operation S230, the control logic circuit 210 may control the ECC engine 400 to generate first parity data based on the main data.

[0133] When the first command specifies a masked write operation (Yes in S210), in operation S250, the control logic circuit 210 can control the ECC engine 400 and the I / O strobe circuit 290 to perform a read-modify operation in the background (e.g., perform the read-modify operation concurrently with other operations) to generate first parity data.

[0134] The control logic circuit 210 can control the ECC engine 400 and the I / O strobe circuit to perform a read-modify operation such that: the I / O strobe circuit 290 selects a sub-page of a target page corresponding to the target address received through the first command, reads data and parity data from the sub-page, and provides the data and parity data as read data and read parity data to the ECC engine 400. The ECC engine 400 corrects at least one error bit in the read data based on the read parity data to generate corrected data, and generates first parity data based on the corrected data and the first write data.

[0135] Figure 16 is a flowchart showing the operations of performing Figure 14 the read-modify operation in

[0136] Referring to Figures 2 to 14 and Figure 16 , to perform a read-modify operation in operation S300 to generate first parity data, the control logic circuit 210 can determine in operation S310 whether a second command is received before the expiration of a reference time interval.

[0137] If a second command is received before the expiration of the reference time interval (Yes in S310), then in operation S330, the control logic circuit 210 can control the ECC engine 400 and the I / O strobe circuit 290 such that the first parity data is written to the parity region at a second timing when the second write data received through the second command is written to the data region.

[0138] If a second command is received after the expiration of the reference time interval (No in S310), then in operation S350, the control logic circuit 210 can control the ECC engine 400 and the I / O strobe circuit 290 such that the first parity data is written to the parity region in response to an internal write command, which is generated by the control logic circuit 210 at a second timing at the end of the reference time interval.

[0139] As described above, the reference time interval corresponds to the time interval during which the parity generator 410 generates first parity data based on the write data or the merged data.

[0140] The control logic circuit 210 can control the I / O strobe circuit 290, the address FIFO buffer 283, and / or the parity FIFO buffer 281 such that the first write data and the first parity data are respectively written into the data region and the parity region based on the same column address at different timings (e.g., at different times). The control logic circuit 210 can control the I / O strobe circuit 290, the address FIFO buffer 283, and / or the parity FIFO buffer 281 such that the first write data and the first parity data are respectively written into the data region DCR and the parity region PCR based on the column selection signals activated at different timings (e.g., at different times). Accordingly, based on the same column address, the first write data can be written into the data region at a first time, and the first parity data can be written into the parity region at a second time after the first time.

[0141] In addition, the control logic circuit 210 can cause the generation of the first parity data to be included in the background operation of the semiconductor memory device 200 such that the writing of the write data is not affected by the generation of the first parity data. Accordingly, the semiconductor memory device 200 can separate the writing timing of the write data and the writing timing of the parity data, and can improve the performance.

[0142] Figure 17 is a block diagram illustrating a semiconductor memory device 600 according to an exemplary embodiment of the inventive concept.

[0143] Referring to Figure 17 , the semiconductor memory device 600 may include: a first set of dies 610 and a second set of dies 620 that provide soft error analysis and correction functions in a stacked chip structure. In some embodiments, the second set of dies 620 may be a high bandwidth memory (HBM).

[0144] The first set of dies 610 may include at least one buffer die 611. The second set of dies 620 may include a plurality of memory dies 620-1 to 620-p, and the plurality of memory dies 620-1 to 620-p may be stacked on the first set of dies 610 and may transfer data through a plurality of through-silicon via (TSV) lines.

[0145] Each of the memory dies 620-1 to 620-p may include a cell core 622, and the cell core 622 may include a memory cell array including a data region and a parity region, an I / O strobe circuit, and a control logic circuit such as according to the inventive concept described herein.

[0146] The buffer die 611 may include an ECC engine 612. When a transmission error is detected in the transmission data received through the TSV lines, the ECC engine 612 corrects the transmission error using the transmission parity bits and generates error-corrected data. The ECC engine 612 may be referred to as a path ECC engine.

[0147] In some embodiments, the semiconductor memory device 600 may be a stacked chip type memory device or a stacked memory device that transmits data and control signals through TSV lines. The TSV lines may also be referred to as through electrodes.

[0148] The transmission errors that occur during data transmission may be caused by noise in the TSV lines. The data failures caused by the noise in the TSV lines can be distinguished from the data failures caused by the malfunctioning of the memory die. Therefore, the data failures caused by the noise in the TSV lines can be regarded as soft data failures (or soft errors). Soft data failures may be caused by transmission failures on the transmission path and can be detected and corrected through ECC operations.

[0149] For example, when the transmission data is 64-bit data, the transmission parity bits may be set to 8 bits. However, the scope and spirit of the inventive concept are not limited thereto. The number of transmission parity bits may be increased or decreased.

[0150] Through the above description, the TSV line group 632 formed in one memory die 620-p may include 64 TSV lines L1 to Lp, and the parity check TSV line group 634 may include 8 TSV lines L10 to Lq.

[0151] The TSV lines L1 to Lp of the data TSV line group 632 and the parity check TSV lines L10 to Lq of the parity check TSV line group 634 may be connected to the microbumps MCB formed correspondingly between the memory dies 620-1 to 620-p.

[0152] Each of the memory dies 620-1 to 620-p may include DRAM cells, and each DRAM cell includes at least one access transistor and one storage capacitor.

[0153] The semiconductor memory device 600 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with a host through a data bus B10. The buffer die 611 may be connected to the host through the data bus B10.

[0154] The ECC engine 612, represented as a path ECC circuit, can determine whether a transmission error has occurred in the transmission data received through the data TSV line group 632 based on the transmission parity bits received through the parity TSV line group 634. When a transmission error is detected, the ECC engine 612 can use the transmission parity bits to correct the transmission error on the transmission data. When the transmission error is uncorrectable, the ECC engine 612 can output information indicating that an uncorrectable data error has occurred.

[0155] The ECC engine 612 can employ Figure 4 the ECC engine 400. Accordingly, the ECC engine 612 can separately set the timing of writing data and the timing of writing parity data. In some embodiments, at least one of the memory dies 620-1 to 620-p can employ Figure 4 the ECC engine 400. In this case, the ECC engine included in at least one of the memory dies 620-1 to 620-p can separately (adjust) the writing timing of writing data and the writing timing of writing parity data.

[0156] When an error is detected in the read data from a high bandwidth memory (HBM) or a stacked memory structure, the error may be an error that occurs due to noise during data transmission through the TSV.

[0157] According to an exemplary embodiment of the inventive concept, as Figure 17 shown, the ECC engine 612 can be included in the buffer die 611. Accordingly, soft data failures can be detected and corrected. Soft data failures can include transmission errors generated due to noise during data transmission through the TSV lines.

[0158] Figure 18 is a cross-sectional view of a 3D chip structure 700 of a semiconductor memory device 600 employing Figure 17 according to an exemplary embodiment of the inventive concept.

[0159] Figure 18 The 3D chip structure 700 in which the host and the HBM are directly connected without an interposer is shown.

[0160] Referring to Figure 18 , a host die 710 (such as, for example, a system-on-chip (SoC), a central processing unit (CPU), and / or a graphics processing unit (GPU)) can be disposed on a printed circuit board (PCB) 720 using flip chip bumps (FB). Memory dies D11 to D14 can be stacked on the host die 720 to implement the HBM structure 620 of the memory dies as in Figure 17 . In Figure 18 , Figure 17The buffer die 611 or the logic die. However, in some embodiments, the buffer die 611 or the logic die may be disposed between the memory die D11 and the host die 720. To implement the HBM (620) structure, TSV lines may be formed in the memory dies D11 to D14. The TSV lines may be electrically connected to the micro-bumps MCB located between the memory dies.

[0161] Figure 19 is a diagram illustrating a semiconductor package 900 including a stacked memory device according to an exemplary embodiment of the inventive concept.

[0162] Referring to Figure 19 , the semiconductor package 900 may include one or more stacked memory devices 910 and a memory controller 920.

[0163] The stacked memory device 910 and the memory controller 920 may be mounted on an interposer 930, and the interposer 930 on which the stacked memory device 910 and the memory controller 920 are mounted may be mounted on a package substrate 940.

[0164] In some embodiments, one of the stacked memory devices 910 may employ Figure 17 the semiconductor memory device 600 in, and the memory controller 920 may employ Figure 1 the memory controller 100 in.

[0165] Each stacked memory device 910 may be implemented in various forms and may be a memory device in the form of a high bandwidth memory (HBM) having multiple stacked layers. Thus, in some embodiments, each stacked memory device 910 may include a buffer die and a plurality of memory dies. The buffer die may include an ECC engine, such as the ECC engine 400 described herein, each memory die may include a memory cell array, such as the memory cell array 300 described herein, and the memory cell array may include a data region (e.g., DCR) and a parity region (e.g., PCR). Additionally, each memory die may include an address FIFO buffer and a parity FIFO buffer such as those described herein. Thus, each memory die may separate the write timing of the write data and the write timing of the write parity data, and may adjust the write timing of the parity data.

[0166] Multiple stacked memory devices 910 may be mounted on an interposer 930, and a memory controller 920 may communicate with the multiple stacked memory devices 910. For example, each of the stacked memory devices 910 and the memory controller 920 may include a physical region, and communication may be performed between the stacked memory device 910 and the memory controller 920 through the physical region. In some embodiments, when each stacked memory device 910 includes a direct access region, test signals may be provided to each stacked memory device 910 through conductive devices (e.g., solder balls 950) mounted under a package substrate 940 and the direct access region.

[0167] As described above, according to an exemplary embodiment of the inventive concept, a semiconductor memory device may adjust a write timing of parity data based on reception timings of a first command and a second command. Additionally, the semiconductor memory device may include generation of parity data in a background operation of the semiconductor memory device such that a write of write data is not affected by the generation of the parity data. Accordingly, the semiconductor memory device may separate a write timing of the write data and a write timing of writing the parity data and may improve performance.

[0168] Aspects of the present disclosure may be applied to semiconductor memory devices and various systems using semiconductor memory devices.

[0169] The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although some example embodiments have been described, it will be readily apparent to those skilled in the art that many modifications may be made to the example embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined by the claims.

Claims

1. A semiconductor memory device, comprising: A memory cell array including a data area and a parity area; An error correction code engine; An input / output strobe circuit connected to the error correction code engine and the memory cell array; And A control logic circuit configured to generate control signals by decoding commands received from a memory controller, wherein the error correction code engine is configured to generate first parity data based on first write data associated with a first command, and wherein the control logic circuit is further configured to: adjust a first write timing for writing the first parity data into the parity area based on a reception timing of a second command following the first command and a reference time interval.

2. The semiconductor memory device according to claim 1, further comprising: An address first-in-first-out buffer configured to store column addresses for accessing the parity area; And A parity first-in-first-out buffer configured to store the first parity data.

3. The semiconductor memory device according to claim 2, wherein, The control logic circuit is further configured to: in response to the control logic circuit receiving the second command before the reference time interval expires, control the input / output strobe circuit, the address first-in-first-out buffer, and the parity first-in-first-out buffer such that the first parity data is written into the parity area in response to second write data associated with the second command being written into the data area.

4. The semiconductor memory device according to claim 2, wherein, The control logic circuit is further configured to: in response to the control logic circuit receiving the second command after the reference time interval expires, control the input / output strobe circuit, the address first-in-first-out buffer, and the parity first-in-first-out buffer such that the first parity data is written into the parity area in response to an internal write command generated by the control logic circuit in response to the expiration of the reference time interval.

5. The semiconductor memory device according to claim 2, wherein The control logic circuit is further configured to: control the input / output strobe circuit, the address first-in-first-out buffer, and the parity first-in-first-out buffer such that the first write data and the first parity data are respectively written into the data area and the parity area based on a first column selection signal and a second column selection signal, and wherein the first column selection signal and the second column selection signal are activated at different timings.

6. The semiconductor memory device according to claim 1, wherein, The reference time interval is equal to or greater than the sum of a first time interval and a second time interval, wherein the first time interval corresponds to an interval during which the error correction code engine generates the first parity data based on the first write data, and wherein the second time interval corresponds to an interval from a first time point when the first write data is written to a second time point when the first write data can be read from the data area.

7. The semiconductor memory device according to claim 1, wherein, The control logic circuit is further configured to: in response to the first command specifying a masked write operation, control the input / output strobe circuit and the error correction code engine to perform a read-modify operation such that: the input / output strobe circuit selects a sub-page of a target page corresponding to a target address associated with the first command, reads data and parity data from the sub-page, and provides the data and the parity data as read data and read parity data to the error correction code engine; and the error correction code engine corrects at least one error bit in the read data based on the read parity data to generate corrected data, and generates the first parity data based on the corrected data and the first write data.

8. The semiconductor memory device according to claim 7, wherein, The control logic circuit is further configured to: control the input / output strobe circuit and the error correction code engine to perform the read-modify operation independently of the write operation of the first write data.

9. The semiconductor memory device according to claim 1, wherein, The control logic circuit is further configured to: based on whether the second command is received before the expiration of the reference time interval, write the first write data to the data area of the memory cell array at a first time and write the first parity data to the parity area of the memory cell array at a second time.

10. The semiconductor memory device according to claim 1, wherein, The error correction code engine includes: an error correction code decoder; and a parity generator, and wherein, the error correction code decoder includes: a syndrome generation circuit, the syndrome generation circuit is connected to the memory cell array through the input / output strobe circuit; a syndrome decoder, the syndrome decoder is connected to the syndrome generation circuit; and a data corrector, the data corrector is connected to the syndrome decoder.

11. The semiconductor memory device according to claim 10, wherein, In response to the first command specifying a masked write operation, the syndrome generation circuit receives data and parity data as read data and read parity data from a sub-page of a target page corresponding to a target address associated with the first command, and generates syndrome data based on the read data and the read parity data, the syndrome decoder decodes the syndrome data to generate an error position signal indicating the position of at least one error bit in the read data, and the data corrector corrects the at least one error bit in the read data based on the error position signal to output corrected data.

12. The semiconductor memory device according to claim 11, wherein, The parity generator is configured to: based on a flag signal, combine the first write data and the corrected data to generate the first parity data.

13. The semiconductor memory device according to claim 12, further comprising a flag generator configured to generate the flag signal based on a data mask signal specifying the masked write operation.

14. The semiconductor memory device according to claim 10, wherein, The parity generator is configured to, in response to the first command specifying a normal write operation, generate the first parity data using the first write data.

15. The semiconductor memory device according to claim 1, wherein, The control logic circuit includes a command monitor configured to monitor the reception timing of the first command and the reception timing of the second command, and wherein the control logic circuit is configured to further generate the control signal based on the monitored result.

16. The semiconductor memory device according to claim 1, wherein, The memory cell array includes a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, and each of the memory cells includes an access transistor and a storage capacitor, wherein the semiconductor memory device further includes: at least one buffer die; and a plurality of memory dies stacked on the at least one buffer die and transmitting data through a plurality of through-silicon vias, wherein the plurality of memory dies includes the memory cell array, and wherein the at least one buffer die includes the error correction code engine.

17. A semiconductor memory device, comprising: a memory cell array including a data area and a parity area; an error correction code engine; an input / output strobe circuit connected to the error correction code engine and the memory cell array; a control logic circuit; an address first-in-first-out buffer configured to store a column address for accessing the parity area; and a parity first-in-first-out buffer configured to store first parity data, wherein the error correction code engine is configured to generate the first parity data based on first write data associated with a first command, and wherein the control logic circuit is configured to control the input / output strobe circuit, the address first-in-first-out buffer, and the parity first-in-first-out buffer such that, based on the same column address, the first write data is written to the data area at a first time and the first parity data is written to the parity area at a second time after the first time.

18. The semiconductor memory device according to claim 17, wherein the control logic circuit is further configured to, in response to the first command specifying a masked write operation, control the input / output strobe circuit and the error correction code engine to perform a read-modify operation such that: the input / output strobe circuit selects a sub-page of a target page corresponding to a target address received together with the first command, reads data and parity data from the sub-page, and provides the data and the parity data as read data and read parity data to the error correction code engine; and the error correction code engine corrects at least one error bit in the read data based on the read parity data to generate corrected data, and generates the first parity data based on the corrected data and the first write data.

19. A semiconductor memory device, comprising: a memory cell array including a data area and a parity area; An error correction code engine configured to write write data associated with a first command into a target page of the data region and generate first parity data based on the write data; And A control logic circuit configured to receive the first command from a storage controller and write the first parity data into the parity region in response to a reception timing of a second command from the storage controller.

20. The semiconductor memory device according to claim 19, wherein, The error correction code engine is configured to write the write data associated with the first command into the data region at a first time, and wherein the control logic circuit is further configured to write the first parity data into the parity region at a second time in response to receiving the second command before the expiration of a reference time interval.

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