High Electron Mobility Transistor Device and Method of Manufacturing the Same

Abstract

The present invention provides a high electron mobility transistor device and a manufacturing method thereof, wherein the device includes a semiconductor layer, a gate electrode, a first dielectric layer, a source field plate, a second dielectric layer, a source electrode, a third dielectric layer, and a drain structure. The gate electrode is disposed on the semiconductor layer. The first dielectric layer is disposed on the gate electrode and has a first groove located on a first side of the gate electrode, wherein a bottom surface of the first groove is lower than a top surface of the gate electrode. The source field plate is disposed on the first dielectric layer and extends from a second side of the gate electrode into the first groove. The second dielectric layer is disposed on the source field plate. The source electrode is disposed on the second dielectric layer and is electrically connected to the source field plate. The third dielectric layer is disposed on the source electrode. The drain structure is disposed on the first side of the gate electrode and penetrates through the third dielectric layer, wherein the first groove is located between the drain structure and the gate electrode.

Description

Technical Field

[0001] The present invention relates to semiconductor manufacturing technology, and more particularly to high electron mobility transistor devices and methods for manufacturing the same. Background Art

[0002] A high electron mobility transistor (HEMT), also known as a heterostructure field effect transistor (HFET) or a modulation-doped field effect transistor (MODFET), is a type of field effect transistor composed of semiconductor materials with different energy gaps. A two-dimensional electron gas layer is generated at the interface adjacent to different semiconductor materials. Due to the high electron mobility of the two-dimensional electron gas, high electron mobility transistor devices can have advantages such as high breakdown voltage, high electron mobility, low on-resistance, and low input capacitance, and are thus suitable for use in high-power components.

[0003] However, although these high electron mobility transistor devices generally meet the requirements, they are still not satisfactory in every aspect. Therefore, it is necessary to further improve high electron mobility transistor devices and methods for manufacturing the same to enhance performance and reliability. Summary of the Invention

[0004] According to some embodiments of the present invention, a high electron mobility transistor device is provided. The high electron mobility transistor device includes a gate electrode disposed on a semiconductor layer; a first dielectric layer disposed on the gate electrode and having a first groove located on a first side of the gate electrode, wherein a bottom surface of the first groove is lower than a top surface of the gate electrode; a source field plate disposed on the first dielectric layer and extending from a second side of the gate electrode into the first groove; a second dielectric layer disposed on the source field plate; a source electrode disposed on the second dielectric layer and electrically connected to the source field plate; a third dielectric layer disposed on the source electrode; and a drain structure disposed on the first side of the gate electrode and passing through the third dielectric layer, wherein the first groove is located between the drain structure and the gate electrode.

[0005] In some embodiments, a portion of the first dielectric layer is located between the first groove and the drain structure, and the source field plate does not cover the portion.

[0006] In some embodiments, a width of the first groove is greater than a width of the portion.

[0007] In some embodiments, a width of the first groove is less than a width of the portion.

[0008] In some embodiments, the source electrode extends directly above the portion.

[0009] In some embodiments, the second dielectric layer has a second groove, where the second groove is located between the first groove and the drain structure, and the source electrode extends into the second groove.

[0010] In some embodiments, the bottom surface of the second groove is not lower than the bottom surface of the first groove.

[0011] In some embodiments, the bottom surface of the second groove is located within the first dielectric layer.

[0012] In some embodiments, the high electron mobility transistor device further includes a source contact, disposed on the third dielectric layer and electrically connected to the source electrode.

[0013] In some embodiments, the source contact extends directly above the first groove.

[0014] In some embodiments, the third dielectric layer has a third groove, where the third groove is located between the first groove and the drain structure, and the source contact extends into the third groove.

[0015] In some embodiments, the bottom surface of the third groove is not lower than the bottom surface of the first groove.

[0016] In some embodiments, the bottom surface of the third groove is located within the first dielectric layer.

[0017] According to some embodiments of the present disclosure, a method of manufacturing a high electron mobility transistor device is provided. The method includes forming a gate electrode on a semiconductor layer; forming a first dielectric layer on the gate electrode; performing a first patterning process on the first dielectric layer to form a first groove on a first side of the gate electrode, where the bottom surface of the first groove is lower than the top surface of the gate electrode; performing a second patterning process on the first dielectric layer to form a first via hole on the first side of the gate electrode and a second via hole on a second side of the gate electrode, where the first groove is located between the first via hole and the gate electrode; conformally forming a source field plate on the first dielectric layer, where the source field plate extends into the second via hole and the first groove; forming a second dielectric layer on the source field plate; forming a source electrode on the second dielectric layer, where the source electrode is electrically connected to the source field plate; forming a third dielectric layer on the source electrode; and forming a drain structure in the first via hole.

[0018] In some embodiments, a portion of the first dielectric layer is located between the first groove and the drain structure, and the source field plate is etched to expose the portion.

[0019] In some embodiments, the source electrode extends directly above the portion.

[0020] In some embodiments, the method further includes performing a third patterning process on the second dielectric layer to form a second groove between the first groove and the drain structure, wherein the source electrode extends into the second groove.

[0021] In some embodiments, the method further includes forming a source contact on the third dielectric layer, wherein the source contact is electrically connected to the source electrode.

[0022] In some embodiments, the source contact extends directly above the first groove.

[0023] In some embodiments, the method further includes performing a fourth patterning process on the third dielectric layer to form a third groove between the first groove and the drain structure, wherein the source contact extends into the third groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present invention.

[0025] Figures 1A to 1E are cross-sectional schematic views showing various stages in the manufacture of a high electron mobility transistor device according to some embodiments;

[0026] Figure 2 is a cross-sectional schematic view of a high electron mobility transistor device according to some embodiments;

[0027] Figure 3 is a cross-sectional schematic view of a high electron mobility transistor device according to some embodiments;

[0028] Figure 4 is a cross-sectional schematic view of a high electron mobility transistor device according to some embodiments;

[0029] Figure 5 is a cross-sectional schematic view of a high electron mobility transistor device according to some embodiments;

[0030] Figure 6 is a cross-sectional schematic view of a high electron mobility transistor device according to some embodiments;

[0031] Figure 7 is a cross-sectional schematic view of a high electron mobility transistor device according to some embodiments.

[0032] REFERENCE NUMERALS:

[0033] 100, 200, 300, 400, 500, 600, 700 - high electron mobility transistor devices;

[0034] 101~Semiconductor layer;

[0035] 102~Substrate;

[0036] 104~Buffer layer;

[0037] 106~Channel layer;

[0038] 108~Barrier layer;

[0039] 110~Isolation structure;

[0040] 112~Compound semiconductor layer;

[0041] 114, 116, 120, 130, 136~Dielectric layer;

[0042] 118~Gate electrode;

[0043] 119~First part;

[0044] 121~Second part;

[0045] 122~First groove;

[0046] 124, 126~Via hole;

[0047] 127~Source field plate;

[0048] 128~Conductive layer;

[0049] 132~Source electrode;

[0050] 134~Drain electrode;

[0051] 138~Source contact;

[0052] 140~Drain contact;

[0053] 141~Source structure;

[0054] 142~Protective layer;

[0055] 143~Drain structure;

[0056] 144, 146~Opening;

[0057] 148~Second groove;

[0058] 150~Third groove;

[0059] D1, D2~Distance. Detailed implementation mode

[0060] The following outlines some embodiments to make it easier for those skilled in the art to which the present invention pertains to understand the present invention. However, these embodiments are merely examples and are not used to limit the present invention. It can be understood that those skilled in the art to which the present invention pertains can adjust the embodiments described below according to requirements, such as changing the process sequence and / or including more or fewer steps than those described herein, and such adjustments do not exceed the scope of the present invention.

[0061] In addition, other elements can be added based on the embodiments described below. For example, the description of "forming a second element on a first element" may include embodiments where the first element and the second element are in direct contact, and may also include embodiments where there are other elements between the first element and the second element such that the first element and the second element are not in direct contact, and the up-down relationship between the first element and the second element may change as the device operates or is used in different orientations. Additionally, the present invention may repeat reference numerals and / or letters in different embodiments, and this repetition is for simplicity and clarity and not to indicate the relationship between the different embodiments being discussed.

[0062] The following describes a high electron mobility transistor device and a method for manufacturing the same according to some embodiments of the present invention, and is particularly applicable to a gallium nitride high electron mobility transistor device. In the high electron mobility transistor device of the present invention, dielectric layers with different thicknesses are provided such that the source field plate can shield the electric field and improve the problem of charge trapping.

[0063] Figures 1A to 1E are cross-sectional schematic diagrams showing various stages in the manufacture of a high electron mobility transistor device 100 according to some embodiments. In some embodiments, as Figure 1A shown, the high electron mobility transistor device 100 includes a substrate 102. Any substrate material suitable for a high electron mobility transistor device can be used. The substrate 102 can be a bulk semiconductor substrate or a composite substrate including different materials formed, and the substrate 102 can be doped (e.g., using p-type or n-type dopants) or undoped. In some embodiments, the substrate 102 can include a semiconductor substrate, a glass substrate, or a ceramic substrate, such as one of a silicon substrate, a silicon germanium substrate, silicon carbide, an aluminum nitride substrate, a sapphire substrate, or any combination or similar materials. In some embodiments, the substrate 102 can include a semiconductor-on-insulator (SOI) substrate formed by disposing a semiconductor material on an insulating layer.

[0064] In some embodiments, a buffer layer 104 is formed above the substrate 102 to alleviate the lattice difference between the substrate 102 and the film layer on the buffer layer 104 and improve the crystallization quality. In some embodiments, the material of the buffer layer 104 may include a III-V compound semiconductor material, such as a group III nitride. For example, the material of the buffer layer 104 may include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), one of the similar materials or any combination thereof. In some embodiments, the formation of the buffer layer 104 may include a deposition process, such as chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, one of the similar processes or any combination thereof.

[0065] In addition, although in Figure 1A the illustrated embodiment, the buffer layer 104 is directly formed on the substrate 102, in other embodiments, a nucleation layer (not shown) may be formed on the substrate 102 before forming the buffer layer 104 to further alleviate the lattice difference between the buffer layer 104 and the substrate 102 and improve the crystallization quality. In some embodiments, the material of the nucleation layer may include a III-V compound semiconductor material, such as a group III nitride.

[0066] Then, according to some embodiments, a channel layer 106 is formed above the buffer layer 104. In some embodiments, the material of the channel layer 106 may include one or more III-V compound semiconductor materials, such as a group III nitride. In some embodiments, the material of the channel layer 106 is, for example, GaN, AlGaN, InGaN, InAlGaN, one of the similar materials or any combination thereof. In addition, the channel layer 106 may be doped or undoped. According to some embodiments, the formation of the channel layer 106 may include a deposition process, such as chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, one of the similar processes or any combination thereof.

[0067] Then, according to some embodiments, a barrier layer 108 is formed over the channel layer 106 to generate a two-dimensional electron gas at the interface between the channel layer 106 and the barrier layer 108. The formation of the barrier layer 108 may include a deposition process, such as chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, one of the similar processes or any combination thereof. In some embodiments, the material of the barrier layer 108 may include III-V compound semiconductor materials, such as group III nitrides. For example, the barrier layer 108 may include one of AlN, AlGaN, AlInN, AlGaInN, similar materials or any combination thereof. The barrier layer 108 may include a single-layer or multi-layer structure, and the barrier layer 108 may be doped or undoped. For the purpose of simplicity, the substrate 102, the buffer layer 104, the channel layer 106 and the barrier layer 108 may be collectively referred to as the semiconductor layer 101.

[0068] Then, according to some embodiments, an isolation structure 110 is provided. In some embodiments, a mask layer (not shown) is provided on the semiconductor layer 101, and then the above mask layer is used as an etching mask for an etching process to etch trenches in the semiconductor layer 101. For example, the mask layer may include a photoresist, such as a positive photoresist or a negative photoresist. In some embodiments, the mask layer may include a hard mask and may be formed of one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), similar materials or any combination thereof. The mask layer may be a single-layer or multi-layer structure. The formation of the mask layer may include one of a deposition process, a photolithography process, other suitable processes or any combination thereof. In some embodiments, the deposition process includes spin-on coating, chemical vapor deposition, atomic layer deposition, one of the similar processes or any combination thereof. For example, the photolithography process may include photoresist coating (such as spin-on coating), soft baking, mask aligning, exposure, post-exposure baking (PEB), developing, rinsing, drying (such as hard baking), one of other suitable processes or any combination thereof.

[0069] In some embodiments, the above etching process may include a dry etching process and / or a wet etching process. For example, the dry etching process may include reactive ion etch (RIE), inductively-coupled plasma (ICP) etching, neutral beam etch (NBE), electron cyclotron resonance (ERC) etching, one of the similar etching processes or any combination thereof. For example, the wet etching process may use, for example, hydrofluoric acid (HF), ammonium hydroxide (NH4OH) or any suitable etchant.

[0070] Then, according to some embodiments, an insulating material is deposited in the trench to form the isolation structure 110. In some embodiments, the deposition of the insulating material may include one of metal organic chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, similar processes or any combination thereof. In some embodiments, the insulating material may include, for example, an oxide such as silicon oxide, a nitride such as silicon nitride, one of the similar materials or any combination thereof.

[0071] Then, according to some embodiments, a compound semiconductor layer 112 is disposed above the barrier layer 108 to deplete the two-dimensional electron gas under the gate, achieving a normally-off state of the semiconductor device. In some embodiments, the material of the compound semiconductor layer 112 is formed above the barrier layer 108 by a deposition process. For example, the deposition process includes one of chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, similar processes or any combination thereof. In some embodiments, the material of the compound semiconductor layer 112 includes gallium nitride doped with u-type, n-type or p-type, and may be doped with dopants.

[0072] Then, according to some embodiments, a patterning process is performed to adjust the position of the compound semiconductor layer 112 according to a predetermined position of the gate. In some embodiments, the patterning process includes forming a mask layer (not shown) on the deposited material layer, then etching the portion of the deposited material layer not covered by the mask layer, and forming the compound semiconductor layer 112. Examples of the material of the mask layer, the formation method, and the etching process are as described above, and thus will not be described again.

[0073] Then, according to some embodiments, a dielectric layer 114 is conformally formed on the barrier layer 108, the isolation structure 110, and the compound semiconductor layer 112. In some embodiments, the dielectric layer 114 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, aluminum oxide, aluminum nitride, one of the similar materials or any combination thereof. In some embodiments, the formation of the dielectric layer 114 includes a deposition process, such as a chemical vapor deposition process, an atomic layer deposition process, a spin coating process, one of the similar deposition processes or any combination thereof.

[0074] Then, according to some embodiments, a dielectric layer 116 is formed on the dielectric layer 114. In some embodiments, the material and the formation method of the dielectric layer 116 can be selected as the material and the formation method of the dielectric layer 114 as described above.

[0075] Then, according to some embodiments, a patterning process is performed on the dielectric layers 114 and 116 to etch openings in the dielectric layers 114 and 116. Examples of the patterning process are as described above, so they will not be elaborated here. Then, according to some embodiments, a gate electrode 118 is formed on the dielectric layer 116 and in the openings. In some embodiments, the material of the gate electrode 118 comprises a conductive material, such as a metal, a metal silicide, one of the similar materials or any combination thereof. For example, the metal can be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), one of the similar materials, one of the aforementioned alloys or any combination thereof. In some embodiments, the formation of the gate electrode 118 may include physical vapor deposition, chemical vapor deposition, atomic layer deposition, evaporation, sputtering, one of the similar processes or any combination thereof.

[0076] Then, according to some embodiments, a patterning process is performed on the gate electrode 118. Examples of the patterning process are as described above, so they will not be elaborated here. According to some embodiments, as Figure 1A shown, after the patterning process, the width of the gate electrode 118 is greater than the width of the compound semiconductor layer 112.

[0077] Then, according to some embodiments, as Figure 1BAs shown, a dielectric layer 120 is formed on the dielectric layer 116 and the gate electrode 118. In some embodiments, the dielectric layer 120 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, aluminum oxide, aluminum nitride, one of the similar materials or any combination thereof. In some embodiments, the formation of the dielectric layer 120 includes a deposition process, such as chemical vapor deposition process, atomic layer deposition process, spin coating process, one of the similar deposition processes or any combination thereof. Then, according to some embodiments, after depositing the dielectric layer 120, a planarization process, such as chemical mechanical polishing process, is performed on the dielectric layer 120.

[0078] Then, according to some embodiments, a first patterning process is performed on the dielectric layer 120 to form a first groove 122 on the first side of the gate electrode 118, and a second patterning process is performed to form vias 126 and 124 on the first side and the second side of the gate electrode 118 respectively, wherein the first groove 122 is located between the via 126 and the gate electrode 118. Examples of the patterning process are as described above and will not be elaborated herein. The first patterning process may be performed before, during or after the second patterning process, and the via 126 may be formed before, during or after the via 124.

[0079] According to some embodiments, as Figure 1B shown, a first portion 119 of the dielectric layer 120 is present between the via 126 and the first groove 122, and a second portion 121 of the dielectric layer 120 is present between the via 124 and the first groove 122. According to some embodiments, as Figure 1B shown, the width of the first groove 122 is greater than the width of the first portion 119 of the dielectric layer 120. In other embodiments, the position and / or shape of the first groove 122 may be adjusted such that the width of the first groove 122 is less than or substantially equal to the width of the first portion 119 of the dielectric layer 120. According to some embodiments, as Figure 1B shown, the bottom surface of the first groove 122 is lower than the top surface of the gate electrode 118.

[0080] Then, according to some embodiments, as Figure 1C shown, a source field plate 127 and a conductive layer 128 are disposed on the dielectric layer 120. In some embodiments, a conductive material is formed on the dielectric layer 120 by a deposition process, and the conductive material located on the first portion 119 of the dielectric layer 120 is etched to expose the first portion 119 of the dielectric layer 120 and form the source field plate 127 and the conductive layer 128. Examples of the conductive material, deposition process and etching process are as described above and will not be elaborated herein. In some embodiments, not covering the first portion 119 of the dielectric layer 120 by the source field plate 127 may reduce the risk of short circuit between the source field plate 127 and the conductive layer 128.

[0081] In the off state, a high electron mobility transistor device may generate leakage current, and the leakage current may be trapped at the interface when flowing through the interface. According to some embodiments, such as Figure 1C shown, the source field plate 127 extends from the second side of the gate electrode 118 into the first groove 122, such that the source field plate 127 covers the second portion 121 of the dielectric layer 120, to reduce charge accumulation caused by interface leakage current, and can block the influence of the electric field from the drain electrode on the gate electrode 118, improving the performance of the high electron mobility transistor device 100.

[0082] Then, according to some embodiments, such as Figure 1C shown, a dielectric layer 130 is formed on the source field plate 127 and the conductive layer 128. In some embodiments, the formation of the dielectric layer 130 includes a deposition process and a planarization process, and the material and formation method of the dielectric layer 130 can be selected as the material and formation method of the dielectric layer 120 described above. Then, according to some embodiments, a patterning process is performed on the dielectric layer 130 to re-form the vias 124 and 126, which expose the source field plate 127 and the conductive layer 128 respectively. Examples of the patterning process are as described above, and thus will not be elaborated.

[0083] Then, according to some embodiments, such as Figure 1D shown, a source electrode 132 and a drain electrode 134 are disposed on the dielectric layer 130. In some embodiments, a conductive material is formed on the dielectric layer 130 by a deposition process, and a patterning process is performed on the conductive material to form the source electrode 132 and the drain electrode 134. In some embodiments, the source electrode 132 and the drain electrode 134 are electrically connected to the source field plate 127 and the conductive layer 128 via the vias 124 and 126 respectively. Examples of the conductive material, the deposition process, and the patterning process are as described above, and thus will not be elaborated.

[0084] Then, according to some embodiments, a dielectric layer 136 is formed on the source electrode 132 and the drain electrode 134. In some embodiments, the formation of the dielectric layer 136 includes a deposition process and a planarization process, and the material and formation method of the dielectric layer 136 can be selected as the material and formation method of the dielectric layer 120 described above. Then, according to some embodiments, a patterning process is performed on the dielectric layer 136 to re-form the vias 124 and 126, which expose the source electrode 132 and the drain electrode 134 respectively. Examples of the patterning process are as described above, and thus will not be elaborated.

[0085] Then, according to some embodiments, such as Figure 1EAs shown, a source contact 138 and a drain contact 140 are disposed on the dielectric layer 136. In some embodiments, a conductive material is formed on the dielectric layer 130 by a deposition process, and the conductive material is patterned to form the source contact 138 and the drain contact 140. In some embodiments, the source contact 138 and the drain contact 140 are electrically connected to the source electrode 132 and the drain electrode 134 via vias 124 and 126 ( Figure 1D ), respectively. Examples of the conductive material, the deposition process, and the patterning process are as described above, and thus will not be elaborated further. For the purpose of simplification, the source field plate 127, the source electrode 132, and the source contact 138 may be collectively referred to as the source structure 141, and the conductive layer 128, the drain electrode 134, and the drain contact 140 may be collectively referred to as the drain structure 143.

[0086] In some embodiments, as Figure 1E shown, there is a distance D1 between the bottom surface of the source field plate 127 in the first groove 122 and the top surface of the barrier layer 108, and there is a distance D2 between the top surface of the dielectric layer 136 adjacent to the drain contact 140 and the top surface of the barrier layer 108, where the distance D2 is greater than the distance D1. The smaller distance D1 can enable the source field plate 127 to block the influence of the electric field from the drain structure 143 on the gate electrode 118 and absorb the charge accumulation caused by the interface leakage current, and the larger distance D2 can keep the top of the drain contact 140 away from the gate electrode 118 to reduce the influence of the electric field from the top of the drain contact 140 on the gate electrode 118, thereby improving the performance and reliability of the high electron mobility transistor device 100.

[0087] Then, according to some embodiments, a protective layer 142 is formed on the source contact 138 and the drain contact 140 to block moisture. In some embodiments, the protective layer 142 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, aluminum oxide, aluminum nitride, one of the similar materials or any combination thereof. In some embodiments, the formation of the protective layer 142 includes a deposition process, such as chemical vapor deposition process, atomic layer deposition process, spin coating process, one of the similar deposition processes or any combination thereof. Then, according to some embodiments, the protective layer 142 is patterned to form openings 144 and 146, which expose the source contact 138 and the drain contact 140, respectively.

[0088] In the above embodiments, the present invention forms the dielectric layer 120, the dielectric layer 130, and the dielectric layer 136 through a patterning process and a planarization process, such that the source field plate 127 formed on the dielectric layer 120 can cover the gate electrode 118, and the top of the drain contact 140 formed on the dielectric layer 136 is far from the gate electrode 118, so as to block and reduce the influence of the electric field from the drain structure 143 on the gate electrode 118, and the extended source field plate 127 can also improve the problem of charge trapping and improve the performance of the high electron mobility transistor device 100.

[0089] Figure 2 , Figure 3 and Figure 4 are cross-sectional schematic views showing high electron mobility transistor devices 200, 300, and 400 according to some embodiments. Similarly, Figures 2 to 4 the manufacturing steps of the illustrated embodiments are generally the same as Figures 1A to 1E those described above. For simplicity, the same elements will be described with the same reference numerals hereinafter, and the materials and formation methods of these elements are as described above, so they will not be elaborated further. Compared with Figures 1A to 1E the embodiments of

[0090] in some embodiments, as Figure 2 shown, the source electrode 132 extends from the second side of the gate electrode 118 to the first side of the gate electrode 118. The position of the source electrode 132 can be adjusted such that the source electrode 132 extends directly above the first groove 122. In some embodiments, the source electrode 132 can further extend directly above the first portion 119 of the dielectric layer 120.

[0091] In some embodiments, as Figure 3 shown, the source contact 138 extends from the second side of the gate electrode 118 to the first side of the gate electrode 118. The position of the source contact 138 can be adjusted such that the source contact 138 extends directly above the first groove 122. In some embodiments, the source contact 138 can further extend directly above the first portion 119 of the dielectric layer 120. Additionally, the position of the protective layer 142 can be adjusted according to the position of the source contact 138 to cover the source contact 138.

[0092] In some embodiments, as Figure 4As shown, the source electrode 132 and the source contact 138 extend from the second side of the gate electrode 118 to the first side of the gate electrode 118. The positions of the source electrode 132 and the source contact 138 can be adjusted such that the source electrode 132 and the source contact 138 extend directly above the first groove 122. In some embodiments, the source electrode 132 and the source contact 138 can further extend directly above the first portion 119 of the dielectric layer 120. As described above, the position of the protective layer 142 can be adjusted according to the position of the source contact 138 to cover the source contact 138.

[0093] In addition, in Figures 1A to 1E , Figure 2 and Figure 3 embodiments, the width of the first groove 122 is greater than the width of the first portion 119 of the dielectric layer 120, but the present invention is not limited thereto. In some embodiments, as Figure 4 shown, the width of the first groove 122 is less than the width of the first portion 119 of the dielectric layer 120. In other embodiments, the width of the first groove 122 is substantially equal to the width of the first portion 119 of the dielectric layer 120.

[0094] In the above embodiments, the present invention extends the source electrode 132 and / or the source contact 138 towards the drain structure 143 to block the influence of the electric field from the drain structure 143 on the gate electrode 118, and the extended source electrode 132 and / or source contact 138 can improve the problem of charge trapping, further improving the performance and reliability of the high electron mobility transistor devices 200, 300, and 400.

[0095] Figure 5 is a cross-sectional schematic view of a high electron mobility transistor device 500 according to some embodiments. Similarly, Figure 5 the manufacturing steps of the illustrated embodiments are substantially the same as Figures 1A to 1E , with the difference that a second groove 148 is provided and the source electrode 132 extends into the second groove 148. For simplicity, the same reference numerals will be used to describe the same elements below, and the materials and formation methods of these elements are as described above and will not be repeated.

[0096] In some embodiments, following Figure 1C the steps, after forming the dielectric layer 130, a patterning process is performed on the dielectric layer 130 to form the second groove 148, where the second groove 148 is located between the first groove 122 and the drain structure 143. Examples of the patterning process are as described above and will not be repeated. Then, according to some embodiments, as Figure 5As shown, a source electrode 132 and a drain electrode 134 are formed on the patterned dielectric layer 130, where the source electrode 132 extends into the second groove 148 and does not cover the portion of the dielectric layer 130 between the second groove 148 and the drain electrode 134.

[0097] The patterning process can be adjusted to change the depth of the second groove 148. In some embodiments, as Figure 5 shown, the bottom surface of the second groove 148 is not lower than the bottom surface of the first groove 122. In some embodiments, the bottom surface of the second groove 148 is located within the first portion 119 of the dielectric layer 120.

[0098] Figure 6 is a cross-sectional schematic view of a high electron mobility transistor device 600 according to some embodiments. Similarly, Figure 6 the manufacturing steps of the shown embodiment are substantially the same as Figures 1A to 1E those, with the difference being that a third groove 150 is provided and the source contact 138 extends into the third groove 150. For simplicity, the same elements will be described with the same reference numerals hereinafter, and the materials and formation methods of these elements are as described above and will not be elaborated further.

[0099] In some embodiments, following Figure 1D the steps, after forming the dielectric layer 136, a patterning process is performed on the dielectric layer 136 to form a third groove 150, where the third groove 150 is located between the first groove 122 and the drain structure 143. Examples of the patterning process are as described above and will not be elaborated further. Then, according to some embodiments, as Figure 6 shown, a source contact 138 and a drain contact 140 are formed on the patterned dielectric layer 136, where the source contact 138 extends into the third groove 150 and does not cover the portion of the dielectric layer 136 between the third groove 150 and the drain contact 140.

[0100] The patterning process can be adjusted to change the depth of the third groove 150. In some embodiments, as Figure 6 shown, the bottom surface of the third groove 150 is not lower than the bottom surface of the first groove 122. In some embodiments, the bottom surface of the third groove 150 is located within the first portion 119 of the dielectric layer 120. As described above, the position of the protective layer 142 can be adjusted according to the position of the source contact 138 to cover the source contact 138.

[0101] Figure 7 is a cross-sectional schematic view of a high electron mobility transistor device 700 according to some embodiments. Similarly, Figure 7 the manufacturing steps of the shown embodiment are substantially the same as Figures 1A to 1EThe same, with the difference that the source electrode 132 extends into the second groove 148 and the source contact 138 extends into the third groove 150. For simplicity, the same elements will be described with the same symbols below, and the materials and formation methods of these elements are as described above, so they will not be elaborated further.

[0102] In some embodiments, following Figure 1C the steps, after forming the dielectric layer 130, a patterning process is performed on the dielectric layer 130 to form the second groove 148, where the second groove 148 is located between the first groove 122 and the drain structure 143. Examples of the patterning process are as described above, so they will not be elaborated further. Then, according to some embodiments, a source electrode 132 and a drain electrode 134 are formed on the patterned dielectric layer 130, where the source electrode 132 extends into the second groove 148 and does not cover the portion of the dielectric layer 130 between the second groove 148 and the drain electrode 134.

[0103] Then, according to some embodiments, a dielectric layer 136 is formed on the source electrode 132 and the drain electrode 134, and a patterning process is performed on the dielectric layer 136 to form the third groove 150, where the third groove 150 is located between the second groove 148 and the drain structure 143. Examples of the patterning process are as described above, so they will not be elaborated further. Then, according to some embodiments, a source contact 138 and a drain contact 140 are formed on the patterned dielectric layer 136, where the source contact 138 extends into the third groove 150 and does not cover the portion of the dielectric layer 136 between the third groove 150 and the drain contact 140.

[0104] The patterning process can be adjusted to change the depths of the second groove 148 and the third groove 150. In some embodiments, as Figure 7 shown, the bottom surface of the second groove 148 is not lower than the bottom surface of the first groove 122, and the bottom surface of the third groove 150 is not lower than the bottom surface of the second groove 148. In some embodiments, the bottom surfaces of the second groove 148 and the third groove 150 are located in the first portion 119 of the dielectric layer 120. As described above, the position of the protective layer 142 can be adjusted according to the position of the source contact 138 to cover the source contact 138.

[0105] In Figure 5 , Figure 6 and Figure 7 's embodiments, the present invention enables the source electrode 132 and / or the source contact 138 to cover the gate electrode 118 to further shield the electric field and improve the problem of charge trapping, improving the performance and reliability of the high electron mobility transistor devices 500, 600, and 700.

[0106] In summary, the present invention forms dielectric layers with different thicknesses through a patterning process and a planarization process, where the dielectric layer under the source field plate is thinner, while the dielectric layer adjacent to the top of the drain structure is thicker. The thin dielectric layer can enable the source field plate to shield the electric field and improve the problem of charge capture, and the thick dielectric layer can keep the top of the drain structure away from the gate electrode to reduce the influence of the electric field from the drain structure on the gate electrode, thereby improving the performance and reliability of the high electron mobility transistor device.

[0107] In addition, in some embodiments, the source electrode and / or the source contact is extended towards the drain structure to block the influence of the electric field from the drain structure on the gate electrode, and the extended source electrode and / or source contact can also improve the problem of charge capture, further improving the performance and reliability of the high electron mobility transistor device.

[0108] Furthermore, in some embodiments, the source electrode and / or the source contact is made to cover the gate electrode to block the influence of the electric field from the drain structure on the gate electrode, and the extended source electrode and / or source contact can also improve the problem of charge capture, further improving the performance and reliability of the high electron mobility transistor device.

[0109] Although the embodiments of the present invention have been described above with multiple embodiments, these embodiments are not used to limit the embodiments of the present invention. Those skilled in the art to which the present invention pertains should understand that they can make various changes, substitutions, and replacements based on the embodiments of the present invention to achieve the same purposes and / or advantages as those described in the multiple embodiments herein. Those skilled in the art to which the present invention pertains can also understand that such modifications or designs do not depart from the spirit and scope of the embodiments of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended claims.

Claims

1. A high electron mobility transistor device, characterized in that, Comprising: A gate electrode disposed on a semiconductor layer; A first dielectric layer disposed on the gate electrode and having a first groove on a first side of the gate electrode, wherein a bottom surface of the first groove is lower than a top surface of the gate electrode; A source field plate disposed on the first dielectric layer and extending from a second side of the gate electrode into the first groove; A second dielectric layer disposed on the source field plate and having an opening on the second side of the gate electrode; A source electrode conformally disposed in the opening of the second dielectric layer and electrically connected to the source field plate; A third dielectric layer disposed on the source electrode; A source contact extending from below a top surface of the source field plate to above a top surface of the source electrode; And A drain structure disposed on the first side of the gate electrode and passing through the third dielectric layer, wherein the first groove is located between the drain structure and the gate electrode, wherein The second dielectric layer has a second groove, and wherein the second groove is located between the first groove and the drain structure, and the source electrode extends into the second groove.

2. The high electron mobility transistor device according to claim 1, wherein A portion of the first dielectric layer is located between the first groove and the drain structure, and the source field plate does not cover this portion.

3. The high electron mobility transistor device according to claim 2, wherein The width of the first groove is greater than the width of this portion.

4. The high electron mobility transistor device according to claim 2, wherein, The width of the first groove is less than the width of this portion.

5. The high electron mobility transistor device according to claim 2, wherein The source electrode extends directly above this portion.

6. The high electron mobility transistor device according to claim 1, wherein, A bottom surface of the second groove is not lower than the bottom surface of the first groove.

7. The high electron mobility transistor device according to claim 6, characterized in that, The bottom surface of the second groove is located within the first dielectric layer.

8. The high electron mobility transistor device according to claim 1, characterized in that, The source contact is disposed on the third dielectric layer and electrically connected to the source electrode.

9. The high electron mobility transistor device according to claim 8, wherein The source contact extends directly above the first groove.

10. The high electron mobility transistor device according to claim 8, wherein, The third dielectric layer has a third groove, wherein the third groove is located between the first groove and the drain structure, and the source contact extends into the third groove.

11. The high electron mobility transistor device according to claim 10, characterized in that, A bottom surface of the third groove is not lower than the bottom surface of the first groove.

12. The high electron mobility transistor device according to claim 11, wherein, The bottom surface of the third groove is located within the first dielectric layer.

13. A manufacturing method of a high electron mobility transistor device, characterized in that, Comprising: Forming a gate electrode on a semiconductor layer; Forming a first dielectric layer on the gate electrode; Performing a first patterning process on the first dielectric layer to form a first groove on a first side of the gate electrode, wherein a bottom surface of the first groove is lower than a top surface of the gate electrode; Performing a second patterning process on the first dielectric layer to form a first through hole on the first side of the gate electrode and a second through hole on a second side of the gate electrode, wherein the first groove is located between the first through hole and the gate electrode; Conformally forming a source field plate on the first dielectric layer, wherein the source field plate extends into the second through hole and the first groove; Forming a second dielectric layer on the source field plate, and the second dielectric layer has an opening on the second side of the gate electrode; Conformally forming a source electrode in the opening of the second dielectric layer, wherein the source electrode is electrically connected to the source field plate; Forming a third dielectric layer on the source electrode; Forming a source contact on the third dielectric layer, wherein the source contact extends from below a top surface of the source field plate to above a top surface of the source electrode; Form a drain structure within the first through hole; And Perform a third patterning process on the second dielectric layer to form a second groove between the first groove and the drain structure, wherein the source electrode extends into the second groove.

14. The manufacturing method of the high electron mobility transistor device according to claim 13, characterized in that, A part of the first dielectric layer is located between the first groove and the drain structure, and the source field plate is etched to expose this part.

15. The manufacturing method of the high electron mobility transistor device according to claim 14, characterized in that, The source electrode extends directly above this part.

16. The manufacturing method of a high electron mobility transistor device according to claim 13, characterized in that, The source contact is electrically connected to the source electrode.

17. The manufacturing method of the high electron mobility transistor device according to claim 16, characterized in that, The source contact extends directly above the first groove.

18. The manufacturing method of a high electron mobility transistor device according to claim 16, characterized in that, Further include performing a fourth patterning process on the third dielectric layer to form a third groove between the first groove and the drain structure, wherein the source contact extends into the third groove.

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