Silicon carbide based electronic devices and methods of manufacturing the same

Abstract

Embodiments of the present disclosure relate to silicon carbide based electronic devices and methods of manufacturing the same. An electronic device comprising: a semiconductor body of silicon carbide, SiC, having a first face and a second face opposite each other along a first direction, a positive electrical charge carrier being present on the first face, the positive electrical charge carrier forming a positive interface charge; a first electrically conductive terminal extending at the first face of the semiconductor body; a second electrically conductive terminal extending at the second face of the semiconductor body; a channel region in the semiconductor body, the channel region being configured to accommodate, in use, an electronic current flow between the first electrically conductive terminal and the second electrically conductive terminal; and a trap layer of insulating material extending in electrical contact with the semiconductor body at the channel region and designed to present an electron trapping state generating a negative electrical charge, such as at least partially balancing the positive interface charge.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an electronic device, in particular to a power MOSFET or Schottky diode, and to a method of manufacturing the electronic device. BACKGROUND

[0002] It is known that semiconductor materials with wide band gap, in particular with high band gap value, low on-resistance (R ON ), high thermal conductivity value, high operating frequency and high carrier saturation velocity, are ideal for the production of electronic components such as diodes or transistors, in particular for electrical applications. One material with the above-mentioned characteristics and suitable for the manufacture of electronic components is silicon carbide (SiC). In particular, with regard to its previously listed characteristics, silicon carbide of various polytypes (for example 3C-SiC, 4H-SiC, 6H-SiC) is more preferable than silicon.

[0003] The hexagonal polytype of SiC (4H-SiC) is the most widely studied polytype to date and is currently available on the market in the form of 4H-SiC wafers produced in quantity, even if it is more expensive than the usual silicon wafers. 3C-SiC has a significant cost advantage over 4H-SiC, since it can be grown directly on Si by CVD (Chemical Vapor Deposition). Providing a high-quality 3C-SiC epitaxial layer on Si enables economical and convenient SiC power devices, for example, suitable for operating in the range of 650 V to 1200 V.

[0004] Electronic devices with silicon carbide substrates present further advantages with respect to similar devices with silicon substrates, such as low emission resistance in conduction mode, low leakage current and high operating frequency. In particular, SiC Schottky diodes exhibit higher switching performance, which makes SiC electronic devices particularly suitable for high-frequency applications.

[0005] A large amount of scientific work has also reported good switching performance of (SiC) MOSFET devices in silicon carbide. From an industrial point of view, in addition to the switching performance, SiC MOSFET devices also present good structural strength, a characteristic required by power systems.

[0006] However, the presence of fixed positive charges in MOS (Metal Oxide Semiconductor) structures, with oxide being silicon dioxide (SiO2) and semiconductor being cubic silicon carbide (3C-SiC), is often observed in experiments. It has also been found that SiO2 thermally grown on 3C-SiC substrates or deposited on 3C-SiC substrates shows similar levels of positive charges to those observed in MOS structures, indicating that the charges come from interface states present at the 3C-SiC surface (interface between SiC and SiO2) rather than from the oxide.

[0007] The presence of positive charges at the oxide interface can alter the operating characteristics of the MOSFET, or can affect the electric field distribution at the edge termination of the device, or in extreme cases, can generate an undesired inversion layer at the oxide / SiC interface, resulting in high levels of junction leakage current. In addition, defects at the oxide / SiC interface can create states that change the duty cycle with modulation of the surface potential at the interface, which also affects the switching of the device and leads to instability. SUMMARY

[0008] According to the present disclosure, an electronic device and a method of manufacturing thereof are provided. BRIEF DESCRIPTION OF DRAWINGS

[0009] For a better understanding of the present disclosure, its preferred embodiments will now be described solely by way of non-limiting examples, with reference to the accompanying drawings, in which:

[0010] Figure 1 A side cross-sectional view of a MOSFET device according to one aspect of the present disclosure is shown; and

[0011] Figure 2 A side cross-sectional view of a Schottky diode according to another aspect of the present disclosure is shown. DETAILED DESCRIPTION

[0012] Figure 1 is a cross-sectional view of a (three-dimensional) Cartesian reference frame of a transistor 20 (in particular a vertical channel MOSFET, more in particular a power MOSFET) according to one aspect of the present disclosure. The transistor 20 comprises a gate terminal G (forming a control terminal) which, in use, can be coupled to a bias voltage V GS generator; a first conductive terminal S comprising a source region 26 (N-type implanted region) and a source metallization 59 (in electrical contact with the source region 26); and a second conductive terminal or drain terminal D (comprising a drain metallization 27). In use, by appropriate biasing, a conductive channel of majority carriers (here electrons) is established between the source region 26 and the drain metallization 27.

[0013] More in detail, the transistor 20 comprises a semiconductor body 48 (in particular SiC, more in particular 3C-SiC) having first and second faces 48a, 48b opposite each other along the Z-axis direction. In particular, Figure 1 A semiconductor body is shown comprising a base substrate 36 on which an epitaxially grown structural layer 38 extends, having the function of a drift layer. The substrate 36 has a first conductivity type (here N-type) and a doping level (for example, in the order of 1 · 1018cm 18 cm -3 and 5 · 1019cm19 cm -3 between 1 · 10 14 cm -3 and 5 · 10 16 cm -3 between 1 · 10

[0014] According to one aspect of the present disclosure, the polytype of the semiconductor body 48 is the cubic polytype of silicon carbide or 3C-SiC. However, the present disclosure is also applicable to different polytypes of silicon carbide, such as, for example, 4H-SiC.

[0015] The gate terminal G extends on the first face 48a of the semiconductor body 48, the body region 45 having a second conductivity type (here a P-type implant region) opposite to the first conductivity type extends in the semiconductor body 48 (more specifically, in the structure layer 38) at (facing) the first face 48a; the source region 26 having the first conductivity type extends in the body region 45 at (facing) the first surface 48a; the drain metallization 27 extends in a position corresponding to the second face 48b of the semiconductor body 48. Thus, the transistor 20 is of vertical conductivity type (i.e., the conduction channel extends in a main direction along the Z axis).

[0016] The gate terminal G comprises an insulating or dielectric layer 52 (having a gate dielectric function), for example made of an aluminum-containing compound, multilayer or alloy (e.g., AI2O3, AIN, AION). The insulating layer 52 can likewise be formed by a plurality of sub-layers or layers forming a stack, including the above-mentioned materials (e.g., AI2O3, AIN, AION, AIN / SiN, AI2O3 / HfO2, SiO2 / AI2O3 / SiO2).

[0017] Other materials that can be used to form the insulating layer 52 include NiO, CeO2, HfO2, SiN and SiO2 / HfO2 / SiO2.

[0018] The insulating layer 52 has a thickness between 10 nm and 100 nm measured along the Z axis.

[0019] The gate terminal G further comprises a gate metallization 53 extending on the insulating layer 52.

[0020] An insulating or dielectric layer 56 extends over the gate region 24 and is in particular made of silicon dioxide (SiO2) or silicon nitride (SiN) with a thickness measured along the Z axis comprised between 0.5 pm and 1.5 pm. Further extending in the vicinity of the insulating layer 56 is a source terminal 58, in particular made of a metallic material (e.g. aluminum) with a thickness measured along the Z axis comprised between 0.5 pm and 2 pm.

[0021] The source terminal 58 extends up to contacting the source region 26 or is connected to the source region 26 through a source metallization 59 (also referred to as optional ohmic contact region 59).

[0022] Extending on the second face 48b of the semiconductor body 48 is a metallic layer 27, e.g. made of Ti / Ni / Au, which forms the drain terminal D. An interface layer (not shown, e.g. made of nickel silicide) facilitating an ohmic contact can be present between the semiconductor body 48 and the metallic layer 27.

[0023] The insulating layer 52 is designed to present a high density of electron traps. Electron traps are known to be widely present in insulating materials, both as a consequence of the deposition process and as a consequence of one or more treatments of the insulating layer 52 after its deposition.

[0024] Al2O3 is deposited, e.g. through an ALD (atomic layer deposition) process or a CVD (chemical vapor deposition) process, obtaining an amorphous insulating layer in which the coordination of the atoms departs from the structure of an ideal crystal. In the embodiments provided by way of non-limiting example, the ALD / CVD process is performed in a growth / deposition chamber at a temperature of about 250°C in an oxygen plasma, with TMA (trimethylaluminum) as aluminum precursor.

[0025] Under these conditions, the defects present in the structure, such as in particular oxygen vacancies, mean that the deposited material is provided with electron traps.

[0026] As mentioned above, further special treatments facilitate the formation of electron traps. Such treatments include:

[0027] a. a thermal annealing treatment in a reducing environment to increase oxygen vacancies (e.g. in a chamber with a gas selected from N2, Ar and NH3);

[0028] b. the application of a voltage (e.g. a positive voltage) to the insulating layer 52 adapted to facilitate the accumulation of electrons in the insulating layer; and

[0029] c. in-situ doping via the introduction of an electronegative atomic species (e.g. fluorine) during the deposition or growth step of the insulating layer 52.

[0030] Based on the above discussion, the negative charge present in the insulating layer 52 compensates for the ionized donors with opposite (positive) charges provided by the SiC semiconductor body 48 (especially 3C-SiC). Therefore, a positive threshold voltage V is obtained. th MOSFET devices. In fact, the inherent characteristics of 3C-SiC, as is known, suggest the formation of positive charges at the interface with the insulator.

[0031] Figure 2 A side cross-sectional view of the Schottky (diode) device 60 in a (three-dimensional) Cartesian reference frame along the X, Y, and Z axes is shown.

[0032] The Schottky device 60 includes a semiconductor body 68 (particularly SiC, more particularly 3C-SiC); however, the description herein also applies to other SiC polymorphs, such as 4H-SiC. The semiconductor body 68 has a first surface and a second surface 68a, 68b that are opposite each other along the Z-axis direction. Figure 2 A semiconductor body 68 according to an embodiment is shown, the semiconductor body including a substrate 69 on which an epitaxially grown structural layer 70 extends, functioning as a drift layer. The substrate 69 has a first conductivity type (here, N-type) and a doping level (e.g., at 1.10). 18 cm -3 and 5.10 19 cm -3 The structural layer 70 has a first conductivity type and a lower doping level than the substrate 69 (e.g., in the range between 1.10). 14 cm -3 To 1.10 17 cm -3 (The range between them).

[0033] The Schottky device 60 also includes: a cathode terminal 72 made of a metallic material extending on a second surface 68b of the semiconductor body 68; and an anode terminal 74 made of a metallic material extending on a first surface 68a of the semiconductor body 68. In use, a conductive channel is established between the anode and cathode terminals by appropriate biasing.

[0034] The Schottky device 60 has one or more trenches 73 which extend in depth in the semiconductor body 68, in particular in the drift layer 70, along a main direction parallel to the Z axis. For example, each trench 73 has a depth dl, measured from the first face 68a to the second face 68b, having a value comprised between 100 nm and 1000 nm. In the case where a plurality of trenches 73 is present, each trench 73 is separated from the immediately adjacent trench 73 along the direction of the X axis by a distance, separated by a portion of the structure layer 70. This portion of the structure layer 70 has an extension d2 along the direction of the X axis, for example having a value comprised between 100 nm and 5000 nm.

[0035] Each trench 73 is partially filled by an insulating layer 80 which covers the side walls and the bottom of each respective trench 73. In addition, the filling of each trench 73 is completed by a portion 82 which penetrates and / or covers the anode terminal 74 of the trench 73. Therefore, each portion 82 is insulated from the structure layer 70 by the respective insulating layer 80.

[0036] The material chosen for the insulating layer 80 is of the same type as that of the insulating layer 52 described previously. In addition, the insulating layer 80 is designed in a similar way to that described with reference to the insulating layer 52, i.e. so as to present a high number of traps for the majority carriers, here the electrons.

[0037] Therefore, the insulating layer 80 can be manufactured in a similar way to that described previously with reference to the insulating layer 52, so as to obtain the required characteristics in terms of presence of electron traps.

[0038] The Schottky junction 71 is formed by a plurality of metal-semiconductor junctions which exist at the interface between the metal layer of the drift layer 70 and the anode metallization 74. In particular, the Schottky (semiconductor-metal) junction 71 is formed by the direct electrical contact between a portion of the drift layer 70 (N-type doped) and a respective portion of the anode metallization 74.

[0039] The presence of the net negative charge at the insulating layer 80 makes it possible to balance the positive charge at the interface with the structure layer 70, thus making it possible to optimize the pinch-off characteristics of the diode 60. In particular, it is possible to optimize the surface depletion layer by modifying the pinch-off characteristics of the ON voltage and of the negative bias of the Schottky contact of the diode.

[0040] In general, the present disclosure is applicable to a generic electronic device comprising: a semiconductor body of silicon carbide, SiC, having a first face and a second face opposite each other along a first direction (Z), on said first face presenting positive charge carriers forming a positive interface charge; a first electrically conductive terminal extending at the first face of the semiconductor body; a second electrically conductive terminal extending at the second face of the semiconductor body; a channel region in the semiconductor body configured to accommodate, in use, an electronic flow between the first electrically conductive terminal and the second electrically conductive terminal; a trap layer of insulating material extending in electrical contact with the semiconductor body at said channel region and designed to present an electron-trapping state generating negative charges, such as at least partially balancing said positive interface charge.

[0041] In particular, the trap layer 52, 80 is an insulating layer having at least an energy level arranged very close in energy (for example, between 0 eV and 2 eV) to the conduction band of the semiconductor used to make the above-mentioned devices.

[0042] From the examination of the features of the present disclosure, the advantages it provides are evident.

[0043] Finally, it is clear that modifications and changes can be made to what is described and illustrated herein, without departing from the scope of the present disclosure.

[0044] For example, the present disclosure can be applied to devices based on SiC polytypes other than 3C-SiC or 4H-SiC in general transistors and diodes.

[0045] Furthermore, the present disclosure can be applied to devices based on materials other than SiC, such as GaN and AlGaN / GaN (normally-off HEMT).

[0046] Furthermore, the present disclosure finds wide application in electronic devices other than those described in the above-mentioned embodiments, such as VMOS (vertical channel MOSFET), DMOS (diffused MOSFET), CMOS (complementary MOSFET).

[0047] The present disclosure can also find application in horizontal channel devices, using a trapping layer within an insulating layer arranged in contact with a P-type semiconductor.

[0048] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the detailed description. In general, the selected terms employed in the following claims are to be interpreted as including all equivalents which would be ascribed to such terms by one skilled in the art and their equivalents. The claims are not to be limited to the embodiments specifically recited therein.

Claims

1. A semiconductor electronic device, comprising: a semiconductor body of silicon carbide, the semiconductor body having first and second faces opposite one another, the semiconductor body having positive charge carriers on the first face; a first conductive terminal at the first face of the semiconductor body; a second conductive terminal at the second face of the semiconductor body; a channel region in the semiconductor body, the channel region configured to accommodate, in use, a flow of electrons between the first and second conductive terminals; a trap layer of amorphous insulating material, the trap layer in electrical contact with the semiconductor body at the channel region, the trap layer comprising a plurality of electron traps; and an interface between the semiconductor body and the trap layer, the interface having positive charge, the plurality of electron traps generating negative charge to at least partially balance the positive charge.

2. The semiconductor electronic device of claim 1, wherein the trap layer has an energy level very close in energy to a conduction band of the semiconductor body.

3. The semiconductor electronic device of claim 1, wherein the trap layer is an insulating alloy containing aluminum.

4. The semiconductor electronic device of claim 1, wherein the trap layer comprises AI2O3.

5. The semiconductor electronic device of claim 1, wherein the trap layer has a thickness of 30 nm to 100 nm.

6. The semiconductor electronic device of claim 1, wherein: the electronic device is a transistor comprising a gate terminal, the gate terminal extending at the first face of the semiconductor body, and the gate terminal comprising a gate metallization, the first conductive terminal is a source terminal of the transistor, and the second conductive terminal is a drain terminal of the transistor, and the trap layer is a gate oxide layer disposed between the gate metallization and the first face of the semiconductor body.

7. The semiconductor electronic device of claim 1, wherein the electronic device is a diode and comprises: an anode terminal extending at the first face of the semiconductor body; a cathode terminal extending at the second face of the semiconductor body; and a trench in the semiconductor body extending from the first face toward the second face, the trap layer extending in the trench.

8. The semiconductor electronic device of claim 7, wherein: the anode terminal is a metal layer, the anode terminal having a portion extending in the trench, and the trap layer extends between the portion of the anode terminal and the channel region.

9. The semiconductor electronic device of claim 7, wherein the diode is a Schottky diode, the Schottky diode comprising a metal-semiconductor junction formed by an electrical contact area between the anode terminal and the channel region along the trench.

10. A method for manufacturing a semiconductor electronic device, comprising: ​ forming a first conductive terminal at a first face of a semiconductor body of silicon carbide, the semiconductor body having a second face opposite the first face, the semiconductor body exhibiting positive charge carriers at the first face; forming a second conductive terminal at the second face of the semiconductor body, the semiconductor body including a channel region configured to accommodate, in use, a flow of electrons between the first conductive terminal and the second conductive terminal; and forming a trap layer of amorphous insulating material in electrical contact with the semiconductor body at the channel region, the trap layer including a plurality of electron traps, wherein an interface between the semiconductor body and the trap layer has a positive charge and the plurality of electron traps generate a negative charge to at least partially balance the positive charge.

11. The method of claim 10, wherein forming the trap layer comprises: forming an insulating layer having at least an energy level disposed in close energetic proximity to a conduction band of the semiconductor body.

12. The method of claim 10, wherein forming the trap layer includes depositing an insulating alloy including aluminum.

13. The method of claim 10, wherein forming the trap layer includes forming one of: AI2O3, AI2O3 / HfO2, and SiO2 / AI2O3 / SiO2.

14. The method of claim 10, wherein forming the trap layer includes one of: performing a thermal anneal process in a reducing environment; biasing the trap layer by a voltage adapted to favor accumulation of electrons in the trap layer; or doping the trap layer by an electronegative atomic species.

15. A semiconductor electronic device, comprising: a semiconductor body having first and second faces opposite one another, the semiconductor body having a first type of charge carrier; a first conductive terminal at the first face of the semiconductor body; a second conductive terminal at the second face of the semiconductor body, wherein the semiconductor body is configured to accommodate, in use, a flow of electrons between the first conductive terminal and the second conductive terminal; and a trap layer of amorphous insulating material in electrical contact with the semiconductor body, the trap layer including a plurality of charge traps; and an interface between the semiconductor body and the trap layer, the interface having a first type of charge and the plurality of charge traps generating a second type of charge to at least partially balance the first type of charge.

16. The semiconductor electronic device of claim 15, wherein: the electronic device is a transistor including a gate terminal extending at the first face of the semiconductor body and including a gate metallization, the first conductive terminal is a source terminal of the transistor and the second conductive terminal is a drain terminal of the transistor, and the trap layer is a gate insulator disposed between the gate metallization and the first face of the semiconductor body.

17. The semiconductor electronic device of claim 15, wherein the electronic device is a diode, and comprising: an anode terminal extending at the first face of the semiconductor body; a cathode terminal extending at the second face of the semiconductor body; and a trench extending in the semiconductor body from the first face towards the second face, the trap layer extending in the trench.

18. The semiconductor electronic device of claim 17, wherein: the anode terminal is a metal layer having a portion extending in the trench, and the trap layer extends between the portion of the anode terminal and a channel region of the semiconductor body.

19. The semiconductor electronic device of claim 17, wherein the diode is a Schottky diode comprising a metal-semiconductor junction formed by an electrical contact region between the anode terminal and a channel region of the semiconductor body along the trench.

20. The semiconductor electronic device of claim 15, wherein the trap layer comprises an insulating compound containing aluminum. ​

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