Semiconductor components

Abstract

The present invention discloses a semiconductor element, which includes an active layer, a first semiconductor layer, a first stress buffer structure located between the active layer and the first semiconductor layer, and an intermediate layer located between the first stress buffer structure and the active layer, wherein the first stress buffer structure includes a plurality of first sub-layers and a plurality of second sub-layers overlapping each other, the band gap of the second sub-layer is smaller than the band gap of the first sub-layer, the intermediate layer includes a first portion adjacent to the first stress buffer structure and a second portion adjacent to the active layer, the second portion and the second sub-layer each include an indium content and the indium content of the second portion is smaller than the indium content of the second sub-layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor element, and in particular to a semiconductor element with an intermediate layer. Background Art

[0002] III-V compound semiconductors have been widely developed and applied in various electronic devices, such as high electron-mobility transistors (HEMTs), high-efficiency photovoltaic devices, and light-emitting diodes (LEDs).

[0003] Taking light-emitting diodes as an example, light-emitting diodes have been regarded as one of the best solutions to replace traditional light sources. In order to further achieve energy-saving and carbon-saving effects, brightness improvement has been a long-term research topic for people in this field. The brightness improvement of light-emitting diodes is mainly divided into two parts. One is the improvement of internal quantum efficiency (Internal Quantum Efficiency; IQE), which is mainly achieved by improving the epitaxial film structure to increase the electron-hole combination efficiency; the other is the improvement of light extraction efficiency (Light Extraction Efficiency; LEE), which mainly focuses on allowing the light emitted by the active layer to effectively penetrate to the outside of the device and reduce the light absorbed by the internal structure of the light-emitting diode.

[0004] The present invention aims to improve the quality of the epitaxial thin film structure of the III-V compound semiconductor element, thereby improving the performance of the semiconductor element, such as improving the internal quantum efficiency of the light emitting diode. Summary of the invention

[0005] The present invention provides a semiconductor device, which includes an active layer, a first semiconductor layer, a first stress buffer structure located between the active layer and the first semiconductor layer, and an intermediate layer located between the first stress buffer structure and the active layer, wherein the first stress buffer structure includes a plurality of first sublayers and a plurality of second sublayers overlapping each other, the band gap of the second sublayer is smaller than the band gap of the first sublayer, and the intermediate layer includes a first portion adjacent to the first stress buffer structure and a second portion adjacent to the active layer, the second portion and the second sublayer each including an indium content and the indium content of the second portion is smaller than the indium content of the second sublayer. In another embodiment of the present invention, the semiconductor device further includes a second stress buffer structure located between the second portion and the active layer, wherein the second stress buffer structure includes a plurality of third sublayers and a plurality of fourth sublayers overlapping each other, the band gap of the fourth sublayer is smaller than the band gap of the third sublayer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram illustrating a first embodiment of a semiconductor device according to the present invention;

[0007] Figure 2 FIG. 4 is a schematic diagram illustrating a second embodiment of a semiconductor device according to the present invention.

[0008] Explanation of symbols

[0009] 1.2 Semiconductor components

[0010] 10 substrate

[0011] 20 First semiconductor layer

[0012] 31. First stress buffer structure

[0013] 311 First Sublayer

[0014] 312 Second sublayer

[0015] 32 Second stress buffer structure

[0016] 321 The third sublayer

[0017] 322 Fourth Sublayer

[0018] 40 Middle Layer

[0019] 401 Part 1

[0020] 402 Part 2

[0021] 50 Active layer

[0022] 501 Barrier

[0023] 502 Well layer

[0024] 60 Second semiconductor layer

[0025] 71 first electrode

[0026] 72 second electrode DETAILED DESCRIPTION

[0027] Figure 1A first embodiment of a semiconductor device according to the present invention is disclosed. The semiconductor device 1 includes a substrate 10, a first semiconductor layer 20 formed on the substrate 10, a first stress buffer structure 31 formed on the first semiconductor layer 20, an intermediate layer 40 formed on the first stress buffer structure 20, an active layer 50 formed on the intermediate layer 40, a second semiconductor layer 60 formed on the active layer 50, a first electrode 71 electrically connected to the first semiconductor layer 20, and a second electrode 72 electrically connected to the second semiconductor layer 60. In one embodiment of the present invention, the first semiconductor layer 20 includes a first region and a second region, the first stress buffer layer 31 is formed on the first region, and the first electrode 71 is formed on the second region to be electrically connected to the first semiconductor layer 20; wherein, the first stress buffer structure 31, the intermediate layer 40, the active layer 50, and the second semiconductor layer 60 are not provided between the second region and the first electrode 71.

[0028] In one embodiment of the present invention, the substrate 10, the first semiconductor layer 20, the first stress buffer structure 31, the intermediate layer 40, the active layer 50 and the second semiconductor layer 60 all include single crystal epitaxial structures. Each epitaxial structure is preferably formed by metal organic vapor deposition (MOCVD), and the material composition of each epitaxial structure can be adjusted by changing the flow rate of each reactant introduced into the reactor and / or the temperature of the reactor when forming the epitaxial structure. The difference between the lattice constant of the substrate 10 and the lattice constant of the first semiconductor layer 20 is not less than 1% of the lattice constant of the substrate 10, wherein the material of the substrate 10 includes sapphire, for example. The first semiconductor layer 20 includes a III-V compound having a first conductivity type, for example, including n-type gallium nitride (GaN) and having an n-type dopant (for example, silicon) and an n-type doping concentration between 1×10 18 ~5×10 18 / cm 3 The second semiconductor layer 60 includes a III-V compound having a second conductivity type, such as p-type GaN and a p-type dopant (such as magnesium) and a p-type dopant concentration between 1×10 19 ~5×10 20 / cm 3, wherein the second conductivity type is opposite to the first conductivity type. When the semiconductor element 1 is a light emitting diode (LED), the active layer 50, for example, comprises a III-V compound and a multiple quantum well (MQW) structure, wherein the multiple quantum well structure comprises a plurality of barrier layers 501 and a plurality of well layers 502 that are stacked alternately and emit visible light or invisible light when driven, wherein the number of overlapping pairs is between 3 and 15 pairs. The material of the well layer 501 has an energy band gap corresponding to the wavelength of the emitted light and is smaller than the band gap of the barrier layer 501, and the well layer 502, for example, comprises unintentionally doped In x Ga 1–x N (0.05≤x≤0.25) and has a thickness between 1 and 5 nm. The barrier layer 501 includes, for example, doped or unintentionally doped GaN and / or Al x Ga 1-x N (0.01≤x≤0.1) and has a thickness between 5 and 15 nm.

[0029] In one embodiment of the present invention, the first stress buffer structure 31 includes, for example, a plurality of first sub-layers 311 and a plurality of second sub-layers 312 alternately stacked to form a superlattice structure, wherein the number of overlapping pairs is between 3 and 10 pairs; wherein the second sub-layer 312 closest to the middle layer 40 is directly connected to the middle layer 40; wherein the material of the second sub-layer 312 includes an unintentionally doped III-V compound, such as In x Ga 1-x N (0.01≤x≤0.03); the material of the first sublayer 311 includes a first conductivity type III-V compound, such as n-type GaN or n-type In x Ga 1-x N (0.001≤x≤0.01) and having an n-type dopant (such as silicon) and an n-type doping concentration between 10 17 / cm 3 ~10 18 / cm 3 The first sublayer 311 does not contain indium or contains an indium content less than that of the second sublayer 312. The first sublayer 311 has a thickness between 10 and 50 nm; the second sublayer 312 has a thickness between 0.5 and 3 nm; and the first stress buffer structure 31 has a thickness between 50 and 500 nm.

[0030] In one embodiment of the present invention, the intermediate layer 40 includes a first portion 401 adjacent to the first stress buffer structure 31 and a second portion 402 adjacent to the active layer 50; the first portion 401 does not contain indium or contains an indium content less than that of the second portion 402, for example, contains GaN or In x Ga 1-x N(0 < x ≤ 0.01); the second portion 402 is directly connected to the first portion 401, and its material, for example, contains In x Ga 1-x N(0.001 ≤ x ≤ 0.02) and has an indium content greater than that of the first portion 401. In one embodiment of the present invention, the indium content of the second portion 402 is less than that of the second sub-layer 312 to reduce the piezoelectric strain generated between the first stress buffer structure 31 and the active layer 50. The intermediate layer 40 has a thickness less than 100 nm; preferably between 30 nm and 90 nm; wherein, the first portion 401 has a thickness between 10 nm and 50 nm, and the second portion 402 has a thickness between 0.5 nm and 15 nm; wherein, the ratio of the thickness of the second portion 402 to the thickness of the intermediate layer 40 is between 0.1 and 0.5. In one embodiment of the present invention, the indium content of the second portion 402 is less than that of the second sub-layer 312, and the thickness of the second portion 402 is greater than or equal to the thickness of the second sub-layer 312 to further reduce the piezoelectric strain generated between the first stress buffer structure 31 and the active layer 50. The first portion 401 and the second portion 402 each have an n-type dopant (such as silicon) and an n-type doping concentration between 10 18 / cm 3 and 10 19 / cm 3 . Preferably, the n-type doping concentration of the second portion 402 is greater than that of the first portion 401. In one embodiment of the present invention, the thickness of the intermediate layer 40 is less than the thickness of the first stress buffer structure 31.

[0031] Figure 2Disclosed is a second embodiment of a semiconductor device in accordance with the present invention. The semiconductor device 2 includes a substrate 10, a first semiconductor layer 20 formed on the substrate 10, a first stress buffer structure 31 formed on the first semiconductor layer 20, an intermediate layer 40 formed on the first stress buffer structure 20, a second stress buffer structure 32 formed on the intermediate layer 40, an active layer formed on the second stress buffer structure 32, a second semiconductor layer 60 formed on the active layer 50, a first electrode 71 electrically connected to the first semiconductor layer 20, and a second electrode 72 electrically connected to the second semiconductor layer 60. In an embodiment of the present invention, the first semiconductor layer 20 includes a first region and a second region, and the first stress buffer layer 31 is formed on the first region; the first electrode 71 is formed on the second region so as to be electrically connected to the first semiconductor layer 20; wherein, there is no first stress buffer structure 31, intermediate layer 40, second stress buffer structure 32, active layer 50, and second semiconductor layer 60 between the second region and the first electrode 71. The difference between the second embodiment and the first embodiment is that, in addition to all the structures of the semiconductor device 1, the semiconductor device 2 further includes a second stress buffer structure 32 formed between the intermediate layer 40 and the active layer 50, wherein the second stress buffer structure 32 includes a single crystal epitaxial structure, and the second stress buffer structure 32 includes, for example, a plurality of third sub-layers 321 and a plurality of fourth sub-layers 322 stacked alternately to form a superlattice structure, wherein the number of overlapping pairs is between 3 and 10 pairs. In an embodiment of the present invention, the fourth sub-layer 321 closest to the active layer 50 is directly connected to a barrier layer 502 of the active layer 50; the third sub-layer 321 closest to the intermediate layer 40 is directly connected to a second part 402 of the intermediate layer 40. The indium content of the fourth sub-layer 322 of the second stress buffer structure 32 is greater than the indium content of the second sub-layer 312 of the first stress buffer structure 31, wherein the third sub-layer 321 does not contain indium or contains an indium content less than that of the fourth sub-layer 322; the material of the third sub-layer 321 includes, for example, GaN or In x Ga 1-x N(0 < x ≤ 0.02), and the material of the fourth sub-layer 322 includes, for example, In x Ga 1-x N(0.03 ≤ x ≤ 0.1), wherein the indium content of the fourth sub-layer 322 is greater than that of the second sub-layer 312. Among them, the third sub-layer 321 has an n-type dopant (such as silicon) and an n-type doping concentration between 10 17 / cm 3 ~10 18 / cm 3The n-type doping concentration of the second part 402 of the intermediate layer is greater than the n-type doping concentration of the third sublayer 321 to reduce the compressive stress generated between the first stress buffer structure 31 and the active layer 50. Preferably, the n-type doping concentration of the second part 402 is greater than the n-type doping concentration of the first part 401 and the n-type doping concentration of the second part 402 is greater than the n-type doping concentration of the third sublayer 321 to further reduce the compressive stress generated between the first stress buffer structure 31 and the active layer 50. The third sublayer 321 has a thickness between 5 and 10 nm; the fourth sublayer 322 has a thickness between 0.5 and 3 nm; the second stress buffer structure 32 has a thickness between 30 and 80 nm. In one embodiment of the present invention, the thickness of the intermediate layer 40 is equivalent to or greater than the thickness of the second stress buffer structure 32, and the thickness of the intermediate layer 40 is less than the thickness of the first stress buffer structure 31. The description of the remaining structures of this embodiment is the same as that of the first embodiment, that is, Figure 2 and Figure 1 Structures with the same reference numerals represent the same structures as each other and have been described in detail in the first embodiment, which will not be repeated here.

[0032] The present invention can effectively reduce the compressive stress of semiconductor elements, reduce the forward voltage and improve the luminous efficiency. The embodiments listed in the present invention are only used to illustrate the present invention and are not used to limit the scope of the present invention. Any obvious modification or change made by anyone to the present invention does not deviate from the spirit and scope of the present invention.

Claims

1. A semiconductor element, characterized in that: Include: Active layer; a first semiconductor layer; A first stress buffer structure is located between the active layer and the first semiconductor layer, the first stress buffer structure comprises a plurality of first sub-layers and a plurality of second sub-layers overlapping each other, the band gaps of the plurality of second sub-layers are smaller than the band gaps of the plurality of first sub-layers; An intermediate layer is located between the first stress buffer structure and the active layer, wherein the intermediate layer includes a first portion adjacent to the first stress buffer structure and a second portion adjacent to the active layer, the second portion is directly connected to the first portion, and one of the multiple second sublayers closest to the intermediate layer is directly connected to the intermediate layer, wherein the indium content of the second portion is less than the indium content of the one of the multiple second sublayers.

2. The semiconductor device according to claim 1, wherein The first stress buffer structure includes an n-type doping concentration between 10 17 cm -3 ~10 18 cm -3 between.

3. The semiconductor element according to claim 1 or 2, wherein: The intermediate layer includes an n-type doping concentration between 10 18 cm -3 and 10 19 cm -3 between.

4. The semiconductor device according to claim 1, wherein The thickness of the intermediate layer is smaller than the thickness of the first stress buffer structure. 5 . The semiconductor device as claimed in claim 1 , wherein the number of pairs of the first sub-layers and the second sub-layers overlapping each other is between 3 and 10 pairs.

6. The semiconductor device according to claim 1 or 5, wherein: Each of the plurality of first sub-layers has a thickness ranging from 10 to 50 nm, and each of the plurality of second sub-layers has a thickness ranging from 0.5 to 3 nm.

7. The semiconductor device according to claim 1, wherein: The one of the plurality of second sub-layers includes In x Ga 1-x N.

8. The semiconductor device according to claim 1 or 7, wherein: The plurality of first sub-layers include GaN.

9. The semiconductor device according to claim 1, wherein: The n-type doping concentration of the second portion is greater than the n-type doping concentration of the first portion.

10. The semiconductor device according to claim 1, wherein The active layer includes multiple barrier layers and multiple well layers, and the multiple barrier layers include GaN and Al x Ga 1-x N(0.01≤x≤0.1). 11 . The semiconductor device as claimed in claim 1 , further comprising a second stress buffer structure located between the active layer and the intermediate layer. 12 . The semiconductor device as claimed in claim 11 , wherein the second stress buffer structure comprises a plurality of third sub-layers and a plurality of fourth sub-layers alternately stacked, and the number of overlapping pairs is between 3 and 10 pairs. 13 . The semiconductor device as claimed in claim 12 , wherein the fourth sub-layer closest to the active layer is directly connected to the barrier layer of the active layer. 14 . The semiconductor device as claimed in claim 12 , wherein the third sub-layer closest to the middle layer is directly connected to the second portion of the middle layer. 15 . The semiconductor device as claimed in claim 12 , wherein an indium content of the fourth sub-layer of the second stress buffer structure is greater than an indium content of the second sub-layer of the first stress buffer structure. 16 . The semiconductor device as claimed in claim 12 , wherein the third sub-layer does not contain indium, or an indium content of the third sub-layer is less than an indium content of the fourth sub-layer. 17 . The semiconductor device as claimed in claim 11 , wherein a thickness of the intermediate layer is equal to or greater than a thickness of the second stress buffering structure.

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