Integrated circuit device

Abstract

An integrated circuit device is provided, including: a plurality of fin-type active regions protruding from a top surface of a substrate and extending along a first horizontal direction; at least one semiconductor layer, each semiconductor layer including a lower semiconductor layer and an upper semiconductor layer sequentially stacked on at least one of the plurality of fin-type active regions; and a plurality of gate electrodes extending on the plurality of fin-type active regions along a second horizontal direction crossing the first horizontal direction, wherein the lower semiconductor layer includes a same material as a material of the upper semiconductor layer, and wherein there is a semiconductor interface between the lower semiconductor layer and the upper semiconductor layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0063309, filed on May 29, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The apparatus and method according to one or more exemplary embodiments relates to integrated circuit devices, and more specifically, to integrated circuit devices having multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). Background Technology

[0004] As the integration density of integrated circuit devices increases, the size of the devices has been reduced as much as possible, and the proportional reduction of devices has reached its limit. Therefore, to enhance device performance, it is necessary to change the device structure. In addition, it is also necessary to incorporate transistors with multiple characteristics within integrated circuit devices. Summary of the Invention

[0005] One or more exemplary embodiments provide an integrated circuit device having transistors with a variety of characteristics, such as multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0006] According to one aspect of an exemplary embodiment, an integrated circuit device is provided. The integrated circuit device includes: a plurality of finned active regions protruding from a top surface of a substrate and extending along a first horizontal direction; at least one semiconductor layer, each semiconductor layer including a lower semiconductor layer and an upper semiconductor layer sequentially stacked on at least one of the plurality of finned active regions; and a plurality of gate electrodes extending over the plurality of finned active regions along a second horizontal direction intersecting the first horizontal direction, wherein the lower semiconductor layer includes a material identical to that of the upper semiconductor layer, and wherein a semiconductor interface is provided between the lower semiconductor layer and the upper semiconductor layer.

[0007] According to one aspect of another exemplary embodiment, an integrated circuit device is provided, comprising: a plurality of first fin active regions extending from a top surface of a substrate in a first peripheral circuit region along a first horizontal direction; a plurality of second fin active regions extending from a top surface of the substrate in a second peripheral circuit region along the first horizontal direction; a plurality of first semiconductor layers on the plurality of first fin active regions, each first semiconductor layer including a first lower semiconductor layer and a first upper semiconductor layer sequentially stacked on a respective first fin active region in the plurality of first fin active regions, and a first semiconductor interface between the first lower semiconductor layer and the first upper semiconductor layer; a plurality of second semiconductor layers on the plurality of second fin active regions, each second semiconductor layer including a second lower semiconductor layer and a second upper semiconductor layer sequentially stacked on a respective second fin active region in the plurality of second fin active regions, and a second semiconductor interface between the second lower semiconductor layer and the second upper semiconductor layer; and a plurality of gate electrodes extending on the substrate in a second horizontal direction intersecting the first horizontal direction, wherein the highest height of the first semiconductor interface relative to the substrate in a vertical direction is higher than the highest height of the second semiconductor interface relative to the substrate in a vertical direction.

[0008] According to one aspect of another exemplary embodiment, an integrated circuit device is provided, comprising: a plurality of fin active regions protruding from a top surface of a substrate including cell regions and peripheral circuit regions and extending along a first horizontal direction; a nanosheet stack structure including a plurality of nanosheets stacked separately above the top surface of a first fin active region in a cell region among the plurality of fin active regions and extending parallel to the top surface of the first fin active region, each of the plurality of nanosheets including a channel region; at least one semiconductor layer, each semiconductor layer including a lower semiconductor layer and an upper semiconductor layer sequentially stacked on at least one second fin active region in a peripheral circuit region among the plurality of fin active regions and a semiconductor interface between the lower semiconductor layer and the upper semiconductor layer; and a plurality of gate electrodes extending over the plurality of fin active regions along a second horizontal direction intersecting the first horizontal direction. Attached Figure Description

[0009] Exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figures 1 to 13 , Figure 14A , Figure 14B , Figures 15 to 19 , Figure 20A and Figure 20B This is a cross-sectional view of the operation in a method of manufacturing an integrated circuit device according to one or more exemplary embodiments and the integrated circuit device thereby manufactured;

[0011] Figures 21 to 32 , Figure 33A , Figure 33B , Figures 34 to 38 , Figure 39A and Figure 39B This is a cross-sectional view of the operation in a method of manufacturing an integrated circuit device according to one or more exemplary embodiments and the integrated circuit device thereby manufactured; and

[0012] Figures 40 to 42 This is a cross-sectional view of the operation in a method of manufacturing an integrated circuit device according to one or more exemplary embodiments and the integrated circuit device thereby manufactured. Detailed Implementation

[0013] In the following text, it should be understood that expressions such as “at least one of A and B” include all possible combinations of the listed items. That is, “at least one of A and B” includes: (1) at least one A; (2) at least one B; or (3) at least one A and at least one B.

[0014] Figures 1 to 13 , Figure 14A , Figure 14B , Figures 15 to 19 , Figure 20A and Figure 20B This is a cross-sectional view of the operation in a method for manufacturing an integrated circuit device according to an exemplary embodiment of the present invention, and the integrated circuit device thereby manufactured. Specifically, Figures 1 to 13 , Figure 14A and Figure 20A It is a cross-sectional view taken along the YZ plane. Figure 14B , Figures 15 to 19 and Figure 20B It is a cross-sectional view taken along the XZ plane. Figure 14B It is along Figure 14A A cross-sectional view taken by the C-C' line and the P-P' line. Figures 15 to 19 Is along with Figure 14A A cross-sectional view taken at the corresponding positions of the C-C' line and the P-P' line, and Figure 20B It is along Figure 20A A cross-sectional view taken by the C-C' line and the P-P' line.

[0015] Reference Figure 1Multiple sacrificial semiconductor layers 106S and multiple nanosheet semiconductor layers NS are alternately stacked on a substrate 102 having a cell region CR and a peripheral circuit region PR. The sacrificial semiconductor layers 106S and nanosheet semiconductor layers NS may comprise different semiconductor materials. In some exemplary embodiments, the nanosheet semiconductor layer NS may comprise a single material. Alternatively, in some exemplary embodiments, the nanosheet semiconductor layer NS may comprise the same material as the material constituting the substrate 102. For example, the sacrificial semiconductor layer 106S may comprise SiGe, and the nanosheet semiconductor layer NS may comprise Si; however, it should be understood that one or more other exemplary embodiments are not limited thereto.

[0016] Each sacrificial semiconductor layer 106S may have the same thickness, although one or more other exemplary embodiments are not limited thereto. For example, according to another exemplary embodiment, the thickness of the sacrificial semiconductor layer 106S closest to the substrate 102 may be greater than the thickness of the other sacrificial semiconductor layers 106S.

[0017] Substrate 102 may include semiconductor materials such as Si or Ge, or compound semiconductor materials such as SiGe, SiC, GaAs, InAs, or InP. In some exemplary embodiments, substrate 102 may include at least one of group III-V and group IV materials. Group III-V materials may be binary, ternary, or quaternary compounds comprising at least one group III element and at least one group V element. In some exemplary embodiments, where an NMOS transistor is formed on a portion of substrate 102, that portion of substrate 102 may include any of the aforementioned group III-V materials. According to one or more other exemplary embodiments, where a PMOS transistor is formed on a portion of substrate 102, that portion of substrate 102 may include Ge. In another example, substrate 102 may have a semiconductor-on-insulator (SOI) structure. Substrate 102 may include conductive regions, such as impurity-doped wells or impurity-doped structures.

[0018] Reference Figure 2 A hard mask pattern HM is formed on the stacked structure of multiple sacrificial semiconductor layers 106S and multiple nanosheet semiconductor layers NS in the cell region CR. The hard mask pattern HM may not cover the stacked structure of the peripheral circuit region PR, which includes the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer NS, but may cover the entire stacked structure of the cell region CR, which includes the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer NS.

[0019] The hard mask pattern HM may have a stacked structure including a first hard mask layer HM-A and a second hard mask layer HM-B. For example, the first hard mask layer HM-A may include silicon oxide, and the second hard mask layer HM-B may include silicon nitride, polysilicon, spin-on hard mask (SOH) material, or a combination thereof. However, it should be understood that one or more other exemplary embodiments are not limited thereto.

[0020] A stacked recess SR is formed by removing a portion of the stacked structure, including the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer NS, within the peripheral circuit region PR using a hard mask pattern HM as an etching mask. Therefore, the top surface of the substrate 102 can be exposed within the peripheral circuit region PR.

[0021] After forming the stacked recess SR, a cover insulating layer 108 is formed, which conformally covers the inner sidewalls and bottom surface of the stacked recess SR, as well as the surface of the stacked structure, including the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer NS, on which the hard mask pattern HM is formed. The cover insulating layer 108 may include, for example, silicon oxide.

[0022] Reference Figure 2 and Figure 3 A portion of the covering insulating layer 108 is removed, for example, a portion of the covering insulating layer 108 on the top surface of the hard mask pattern HM in the cell region CR and a portion of the covering insulating layer 108 covering the top surface of the substrate 102 in the peripheral circuit region PR. Thus, a covering partition 108S is formed, covering the outer wall (i.e., the inner wall of the stacked groove RS) of the stacked structure on which the hard mask pattern HM is formed (i.e., the inner wall of the stacked groove RS).

[0023] Reference Figure 4 A semiconductor epitaxial layer 112 is formed on a substrate 102 in the peripheral circuit region PR. The crystallinity of the semiconductor epitaxial layer 112 may be the same as that of the substrate 102. The semiconductor epitaxial layer 112 can be formed by epitaxial growth using the exposed substrate 102 in the peripheral circuit region PR as a seed at a first temperature. The first temperature may be, for example, about 700°C to about 800°C. In some exemplary embodiments, the semiconductor epitaxial layer 112 may include the same material as the substrate 102, but is not limited thereto in one or more other exemplary embodiments. For example, the substrate 102 may include Si, and the semiconductor epitaxial layer 112 may include Ge or a compound semiconductor.

[0024] The thickness of the semiconductor epitaxial layer 112 can be greater than the thickness of the sacrificial semiconductor layer 106S closest to the substrate 102 among the sacrificial semiconductor layers 106S. In other words, the semiconductor epitaxial layer 112 can be grown such that the height LV of the top surface of the semiconductor epitaxial layer 112 is higher than the height LVN of the top surface of the sacrificial semiconductor layer 106S closest to the substrate 102 or the height LVN of the bottom surface of the nanosheet semiconductor layer NS closest to the substrate 102 among the nanosheet semiconductor layers NS. In some exemplary embodiments, the height LV of the top surface of the semiconductor epitaxial layer 112 can be lower than the height of the top surface of the nanosheet semiconductor layer NS closest to the substrate 102 among the nanosheet semiconductor layers NS.

[0025] In some exemplary embodiments, the top surface of the semiconductor epitaxial layer 112 may have a facet parallel to the top surface of the substrate 102. In one or more other exemplary embodiments, the top surface of the semiconductor epitaxial layer 112 may have multiple facets with different inclinations.

[0026] Reference Figure 5 An amorphous semiconductor layer 114A is formed on substrate 102, filling the stacking trench SR. The amorphous semiconductor layer 114A may cover the stacked structure of a sacrificial semiconductor layer 106S and a nanosheet semiconductor layer NS on which a hard mask pattern HM is formed, as well as the semiconductor epitaxial layer 112, and fill the stacking trench SR. The amorphous semiconductor layer 114A may comprise an amorphous semiconductor material. The amorphous semiconductor layer 114A may be formed at a second temperature. The second temperature may be lower than the first temperature used to grow the semiconductor epitaxial layer 112. The second temperature may be, for example, from about 500°C to about 650°C. In some exemplary embodiments, the amorphous semiconductor layer 114A may comprise the same material as the semiconductor epitaxial layer 112.

[0027] Reference Figure 5 and Figure 6 It can remove Figure 5 The portion of the semiconductor amorphous layer 114A shown outside the stacking recess SR, i.e., the portion of the semiconductor amorphous layer 114A above the top surface of the hard mask pattern HM, can be partially removed by, for example, a chemical mechanical polishing (CMP) operation, such that the top surface of the semiconductor amorphous layer 114A is at the same height as the top surface of the hard mask pattern HM.

[0028] Reference Figure 6 and Figure 8 It can be achieved by performing heat treatment at a third temperature. Figure 6The semiconductor amorphous layer 114A shown is crystallized to form the semiconductor crystalline layer 114. The third temperature can be lower than the first temperature used to grow the semiconductor epitaxial layer 112 and higher than the second temperature used to form the semiconductor amorphous layer 114A. For example, the third temperature can be lower than the first temperature and higher than the second temperature, and can be about 600°C to about 700°C.

[0029] The crystallinity of the semiconductor crystal layer 114 can be the same as that of the semiconductor epitaxial layer 112. Since the semiconductor epitaxial layer 112 is used as a seed during the heat treatment at the third temperature, the semiconductor crystal layer 114 can be formed when the semiconductor amorphous layer 114A crystallizes.

[0030] The semiconductor epitaxial layer 112 can be referred to as the lower semiconductor layer 112, and the semiconductor crystal layer 114 can be referred to as the upper semiconductor layer 114. The upper semiconductor layer 114 can be stacked on the lower semiconductor layer 112 and form a semiconductor layer 110 including the lower semiconductor layer 112 and the upper semiconductor layer 114.

[0031] In the following text, the semiconductor epitaxial layer 112 and the semiconductor crystal layer 114 can be used primarily to describe the method of manufacturing integrated circuit devices, while the lower semiconductor layer 112 and the upper semiconductor layer 114 can be used primarily to describe the structure of integrated circuit devices.

[0032] The semiconductor interface 110IF may exist between the semiconductor epitaxial layer 112 and the semiconductor crystalline layer 114. In some exemplary embodiments, the semiconductor interface 110IF may be along a plane parallel to the top surface of the substrate 102.

[0033] Common Reference Figure 5 and Figure 7 According to one or more other exemplary embodiments, heat treatment is performed at a third temperature to make Figure 5 The semiconductor amorphous layer 114A shown is crystallized to form the semiconductor crystalline layer 114. (Refer to...) Figure 7 and Figure 8 Remove Figure 7 The portion of the semiconductor crystal layer 114 shown outside the stacking recess SR, i.e., the portion of the semiconductor crystal layer 114 above the top surface of the hard mask pattern HM, can be partially removed by, for example, a CMP operation, such that the top surface of the semiconductor crystal layer 114 is at the same height as the top surface of the hard mask pattern HM.

[0034] Common Reference Figure 8 and Figure 9 Partial removal Figure 8The upper portion of the semiconductor crystal layer 114 shown is positioned such that the top surface of the semiconductor crystal layer 114 is at the same height as the top surface of the stacked structure of the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer NS (i.e., the top surface of the nanosheet semiconductor layer NS furthest from the substrate 102). The upper portion of the semiconductor crystal layer 114 can be partially removed, for example, by an etch-back operation. During the operation for partially removing the upper portion of the semiconductor crystal layer 114, the upper portion of the covering partition 108S can also be partially removed.

[0035] Common Reference Figure 9 and Figure 10 The hard mask pattern HM formed on the stacked structure including the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer NS in the cell region CR is removed. The top surface of the stacked structure of the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer NS (i.e., the top surface of the nanosheet semiconductor layer NS that is furthest from the substrate 102) can be at the same height as the top surface of the semiconductor layer 110 (i.e., the top surface of the semiconductor crystal layer 114) and can form a coplanar structure.

[0036] Common Reference Figure 10 and Figure 11 The stacked structure of the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer NS, the semiconductor layer 110 (i.e., the stacked structure of the semiconductor epitaxial layer 112 and the semiconductor crystal layer 114), and a portion of the substrate 102 are etched to form a plurality of trench TREs. Therefore, a plurality of finned active regions FA defined by the trench TREs can be formed in each of the cell region CR and the peripheral circuit region PR. The finned active regions FA can extend parallel to each other along a first horizontal direction (X direction). The finned active regions FA can protrude upward from the main surface 102M (e.g., the top surface) of the substrate 102 along a vertical direction (Z direction). In the cell region CR, the finned active regions FA can be arranged at a constant spacing in a second horizontal direction (Y direction). In the peripheral circuit region PR, the finned active regions FA can be arranged at a constant spacing in the second horizontal direction (Y direction). In some exemplary embodiments, the finned active regions FA can be arranged at the same spacing in the second horizontal direction (Y direction) in each of the cell region CR and the peripheral circuit region PR; however, it should be understood that one or more other exemplary embodiments are not limited thereto. For example, the fin-type active region FA can be arranged with a constant first spacing in the second horizontal direction (Y direction) in the cell region CR, and can be arranged with a constant second spacing in the second horizontal direction (Y direction) in the peripheral circuit region PR, where the second spacing is different from the first spacing.

[0037] A stacked structure NSS consisting of a sacrificial semiconductor layer 106S and multiple nanosheets N1, N2, and N3 can be disposed on the fin-type active region FA in the unit region CR. The nanosheet stacked structure NSS consisting of nanosheets N1, N2, and N3 can be formed by etching away a portion of the nanosheet semiconductor layer NS. A semiconductor layer 110 consisting of a lower semiconductor layer 112 and an upper semiconductor layer 114 can be disposed on the fin-type active region FA in the peripheral circuit region PR.

[0038] During the formation of the nanosheet stacked structure NSS of nanosheets N1, N2 and N3 and the fin-shaped active region FA, the covering wall 108S can be completely removed.

[0039] The nanosheet stacked structure NSS of nanosheets N1, N2, and N3 arranged on the fin-type active region FA in the unit region CR can be at essentially the same height as the semiconductor layer 110 arranged on the fin-type active region FA in the peripheral circuit region PR.

[0040] In the following text, the portion of substrate 102 defined by trench TRE in each of the cell region CR and peripheral circuit region PR is referred to as the fin active region FA. However, since the stacked structure of a portion of substrate 102, lower semiconductor layer 112, and upper semiconductor layer 114 essentially serves as the fin active region constituting the fin field-effect transistor (FinFET) in peripheral circuit region PR, the stacked structure of fin active region FA, lower semiconductor layer 112, and upper semiconductor layer 114 in peripheral circuit region PR can be referred to as fin stack structure FS. The fin stack structure FS may extend parallel to each other in a first horizontal direction (X direction) and protrude upward from the main surface 102M of substrate 102 in a vertical direction (Z direction).

[0041] Reference Figure 12 A pre-device isolation layer 118p is formed to fill the trench TRE. The pre-device isolation layer 118p can be formed to cover the sidewalls of the fin active region FA, the sidewalls and top surface of the nanosheet stacked structure NSS of nanosheets N1, N2 and N3, and the sidewalls and top surface of the semiconductor layer 110.

[0042] Common Reference Figure 12 and Figure 13 The device isolation layer 118 is formed by performing a recessing operation to remove a portion of the prepared device isolation layer 118p from its top surface to form a certain thickness. To perform the recessing operation, an etching process such as dry etching, wet etching, or a combination of dry and wet etching can be used.

[0043] A recessed operation can be performed so that the top surface of the device isolation layer 118 is at the same height or substantially similar to the top surface of the fin active region FA. Therefore, the sidewalls of the nanosheet stacked structure NSS of nanosheets N1, N2 and N3 on the fin active region FA in the cell region CR and the sidewalls of the semiconductor layer 110 on the fin active region FA in the peripheral circuit region PR can be exposed.

[0044] Common Reference Figure 14A and Figure 14B In the cell region CR and the peripheral circuit region PR, at least some of the following dummy gate structures DGS are formed, intersecting with at least some of the nanosheet stacked structure NSS, on which nanosheets N1, N2 and N3 are formed, the sacrificial semiconductor layer 106S, the fin active region FA, and the fin active region FA on which the semiconductor layer 110 is formed. The dummy gate structures DGS may extend parallel to each other along the second horizontal direction (Y direction).

[0045] The dummy gate structure (DGS) can have a structure in which an oxide film D12, a dummy gate layer D14, and a capping layer D16 are sequentially stacked. In an example of forming the dummy gate structure DGS, the oxide film D12, the dummy gate layer D14, and the capping layer D16 can be sequentially formed to cover the exposed surfaces of the nanosheet stacked structure NSS of nanosheets N1, N2, and N3 on the finned active region FA in the cell region CR, the exposed surface of the semiconductor layer 110 on the finned active region FA in the peripheral circuit region PR, and the top surface of the device isolation layer 118, respectively. Alternatively, the oxide film D12, the dummy gate layer D14, and the capping layer D16 can be patterned to leave only the necessary portions.

[0046] In some exemplary embodiments, the dummy gate layer D14 may include polysilicon and the capping layer D16 may include silicon nitride, but it should be understood that one or more other exemplary embodiments are not limited thereto.

[0047] Next, gate partitions 130 are formed covering the two sidewalls of the dummy gate structure DGS. To form the gate partitions 130, a partition layer can be formed on the semiconductor substrate 102 on which the dummy gate structure DGS is formed, and the partition layer can be etched back to leave the gate partitions 130. The gate partitions 130 may include, for example, a silicon nitride film.

[0048] Reference Figure 15The recessed region RS is formed by removing a portion of the nanosheet stacked structure NSS of nanosheets N1, N2, and N3, a portion of the sacrificial semiconductor layer 106S, and a portion of the semiconductor layer 110 through an etching operation using a dummy gate structure DGS and a gate partition 130 as an etching mask. The finned active region FA may be exposed at the bottom surface of the recessed region RS. In some exemplary embodiments, during the operation for etching the nanosheet stacked structure NSS of nanosheets N1, N2, and N3, a portion of the sacrificial semiconductor layer 106S, and a portion of the semiconductor layer 110, the upper portion of the finned active region FA may also be partially removed.

[0049] Common Reference Figure 15 and Figure 16 A removal space is formed by removing a portion of the sacrificial semiconductor layer 106S exposed on both sides of the nanosheet stacked structure NSS, for example, by performing an isotropic etching operation on the cell region CR. Then, an insulating partition 140 is formed to fill the removal space formed between the nanosheets N1, N2, and N3 in the cell region CR. The insulating partition 140 may include, for example, a silicon nitride film. In some exemplary embodiments, the insulating partition 140 may be formed by stacking multiple insulating layers.

[0050] After forming the insulating partition 140, a plurality of source / drain regions 160 are formed by epitaxially growing semiconductor materials from the two exposed sidewalls of nanosheets N1, N2 and N3 in the unit region CR and the exposed surface of the fin active region FA, as well as the exposed surface of the semiconductor layer 110 and the fin active region FA in the peripheral circuit region PR.

[0051] In some exemplary embodiments, some source / drain regions 160 and the remaining source / drain regions 160 may include different materials, and these source / drain regions 160 and the remaining source / drain regions 160 including different materials may be formed by performing separate epitaxial growth operations. For example, these source / drain regions 160 may include Ge. In some exemplary embodiments, some source / drain regions 160 may have a multilayer structure comprising a semiconductor material including Si and a semiconductor material including Ge.

[0052] For example, the remaining source / drain regions 160 may include Si instead of Ge. In some exemplary embodiments, the remaining source / drain regions 160 may include a multilayer structure of semiconductor materials such as Si and compound semiconductor materials such as SiC.

[0053] Common Reference Figure 16 and Figure 17An inter-gate insulating film 172 is formed on the dummy gate structure DGS and the source / drain region 160. The capping layer D16 covering the top surface of the dummy gate layer D14 is removed by planarizing the inter-gate insulating film 172, and the gate partition 130 surrounding the capping layer D16 and the inter-gate insulating film 172 are polished from their top surfaces to a portion of their thickness. Therefore, the top surface of the inter-gate insulating film 172 is at approximately the same height as the top surface of the dummy gate layer D14. In some exemplary embodiments, the inter-gate insulating film 172 may include a silicon oxide film.

[0054] Common Reference Figure 17 and Figure 18 The dummy gate layer D14 exposed through the inter-gate insulating film 172 and the gate partition 130, as well as the oxide film D12 beneath the dummy gate layer D14, are removed, and the sacrificial semiconductor layer 106S remaining on the fin active region FA is at least partially removed, thereby forming a plurality of gate spaces GS. The surfaces of nanosheets N1, N2, and N3 in the cell region CR and the top surface of the fin active region FA can be partially exposed through the gate spaces GS, and the surface of the fin stack structure FS in the peripheral circuit region PR can be exposed. In some exemplary embodiments, a portion of the sacrificial semiconductor layer 106S may be retained without removal.

[0055] Common Reference Figure 18 and Figure 19 A gate dielectric film 145 is formed on the exposed surface in the gate space GS, and a plurality of gate electrodes 150 are formed to fill the gate space GS above the gate dielectric film 145. The gate electrodes 150 may extend parallel to each other along a second horizontal direction (Y direction).

[0056] The gate dielectric film 145 may include a stacked structure of an interface layer and a high-k film. In some exemplary embodiments, the interface layer may include a low-k material layer with a dielectric constant of about 9 or less, such as a silicon oxide film, a silicon oxynitride film, or a combination thereof. In some exemplary embodiments, the interface layer may be omitted. The high-k film may include a material with a dielectric constant greater than that of the silicon oxide film. For example, the high-k film may have a dielectric constant of about 10 to about 25.

[0057] The gate electrode 150 may include a work function control metal layer and a gap-filled metal layer for filling the space above the work function control metal layer. In some exemplary embodiments, the gate electrode 150 may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-filled metal layer are stacked in sequence.

[0058] In the cell region CR, the gate electrode 150 may include a main gate portion 150M covering the top surface of the nanosheet stacked structure NSS including nanosheets N1, N2 and N3, and a plurality of sub-gate portions 150S connected to the main gate portion 150M and formed in the space between the nanosheets N1, N2 and N3 and the fin active region FA.

[0059] In the cell region CR, insulating partitions 140 can be provided at both ends of each sub-grid portion 150S, with a grid dielectric film 145 between them.

[0060] In the peripheral circuit region PR, the gate electrode 150 may include a main gate portion 150M covering the top surface of the fin stack structure FS, but does not include a sub-gate portion 150S.

[0061] Common Reference Figure 20A and Figure 20B An interlayer insulating film 174 is formed covering the gate electrode 150 and the inter-gate insulating film 172. Then, a plurality of first contact holes 192H exposing the source / drain regions 160 are formed by partially etching the interlayer insulating film 174 and the inter-gate insulating film 172, and metal silicide films 162 are formed on the top surfaces of the source / drain regions 160 exposed through the first contact holes 192H. Furthermore, a plurality of second contact holes 194H exposing the top surface of the gate electrode 150 (i.e., the top surface of the main gate portion 150M) are formed by partially etching the interlayer insulating film 174. In some exemplary embodiments, the first contact holes 192H and the second contact holes 194H can be formed together by a single etching operation. However, it should be understood that one or more other exemplary embodiments are not limited thereto, and the first contact holes 192H and the second contact holes 194H can be formed by separate etching operations.

[0062] Next, a plurality of first contact plugs 192 filling the first contact hole 192H and a plurality of second contact plugs 194 filling the second contact hole 194H are formed, thereby forming an integrated circuit device 1.

[0063] The first contact plug 192 can be connected to the source / drain region 160 via a metal silicide film 162, and the second contact plug 194 can be connected to the gate electrode 150. In some exemplary embodiments, the first contact plug 192 and the second contact plug 194 can be formed together, but it should be understood that one or more other exemplary embodiments are not limited thereto. For example, according to another exemplary embodiment, a plurality of first contact plugs 192 and a plurality of second contact plugs 194 can be formed by separate operations.

[0064] The integrated circuit device 1 includes: a fin-type active region FA protruding from the main surface 102M of the substrate 102 in a vertical direction (Z direction) and extending in a first horizontal direction (X direction); a nanosheet stacked structure NSS facing the top surface of the fin-type active region FA at a position separated from the top surface of the fin-type active region FA in the cell region CR; and semiconductor layers 110 respectively disposed on the fin-type active region FA in the peripheral circuit region PR. The cell region CR may be provided with a multi-gate MOSFET, and the peripheral circuit region PR may be provided with a single-gate MOSFET.

[0065] A trench TRE defining a fin-type active region FA can be formed in the substrate 102. The sidewalls of the fin-type active region FA can be covered by a device isolation layer 118 that fills the trench TRE. The top surface of the fin-type active region FA and the top surface of the device isolation layer 118 can be the same or similar in height.

[0066] The nanosheet stacked structure NSS is separated from the top surface of the fin-type active region FA. The nanosheet stacked structure NSS may include nanosheets N1, N2 and N3 extending on the substrate 102 parallel to the top surface of the fin-type active region FA.

[0067] Nanosheets N1, N2, and N3 constituting a nanosheet stacked structure NSS are sequentially stacked on the top surface of the fin-shaped active region FA in the unit cell region CR. Although the present exemplary embodiment illustrates a nanosheet stacked structure NSS comprising three nanosheets N1, N2, and N3, this is merely an example, and it should be understood that one or more other exemplary embodiments are not limited thereto. Nanosheets N1, N2, and N3 may each have a channel region. For example, nanosheets N1, N2, and N3 may comprise a single material. In some exemplary embodiments, nanosheets N1, N2, and N3 may comprise the same material as the substrate 102 constituting the unit cell region CR.

[0068] A lower semiconductor layer 112 and an upper semiconductor layer 114 constituting a semiconductor layer 110 are sequentially stacked on the top surface of the finned active region FA in the peripheral circuit region PR. For example, the lower semiconductor layer 112 and the upper semiconductor layer 114 may comprise a single material. In the peripheral circuit region PR, the finned active region FA, the lower semiconductor layer 112, and the upper semiconductor layer 114 have the same crystallinity, wherein a semiconductor interface 110IF may be present between the top surface of the lower semiconductor layer 112 and the bottom surface of the upper semiconductor layer 114, which are in contact with each other. In some exemplary embodiments, the lower semiconductor layer 112 and the upper semiconductor layer 114 may comprise the same material as the material constituting the finned active region FA in the peripheral circuit region PR.

[0069] In some exemplary embodiments, the semiconductor interface 110IF may be along a plane parallel to the top surface or main surface 102M of the substrate 102. For example, in the peripheral circuit region PR, the semiconductor interface 110IF of each semiconductor layer 110 stacked on the top surface of the fin active region FA may be on the same plane parallel to the top surface or main surface 102M of the substrate 102.

[0070] In the vertical direction (Z direction), the height LV of the semiconductor interface 110IF can be higher than the height LVN of the bottom surface of the nanosheet N1 closest to the substrate 102 in the nanosheet stacked structure NSS of nanosheets N1, N2, and N3. The height LVN of the bottom surface of the nanosheet N1 closest to the substrate 102 in the nanosheet stacked structure NSS of nanosheets N1, N2, and N3 can be referred to as the reference height LVN. In some embodiments, the height LV of the semiconductor interface 110IF can be higher than the reference height LVN, but lower than the height of the top surface of the nanosheet N1 closest to the substrate 102 in the nanosheet stacked structure NSS of nanosheets N1, N2, and N3.

[0071] The nanosheet stacked structure NSS of nanosheets N1, N2, and N3 arranged on the fin-type active region FA in the unit region CR can be at essentially the same height as the semiconductor layer 110 arranged on the fin-type active region FA in the peripheral circuit region PR.

[0072] On the finned active region FA, the gate electrode 150 may extend along a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction). The gate electrode 150 may at least partially overlap with the nanosheet stacked structure NSS in the unit region CR in the vertical direction (Z direction), and may at least partially overlap with the finned stacked structure FS in the peripheral circuit region PR in the vertical direction (Z direction).

[0073] Each gate electrode 150 in the cell region CR can be formed to at least partially surround nanosheets N1, N2, and N3, while covering the nanosheet stacked structure NSS. In the cell region CR, the gate electrode 150 may include a main gate portion 150M covering the top surface of the nanosheet stacked structure NSS and a sub-gate portion 150S connected to the main gate portion 150M and formed in the space between the fin-type active region FA and nanosheets N1, N2, and N3 (i.e., below nanosheets N1, N2, and N3). A gate dielectric film 145 is formed between the nanosheet stacked structure NSS and the gate electrode 150.

[0074] In the peripheral circuit region PR, the gate electrode 150 can be formed to cover the surface of the fin stack structure FS. In the peripheral circuit region PR, the gate electrode 150 may include only the main gate portion 150M, and may not include the sub-gate portion 150S. A gate dielectric film 145 is formed between the fin stack structure FS and the gate electrode 150.

[0075] Source / drain regions 160 are formed on fin-type active regions FA in the unit cell region CR and the peripheral circuit region PR. In the unit cell region CR, source / drain regions 160 are connected to one of the ends of adjacent nanosheets N1, N2, and N3. In the peripheral circuit region PR, source / drain regions 160 are connected to the sidewalls of adjacent fin-type stacked structures FS.

[0076] A gate partition 130 is formed on the nanosheet stacked structure NSS and the fin stacked structure FS, covering the sidewalls of the gate electrode 150. The gate partition 130 may include a silicon nitride film, but is not limited thereto in one or more other exemplary embodiments. The gate partition 130 may cover the sidewalls of the main gate portion 150M of the gate electrode 150.

[0077] In the cell region CR, an insulating partition 140 in contact with the source / drain region 160 is formed in the space between nanosheets N1, N2, and N3. The insulating partition 140 may be disposed between the sub-gate portion 150S and the source / drain region 160 in the space between the finned active region FA and the nanosheets N1, N2, and N3.

[0078] On the source / drain region 160, an inter-gate insulating film 172 and an inter-layer insulating film 174 are sequentially formed. Both the inter-gate insulating film 172 and the inter-layer insulating film 174 may comprise silicon oxide films, but it should be understood that one or more other exemplary embodiments are not limited thereto.

[0079] The first contact plug 192 can be connected to the source / drain region 160. The first contact plug 192 can be connected to the source / drain region 160 through the interlayer insulating film 174 and the gate insulating film 172. The metal silicide film 162 can be located between the source / drain region 160 and the first contact plug 192. In some exemplary embodiments, the metal silicide film 162 can be omitted.

[0080] The second contact plug 194 can be connected to the gate electrode 150. The second contact plug 194 can be connected to the gate electrode 150 through the interlayer insulating film 174.

[0081] Both the first contact plug 192 and the second contact plug 194 may include metal, conductive metal nitride, or a combination thereof.

[0082] In the integrated circuit device 1 according to an exemplary embodiment, the lower semiconductor layer 112 of the semiconductor layer 110, which is substantially at the same height as the nanosheet stacked structure NSS of nanosheets N1, N2, and N3, can be formed by epitaxial growth at a first temperature. Simultaneously, the upper semiconductor layer 114 can be formed by forming a semiconductor amorphous layer at a second temperature below the first temperature and crystallizing the semiconductor amorphous layer by heat treatment at a third temperature below the first temperature and above the second temperature. Therefore, all semiconductor layers (with the fin-type stacked structure FS formed at the first temperature) Figure 10 Compared to the case of 110), the semiconductor layer 110 can be formed at a relatively low temperature range. Therefore, it is possible to prevent the formation of the semiconductor layer 110 due to sacrificial semiconductor layer ( Figure 10 106S) and nanosheet semiconductor layer ( Figure 10 The diffusion that occurs in the stacked structure of the NS (NS) results in changes in the thickness of the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer NS, thereby ensuring the reliability of the integrated circuit device 1.

[0083] Figures 21 to 32 , Figure 33A , Figure 33B , Figures 34 to 38 , Figure 39A and Figure 39B This is a cross-sectional view of the operation in a method of manufacturing an integrated circuit device according to one or more exemplary embodiments, and the integrated circuit device thereby manufactured. The following references may be omitted. Figures 1 to 13 , Figure 14A , Figure 14B , Figures 15 to 19 , Figure 20A and Figure 20B Descriptions that are identical or substantially similar are given. Specifically, Figures 21 to 32 , Figure 33A and Figure 39A It is a cross-sectional view taken along the YZ plane. Figure 33B , Figures 34 to 38 and Figure 39B It is a cross-sectional view taken along the XZ plane. Figure 33B It is along Figure 33A Cross-sectional views taken by lines C-C', P1-P1', and P2-P2'. Figures 34 to 38 Is along with Figure 33A Cross-sectional views taken at the positions corresponding to lines C-C', P1-P1', and P2-P2'. Figure 39B It is along Figure 39A A cross-sectional view taken from the C-C' line, P1-P1' line, and P2-P2' line.

[0084] Reference Figure 21A sacrificial semiconductor layer 106S and a nanosheet semiconductor layer NS are alternately stacked on a substrate 102 having a cell region CR, a first peripheral circuit region PRN, and a second peripheral circuit region PRW. In some exemplary embodiments, the width of the second peripheral circuit region PRW in the second horizontal direction (Y direction) may be greater than the width of the first peripheral circuit region PRN.

[0085] Reference Figure 22 A hard mask pattern HM is formed on a stacked structure comprising multiple sacrificial semiconductor layers 106S and multiple nanosheet semiconductor layers NS in the cell region CR. The hard mask pattern HM may have a stacked structure comprising a first hard mask layer HM-A and a second hard mask layer HM-B.

[0086] A stacked recess SR is formed by removing portions of the stacked structure, including the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer NS, in the first peripheral circuit region PRN and the second peripheral circuit region PRW using a hard mask pattern HM as an etching mask. Therefore, the top surface of the substrate 102 can be exposed in the first peripheral circuit region PRN and the second peripheral circuit region PRW.

[0087] After forming the stacked groove SR, a covering insulating layer 108 is formed, which conformally covers the inner sidewalls and bottom surface of the stacked groove SR, as well as the surface of the stacked structure including the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer NS on which the hard mask pattern HM is formed.

[0088] In some exemplary embodiments, the first width W1 of the stacked recess SR defined by the covering insulating layer 108 in the first peripheral circuit region PRN in the second horizontal direction (Y direction) may be smaller than the second width W2 in the second peripheral circuit region PRW.

[0089] Reference Figure 22 and Figure 23 A portion of the covering insulating layer 108 is removed, for example, a portion of the covering insulating layer 108 on the top surface of the hard mask pattern HM in the cell region CR and a portion of the covering insulating layer 108 covering the top surface of the substrate 102 in the first peripheral circuit region PRN and the second peripheral circuit region PRW, to form a covering partition 108S covering the outer wall (i.e., the inner wall of the stacking groove RS) of the stacked structure on which the hard mask pattern HM is formed.

[0090] Reference Figure 24A first semiconductor epitaxial layer 112N is formed on substrate 102 in the first peripheral circuit region PRN, and a second semiconductor epitaxial layer 112W is formed on substrate 102 in the second peripheral circuit region PRW. Both the first semiconductor epitaxial layer 112N and the second semiconductor epitaxial layer 112W can be formed by epitaxial growth at a first temperature to have the same crystallinity as the substrate 102 beneath them. The first temperature can be, for example, from about 700°C to about 800°C.

[0091] Both the first semiconductor epitaxial layer 112N and the second semiconductor epitaxial layer 112W can be formed with a thickness greater than that of the sacrificial semiconductor layer 106S closest to the substrate 102 among the sacrificial semiconductor layers 106S. In other words, the first height LV1, which is the highest height of the top surface of the first semiconductor epitaxial layer 112N, and the second height LV2, which is the highest height of the top surface of the second semiconductor epitaxial layer 112W, can be higher than the height LVN of the top surface of the sacrificial semiconductor layer 106S closest to the substrate 102 among the sacrificial semiconductor layers 106S, or the height LVN of the bottom surface of the nanosheet semiconductor layer NS closest to the substrate 102 among the nanosheet semiconductor layers NS. In some exemplary embodiments, the first height LV1 can be higher than the second height LV2. In other words, the thickness of the first semiconductor epitaxial layer 112N can be greater than the thickness of the second semiconductor epitaxial layer 112W.

[0092] In some exemplary embodiments, the top surfaces of the first semiconductor epitaxial layer 112N and the second semiconductor epitaxial layer 112W may each have multiple surfaces with different inclinations. For example, the top surfaces of the first semiconductor epitaxial layer 112N and the second semiconductor epitaxial layer 112W may each have a surface parallel to the top surface of the substrate 102 and at least one surface with an inclination relative to the top surface of the substrate 102.

[0093] Reference Figure 25 An amorphous semiconductor layer 114A is formed on substrate 102 to fill the stacking trench SR. The amorphous semiconductor layer 114A can be formed at a second temperature to cover the stacked structure of a sacrificial semiconductor layer 106S and a nanosheet semiconductor layer NS on which a hard mask pattern HM is formed, a first semiconductor epitaxial layer 112N, and a second semiconductor epitaxial layer 112W, and to fill the stacking trench SR. The second temperature can be lower than the first temperature. The second temperature can be, for example, from about 500°C to about 650°C.

[0094] Reference Figure 26 Remove Figure 25 The portion of the semiconductor amorphous layer 114A shown is outside the stacking groove SR, that is, the portion of the semiconductor amorphous layer 114A above the top surface of the hard mask pattern HM.

[0095] Reference Figure 26 and Figure 27 The semiconductor crystalline layer 114 is formed by crystallizing the semiconductor amorphous layer 114A through heat treatment at a third temperature. The third temperature can be lower than the first temperature and higher than the second temperature. For example, the third temperature can be about 600°C to about 700°C.

[0096] In some exemplary embodiments, such as Figure 5 , Figure 7 and Figure 8 As shown, in making Figure 25 After the semiconductor amorphous layer 114A shown is crystallized, the portion in which the height corresponds to the height above the top surface of the hard mask pattern HM can be removed, thereby forming the semiconductor crystalline layer 114.

[0097] The first semiconductor epitaxial layer 112N and semiconductor crystal layer 114 in the first peripheral circuit region PRN can be referred to as the first lower semiconductor layer 112N and the first upper semiconductor layer 114, respectively, and can constitute the first semiconductor layer 110N in the first peripheral circuit region PRN, including the first lower semiconductor layer 112N and the first upper semiconductor layer 114. The second semiconductor epitaxial layer 112W and semiconductor crystal layer 114 in the second peripheral circuit region PRW can be referred to as the second lower semiconductor layer 112W and the second upper semiconductor layer 114, respectively, and can constitute the second semiconductor layer 110W in the second peripheral circuit region PRW, including the second lower semiconductor layer 112N and the second upper semiconductor layer 114.

[0098] A first semiconductor interface 110NIF and a second semiconductor interface 110WIF can be observed between the first semiconductor epitaxial layer 112N and the semiconductor crystal layer 114, and between the second semiconductor epitaxial layer 112W and the semiconductor crystal layer 114, respectively. In some exemplary embodiments, both the first semiconductor interface 110NIF and the second semiconductor interface 110WIF may include multiple planes with different tilt angles. For example, both the first semiconductor interface 110NIF and the second semiconductor interface 110WIF may have a surface parallel to the top surface of the substrate 102 and at least one surface with a tilt angle relative to the top surface of the substrate 102.

[0099] Common Reference Figure 27 and Figure 28 Partial removal Figure 27 The upper portion of the semiconductor crystal layer 114 shown is positioned such that the top surface of the semiconductor crystal layer 114 is at the same height as the top surface of the stacked structure of the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer NS (i.e., the top surface of the nanosheet semiconductor layer NS furthest from the substrate 102). During the operation of partially removing the upper portion of the semiconductor crystal layer 114, the upper portion of the covering partition 108S can also be partially removed.

[0100] Common Reference Figure 28 and Figure 29 The hard mask pattern HM formed on the stacked structure including the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer NS in the cell region CR is removed.

[0101] Common Reference Figure 29 and Figure 30 The stacked structure of the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer NS, the first semiconductor layer 110N, the second semiconductor layer 110W, and a portion of the substrate 102 are etched to form a trench TRE. Therefore, a plurality of first finned active regions FA-N defined by the trench TRE can be formed in the first peripheral circuit region PRN, a plurality of second finned active regions FA-W defined by the trench TRE can be formed in the second peripheral circuit region PRW, and a plurality of third finned active regions FA defined by the trench TRE can be formed in the cell region CR. The first finned active regions FA-N, the second finned active regions FA-W, and the third finned active regions FA can extend parallel to each other along a first horizontal direction (X direction). The first finned active regions FA-N, the second finned active regions FA-W, and the third finned active regions FA can protrude upward from the main surface 102M of the substrate 102 in the vertical direction (Z direction) of the first peripheral circuit region PRN, the second peripheral circuit region PRW, and the cell region CR, respectively.

[0102] The first semiconductor layer 110N, as a stacked structure of the first lower semiconductor layer 112N and the first upper semiconductor layer 114, can be disposed on the first fin active region FA-N in the first peripheral circuit region PRN. The second semiconductor layer 110W, as a stacked structure of the second lower semiconductor layer 112W and the second upper semiconductor layer 114, can be disposed on the second fin active region FA-W in the second peripheral circuit region PRW. In the second horizontal direction (Y direction), the width of the first semiconductor layer 110N can be smaller than the width of the second semiconductor layer 110W.

[0103] A stacked structure NSS consisting of a sacrificial semiconductor layer 106S and multiple nanosheets N1, N2 and N3 can be set on the third fin-type active region FA in the cell region CR.

[0104] The nanosheet stacked structure NSS of nanosheets N1, N2 and N3 arranged on the third fin active region FA in the unit region CR, the first semiconductor layer 110N arranged on the first fin active region FA-N in the first peripheral circuit region PRN, and the second semiconductor layer 110W arranged on the second fin active region FA-W in the second peripheral circuit region PRW can be at substantially the same height.

[0105] During the formation of the nanosheet stacked structure NSS of nanosheets N1, N2 and N3, the first semiconductor layer 110N and the second semiconductor layer 110W, the covering partition 108S can be completely removed.

[0106] Each first semiconductor layer 110N may have a first semiconductor interface 110NIF between a first lower semiconductor layer 112N and a first upper semiconductor layer 114. In some exemplary embodiments, some first semiconductor interfaces 110NIF may be along a plane having an inclination relative to the top surface or main surface 102M of the substrate 102. Furthermore, some first semiconductor interfaces 110NIF may be along a plane parallel to the top surface or main surface 102M of the substrate 102. Additionally, at least one outer first semiconductor layer 110N of the first semiconductor layers 110N disposed in the first peripheral circuit region PRN may have a first semiconductor interface 110NIF along a plane having an inclination relative to the top surface or main surface 102M of the substrate 102, and at least one inner first semiconductor layer 110N of the first semiconductor layers 110N may have a first semiconductor interface 110NIF along a plane parallel to the top surface or main surface 102M of the substrate 102.

[0107] Each second semiconductor layer 110W may have a second semiconductor interface 110WIF between the second lower semiconductor layer 112W and the second upper semiconductor layer 114. In some exemplary embodiments, some second semiconductor interfaces 110WIF may be along a plane having an inclination relative to the top surface or main surface 102M of the substrate 102. Furthermore, some second semiconductor interfaces 110WIF may be along a plane parallel to the top surface or main surface 102M of the substrate 102. Additionally, the second semiconductor interface 110WIF of at least one outer second semiconductor layer 110W disposed in the second peripheral circuit region PRW may have multiple surfaces with different inclinations. For example, the second semiconductor interface 110WIF of at least one outer second semiconductor layer 110W disposed in the second peripheral circuit region PRW may simultaneously have a surface having an inclination relative to the top surface or main surface 102M of the substrate 102 and a surface parallel to the top surface or main surface 102M of the substrate 102. In some exemplary embodiments, the second semiconductor interface 110WIF of at least one inner second semiconductor layer 110W disposed in the second peripheral circuit region PRW may be along a plane parallel to the top surface or main surface 102M of the substrate 102.

[0108] Furthermore, the second semiconductor interface 110WIF of at least one second semiconductor layer 110W disposed in the second peripheral circuit region PRW, which includes a second semiconductor interface 110WIF having multiple surfaces with different inclinations, and the second semiconductor layer 110W including a second semiconductor interface 110WIF having a surface parallel to the top surface or main surface 102M of the substrate 102, may be along a plane having an inclination relative to the top surface or main surface 102M of the substrate 102.

[0109] The stacked structure of the first fin-type active region FA-N, the first lower semiconductor layer 112N, and the first upper semiconductor layer 114 in the first peripheral circuit region PRN can be referred to as the first fin-type stacked structure FS-N, while the stacked structure of the second fin-type active region FA-W, the second lower semiconductor layer 112W, and the second upper semiconductor layer 114 in the second peripheral circuit region PRW can be referred to as the second fin-type stacked structure FS-W.

[0110] Reference Figure 31 A pre-device isolation layer 118p is formed to fill the trench TRE. The pre-device isolation layer 118p can be formed to cover the sidewalls and top surface of the third fin active region FA and the nanosheet stacked structure NSS of nanosheets N1, N2 and N3 in the cell region CR, the sidewalls and top surface of the first fin stacked structure FS-N in the first peripheral circuit region PRN, and the sidewalls and top surface of the second fin stacked structure FS-W in the second peripheral circuit region PRW.

[0111] Common Reference Figure 31 and Figure 32 The device isolation layer 118 is formed by performing a recess operation to remove a portion of its thickness from the top surface of the prepared device isolation layer 118p. The sidewalls of the nanosheet stacked structure NSS of nanosheets N1, N2 and N3 in the cell region CR and the sacrificial semiconductor layer 106S, the sidewalls of the first semiconductor layer 110N in the first peripheral circuit region PRN and the sidewalls of the second semiconductor layer 110W in the second peripheral circuit region PRW can be exposed and not covered by the device isolation layer 118.

[0112] In the second horizontal direction (Y direction), the third width w3 of the first semiconductor layer 110N can be smaller than the fourth width w4 of the second semiconductor layer 110W. Furthermore, the width of the first finned active region FA-N in the second horizontal direction (Y direction) can be approximately similar to or slightly larger than the third width W3, and the width of the second finned active region FA-W in the second horizontal direction (Y direction) can be approximately similar to or slightly larger than the fourth width W4. In other words, the width of the first finned active region FA-N in the second horizontal direction (Y direction) can be smaller than the width of the second finned active region FA-W.

[0113] Common Reference Figure 33A and Figure 33B A dummy gate structure DGS is formed that extends and intersects with at least a portion of the following: a first finned active region FA-N in the first peripheral circuit region PRN on which a first semiconductor layer 110N is formed; a second finned active region FA-W in the second peripheral circuit region PRW on which a second semiconductor layer 110W is formed; a nanosheet stacked structure NSS in the unit region CR on which nanosheets N1, N2, and N3 are formed; and a third finned active region FA in the sacrificial semiconductor layer 160S. The dummy gate structure DGS may extend parallel to each other along a second horizontal direction (Y direction). The dummy gate structure DGS may have a structure in which an oxide film D12, a dummy gate layer D14, and a capping layer D16 are sequentially stacked. Next, gate partitions 130 are formed covering the two sidewalls of the dummy gate structure DGS.

[0114] Reference Figure 34 The recessed region RS is formed by removing a portion of the nanosheet stacked structure NSS of nanosheets N1, N2, and N3, a portion of the sacrificial semiconductor layer 106S, a portion of the first semiconductor layer 110N, and a portion of the second semiconductor layer 110W through an etching operation using a dummy gate structure DGS and a gate partition 130 as an etching mask. In some exemplary embodiments, during the formation of the recessed region RS, the upper portions of the first finned active region FA-N, the second finned active region FA-W, and the third finned active region FA may be partially removed together.

[0115] Common Reference Figure 34 and Figure 35 After removing a portion of the sacrificial semiconductor layer 106S exposed on both sides of the nanosheet stacked structure NSS by performing an isotropic etching operation on the cell region CR to form a removal space, an insulating partition 140 is formed to fill the removal space formed between the nanosheets N1, N2 and N3.

[0116] Next, source / drain regions 160 are formed by epitaxially growing semiconductor materials from the exposed sidewalls of nanosheets N1, N2 and N3 in the cell region CR, the exposed surface of the third fin active region FA, the exposed surface of the first fin stacked structure FS-N in the first peripheral circuit region PRN, and the exposed surface of the second fin stacked structure FS-W in the second peripheral circuit region PRW.

[0117] Common Reference Figure 35 and Figure 36 An inter-gate insulating film 172 is formed on the dummy gate structure DGS and the source / drain region 160. The capping layer D16 covering the top surface of the dummy gate layer D14 is removed by planarizing the inter-gate insulating film 172, and the gate partition 130 surrounding the capping layer D16 and the inter-gate insulating film 172 are polished from their top surfaces to a certain thickness. Therefore, the top surface of the inter-gate insulating film 172 is at approximately the same height as the top surface of the dummy gate layer D14.

[0118] Common Reference Figure 36 and Figure 37 The dummy gate layer D14 exposed through the inter-gate insulating film 172 and the oxide film D12 below the dummy gate layer D14 are removed, and the sacrificial semiconductor layer 106S remaining on the third fin active region FA in the cell region CR is removed at least partially, thereby forming a plurality of gate spaces GS.

[0119] Common Reference Figure 37 and Figure 38 A gate dielectric film 145 is formed on the exposed surface in the gate space GS of the cell region CR, the first peripheral circuit region PRN, and the second peripheral circuit region PRW, and a gate electrode 150 is formed to fill the gate space GS above the gate dielectric film 145. The gate electrodes 150 may extend parallel to each other along the second horizontal direction (Y direction).

[0120] In the cell region CR, the gate electrode 150 may include a main gate portion 150M and a sub-gate portion 150S connected to the main gate portion 150M. In the cell region CR, an insulating partition 140 may be disposed at both ends of each sub-gate portion 150S, with a gate dielectric film 145 between them.

[0121] In the first peripheral circuit region PRN and the second peripheral circuit region PRW, the gate electrode 150 may include a main gate portion 150M covering the first fin stacked structure FS-N and the second fin stacked structure FS-W, and may not include a sub-gate portion 150S.

[0122] Common Reference Figure 39A and Figure 39BAn integrated circuit device 2 is formed by forming an interlayer insulating film 174, forming a first contact plug 192 that fills a first contact hole 192H passing through the interlayer insulating film 174 and the gate insulating film 172, and forming a second contact plug 194 that fills a second contact hole 194H passing through the interlayer insulating film 174. A metal silicide film 162 may be disposed between the source / drain region 160 and the first contact plug 192.

[0123] The integrated circuit device 2 includes: a first finned active region FA-N, a second finned active region FA-W, and a third finned active region FA that protrude upward from the main surface 102M (e.g., the top surface) of a substrate 102 in a vertical direction (Z direction) and extend in a first horizontal direction (X direction) in a first peripheral circuit region PRN, a second peripheral circuit region PRW, and a cell region CR, respectively; a nanosheet stacked structure NSS facing the top surface of the third finned active region FA at a location separated from the top surface of the third finned active region FA; a first semiconductor layer 110N disposed on the first finned active region FA-N in the first peripheral circuit region PRN; and a second semiconductor layer 110W disposed on the second finned active region FA-W in the second peripheral circuit region PRW. A trench TRE defining the first finned active region FA-N, the second finned active region FA-W, and the third finned active region FA can be formed in the substrate 102.

[0124] The nanosheet stacked structure NSS is separated from the top surface of the third fin active region FA. The nanosheet stacked structure NSS may include nanosheets N1, N2 and N3 extending on the substrate 102 parallel to the top surface of the third fin active region FA.

[0125] A first lower semiconductor layer 112N and a first upper semiconductor layer 114 constituting the first semiconductor layer 110N are sequentially stacked on the top surface of the first fin-type active region FA-N in the first peripheral circuit region PRN. The top surface of the first fin-type active region FA-N and the bottom surface of the first lower semiconductor layer 112N can be in contact with each other. The top surface of the first lower semiconductor layer 112N and the bottom surface of the first upper semiconductor layer 114 can be in contact with each other and can have a first semiconductor interface 110NIF.

[0126] In some exemplary embodiments, the first semiconductor interface 110NIF of at least one outer first semiconductor layer 110N disposed in the first peripheral circuit region PRN may be along a plane having an inclination relative to the top surface or main surface 102M of the substrate 102, and the first semiconductor interface 110NIF of at least one inner first semiconductor layer 110N may be along a plane parallel to the top surface or main surface 102M of the substrate 102.

[0127] A second lower semiconductor layer 112W and a second upper semiconductor layer 114 constituting the second semiconductor layer 110W are sequentially stacked on the top surface of the second fin-type active region FA-W in the second peripheral circuit region PRW. The top surface of the second fin-type active region FA-W and the bottom surface of the second lower semiconductor layer 112W can be in contact with each other. The top surface of the second lower semiconductor layer 112W and the bottom surface of the second upper semiconductor layer 114 can be in contact with each other and can have a second semiconductor interface 110WIF.

[0128] In some exemplary embodiments, the second semiconductor interface 110WIF of at least one outer second semiconductor layer 110W disposed in the second peripheral circuit region PRW may have multiple surfaces with different inclinations. For example, the second semiconductor interface 110WIF of at least one outer second semiconductor layer 110W disposed in the second peripheral circuit region PRW may simultaneously have a surface inclined relative to the top surface or main surface 102M of the substrate 102 and a surface parallel to the top surface or main surface 102M of the substrate 102. In some exemplary embodiments, the second semiconductor interface 110WIF of at least one inner second semiconductor layer 110W disposed in the second peripheral circuit region PRW may be along a plane parallel to the top surface or main surface 102M of the substrate 102.

[0129] The gate electrode 150 can extend along a second horizontal direction (Y direction) that intersects with the first horizontal direction (X direction) on the first fin active region FA-N, the second fin active region FA-W and the third fin active region FA.

[0130] Source / drain regions 160 are formed on the first fin-type active region FA-N in the first peripheral circuit region PRN, the second fin-type active region FA-W in the second peripheral circuit region PRW, and the third fin-type active region FA in the cell region CR.

[0131] An inter-gate insulating film 172 and an interlayer insulating film 174 are sequentially formed on the source / drain region 160. A first contact plug 192 passing through the interlayer insulating film 174 and the inter-gate insulating film 172 can be connected to the source / drain region 160. A metal silicide film 162 may be located between the source / drain region 160 and the first contact plug 192. A second contact plug 194 passing through the interlayer insulating film 174 can be connected to the gate electrode 150.

[0132] In an integrated circuit device 2 according to one or more exemplary embodiments, the first semiconductor layer 110N and the second semiconductor layer 110W can be formed in a relatively low temperature range, thereby ensuring the reliability of the integrated circuit device 2.

[0133] Figures 40 to 42This is a cross-sectional view of the operations in a method of manufacturing an integrated circuit device according to one or more exemplary embodiments, and the integrated circuit device thus manufactured. Descriptions identical or substantially similar to those given above may be omitted below. Specifically, Figures 40 to 42 It is a cross-sectional view taken along the YZ plane.

[0134] Common Reference Figure 27 and Figure 40 Remove Figure 27 The upper portion of the semiconductor crystal layer 114 shown. During the operation of partially removing the upper portion of the semiconductor crystal layer 114, the upper portion of the covering partition 108S can also be partially removed.

[0135] In some exemplary embodiments, a loading effect may occur when the second width W2 of the stacked recess SR defined by the covering insulating layer 108 in the second horizontal direction (Y direction) is greater than the first width W1 in the first peripheral circuit region PRN. In this case, the upper portion of the semiconductor crystal layer 114 removed in the second peripheral circuit region PRW may be greater than the upper portion of the semiconductor crystal layer 114 removed in the first peripheral circuit region PRN. Consequently, the height of the top surface of the semiconductor crystal layer 114 in the second peripheral circuit region PRW may be lower than the height of the top surface of the semiconductor crystal layer 114 in the first peripheral circuit region PRN.

[0136] Common Reference Figure 40 and Figure 41 After removing the hard mask pattern HM formed on the stacked structure of the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer NS in the cell region CR, a portion of the stacked structure of the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer NS, the first semiconductor layer 110N, the second semiconductor layer 110W, and the substrate 102 is etched to form a trench TRE. Therefore, a plurality of first finned active regions FA-N defined by the trench TRE can be formed in the first peripheral circuit region PRN, a plurality of second finned active regions FA-W defined by the trench TRE can be formed in the second peripheral circuit region PRW, and a plurality of third finned active regions FA defined by the trench TRE can be formed in the cell region CR.

[0137] The first semiconductor layer 110N, as a stacked structure of the first lower semiconductor layer 112N and the first upper semiconductor layer 114, can be disposed on the first fin active region FA-N in the first peripheral circuit region PRN. The second semiconductor layer 110Wa, as a stacked structure of the second lower semiconductor layer 112W and the second upper semiconductor layer 114L, can be disposed on the second fin active region FA-W in the second peripheral circuit region PRW. In the second horizontal direction (Y direction), the third width w3 of the first semiconductor layer 110N can be smaller than the fourth width w4 of the second semiconductor layer 110Wa. The third height LV3 of the top of the first semiconductor layer 110N can be higher than the fourth height LV4 of the top of the second semiconductor layer 110Wa.

[0138] A stacked structure NSS consisting of a sacrificial semiconductor layer 106S and multiple nanosheets N1, N2 and N3 can be set on the third fin-type active region FA in the cell region CR.

[0139] Reference Figure 42 The integrated circuit device 3 includes: a first finned active region FA-N, a second finned active region FA-W, and a third finned active region FA that protrude upward from the main surface 102M (e.g., the top surface) of the substrate 102 in a vertical direction (Z direction) and extend in a first horizontal direction (X direction) in the first peripheral circuit region PRN, the second peripheral circuit region PRW, and the cell region CR, respectively; a nanosheet stacked structure NSS facing the top surface of the third finned active region FA at a location separated from the top surface of the third finned active region FA; a first semiconductor layer 110N disposed on the first finned active region FA-N in the first peripheral circuit region PRN; and a second semiconductor layer 110Wa disposed on the second finned active region FA-W in the second peripheral circuit region PRW. A trench TRE defining the first finned active region FA-N, the second finned active region FA-W, and the third finned active region FA can be formed in the substrate 102.

[0140] The nanosheet stacked structure NSS is separated from the top surface of the third fin active region FA and may include nanosheets N1, N2 and N3 extending on the substrate 102 parallel to the top surface of the third fin active region FA.

[0141] The top heights of the first finned active region FA-N, the second finned active region FA-W, and the third finned active region FA can be substantially the same. The third height LV3 of the top of the first semiconductor layer 110N on the first finned active region FA-N can be higher than the fourth height LV4 of the top of the second semiconductor layer 110Wa on the second finned active region FA-W. In some exemplary embodiments, the top surface of the nanosheet N3, which is furthest from the substrate 102 among nanosheets N1, N2, and N3, can be at the third height LV3.

[0142] In the integrated circuit device 3 according to one or more exemplary embodiments, the first semiconductor layer 110N and the second semiconductor layer 110Wa can be formed in a relatively low temperature range, thereby ensuring the reliability of the integrated circuit device 3.

[0143] Although exemplary embodiments have been specifically shown and described with reference to the accompanying drawings, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the inventive concept, which is defined at least in the appended claims.

Claims

1. An integrated circuit device, comprising: Multiple fin-shaped active regions protrude from the top surface of the substrate and extend along a first horizontal direction; At least one semiconductor layer, each semiconductor layer comprising a lower semiconductor layer and an upper semiconductor layer sequentially stacked on at least one of the plurality of fin active regions; as well as Multiple gate electrodes extend over the multiple finned active regions along a second horizontal direction that intersects the first horizontal direction. The lower semiconductor layer comprises the same material as the upper semiconductor layer. A semiconductor interface is provided between the lower semiconductor layer and the upper semiconductor layer, and The semiconductor interface includes: a first portion extending from a first end of the semiconductor interface toward a second end of the semiconductor interface and parallel to the top surface of the substrate, and a second portion having an inclination relative to the top surface of the substrate at the second end of the semiconductor interface.

2. The integrated circuit device according to claim 1, wherein, The lower semiconductor layer and the upper semiconductor layer have the same degree of crystallinity.

3. The integrated circuit device according to claim 1, further comprising: A nanosheet stacked structure includes a plurality of nanosheets stacked separately above the top surface of a first fin active region in a plurality of fin active regions and extending parallel to the top surface of the first fin active region, each of the plurality of nanosheets including a channel region. A portion of the first gate electrode among the plurality of gate electrodes fills the space between the nanosheets.

4. The integrated circuit device according to claim 3, wherein, The highest vertical height of the semiconductor interface relative to the substrate is higher than the height of the bottom surface of the nanosheet closest to the substrate among the plurality of nanosheets.

5. The integrated circuit device according to claim 4, wherein, The highest height of the semiconductor interface relative to the substrate in the vertical direction is lower than the height of the top surface of the nanosheet closest to the substrate.

6. The integrated circuit device according to claim 1, wherein, The at least one semiconductor layer includes at least three semiconductor layers, respectively disposed on at least three fin active regions arranged at a constant spacing in the second horizontal direction among the plurality of fin active regions; A portion of the semiconductor interface of one of the at least three semiconductor layers, an outer semiconductor layer, has an inclination relative to the top surface of the substrate; as well as The semiconductor interface of at least one inner semiconductor layer of the at least three semiconductor layers runs along a plane parallel to the top surface of the substrate.

7. The integrated circuit device according to claim 6, wherein, The semiconductor interface of one of the at least three semiconductor layers, an outer semiconductor layer, has a portion parallel to the top surface of the substrate and a second portion having an inclination relative to the top surface of the substrate.

8. An integrated circuit device, comprising: Multiple first fin-type active regions extend from the top surface of the substrate along a first horizontal direction in the first peripheral circuit region; Multiple second fin-type active regions extend from the top surface of the substrate along the first horizontal direction in the second peripheral circuit region; The plurality of first semiconductor layers on the plurality of first fin-shaped active regions, each first semiconductor layer comprising: A first lower semiconductor layer and a first upper semiconductor layer are sequentially stacked on corresponding first fin active regions in the plurality of first fin active regions, and The first semiconductor interface between the first lower semiconductor layer and the first upper semiconductor layer; The plurality of second semiconductor layers on the plurality of second fin-shaped active regions, each second semiconductor layer comprising: A second lower semiconductor layer and a second upper semiconductor layer are sequentially stacked on corresponding second fin active regions in the plurality of second fin active regions, and The second semiconductor interface between the second lower semiconductor layer and the second upper semiconductor layer; and Multiple gate electrodes extend on the substrate along a second horizontal direction that intersects the first horizontal direction. Wherein the highest vertical height of the first semiconductor interface relative to the substrate is higher than the highest vertical height of the second semiconductor interface relative to the substrate, and Each of the first semiconductor interface and the second semiconductor interface includes: a first portion extending from a first end of each semiconductor interface toward a second end of each semiconductor interface and parallel to the top surface of the substrate, and a second portion having an inclination relative to the top surface of the substrate at the second end of each semiconductor interface.

9. The integrated circuit device according to claim 8, wherein, In the second horizontal direction, the first width of the first peripheral circuit area is smaller than the second width of the second peripheral circuit area.

10. The integrated circuit device according to claim 8, wherein, In the second horizontal direction, the third width of each of the plurality of first semiconductor layers is smaller than the fourth width of each of the plurality of second semiconductor layers.

11. The integrated circuit device according to claim 8, wherein, The height of the top surface of each of the plurality of first semiconductor layers is greater than the height of the top surface of each of the plurality of second semiconductor layers.

12. The integrated circuit device according to claim 8, wherein, The first semiconductor interface of one of the outer first semiconductor layers of the plurality of first semiconductor layers has an inclination relative to the top surface of the substrate; as well as The first semiconductor interface of at least one inner first semiconductor layer of the plurality of first semiconductor layers runs along a plane parallel to the top surface of the substrate.

13. The integrated circuit device according to claim 8, wherein, The second semiconductor interface of one of the outer second semiconductor layers of the plurality of second semiconductor layers has an inclination relative to the top surface of the substrate; as well as The second semiconductor interface of at least one inner second semiconductor layer of the plurality of second semiconductor layers runs along a plane parallel to the top surface of the substrate.

14. An integrated circuit device, comprising: Multiple fin-shaped active regions protrude from the top surface of the substrate and extend along a first horizontal direction, the substrate including a cell region and a peripheral circuit region; A nanosheet stacked structure includes a plurality of nanosheets stacked separately above the top surface of a first fin active region located in a unit region of a plurality of fin active regions and extending parallel to the top surface of the first fin active region, each of the plurality of nanosheets including a channel region. At least one semiconductor layer, each semiconductor layer comprising: A lower semiconductor layer and an upper semiconductor layer are sequentially stacked on at least one second fin active region located in the peripheral circuit region among the plurality of fin active regions, and The semiconductor interface between the lower semiconductor layer and the upper semiconductor layer; and Multiple gate electrodes extend over the multiple finned active regions along a second horizontal direction that intersects the first horizontal direction. The semiconductor interface includes: a first portion extending from a first end of the semiconductor interface toward a second end of the semiconductor interface and parallel to the top surface of the substrate, and a second portion having an inclination relative to the top surface of the substrate at the second end of the semiconductor interface.

15. The integrated circuit device according to claim 14, wherein, The highest vertical height of the semiconductor interface relative to the substrate is lower than the height of the top surface of the nanosheet closest to the substrate among the plurality of nanosheets.

16. The integrated circuit device according to claim 14, wherein, In the peripheral circuit region, the fin active regions, the lower semiconductor layer, and the upper semiconductor layer among the plurality of fin active regions have the same degree of crystallinity.

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