Magnification device and method

Abstract

Embodiments of the present disclosure relate to amplification apparatuses and methods. The present disclosure provides an amplification apparatus for performing linear amplification and switching amplification operations on an incoming signal, and a method capable of miniaturizing the apparatus. The amplification apparatus includes a first amplification unit for amplifying an input signal and outputting a first output signal, an input switching unit connected in parallel with the first amplification unit for performing a switching operation by the input signal and outputting a switching output signal, and a second amplification unit for amplifying the first output signal or the switching output signal and outputting a second output signal, and the first amplification unit or the input switching unit operates based on a type of the input signal.

Description

[0001] Cross Reference to Related Applications

[0002] Japanese Patent Application No. 2019-099501, filed on May 28, 2019, including the specification, drawings and abstract, the entire contents of which are incorporated herein by reference. Background Technology

[0003] This disclosure relates to an amplifier device and method, and for example, to an amplifier device for performing linear amplification and switching amplification operations on an incoming signal and a method for miniaturizing the device.

[0004] In radio transmission equipment using sub-gigahertz frequencies targeting the power meter and smart grid markets, extending data rates requires addressing modulation systems. These systems include not only constant envelope modulation (FSK), but also amplitude modulation (OFDM / OQPSK). The characteristics required to amplify OFDM signals differ from those required to amplify frequency-modulated signals. Therefore, a separate transmit amplifier corresponding to the OFDM signal is typically needed.

[0005] The publicly available technologies are listed below.

[0006] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2004-140518

[0007] Patent Document 1 discloses an n-square root converter or logarithmic converter circuit disposed between a current detection circuit and a current-to-voltage conversion circuit in an electronic component used for high-frequency power amplification. The current detection circuit and the current-to-voltage conversion circuit constitute a radio communication system. This radio communication system uses a current detection method to detect the output level required for feedback control of the output power, compares the output level detection signal with the output level command signal, generates a bias voltage for the high-frequency power amplification circuit based on the difference, and performs gain control. When the technology disclosed in Patent Document 1 is used to address amplitude modulation and constant envelope modulation methods, filtering for the amplifier, amplitude modulation methods for the amplifier, constant envelope modulation methods for amplitude modulation methods, and filtering for constant envelope modulation methods are required. Therefore, the chip area of ​​the device used in the amplifier increases, making it difficult to miniaturize the amplifier device. Summary of the Invention

[0008] As mentioned above, when the signal corresponds to an OFDM signal, it is difficult to miniaturize the amplifier device because a separate transmitting amplifier corresponding to the OFDM needs to be added.

[0009] Other objects and novel features will become apparent from the following specification and accompanying drawings.

[0010] According to one embodiment, an amplifier apparatus includes a first amplification unit to amplify an input signal and output a first output signal, an input switch unit connected in parallel with the first amplification unit to perform a switching operation by the input signal and output a switching output signal, and a second amplification unit to amplify the first output signal or the switching output signal and output a second output signal. The first amplification unit or the input switch unit operates based on a type of the input signal.

[0011] According to another embodiment, an amplifier apparatus includes a plurality of power amplifier circuits including a first amplification unit, an input switch unit, and a second amplification unit. All outputs of the plurality of power amplifier circuits are connected to an input of a passive circuit. All inputs of the plurality of first amplification units are connected to a first input terminal. Inputs of the plurality of input switch units are connected to a second input terminal provided for each of the plurality of input switch units. When an amplitude modulation signal is input from the first input terminal, the number of operations of the first amplification unit is controlled by a first control signal, and the number of operations of the second amplification unit is controlled by a second control signal. When a constant envelope signal is input from the second input terminal, the input switch unit is operated by the constant envelope signal, and the number of operations of the second amplification unit is controlled by the second control signal. Also, a transmission power at an output terminal of the passive circuit is controlled to be a desired transmission power.

[0012] According to another embodiment, a method includes amplifying an input signal and outputting a first output signal, performing a switching operation by the input signal and outputting a switching output signal, and amplifying the first output signal or the switching output signal based on a type of the input signal to output a second output signal.

[0013] According to the above-described embodiments, an amplifier apparatus for performing a linear amplification operation and a switching amplification operation on an input signal can be provided, and a method by which the apparatus can be miniaturized can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a block diagram illustrating an amplifier apparatus according to a first embodiment.

[0015] Figure 2 is a circuit diagram illustrating an amplifier apparatus according to the first embodiment.

[0016] Figure 3 is a circuit diagram illustrating a passive circuit according to the first embodiment.

[0017] Figure 4 is a circuit diagram illustrating an amplifier apparatus according to the first embodiment.

[0018] Figure 5 is a setting diagram illustrating an amplifier device according to a first embodiment.

[0019] Figure 6 is a block diagram illustrating an amplifier device according to a second embodiment.

[0020] Figure 7 is a circuit diagram illustrating an amplifier device according to the second embodiment.

[0021] Figure 8 is a setting diagram illustrating an amplifier device according to the second embodiment.

[0022] Figure 9 is a graph illustrating a relationship between a voltage of control 2 and a voltage of output Dl of the amplifier device according to the second embodiment.

[0023] Figure 10 is a block diagram illustrating an amplifier device according to a third embodiment.

[0024] Figure 11 is a circuit diagram illustrating an amplifier device according to the third embodiment.

[0025] Figure 12 is a block diagram illustrating an amplifier device according to a fourth embodiment.

[0026] Figure 13 is a circuit diagram illustrating an amplifier device according to the fourth embodiment.

[0027] Figure 14 is a graph illustrating output power of an amplifier device according to the fourth embodiment.

[0028] Figure 15 is a circuit diagram illustrating an amplifier device according to the fourth embodiment.

[0029] Figure 16 is a setting diagram illustrating an amplifier device according to the fourth embodiment.

[0030] Figure 17 is a graph illustrating a relationship between a voltage of control 2 and a voltage of output Dl of the amplifier device according to the fourth embodiment.

[0031] Figure 18 is a circuit diagram illustrating an amplifier device according to the fourth embodiment.

[0032] Figure 19 is a circuit diagram illustrating an amplifier device according to a fifth embodiment.

[0033] Figure 20is a setting diagram illustrating an amplifier apparatus according to a fifth embodiment.

[0034] Figure 21 is a circuit diagram illustrating an amplifier apparatus according to a sixth embodiment.

[0035] Figure 22 is a block diagram illustrating an amplifier apparatus according to a seventh embodiment.

[0036] Figure 23 is a circuit diagram illustrating a passive circuit according to the seventh embodiment.

[0037] Figure 24 is a circuit diagram illustrating a variable capacitor element according to the seventh embodiment.

[0038] Figure 25 is a block diagram illustrating an amplifier apparatus according to an eighth embodiment.

[0039] Figure 26 is a block diagram illustrating an amplifier apparatus according to a ninth embodiment. DETAILED DESCRIPTION

[0040] The following description and accompanying drawings are presented to illustrate the present application and should not be interpreted to limit the scope of the application. It will be readily understood that the functions explained herein are separate functions and can be carried out in various combinations of hardware and software. Moreover, various functions can be implemented using dedicated hardware-based circuitry, using a processor-based system executing appropriate software, or using any combination of hardware and software. The present application can be realized in a centralized fashion in one computer system or network, or in a distributed fashion where different elements are spread across several computer systems or sub-networks. Any kind of computer system or other apparatus adapted for carrying out the functions described herein is suited. A typical combination of hardware and software could be a general purpose computer system with a computer program that, when being loaded and executed, carries out the functions described herein. Alternatively, a custom-made hardware and / or software product, such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), can also be used. The present application can also be embedded in a computer program product, which comprises all the features enabling the implementation of the functions described herein, and which - when being loaded in a computer system - is able to carry out these functions. Computer program or program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: (a) conversion to another language, code or notation; and / or (b) reproduction in a different material form.

[0041] Also, the programs described above can be stored and provided to a computer using various types of non-transitory computer-readable media. The non-transitory computer-readable media include a variety of types of tangible storage media. Examples of the non-transitory computer-readable media include a magnetic recording medium (e.g., a floppy disk, a magnetic tape, and a hard disk drive), a magneto-optical recording medium (e.g., a magneto-optical disk), a CD-ROM (Read Only Memory), a CD-R, a CD-R / W, and a solid-state memory (e.g., a mask ROM, a PROM (Programmable ROM), an EPROM (Erasable PROM), a flash ROM, and a RAM (Random Access Memory)). The programs can also be provided to a computer by various types of transitory computer-readable media. Examples of the transitory computer-readable media include an electrical signal, an optical signal, and an electromagnetic wave. The transitory computer-readable media can provide the programs to a computer via a wired or wireless communication path, such as an electrical wire and an optical fiber.

[0042] (First Embodiment)

[0043] The first embodiment according to an amplifier device is outlined. Figure 1 is a block diagram illustrating an amplifier device according to the first embodiment.

[0044] As Figure 1 shown, the amplifier device 11 according to the first embodiment includes a power amplification unit 11a and a passive circuit 115. The power amplification unit 11a includes an input amplification unit 111, an input switching unit 112, and a grounded gate amplification unit 113.

[0045] The input amplification unit can be referred to as a first amplification unit. The grounded gate amplification unit can be referred to as a second amplification unit. The passive circuit can also be referred to as a matching circuit. The power amplification unit can be referred to as a power amplifier unit.

[0046] The input amplification unit 111 amplifies an input signal input via an input 1 terminal and outputs a first output signal.

[0047] The input switching unit 112 is connected in parallel with the input amplification unit 111, performs a switching operation by an input signal input via an input 2 terminal, and outputs a switching output signal. For example, the switching operation refers to controlling the opening and closing of a switch.

[0048] The first output signal, which is the output of the input amplification unit 111, is connected with the switching output signal, which is the output of the input switching unit 112, and is input to the grounded gate amplification unit 113. The connection point at which the first output signal and the switching output signal are connected is referred to as an output D1.

[0049] The grounded gate amplification unit 113 amplifies the first output signal or the switching output signal and outputs a second output signal.

[0050] The second output signal is input to the passive circuit 115. The passive circuit 115 is a passive circuit for matching the second output signal.

[0051] The input amplification unit 111 or the input switching unit 112 operates based on the type of input signal. The amplifier device 11 controls the following two states based on the input signal input to the input 1 terminal, the input signal input to the input 2 terminal, and the control signal input to the control 1 terminal, in which the input amplification unit 111 is operated to stop the input switching unit 112, and the input switching unit 112 is operated to stop the input amplification unit 111.

[0052] Specifically, when the type of the input signal is the amplitude modulation signal, the input amplification unit 111 operates, and the input switching unit 112 stops operating. Accordingly, when the input signal is the amplitude modulation signal, the amplifier device 11 outputs the first output signal from the input amplification unit 111 and does not output the switching output signal from the input switching unit 112. That is, when the input amplification unit 111 operates, the input switching unit 112 stops its operation.

[0053] When the type of the input signal is the constant envelope signal, the input switching unit 112 operates, and the first amplification unit 111 stops operating. Therefore, when the input signal is the constant envelope signal, the amplifier device 11 does not output the first output signal from the input amplification unit 111, but outputs the switching output signal from the input switching unit 112. That is, when the input switching unit 112 operates, the input amplification unit 111 stops operating.

[0054] By such exclusive operations, it is possible to provide the power amplification unit 11a with a linear amplification operation for amplifying the input signal to be input to the input 1 terminal as Class A or AB, and a switching amplification operation for amplifying the input signal to be input to the input 2 terminal as Class E.

[0055] Due to the amplifier device 11 according to the first embodiment, it is possible to share the passive circuit 115 according to the linear amplification operation and the switching amplification operation, and to miniaturize the amplifier device 11. In other words, according to the first embodiment, it is possible to provide an amplifier device for performing a linear amplification operation and a switching amplification operation on an input signal, and a method of miniaturizing the device.

[0056] Due to the first embodiment of the amplifier device 11 sharing the passive circuit 115, it is possible to reduce the chip area of components, consume less current, and reduce costs.

[0057] According to the first embodiment of the amplifier device 11, by separating the input amplification unit 111 and the input switching unit 112, it is possible to suppress the deterioration of the characteristics of each of the linear amplification operation and the switching amplification operation. Therefore, it is possible to prevent the deterioration of the power efficiency of the amplification section and the aging due to the withstand voltage of the device.

[0058] A detailed description is given of the first embodiment according to the amplifier device. Figure 2 is a circuit diagram illustrating the amplifier device according to the first embodiment. Figure 3 is a circuit diagram illustrating the first embodiment according to the passive circuit. Figure 4 is a circuit diagram illustrating the amplifier device according to the first embodiment.

[0059] As Figure 2As shown, the input amplifying unit 111 according to the first embodiment of the power amplifying unit 11a includes a transistor Ml, a capacitor element Cdc, and a resistance element Rdc. The input switching unit 112 includes a transistor M2. The ground gate amplifying unit 113 includes a transistor M3.

[0060] The source S of the transistor Ml of the input amplifying unit 111 is grounded, an input signal input from the input 1 is connected to the gate G of the transistor Ml via the capacitor element Cdc, and a control signal input from the control 1 is connected to the gate G of the transistor Ml via the resistance element Rdc.

[0061] An input signal input from the input 2 terminal is connected to the gate G of the transistor M2. The source S of the transistor Ml and the source S of the transistor M2 are connected to the ground.

[0062] The drain D of the transistor Ml and the drain D of the transistor M2 are connected to the source S of the transistor M3. The transistor M3 outputs a second output signal from the drain D, and the second output signal is input to the passive circuit 115.

[0063] When the input signal is an amplitude modulation signal, a first predetermined voltage Vgl is applied to the gate G of the transistor Ml, the input amplifying unit 111 operates, and a low-level voltage is applied to the gate G of the transistor M2, and the input switching unit 112 stops operating. Therefore, the first output signal is output from the input amplifying unit 111, and no switching output signal is output from the input switching unit 112.

[0064] When the input signal is a constant envelope signal, a low-level voltage is applied to the gate G of the transistor Ml, the input amplifying unit 111 stops operating, and the input switching unit 112 operates. Therefore, the switching output signal is output from the input switching unit 112, and no first output signal is output from the input amplifying unit 111.

[0065] The transistor Ml can be referred to as a first transistor, the transistor M2 can be referred to as a second transistor, and the transistor M3 can be referred to as a third transistor.

[0066] In Figure 2 , the parasitic capacitance of the transistor Ml is shown as a parasitic capacitance Cp l. The parasitic capacitance of the transistor M2 is shown as a parasitic capacitance Cp2.

[0067] The passive circuit 115 includes the inductor element LI, the capacitor element CI, the capacitor element C2, the capacitor element C3, and the inductor element L2 that function as a power source and a load. The passive circuit 115 is a matching circuit that performs matching and waveform shaping. The configuration of the circuit responsible for waveform shaping can be freely changed depending on the specifications required by the system (e.g., a prescribed value of unnecessary radiation). The power sources of the power amplification unit 11a and the passive circuit 115 are connected to the power supply terminals of the amplifier device 11 and are supplied with power.

[0068] Figure 3 is a circuit diagram illustrating a minimum configuration of the passive circuit. The capacitor element CI can be replaced by the parasitic capacitances Cp1 and Cp2 shown in Figure 2 . Thus, as shown in Figure 3 , the capacitor element CI of the passive circuit 115 can be omitted.

[0069] The power amplification unit 11a can be replaced by a circuit shown in Figure 4 , which is different from the circuit shown in Figure 2 . That is, the input amplification unit 111 includes the transistor Ml, the input switching unit 112 includes the transistor M2, and the ground gate amplification unit 113 includes the linear amplification transistor M3a and the switching amplification transistor M3b.

[0070] The input signal input from the input 1 terminal is connected to the gate G of the transistor Ml. The input signal input from the input 2 terminal is connected to the gate G of the transistor M2. The source S of the transistor Ml and the source S of the transistor M2 are connected to the ground.

[0071] The drain D of the transistor Ml is connected to the source S of the linear amplification transistor M3a. The drain D of the transistor M2 is connected to the source S of the switching amplification transistor M3b.

[0072] The drain D of the linear amplification transistor M3a is connected to the drain D of the switching amplification transistor M3b. The second output signal is output from the drain D of the linear amplification transistor M3a.

[0073] The operation of the amplifier device 11 according to the first embodiment will now be described. Here, the operation of the circuit shown in Figure 2 will be described. Figure 5 is a setup diagram illustrating the amplifier device according to the first embodiment.

[0074] Figure 2 The power amplification unit 11a shown in performs an amplification operation by two different operations, i.e., a “linear amplification operation” performed by the input amplification unit 111 and the ground gate amplification unit 113, and a “switching amplification operation” performed by the input switching unit 112 and the ground gate amplification unit 113.

[0075] For example, the "linear amplification operation" refers to an operation of linearly amplifying an input signal, such as class A amplification and class AB amplification. The "switching amplification operation" refers to an operation of effectively taking out an amplified signal using a transient phenomenon of a switch controlled by an input signal, such as class E amplification.

[0076] The amplifier device 11 performs the "linear amplification operation" and the "switching amplification operation" by the settings shown in FIG. 1. Figure 5 The amplifier device 11 performs the "linear amplification operation" and the "switching amplification operation" by the settings shown in FIG. 1. Figure 2 The amplifier device 11 performs the "linear amplification operation" and the "switching amplification operation" by the settings shown in FIG. 1.

[0077] When performing linear amplification, the amplifier device 11 inputs a modulated signal, that is, an amplitude modulated signal at input 1 using amplitude modulation. The amplifier device 1 applies a low-level voltage to input 2 to shut off the operation of the input switching unit 112. At this time, since the drain D of the transistor M2 is in a high impedance state, the operation of the transistor M1 is not affected. The low-level voltage is sometimes referred to as a low-level voltage or a low fixed voltage.

[0078] The amplifier device 11 applies a first predetermined voltage Vgl required for the transistor M1 to perform a class A amplification operation or a class AB amplification operation to control 1.

[0079] The amplifier device 11 performs the "linear amplification operation" by the settings shown in FIG. 1 to amplify an input signal input from the input 1 terminal by the linear amplification operation, and outputs an amplified signal for input 1. Figure 5 The amplifier device 11 performs the "linear amplification operation" by the settings shown in FIG. 1 to amplify an input signal input from the input 1 terminal by the linear amplification operation, and outputs an amplified signal for input 1.

[0080] The amplifier device 11 inputs a constant envelope signal to input 2 when performing switching amplification. The amplifier device 11 does not input a signal, that is, no signal to input 1, and applies a low-level voltage to control 1 to shut off the operation of the input amplification unit 111. At this time, since the drain D of the transistor M1 is in a high impedance state, the operation of the transistor M2 is not affected.

[0081] The amplifier device 11 amplifies an input signal input from the input 2 terminal by the switching amplification operation, and outputs an amplified signal to input 2 by the settings shown in FIG. 1. Figure 5 The amplifier device 11 amplifies an input signal input from the input 2 terminal by the switching amplification operation, and outputs an amplified signal to input 2 by the settings shown in FIG. 1.

[0082] The amplifier device 11 according to the first embodiment is divided into the input amplification unit 111 and the input switching unit 112, and each unit performs an amplification operation.

[0083] Therefore, when the power amplification unit 11a performs linear amplification, the potential of the output Dl is determined by the voltage of the gate G of the ground gate amplification unit 113, and the operation is referenced to a certain potential. Therefore, the operation of the power amplification unit 11a becomes a stable operation, and is less likely to be affected by the parasitic capacitance, which can reduce the characteristic deterioration.

[0084] In addition, since the input amplification unit 111 and the input switching unit 112 can be designed separately, the balance between the transmission characteristics and the power efficiency can be optimized.

[0085] In addition, since the passive circuit 115 serving as a load is shared, this can reduce the chip area of components. Therefore, the amplifier device 11 can be miniaturized.

[0086] (Second Embodiment)

[0087] Figure 6 is a schematic diagram illustrating an amplifier device according to the second embodiment. Figure 7 is a circuit diagram illustrating an amplifier device according to the second embodiment. Figure 8 is a diagram illustrating the setting according to the second embodiment of the power amplification unit; Figure 9 is a schematic diagram illustrating the relationship between the voltage of the control 2 and the voltage of the output Dl of the amplifier device according to the second embodiment.

[0088] As Figure 6 shown, the amplifier device 21 according to the second embodiment differs from the amplifier device 11 according to the first embodiment in that another control signal is applied to the ground gate amplification unit 113 via the control 2.

[0089] More specifically, as Figure 7 shown, another control signal is applied to the gate G of the transistor M3 of the ground gate amplification unit 113 via the control 2, thereby preventing the device from being damaged by the peak voltage signal generated during the switching amplification operation. That is, by providing the gate G of the transistor M3 with a voltage value different from the voltage when linear amplification operation is performed, the peak voltage value at the output Dl can be suppressed to be equal to or less than the breakdown voltage threshold of the element, and the elements of the input amplification unit 111 and the elements of the input switching unit 112 are prevented from being damaged.

[0090] The operations other than the operation related to the control 2 of the amplifier device 21 according to the second embodiment are the same as the operations of the amplifier device 11 according to the first embodiment, and therefore, the description thereof is omitted.

[0091] As Figure 8As shown, when the amplifier device 21 performs switching amplification, a third predetermined voltage Vg3, which is required as an analog voltage for the gate-ground amplification operation of the transistor M3, is applied to the control 2 as another control signal. At this time, as long as the peak voltage does not exceed the element breakdown voltage threshold of the transistors Ml and M2, the third predetermined voltage Vg3 is set (selected) at the output Dl connected to the drain D of the transistor Ml and connected to the drain D of the transistor M2. The third predetermined voltage Vg3 is applied to the gate G of the ground-gate amplification unit 113 via the control 2.

[0092] Accordingly, during the linear amplification operation and the switching amplification operation, it is possible to prevent the peak voltage at the drain D of the transistor Ml of the input amplification unit 111 and at the drain D of the transistor M2 of the input switching unit 112 (the voltage at the output Dl) from exceeding the element breakdown voltage threshold.

[0093] Here, the voltage at the output Dl is referred to as a voltage VD, an AC component occurring at the voltage VD is referred to as a voltage Vac, and the voltage of the second output signal, which is the output signal of the power amplification unit 11a, is referred to as a voltage Vpa. The peak voltage Vpeak of the voltage VD at this time can be expressed as Vpeak = Vac + Vg3 - Vth3. Note that Vth3 represents the threshold voltage of the transistor M3.

[0094] The amplifier device 21 can control the peak voltage Vpeak so as not to exceed the element breakdown voltage threshold of the transistors Ml and M2 by reducing the third predetermined voltage Vg3.

[0095] On the other hand, the breakdown voltage of the transistor M3 needs to be taken into consideration. The voltage between the drain D and the source S of the transistor M3 is at most Vpa - Vpeak. As shown, since the peak voltage of the transistor Ml and the transistor M2 are inversely proportional, the transistors Ml, M2, and M3 are optimally controlled so as not to exceed the element breakdown voltage threshold. Figure 9

[0096] When the amplifier device 21 performs the linear amplification operation, the voltage of the second predetermined voltage Vg2 is selected in the same manner as in the switching amplification operation. Since the AC component of the voltage occurring at the output Dl during the linear amplification operation is generally smaller than the AC component of the voltage Vac during the switching operation, the second predetermined voltage Vg2 can be increased.

[0097] Since the gain of the power amplification unit 21a during the linear amplification operation can be increased by increasing the second predetermined voltage Vg2, the second predetermined voltage Vg2 is generally larger than the third predetermined voltage Vg3. Therefore, the value of the control 2 is different between the linear amplifier and the switching amplifier, and the power supply voltage value is equal to or greater than Vg2, and Vg2 is equal to or greater than Vg3.​

[0098] The operation of the amplifier device 21 according to the second embodiment is summarized as follows. In the amplifier device 21, when the input signal is an amplitude modulation signal, the first predetermined voltage Vgl is applied to the gate G of the transistor Ml to operate the input amplifying unit 111, and the second predetermined voltage Vg2 is applied to the gate G of the transistor M3 to operate the ground gate amplifying unit 113. In the amplifier device 21, the low-level voltage is applied to the gate G of the transistor M2, and the input switching unit 112 stops its operation.

[0099] When the input signal is a constant envelope signal, the low-level voltage is applied to the gate G of the transistor Ml, and the input amplifying unit 111 stops the operation of the amplifier device 21. In the amplifier device 21, the third predetermined voltage Vg3 lower than the second predetermined voltage Vg2 is applied to the gate G of the transistor M3 to operate the input switching unit 112 and the ground gate amplifying unit 113.

[0100] For the purpose of improving the power efficiency of the power amplifying unit 21a, a transistor (so-called thin film transistor) having a high transconductance gm and a small parasitic capacitance can be used as the transistor Ml and the transistor M2.

[0101] (Third Embodiment)

[0102] Figure 10 is a block diagram illustrating an amplifier device according to the third embodiment. Figure 11 is a circuit diagram illustrating an amplifier device according to the third embodiment.

[0103] As shown in Figure 10 and 11 , the amplifier device 31 according to the third embodiment differs from the amplifier device 11 according to the first embodiment in that it corresponds to a differential signal. In the amplifier device 31, the input signal, the first output signal, the switching output signal, and the second output signal are differential signals.

[0104] As shown in Figure 10 , the power amplifying unit 31a corresponds to a differential signal by configuring components in a differential pair.

[0105] The input amplifying unit 311 includes the transistor MlN and the transistor MlP corresponding to a differential input signal. The input switching unit 312 includes the transistor M2N and the transistor M2P corresponding to a differential input signal.

[0106] The ground gate amplifying unit 313 includes the transistor M3N and the transistor M3P for amplifying a differential signal. The differential output of the power amplifying unit 31a is the drain D of the transistor M3N and the drain D of the transistor M3P, and is connected to the input of the passive circuit 315.

[0107] The passive circuit 315 includes a balance converter BR for converting a differential signal into a single signal, a capacitor element Cl, a capacitor element C2, and an inductor element LI. Here, N is a natural number. A middle point of a primary side of the balance converter BR is connected to a power supply for supplying power to the power amplification unit 31a.

[0108] The amplifier device 31 according to the third embodiment can eliminate an even harmonic signal by employing a differential configuration. Also, the amplifier device 31 can output higher power than a single output.

[0109] (Fourth Embodiment)

[0110] Figure 12 is a block diagram illustrating an amplifier device according to the fourth embodiment. Figure 13 is a circuit diagram illustrating an amplifier device according to the fourth embodiment. Figure 14 is a graph illustrating power of an amplifier device according to the fourth embodiment. In Figure 14 , the horizontal axis represents the number of power amplification units in an operating state, and the vertical axis represents output power.

[0111] As Figure 12 indicated, the amplifier device 41 according to the fourth embodiment differs from the amplifier device 11 according to the first embodiment in that the gain of the power amplification unit 41a is adjusted to control the transmission power from the power amplification unit 41a.

[0112] The amplifier device 41 includes a plurality of power amplification units 11a each having an input amplification unit 111, an input switching unit 112, and a grounded gate amplification unit 113. The plurality of power amplification units 11a are collectively referred to as a power amplification unit 41a. All outputs of the plurality of power amplification units, that is, the output of the power amplification unit 41a, are connected to an input of a passive circuit 115. All inputs of the plurality of input amplification units 111, that is, the input of the power amplification unit 41a, are connected to a first input terminal. The inputs of the plurality of input switching units 112 are connected to a second input terminal provided for each of the plurality of input switching units 112. The input 1 terminal can be referred to as the first input terminal. The input 2 terminal can be referred to as the second input terminal. The power amplification unit is sometimes referred to as a power amplification circuit.

[0113] In a case where an amplitude modulation signal is input to the input 1 terminal of the amplifier device 41, the number of operations of the input amplification unit 111 is controlled by a first control signal input from the control 1 terminal, and the number of operations of the grounded gate amplification unit 113 is controlled by a second control signal input from the control 2 terminal.

[0114] In a case where the constant envelope signal is input to the input 2 terminal of the amplifier device 41, the input switch unit 112 is operated by the constant envelope signal, and the number of operations of the ground gate amplification unit 113 is controlled by the second control signal input from the control 2 terminal. The number of switches to be opened and closed changes depending on the constant envelope signal.

[0115] The amplifier device 41 controls so that the transmission power at the output terminal of the passive circuit 115 is the desired transmission power.

[0116] An amplifier device 41 according to a fourth embodiment is outlined. A plurality of power amplification units 11a are connected in parallel, and all outputs and all inputs 1 of all power amplification units 11a are shared. The input 2, the control 1, and the control 2 of each of the plurality of power amplification units 11a are independent. The transistor size of each of the plurality of power amplification units 11a can have a single size or can be weighted. In Figure 12 In the figure, a plurality of inputs 2 are shown as input 2 terminal 1, input 2 terminal 2, and input 2 terminal n. Here, n is an integer. A plurality of controls 1 and controls 2 are also shown.

[0117] Here, for ease of description, one of the plurality of power amplification units 11a is described and the other of the power amplification units 11a is described as a power amplification unit 11b. The amplifier device 41 includes the power amplification unit 11a and the other power amplification unit 11b. The power amplification unit 11a includes an input amplification unit 111a, an input switch unit 112a, and a ground gate amplification unit 113a.

[0118] The input amplification unit 111a amplifies the input signal and outputs a first output signal.

[0119] The input switch unit 112a is connected in parallel to the input amplification unit 111a, performs a switching operation according to the input signal, and outputs a switch output signal.

[0120] The ground gate amplification unit 113a amplifies the first output signal and outputs a second output signal when the input amplification unit 111a operates based on the type of the input signal. The ground gate amplification unit 113a amplifies the switch output signal and outputs the second output signal when the input switch unit 112a operates based on the type of the input signal.

[0121] On the other hand, the other power amplification unit 11b has another input amplification unit 111b, another input switch unit 112b, and another ground gate amplification unit 113b.

[0122] The other input amplification unit 111b amplifies the input signal and outputs another first output signal.

[0123] Another input switch unit 112b is connected in parallel with another input amplification unit 111b, performs a switching operation according to an input signal, and outputs another switch output signal.

[0124] When another first amplification unit 111b operates based on the type of the input signal, another ground gate amplification unit 113b amplifies another first output signal, and outputs another second output signal. When another input switch unit 112b operates based on the type of the input signal, another ground gate amplification unit 113b amplifies another switch output signal, and outputs another second output signal.

[0125] An amplifier device 41 combines the second output signal and another second output signal, and outputs the combined signal. It should be noted that there can be a plurality of different power amplification units 11b.

[0126] The operation of the amplifier device 41 according to the fourth embodiment will now be described. In the following description, for simplicity, the transistor sizes are exemplified by connecting a plurality of transistors of a single size in parallel. Further, among the plurality of power amplification units 11a having the power amplification unit 41a, the power amplification unit 11a that becomes an operating state in the amplification operation is referred to as an on unit, and the power amplification unit 11a that becomes a stop state other than the operating state is referred to as an off unit.

[0127] As Figure 13 illustrated, the power amplification unit 41a changes the number of power amplification units 11a to be turned on and enter the operating state, i.e., the number of on units, by changing the control signal input from the control 1 and the input signal input from the input 2 at the logic level. Therefore, as Figure 14 illustrated, the transmission power is controlled in each of the linear amplification operation and the switch amplifier operation.

[0128] In addition, the voltage of the control 2 of the power amplification unit 11a that does not contribute to amplification is given as a constant value, thereby protecting the transistors of the power amplification unit 11a that does not contribute to amplification.

[0129] Figure 15 is a circuit diagram illustrating an amplifier device according to the fourth embodiment. Figure 15 illustrates a plurality of power amplification units 11a divided into on units and off units. Figure 16 is a setting diagram illustrating an amplifier device according to the fourth embodiment.

[0130] In Figure 15In the on unit, the voltage at the output Don is a voltage VDon, and in the off unit, the voltage at the output Doff is a voltage VDoff. The voltage at the output Dt of the power amplification unit 41a is referred to as a voltage Vpa. The on unit and the off unit functions are the same, and the transistors used have the same specifications. In each unit, the input 2, the control 1, and the control 2 of the power amplification unit 11a are independent of each other.

[0131] As shown in FIG. 6, in the amplifier device 41, when performing the linear amplification operation, the amplitude modulation signal is input to all of the inputs 1, the low-level voltage is fixedly applied to all of the inputs 2, and the low-level voltage is applied to the control 1 of the off unit (step S101). Figure 16

[0132] In the amplifier device 41, the first predetermined voltage Vgl, which is a bias voltage required for the transistor Mlon to perform the linear operation, is applied to the control 1 of the on unit, and the second predetermined voltage Vg2, which is a bias voltage required for the transistor M3on to perform the amplification operation, is applied to the control 2 of the on unit (step S102). At this time, as the second predetermined voltage Vg2 to be applied to the control 2 of the on unit, a voltage is selected in which the voltage Vdon does not exceed the transistor Mlon, and the voltage between the terminals of the transistor M2on does not exceed the element breakdown voltage threshold voltage.

[0133] In step S103, the bias voltage Vg2 off, which is a voltage for protecting the elements of the transistor Mloff and the transistor M2off, is applied to the off unit to limit the voltage VDoff.

[0134] In step S101, step S102, and step S103, the linear amplification operation is performed in the case of the plurality of on units connected in parallel, and a signal is obtained by amplifying the amplitude modulation signal output from the power amplification unit 41a (i.e., the amplified signal of the input 1).

[0135] The amplifier device 41, when performing the switching amplification operation, inputs the constant envelope signal to the input 2 of the on unit, fixes the low-level voltage to the input 2 of the off unit, and does not input a signal to the input 1 of the on unit and the input 1 of the off unit (step S201). Further, the low-level voltage is applied to the control 1 of the on unit and the control 1 of the off unit (step S201).

[0136] ​In step S202, the third predetermined voltage Vg3 required for the switching amplification operation of the transistor M3on is applied to the control 2 of the on unit. At this time, as the third predetermined voltage Vg3 to be applied to the control 2 of the on unit, a voltage is selected in which the voltage Vdon does not exceed the transistor Mlon, and the voltage between the terminals of the transistor M2on does not exceed the device breakdown voltage.

[0137] In addition, the bias voltage Vg3_off for protecting the elements of the transistor Mloff and the transistor M2off is applied to the control 2 of the off unit to limit the voltage VDoff.

[0138] In steps S201, S202, and S203, the switching amplification operation is performed when the plurality of on units are connected in parallel. And the signal amplified by the constant envelope signal from the power amplification unit 41a is output (the amplified signal to the input 2).

[0139] In the linear amplification operation of the amplifier device 41, the current flowing through one input amplification unit does not change. In the amplifier device 41, the plurality of input amplification units perform the same operation so that the input amplification units themselves operate in parallel. In the amplifier device 41, the current flowing through the transistor is increased by the number of parallel connections, and the amplification factor of the input amplification unit is increased by the number of parallel connections. Increasing the number of on units operating in parallel increases the transmission power, and decreasing the number of on units operating in parallel decreases the transmission power. Therefore, the amplifier device 41 can control the transmission power.

[0140] In the switching amplification of the amplifier device 41, the input switching unit of the power amplification unit operates as a plurality of switches. At this time, since the switching of the power amplification unit appears as a parallel connection of resistors, the on resistance changes. Therefore, the loss of the on resistance changes, and the transmission power is controlled.

[0141] In the amplifier device 41, the transmission power can be adjusted by changing the power supply voltage. In addition, the transmission power can be controlled by combining the method from steps S201 to S203 with the method of changing the power supply voltage.

[0142] The effects according to the fourth embodiment of the amplifier device 41 will be described. The amplifier device 41 can control the transmission power (output power) in a wider range by controlling (adjusting) the number of on units.

[0143] By performing steps S103 and S203, the amplifier device 41 can limit the drain voltage of the transistors Mloff and M2off during the linear amplification operation and the switching operation so that the drain voltage of the transistor does not exceed the element breakdown voltage threshold (breakdown voltage limit).

[0144] When the transmission power is controlled by a single power amplification unit, there are limitations in adjusting the gate bias and the load. Therefore, in the amplifier device 41 according to the fourth embodiment, by connecting a plurality of power amplification units in parallel, even if the gate bias is small and the load is constant, the transmission power can be controlled in a wide range.

[0145] Now, adjustment will be described so as not to exceed the element breakdown voltage threshold. Figure 17 is a graph illustrating the relationship between the voltage of the control 2 and the voltage at the output Dl of the amplifier device according to the fourth embodiment. Figure 17 The horizontal axis of indicates the voltage of the control 2, and the vertical axis VD indicates the voltage at the output Dl, the output Don, or the output Doff. Vpa on the vertical axis represents the voltage at the output Dt.

[0146] In the first embodiment according to the amplifier device 11, since it is a single power amplification unit, there is no off unit, and only the on units in their respective operation modes (linear amplification operation or switching amplifier operation) are considered.

[0147] On the other hand, in the amplifier device 41 according to the fourth embodiment, there are on units and off units. Unlike the on units, the off units do not operate, and thus no current flows. In the fourth embodiment, the amplifier device 41 causes the on units and the off units to share the same output terminal. Therefore, in the amplifier device 41, when a large signal is output, the voltage Vpa of the large signal is applied to the output Doff by the parasitic capacitance of the ground gate amplification unit of the off unit.

[0148] Since the control 2 is independent for each power amplification unit, the control 2 can individually apply the constant bias voltage Vg2 off, the bias voltage Vg3 off to the gate of the transistor M3 off, and apply the bias to the output Doff. That is, the voltage of the output Doff can be limited, and can be adjusted so as not to exceed the element breakdown voltage threshold of the off unit transistor.

[0149] Similar to the second embodiment, the voltage of the control 2 used for the linear amplification operation and the switching amplifier operation is different. Therefore, the voltage value of the control 2 of the off unit is also different. The voltage of the control 2 is as shown in Figure 17 considering the breakdown voltage of the ground gate amplification unit.

[0150] The amplifier device 41 according to the fourth embodiment can correspond to a differential signal. Figure 18 is a circuit diagram illustrating the amplifier device according to the fourth embodiment. Figure 18 The circuit diagram in the case of a differential configuration is shown.

[0151] As shown in FIG. 38, Figure 18 The power amplification unit 41a in the differential configuration case connects a plurality of power amplification units 31a in parallel. The power amplification unit 31a includes an input amplification unit, an input switching unit, and a grounded gate amplification unit. The input amplification unit includes a transistor M1N and a transistor M1P. The input switching unit includes a transistor M2N and a transistor M2P. The grounded gate amplification unit includes a transistor M3N and a transistor M3P.

[0152] The differential outputs of the power amplification unit 41a, in which a plurality of power amplification units 31a are connected in parallel, are all shared. The differential outputs of the power amplification unit 41a are connected to a passive circuit 415. The passive circuit 415 includes a balun BR having a conversion ratio of N to 1, an inductive element LI, a capacitor element CI, and a capacitor element C2, and is a circuit for performing matching and waveform shaping.

[0153] (Fifth Embodiment)

[0154] Figure 19 is a circuit diagram illustrating an amplifier device according to the fifth embodiment. Figure 19 The dashed line in FIG. 39 shows the power amplification unit 41a and the passive circuit 115.

[0155] The amplifier device 51 according to the fifth embodiment includes a decoder and a driver. The amplifier device 51 illustrates an exemplary configuration for controlling the inputs 2 of a plurality of power amplification units 11a. A constant envelope RF signal (constant envelope signal) is input from IN2, and IN1 is constantly without a signal (GND) at all times. Control 1 and control 2 perform control operations according to the switching amplification operation in the fourth embodiment shown in FIG. 36. Figure 16

[0156] The decoder is a decoder for converting a control bit into a control signal EN. For example, the control bit is a value input by a user. The control signal EN is a logic signal, and has a low state or a high state.

[0157] The driver has an AND circuit. The outputs of the decoder, from the control signal EN1 to the control signal ENn, are connected to one of the inputs of the AND circuit. IN2 is connected to the other of the inputs of the AND circuit. Each of the outputs of IN2 ANDed with each of the control signals EN is connected to the input 2 of each of the power amplification units.

[0158] The decoder and the driver according to the fifth embodiment can be part of the control unit described later.

[0159] Figure 20 is a setting diagram illustrating an amplifier device according to the fifth embodiment. Figure 20 The operation states of the inputs 2 with respect to the control signals EN are shown.​

[0160] As shown in FIG. 4, when the control signal EN is high, the RF signal is output from the driver and input to input 2. When the control signal EN is low, the driver shuts off the RF signal, and input 2 is always low regardless of IN2. That is, by changing the control signals EN1 to ENn to the outputs of the decoder, input 2 can be controlled individually. Figure 20

[0161] According to the fifth embodiment, input 2 can be controlled, and the number of power amplification units can be changed when performing switch amplification.

[0162] (Sixth Embodiment)

[0163] Figure 21 is a circuit diagram illustrating an amplifier device according to the sixth embodiment. The amplifier device 61 according to the sixth embodiment includes a decoder, a voltage generator, and a selector. Control 1 and control 2 perform control operations according to the switch amplifier operation in the fourth embodiment shown in Figure 16

[0164] The voltage generator generates all of the first predetermined voltage Vgl, the second predetermined voltage Vg2, the third predetermined voltage Vg3, the bias voltage Vg2 off, and the bias voltage Vg3 off required for the linear amplification operation and the switch amplifier operation. The decoder converts the control bits from the user.

[0165] The selector has a four-pole switch and a two-pole switch. The output of the four-pole switch is selected from among the second predetermined voltage Vg2, the third predetermined voltage Vg3, the bias voltage Vg2 off, and the bias voltage Vg3 off by the decoder, and the output is input to control 2. The output of the two-pole switch is selected from the first predetermined voltage Vgl or ground, and is input to control 1.

[0166] Incidentally, the decoder, the selector, and the voltage generation unit according to the sixth embodiment can be part of the control unit described later.

[0167] According to the sixth embodiment, as shown in FIG. 6, voltages are applied to control 1 and control 2. Figure 16

[0168] (Seventh Embodiment)

[0169] Figure 22 is a block diagram illustrating an amplifier device according to the seventh embodiment. Figure 23 is a circuit diagram illustrating a passive circuit according to the seventh embodiment. Figure 24 is a schematic diagram illustrating a variable capacitor element according to the seventh embodiment.

[0170] As shown in FIG. 7, when the control signal EN is high, the RF signal is output from the driver and input to input 2. When the control signal EN is low, the driver shuts off the RF signal, and input 2 is always low regardless of IN2. That is, by changing the control signals EN1 to ENn to the outputs of the decoder, input 2 can be controlled individually. Figure 22 ​​​As shown, the amplifier device 71 according to the seventh embodiment differs from the amplifier device 11 according to the first embodiment in that control 3 is added to the passive circuit 715.

[0171] By adding control 3 to the passive circuit 715, as seen in the power amplifier circuit 11a, the impedance of the passive circuit 715 can be changed. Therefore, the impedance can be optimally controlled in both linear amplification and switching amplifier operations to maximize power efficiency.

[0172] Specifically, such as Figure 23 As shown, the capacitance value of the variable capacitor element VC1 is changed by a control signal from control 3. The variable capacitor element VC1 can, for example, be... Figure 24 The circuit shown is implemented.

[0173] In amplifier device 71, in each of the linear amplification and switching amplification operations, the variable capacitor element VC1 is changed to control the impedance of the passive circuit 715, as seen from the power amplification unit 11a, to an impedance that maximizes power efficiency. Therefore, current consumption can be reduced.

[0174] (Eighth Embodiment)

[0175] Figure 25 This is a block diagram illustrating an amplifier device according to the eighth embodiment.

[0176] like Figure 25 As shown, compared to the amplifier device 11 according to the first embodiment, the amplifier device 81 according to the eighth embodiment further includes: a control unit 12, a power supply unit 13, a signal processing unit 14, an oscillation unit 16, and a mixer unit 15. The control unit 12 performs control to operate the input amplification unit 111 or the input switching unit 112 based on the type of the input signal.

[0177] The signal processing unit 14 determines which signal path from input 1 and input 2 of the power amplifier unit 11a should be used based on the data input from the user and the amount of data. Based on the determined signal path, the signal processing unit 14 outputs either a first baseband signal BB1 or a second baseband signal BB2. That is, when it is determined that input 1 of the power amplifier unit 11a should be used, the signal processing unit 14 outputs the first baseband signal BB1. Further, when it is determined that input 2 of the power amplifier unit 11a should be used, the signal processing unit 14 outputs the second baseband signal BB2.

[0178] When using the signal path of input 1, the power amplifier unit 11a inputs the first baseband signal BB1 to the mixer unit 15. The first baseband signal BB1 is an orthogonal modulation signal with amplitude modulation containing data and has a frequency of approximately several megahertz.

[0179] The high frequency local signal LO from the oscillation unit 16 is input to the mixer unit 15. The mixer unit 15 mixes the high frequency local signal and the first baseband signal BB1, and up-converts the first baseband signal BB1 to the first radio frequency signal RF1. The first radio frequency signal RF1 is input to the input 1 of the power amplification unit 11a.

[0180] The power amplification unit 11a suitably amplifies the first radio frequency signal RF1, and transmits the signal from the antenna. The signal is transmitted by this method when the signal is modulated by the OFDM method or the OQPSK method.

[0181] When the signal path of the input 2 is used, the power amplification unit 11a inputs the second baseband signal BB2 to the oscillation unit 16. The oscillation unit 16 directly modulates the second baseband signal BB2, and outputs the second radio frequency signal RF2. The second radio frequency signal RF2 is input to the input 2 of the power amplification unit 11a. The second radio frequency signal RF2 is a constant envelope signal.

[0182] The power amplification unit 11a amplifies the second radio frequency signal RF2 having a high frequency, and transmits the signal from the antenna. The signal is transmitted by this method when the modulation scheme of the signal is the FSK scheme.

[0183] Incidentally, the mixer unit 15 is a circuit of a direct conversion method. The oscillation unit 16 is a circuit of a direct modulation system.

[0184] (Ninth Embodiment)

[0185] Figure 26 is a block diagram illustrating an amplifier apparatus according to the ninth embodiment.

[0186] As Figure 26 shown, the amplifier apparatus 91 according to the ninth embodiment differs from the amplifier apparatus 81 according to the eighth embodiment in that the reception unit 17 is further provided.

[0187] The reception signal received by the reception antenna is suitably amplified by the reception unit, and a signal including data is extracted, and output to the reception output. The signal processing unit 14 determines which signal path of the input 1 and the input 2 of the power amplification unit 11a to use according to the data rate of the received signal and the data amount thereof, and outputs appropriate data to the first baseband signal BB1 and the second baseband signal BB2. The signal processing is the same as in Embodiment 8 thereafter.

[0188] Although the transmission antenna and the reception antenna are separately provided in Embodiment 9, the present application is not limited to this. An antenna for both transmission and reception can be substituted.

[0189] While the present application has been made on the basis of embodiments, the present application is not limited to the embodiments already described, and needless to say, various modifications can be made without departing from the gist thereof.

Claims

1. An amplifier apparatus comprising: a first amplification unit for amplifying an input signal and outputting a first output signal; an input switching unit connected in parallel with the first amplification unit for performing a switching operation by the input signal and outputting a switching output signal; and a second amplification unit for amplifying the first output signal or the switching output signal and outputting a second output signal, wherein the first amplification unit or the input switching unit operates based on a type of the input signal, wherein when the type of the input signal is an amplitude modulated signal, the first amplification unit operates and the input switching unit stops operating, and wherein when the type of the input signal is a constant envelope signal, the input switching unit operates and the first amplification unit stops operating. 2.The amplifier apparatus of claim 1, wherein the input switching unit stops operating while the first amplification unit is operating, and wherein wherein the first amplification unit stops operating while the input switching unit is operating. 3.The amplifier apparatus of claim 1, further comprising: a passive circuit for matching the second output signal. 4.The amplifier apparatus of claim 1, wherein the input signal, the first output signal, the switching output signal and the second output signal are differential signals. wherein 5.The amplifier apparatus of claim 1, wherein the first amplification unit comprises a first transistor, wherein, wherein the input switching unit comprises a second transistor, wherein the second amplification unit comprises a third transistor, wherein the input signal is connected to a gate of the first transistor and a gate of the second transistor, wherein a source of the first transistor and a source of the second transistor are connected to ground, wherein a drain of the first transistor and a drain of the second transistor are connected to a source of the third transistor, wherein the second output signal is output from a drain of the third transistor, wherein when the input signal is an amplitude modulated signal, a first predetermined voltage is applied to the gate of the first transistor and the first amplification unit operates, and a low level voltage is applied to the gate of the second transistor and the input switching unit stops the operation, and wherein when the input signal is a constant envelope signal, the low level voltage is applied to the gate of the first transistor and the first amplification unit stops operating, and the input switching unit operates. 6.The amplifier apparatus of claim 1, wherein the first amplification unit comprises a first transistor, wherein, wherein the input switching unit comprises a second transistor, wherein the second amplification unit comprises a third transistor for linear amplification and a third transistor for switching amplification, wherein the input signal is connected to a gate of the first transistor and a gate of the second transistor, wherein a source of the first transistor and a source of the second transistor are connected to ground, ​ wherein a drain of the first transistor is connected to a source of the third transistor for linear amplification, wherein a drain of the second transistor is connected to a source of the third transistor for switching amplification, wherein a drain of the third transistor for linear amplification is connected to a drain of the third transistor for switching amplification, wherein the second output signal is output from the drain of the third transistor for linear amplification, wherein, when the input signal is an amplitude modulation signal, a first predetermined voltage is applied to the gate of the first transistor, the first amplification unit operates, and a low-level voltage is applied to the gate of the second transistor, and the operation of the input switching unit is stopped, and wherein, when the input signal is a constant envelope signal, the low-level voltage is applied to the gate of the first transistor, the first amplification unit stops operating, and the input switching unit operates.

7. The amplifier device according to claim 1, wherein the first amplification unit includes a first transistor, wherein the input switching unit includes a second transistor, wherein the second amplification unit includes a third transistor, wherein the input signal is connected to a gate of the first transistor and a gate of the second transistor, wherein a source of the first transistor and a source of the second transistor are connected to ground, wherein a drain of the first transistor and a drain of the second transistor are connected to a source of the third transistor, wherein the second output signal is output from a drain of the third transistor, wherein, when the input signal is an amplitude modulation signal, a first predetermined voltage is applied to the gate of the first transistor, the first amplification unit operates, a second predetermined voltage is applied to the gate of the third transistor, the second amplification unit operates, and a low-level voltage is applied to the gate of the second transistor, the operation of the input switching unit is stopped, and wherein, when the input signal is a constant envelope signal, the low-level voltage is applied to the gate of the first transistor, the first amplification unit stops the operation, and a third predetermined voltage lower than the second predetermined voltage is applied to the gate of the third transistor, the input switching unit and the second amplification unit operate.

8. The amplifier device according to claim 7, wherein the third predetermined voltage is a voltage value at which a peak voltage at the drain of the first transistor and the drain of the second transistor does not exceed a device withstand voltage threshold of the first transistor and the second transistor.

9. The amplifier device according to claim 1, a control unit controls the first amplification unit or the input switching unit to operate based on the type of the input signal.

10. The amplifier device according to claim 1, further comprising: a plurality of power amplification circuits including the first amplification unit, the input switching unit, and the second amplification unit, wherein all outputs of the plurality of power amplification circuits are connected to an input of a passive circuit, wherein all inputs of the plurality of first amplification units are connected to a first input terminal, wherein inputs of the plurality of input switching units are connected to second input terminals provided for each of the plurality of input switching units, wherein when an amplitude modulated signal is input from the first input terminal, the number of operations of the first amplification units is controlled by a first control signal, and the number of operations of the second amplification units is controlled by a second control signal, wherein when a constant envelope signal is input from the second input terminal, the input switching units are operated by the constant envelope signal, and the number of operations of the second amplification units is controlled by the second control signal, and wherein a transmission power at an output terminal of the passive circuit is controlled to be a desired transmission power.

11. A method for an amplifier device, the method comprising: amplifying an input signal and outputting a first output signal, performing a switching operation from the input signal and outputting a switching output signal; amplifying the first output signal when a type of the input signal is an amplitude modulated signal to output a second output signal; and amplifying the switching output signal when the type of the input signal is a constant envelope signal to output the second output signal.

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