Digital LDO Circuit for Reducing the Limit Loop Oscillation

Abstract

The present invention provides a digital LDO circuit for reducing the limit loop oscillation, which includes a digital LDO circuit, an LCO detection circuit and an LCO reduction circuit connected in sequence, and the digital LDO circuit is connected to the LCO reduction circuit; the LCO detection circuit is used to compare the output voltage of the digital LDO circuit with the maximum overshoot voltage, and control the opening of the LCO reduction circuit according to the comparison result; when the LCO reduction circuit is opened, it suppresses the increase of the output voltage and reduces the limit loop oscillation. The circuit structure is simple, without the need for excessive theoretical analysis to determine the parameters of the devices in the LCO reduction circuit, nor the need to set the LCO preprocessing mode by analyzing each node in the circuit, and it is very convenient to use.

Description

Technical Field

[0001] The present invention relates to the technical field of digital LDO circuits, and in particular to a digital LDO circuit for reducing ultimate loop oscillation. Background Art

[0002] With the emergence of digital LDOs, the advantages they possess have gradually attracted people's attention. Its low-voltage operating characteristics, high precision, stable output, process variability, etc. have enabled digital LDOs to be widely used in low-input, high-precision, and high-efficiency power management systems. A traditional digital LDO consists of a clock comparator, a digital control section based on a bidirectional shift register, and a switch array. The clock comparator is used to compare the output voltage VOUT with the reference voltage VREF and provide the comparison result CMPout to the bidirectional shift register to control the shift direction sel of the register. The bidirectional shift register controls the number of switches in the switch array that are turned on, playing a role in regulating the output voltage. The switch array is composed of PMOS transistors of the same size. Under normal operation, the turned-on switch transistors operate in the linear region to achieve the low-voltage operating characteristics of the digital LDO. The load capacitor at the output terminal is used to reduce the ripple of the output voltage. The traditional digital LDO will generate ultimate loop oscillation (i.e., LCO) in the steady state, and LCO will increase the power consumption of the system. To solve the problem of LCO, currently, it is usually based on the traditional digital LDO structure, and by adding a feedforward path between the comparator output terminal and the system output terminal, the mode of LCO can be reduced to mode 1, which can significantly reduce the amplitude of LCO, with a simple structure and obvious effect. However, the disadvantages of this method of reducing LCO are as follows: First, it is necessary to model the entire circuit, and through a large number of theoretical calculations, the mode M parameter of LCO and the proportionality coefficient β of the size of the auxiliary transistor relative to the main array switch transistor can be obtained. Second, mode 1 LCO cannot be achieved in the traditional structure. Although mode 1 LCO can be achieved in the structure with the added feedforward path, reasonable matching of the outputs of each node in the system in terms of phase and oscillation frequency is required. Summary of the Invention

[0003] In view of this, the present invention provides a digital LDO circuit for reducing ultimate loop oscillation, which is used to solve the technical problems of a large number of theoretical calculations and reasonable settings of the internal circuit when reducing the mode of LCO to mode 1 in the traditional digital LDO.

[0004] A digital LDO circuit for reducing ultimate loop oscillation includes: a digital LDO circuit, an LCO detection circuit, and an LCO reduction circuit connected in sequence, and the digital LDO circuit is connected to the LCO reduction circuit;

[0005] The LCO detection circuit is used to compare the output voltage of the digital LDO circuit with the maximum overshoot voltage, and control the activation of the LCO reduction circuit according to the comparison result; when the LCO reduction circuit is activated, it suppresses the increase of the output voltage and reduces the limit loop oscillation.

[0006] Optionally, it further includes:

[0007] The LCO detection circuit is also used to control the shutdown of the LCO reduction circuit according to the comparison result and output the output voltage.

[0008] Optionally,

[0009] The digital LDO circuit includes a clock comparator, a bidirectional shift register, and a switch array connected in sequence;

[0010] The negative input terminal of the clock comparator is used to input a reference voltage, and the positive input terminal of the clock comparator is used to input the output voltage;

[0011] The switch array is connected to the LCO reduction circuit.

[0012] Optionally,

[0013] The LCO detection circuit includes a static comparator and an inverter connected in sequence; wherein the positive input terminal of the static comparator is used to input the output voltage, and the negative input terminal of the static comparator is used to input the maximum overshoot voltage; the output terminal of the inverter is connected to the LCO reduction circuit.

[0014] Optionally,

[0015] The LCO reduction circuit includes a current mirror control circuit and the current mirror circuit connected in sequence; wherein, the output terminal of the inverter is connected to the current mirror control circuit, and the switch array is connected to the current mirror circuit;

[0016] When the inverter outputs a low-level signal, the current mirror control circuit is turned off, and the current mirror circuit reduces the output current of the digital LDO circuit to suppress the increase of the output voltage.

[0017] Optionally,

[0018] The current mirror control circuit is a control switch.

[0019] Optionally,

[0020] The current mirror circuit includes two NMOS transistor groups, and the two NMOS transistors are connected; wherein each NMOS transistor group includes multiple NMOS transistors, and the multiple NMOS transistors are connected in series and / or in parallel;

[0021] The current mirror control circuit is connected between two NMOS transistor groups.

[0022] Optionally,

[0023] The switch array is a PMOS transistor switch array.

[0024] Optionally,

[0025] The control switch is an NMOS transistor or a PMOS transistor.

[0026] Optionally,

[0027] The PMOS transistor switch array includes a plurality of PMOS transistors, and the plurality of PMOS transistors are connected in series and / or in parallel.

[0028] The digital LDO circuit for reducing the limit loop oscillation in the embodiment of the present invention includes: a digital LDO circuit, an LCO detection circuit, and an LCO reduction circuit connected in sequence, and the digital LDO circuit is connected to the LCO reduction circuit; the LCO detection circuit is configured to compare the output voltage of the digital LDO circuit with the maximum overshoot voltage, and control the opening of the LCO reduction circuit according to the comparison result; when the LCO reduction circuit is opened, it suppresses the increase of the output voltage and reduces the limit loop oscillation. The above digital LDO circuit for reducing the limit loop oscillation uses the LCO detection circuit to compare the output voltage with the maximum overshoot voltage, and decides whether to open the LCO reduction circuit according to the comparison result. When the LCO reduction circuit is opened, the LCO reduction circuit can suppress the increase of the output voltage, thereby reducing the limit loop oscillation. The circuit structure is simple, and there is no need to perform excessive theoretical analysis to determine the parameters of the devices in the LCO reduction circuit, nor is it necessary to set the LCO preprocessing mode by analyzing each node in the circuit, and it is very convenient to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0030] Figure 1 It is a schematic structural diagram of a digital LDO circuit for reducing the limit loop oscillation provided by an embodiment of the present invention;

[0031] Figure 2 It is a schematic structural diagram of a digital LDO circuit for reducing the limit loop oscillation provided by another embodiment of the present invention;

[0032] Figure 3Schematic diagram of the shift register in the digital LDO circuit provided by an embodiment of the present invention;

[0033] Figure 4 Schematic diagram of the simulation output result of the shift register provided by an embodiment of the present invention;

[0034] Figure 5 Schematic diagram of the clock comparator in the digital LDO circuit provided by an embodiment of the present invention;

[0035] Figure 6 Schematic diagram of the simulation output result of the clock comparator provided by an embodiment of the present invention. Detailed implementation manners

[0036] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Apparently, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0037] To describe the present invention in more detail, a digital LDO circuit for reducing the limit loop oscillation provided by the present invention will be specifically described below with reference to the drawings.

[0038] Please refer to Figure 1 , a digital LDO circuit for reducing the limit loop oscillation, including: a digital LDO circuit 100, an LCO detection circuit 200, and an LCO reduction circuit 300 connected in sequence, and the digital LDO circuit 100 is connected to the LCO reduction circuit 300; the LCO detection circuit 200 is configured to compare the output voltage of the digital LDO circuit 100 with the maximum overshoot voltage, and control the activation of the LCO reduction circuit 300 according to the comparison result; when the LCO reduction circuit 300 is activated, it suppresses the increase of the output voltage and reduces the limit loop oscillation.

[0039] Wherein, the maximum overshoot voltage is the threshold range for the LCO detection circuit to detect the output voltage of the digital LDO circuit, that is, the upper limit of the voltage that the LCO detection circuit can detect, and is used to determine the state of the digital LDO circuit at the next moment; the function of the LCO detection circuit 200 is essentially to adjust the direction of system adjustment according to the magnitude of the current output voltage. When the output voltage is too large or too small, the digital LDO circuit can enter the coarse adjustment state and quickly adjust the output voltage to the expected value; when the output voltage is stable near the expected value, the digital LDO circuit can enter the fine adjustment state and slowly adjust the output voltage.

[0040] In this embodiment, the LCO detection circuit compares the output voltage with the maximum overshoot voltage, and determines whether to start or turn on the LCO reduction circuit according to the comparison result. Usually, when the output voltage is greater than the maximum overcharge voltage, the LCO reduction circuit is turned on to suppress the increase of the output voltage and reduce the limit cycle oscillation.

[0041] The digital LDO circuit for reducing the limit cycle oscillation in the embodiment of the present invention includes: a digital LDO circuit, an LCO detection circuit, and an LCO reduction circuit connected in sequence, and the digital LDO circuit is connected to the LCO reduction circuit; the LCO detection circuit is used to compare the output voltage of the digital LDO circuit with the maximum overshoot voltage, and control the turning on of the LCO reduction circuit according to the comparison result; when the LCO reduction circuit is turned on, it suppresses the increase of the output voltage and reduces the limit cycle oscillation. The above digital LDO circuit for reducing the limit cycle oscillation uses the LCO detection circuit to compare the output voltage with the maximum overshoot voltage, and decides whether to turn on the LCO reduction circuit according to the comparison result. When the LCO reduction circuit is turned on, the LCO reduction circuit can suppress the increase of the output voltage, thereby reducing the limit cycle oscillation. The circuit structure is simple, and it is not necessary to conduct excessive theoretical analysis to determine the parameters of the devices in the LCO reduction circuit, nor is it necessary to set the LCO preprocessing mode by analyzing each node in the circuit, which is very convenient to use.

[0042] In one embodiment, it further includes: the LCO detection circuit is further used to control the LCO reduction circuit to turn off according to the comparison result and output the output voltage.

[0043] Optionally, the LCO detection circuit is used to compare the output voltage of the digital LDO circuit with the maximum overshoot voltage, and control the turning off of the LCO reduction circuit according to the comparison result. Usually, when the output voltage is less than the maximum overshoot voltage, there is no need to adjust the output voltage, so the LCO reduction circuit can be turned off or not turned on at this time, and the LCO phenomenon will not occur, so the output voltage can be directly output.

[0044] In one embodiment, the digital LDO circuit includes a clock comparator, a bidirectional shift register, and a switch array connected in sequence; the negative input terminal of the clock comparator is used to input the reference voltage, and the positive input terminal of the clock comparator is used to input the output voltage; the switch array is connected to the LCO reduction circuit.

[0045] In one embodiment, the switch array is a PMOS transistor switch array.

[0046] In one embodiment, the PMOS transistor switch array includes a plurality of PMOS transistors, and the plurality of PMOS transistors are connected in series and / or in parallel.

[0047] Specifically, such as Figure 2As shown, the digital LDO circuit includes a clock comparator, a bidirectional shift register, and a switch array. The clock comparator is used to compare the output voltage V OUT with the reference voltage V REF and provide the comparison result CMPout to the sel terminal of the bidirectional shift register. The bidirectional shift register consists of a multiplexer and a D flip-flop as the basic unit. The address input terminal sel of the multiplexer controls the shifting direction. When sel = 1, the shift register shifts to the right; when sel = 0, the shift register shifts to the left. In one clock cycle, the shift register can only control the on or off of one PMOS transistor. The outputs Q[0:n] of the shift register determine the number of conducting transistors in the switch array, playing a role in regulating the output voltage. The switch array MP[0:n] is composed of PMOS transistors with the same size. The gates PG[0:n] of the PMOS transistors in the switch array are connected to the outputs Q[0:n] of the bidirectional shift register. Under normal operation, the conducting switch transistors work in the linear region to achieve the low-voltage operating characteristics of the digital LDO.

[0048] The working principle of the shift register is as follows: Most shift registers in digital LDO circuits use a multiplexer and a D edge flip-flop as the basic unit. The working principle of the D edge flip-flop is that the output signal Q depends on the state of D when the rising edge arrives; while the multiplexer determines the shifting situation of the register by the high and low levels of the input signal at the selection port. Its specific working principle is described in combination with Figure 3 and Figure 4 as follows: ① Initially, the outputs of all shift registers are set to 1, so that the transistors controlled by the registers are all turned off before the effective clock signal arrives.

[0049] ② The 1 terminal of the lowest bit and the 0 terminal of the highest bit are grounded (GND) and connected to the power supply (VDD) respectively. This is the basic connection of the shift register.

[0050] ③ When COMPOUT = 1, when the first effective clock signal arrives, Q0 = 0, and the outputs of the remaining shift registers Q1 = Q2 = Q3 = Q4 =... = Qn = 1; when the second effective clock signal arrives, Q0 = Q1 = 0, and the outputs of the remaining shift registers Q2 = Q3 = Q4 =... = Qn = 1,..., when the nth effective clock signal arrives, the outputs of the n-bit shift register are all 0.

[0051] ④ After all the tubes are turned on, that is, when all the outputs of the shift register are 0, if COMPOUT = 0 at this time, when the first valid clock signal arrives temporarily, Qn = 1, Qn-1 = Qn-2 = …… = Q2 = Q1 = 0. When the second valid clock signal arrives, Qn = Qn-1 = 1, and the outputs of the remaining shift registers Qn-2 = …… = Q2 = Q1 = 0, ……, until when the nth valid clock signal arrives, all the outputs of the shift register are 1.

[0052] To sum up: Macroscopically, the working principle of the shift register is that when COMPOUT = 1, every time a valid clock signal arrives, within this clock cycle, the shift register moves one bit to the right, adding a port with an output of 0, so that one more power tube in the power array can be turned on. When COMPOUT = 0, every time a valid clock signal arrives, the shift register moves one bit to the left, increasing the ports of the shift register with an output of 1, so that one conducting power tube in the power array can be turned off. For an n-bit shift register, when all the output terminals are 1, n valid clock signals are required to set all the output ports to 0; similarly, when all the output terminals are 0, n clock signals are also required to set all the output terminals of the shift register to 1. According to the above analysis of the working principle of the shift register and Figure 4 From the simulation results of the 8-bit shift register, it can be known that within a valid clock range, the shift register either moves one bit to the right or one bit to the left, so that within one clock cycle, the shift register only controls the conduction or turn-off of one power tube.

[0053] Please refer to Figure 5 and Figure 6 As shown, the working principle of the clock comparator: (1) When VOUT > VREF, when clk = 0, points A and B are charged, increasing the voltages at points A and B. When CLK = 1, points A and B start to discharge, but the discharge speeds are different due to the different gate voltages of M1 and M2. The discharge speed of point A is greater than that of point B. After the voltage at point A quickly becomes a low voltage, after passing through the RS latch, CMPOUT = 0.

[0054] (2) When VOUT < VREF, when clk = 0, points A and B start to be charged, increasing the voltages at these two points. When clk = 1, points A and B start to discharge, but at this time the discharge speed of point B is greater than that of point A. After passing through the latch, CMPOUT = 1.

[0055] (3) The functions of the auxiliary tubes MA1 and MA2 are to charge the drains of the differential pair tubes when clk is at a low level, increasing the drain voltages, so as to accelerate the discharge speeds of points A and B when clk = 1.

[0056] In summary, the control mechanism of the digital LDO circuit is as follows: Combining Figure 2 with the principle block diagram, when the output voltage vout > vref, the output signal CMPout of the clock comparator is 0. At this time, the shift register moves one bit to the left, and the number of turned-on transistors in the switch array controlled by the shift register decreases by one, making the output voltage vout decrease; when the output voltage vout < vref, the output signal CMPout of the clock comparator is 1. At this time, the shift register moves one bit to the right, and the number of turned-on transistors in the switch array increases by one, thereby increasing the output voltage to achieve the purpose of voltage stabilization.

[0057] In one embodiment, the LCO detection circuit includes a static comparator and an inverter connected in sequence; the positive input terminal of the static comparator is used to input the output voltage, and the negative input terminal of the static comparator is used to input the maximum overshoot voltage; the output terminal of the inverter is connected to the LCO reduction circuit.

[0058] Specifically, as Figure 2 shown, the circuit for detecting LCO consists of a static comparator and an inverter, which real-time detects the output voltage V OUT of the digital LDO voltage, and generates an output signal EN through the inverter, thereby controlling whether the LCO reduction circuit works.

[0059] In one embodiment, the LCO reduction circuit includes a current mirror control circuit and a current mirror circuit connected in sequence; among them, the output terminal of the inverter is connected to the current mirror control circuit, and the switch array is connected to the current mirror circuit; when the inverter outputs a low-level signal, the current mirror control circuit is turned off, and the current mirror circuit reduces the output current of the digital LDO circuit to suppress the increase of the output voltage.

[0060] In one embodiment, the current mirror control circuit is a control switch.

[0061] In one embodiment, the current mirror circuit includes two NMOS transistor groups, and the two NMOS transistors are connected; each NMOS transistor group includes multiple NMOS transistors, and the multiple NMOS transistors are connected in series and / or in parallel; the current mirror control circuit is connected between the two NMOS transistor groups.

[0062] In one embodiment, the control switch is an NMOS transistor or a PMOS transistor.

[0063] The LCO reduction circuit includes a current mirror control circuit and a current mirror circuit; when EN = 0, the current mirror control circuit is disconnected, and at this time the LCO reduction circuit (i.e., the current mirror circuit) starts to work. When EN = 1, the current mirror control circuit is turned on or conducted, and at this time the current mirror circuit is turned off, that is, the LCO reduction circuit is in a prohibited working state.

[0064] Optionally, the current mirror control circuit is essentially a control switch. In an optional implementation, the control switch is a PMOS tube or an NMOS tube. The number of PMOS tubes and NMOS tubes can be multiple. In this embodiment, the control switch is an NMOS tube (i.e. Figure 2 MN3 in ).

[0065] The current mirror circuit includes two NMOS tube groups (i.e. Figure 2 MN1 and MN2 in the current mirror circuit), each NMOS tube group includes multiple NMOS tubes, and multiple NMOS tubes are connected in series and / or in parallel to form an NMOS tube group. The parameter M represents the number of MOS tubes, and β represents the mirror ratio of the MN2 tube in the current mirror circuit relative to the diode-connected MN1 tube.

[0066] like Figure 2 As shown in the figure, the working principle of the LCO reduction circuit is: when EN = 0, the LCO reduction circuit works when the MN3 switch tube is turned on and off. When EN = 1, the MN3 switch tube is turned on, pulling down the gate voltage of the tubes MN1 and MN2 in the current mirror circuit, and the MN1 and MN2 tubes cannot be turned on normally, so the LCO reduction circuit is in a prohibited working state. Figure 2 The parameter M marked in represents the number of MOS tubes, and β represents the mirror ratio of the MN2 tube in the current mirror circuit relative to the diode-connected MN1 tube.

[0067] Combination Figure 2 It can be seen that the working principle of the digital LDO circuit for reducing the limit loop oscillation in the embodiment of the present invention is: first, assuming that the allowable output voltage V of the digital LDO circuit is OUT The maximum overshoot voltage is V REF_H The minimum current of the PMOS switch array of the digital LDO circuit is I LSB , the working principle of the core LCO reduction circuit is as follows:

[0068] When V OUT >V REF_H When the output signal V OUT Through the clock comparator CMP 2 With V REF_H For comparison, CMP 2 The output of is 1, and after passing through the inverter, EN = 0. At this time, the LCO reduction circuit starts to work, and the current source MP[0] provides a current I LSB After the current mirror is β ILSB , the current flows from the output terminal to the ground through the MN2 tube, reducing the output capacitance C L The charging current on V OUT The voltage is increased, thus reducing the output ripple.

[0069] When V OUT < V REF_H When this occurs, the output signal V OUT passes through the clock comparator CMP 2 for comparison with V REF_H At this time, the output of CMP 2 is 0. After passing through the inverter, EN = 1, and MN3 in the LCO reduction circuit conducts, pulling down the gate voltages of MN1 and MN2 in the current mirror circuit to 0, disabling the current mirror circuit and directly outputting the voltage V OUT at the output of the digital LDO.

[0070] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A digital LDO circuit for reducing limit loop oscillation, characterized in that, it includes: A digital LDO circuit, an LCO detection circuit, and an LCO reduction circuit connected in sequence, and the digital LDO circuit is connected to the LCO reduction circuit; The LCO detection circuit is used to compare the output voltage of the digital LDO circuit with the maximum overshoot voltage, and control the activation of the LCO reduction circuit according to the comparison result; when the LCO reduction circuit is activated, it suppresses the increase of the output voltage and reduces the limit loop oscillation; The digital LDO circuit includes a clock comparator, a bidirectional shift register, and a switch array connected in sequence; The negative input terminal of the clock comparator is used to input a reference voltage, and the positive input terminal of the clock comparator is used to input the output voltage; the switch array is respectively connected to the LCO reduction circuit and the LCO detection circuit; the output terminal of the clock comparator is connected to the input terminal of the bidirectional shift register; the output terminal of the bidirectional shift register is connected to the switch array; the CLK terminal of the bidirectional shift register is connected to the clock comparator; The LCO detection circuit includes a static comparator and an inverter connected in sequence; wherein the positive input terminal of the static comparator is used to input the output voltage, and the negative input terminal of the static comparator is used to input the maximum overshoot voltage; the output terminal of the static comparator is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the LCO reduction circuit; The LCO reduction circuit includes a current mirror control circuit and a current mirror circuit connected in sequence; wherein, the output terminal of the inverter is connected to the current mirror control circuit, and the switch array is connected to the current mirror circuit; When the inverter outputs a low-level signal, the current mirror control circuit is turned off, and the current mirror circuit reduces the output current of the digital LDO circuit to suppress the increase of the output voltage; Among them, the bidirectional shift register is composed of a multiplexer and a D flip-flop.

2. The digital LDO circuit for reducing limit loop oscillation according to claim 1, characterized in that, it further includes: The LCO detection circuit is further used to control the LCO reduction circuit to be turned off according to the comparison result and output the output voltage.

3. The digital LDO circuit for reducing limit loop oscillation according to claim 1, characterized in that, The current mirror control circuit is a control switch.

4. The digital LDO circuit for reducing limit loop oscillation according to claim 1, characterized in that, The current mirror circuit includes two NMOS transistor groups, and the two NMOS transistor groups are connected; each NMOS transistor group includes multiple NMOS transistors, and the multiple NMOS transistors are connected in series and / or in parallel to form an NMOS transistor group; the gates of each NMOS transistor group are connected to each other, the drain of one NMOS transistor group is respectively connected to its own gate and a current source, and the drain of the other NMOS transistor group is connected to the output voltage; the source of each NMOS transistor group is grounded; The current mirror control circuit is connected between the two NMOS transistor groups.

5. The digital LDO circuit for reducing the limit loop oscillation according to claim 4, wherein, the switch array is a PMOS transistor switch array.

6. The digital LDO circuit for reducing the limit loop oscillation according to claim 3, wherein, the control switch is an NMOS transistor or a PMOS transistor.

7. The digital LDO circuit for reducing the limit loop oscillation according to claim 5, wherein, the PMOS transistor switch array includes a plurality of PMOS transistors, the sources of each of the PMOS transistors are connected to the input voltage, the drains of each of the PMOS transistors are connected to the output voltage, and the gates of the plurality of PMOS transistors are sequentially connected to the output terminals of the bidirectional shift register.

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