Semiconductor structure

Abstract

The present invention provides a semiconductor structure, comprising: a substrate, a gate structure arranged on the substrate, a source structure and a drain structure located on both sides of the gate structure, and a first dielectric layer. The gate structure comprises a gate electrode arranged on the substrate and a gate metal layer electrically connected to the gate electrode and serving as a gate field plate. The source structure comprises a source electrode arranged on the substrate and a first source metal layer electrically connected to the source electrode and extending in the direction from the gate electrode to the drain structure. The first dielectric layer is arranged on the gate metal layer. The potential of the first source metal layer is different from that of the gate metal layer, and the first source metal layer at least exposes a portion of the first dielectric layer located directly above the gate metal layer. The semiconductor structure provided by the embodiment of the present invention not only has a good balance between the breakdown voltage and the gate-to-drain capacitance, but also can effectively reduce the switching loss, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure with a field plate. Background Art

[0002] GaN-based semiconductor materials have many excellent material properties, such as high heat resistance, wide band-gap, and high electron saturation rate. Therefore, GaN-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, GaN-based semiconductor materials have been widely used in light emitting diode (LED) components, high-frequency components, such as high electron mobility transistor (HEMT) with heterojunction structure.

[0003] In a high electron mobility transistor (HEMT) device, a field plate structure is usually disposed in a high electric field region of a semiconductor device to reduce the peak electric field in the high electric field region. One type of field plate is a field plate connected to the source (i.e., a source field plate), which can reduce the gate-to-drain capacitance (Cgd), while another type of field plate is a field plate connected to the gate (i.e., a gate field plate), which can reduce the electric field strength of the gate on the drain side. However, the configuration of the field plate structure causes a significant increase in the gate-to-source capacitance (Cgs), resulting in severe switching losses.

[0004] With the development of GaN-based semiconductor materials, these semiconductor devices using GaN-based semiconductor materials are applied in more severe working environments, such as higher frequency, higher temperature or higher voltage. Therefore, semiconductor devices using GaN-based semiconductor materials still need to be further improved to overcome the challenges they face. Summary of the invention

[0005] Some embodiments of the present invention provide a semiconductor structure, comprising: a substrate, a gate structure disposed on the substrate, a source structure and a drain structure disposed on the substrate and located on both sides of the gate structure, and a first dielectric layer disposed on a gate metal layer included in the gate structure. The gate structure comprises a gate electrode disposed on the substrate and a gate metal layer electrically connected to the gate electrode and serving as a gate field plate. The source structure comprises a source electrode disposed on the substrate and a first source metal layer electrically connected to the source electrode and extending in a direction from the gate electrode to the drain structure. The potential of the first source metal layer is different from that of the gate metal layer, and the first source metal layer at least exposes a portion of the first dielectric layer located directly above the gate metal layer.

[0006] Some embodiments of the present invention provide a semiconductor structure, comprising: a substrate, a gate structure disposed on the substrate, a source structure disposed on the substrate, and a drain structure disposed on the substrate. The gate structure comprises a gate electrode disposed on the substrate and a gate metal layer electrically connected to the gate electrode and serving as a gate field plate. The source structure comprises a source electrode disposed on the substrate and a first source metal layer electrically connected to the source electrode and serving as a source field plate. The potential of the first source metal layer is different from the potential of the gate metal layer. In the top view, the first source metal layer has an opening located directly above the gate metal layer.

[0007] The semiconductor structure provided by the embodiment of the present invention not only has a good balance between breakdown voltage and gate-to-drain capacitance, but also can effectively reduce switching losses, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components may be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0009] Figure 1 FIG. 1 is a partial top view of an exemplary semiconductor structure according to some embodiments of the present invention.

[0010] Figure 2 According to some embodiments of the present invention, Figure 1 A schematic cross-sectional view of the semiconductor structure taken along line AA' is shown.

[0011] Figure 3 FIG. 2 is a partial top view of an exemplary semiconductor structure according to another embodiment of the present invention.

[0012] Figure 4 According to another embodiment of the present invention, a diagram corresponding to Figure 3 A schematic cross-sectional view of the semiconductor structure taken along line BB' is shown.

[0013] Figure 5 FIG. 2 is a partial top view of an exemplary semiconductor structure according to another embodiment of the present invention.

[0014] Figure 6 According to another embodiment of the present invention, a diagram corresponding to Figure 5 A schematic cross-sectional view of the semiconductor structure taken along the line CC' is shown.

[0015] Figure 7 , Figure 8 , Fig. 9FIG. 2 is a partial top view of an exemplary semiconductor structure according to some other embodiments of the present invention.

[0016] Reference numerals:

[0017] 100, 300, 500, 700, 800, 900~Semiconductor structure

[0018] 101~Substrate

[0019] 110~Compound semiconductor layer

[0020] 111~Buffer layer

[0021] 112~Channel layer

[0022] 113~Barrier layer

[0023] 114~Doped compound semiconductor layer

[0024] 115, 116, 616 ~ Dielectric layer

[0025] 116', 616'~Dielectric layer part

[0026] 120~Gate structure

[0027] 121~Gate electrode

[0028] 122~Gate metal layer

[0029] 130~Source structure

[0030] 131~Source electrode

[0031] 132, 332, 532, 732, 832, 932 ~ Source metal layer

[0032] 133~Source contact

[0033] 140~Drain structure

[0034] 141~Drain electrode

[0035] 142~Drain metal layer

[0036] 143~Drain contact

[0037] A-A', B-B', C-C', D-D', E-E', F-F'~section (section line)

[0038] OP1, OP2, OP3, OP4, OP5, OP6, OP7, OP8~Open

[0039] W, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12~Width DETAILED DESCRIPTION

[0040] Various different embodiments or examples are provided below for implementing different elements of the provided semiconductor structure. When the description mentions that a first component is formed on a second component, it may include an embodiment in which the first and second components are directly in contact, and it may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact. In addition, embodiments of the present invention may use repeated component symbols in many examples. These repetitions are only for the purpose of simplicity and clarity, and do not represent a specific relationship between the various embodiments and / or configurations discussed.

[0041] Furthermore, spatially relative terms such as "above", "below", "above", "below" and similar terms include not only the orientation depicted in the drawings, but also different orientations of the device in use or operation. When the device is rotated to other orientations (rotated 90 degrees or other orientations), the spatially relative descriptions used herein can also be interpreted based on the rotated orientation.

[0042] Here, the terms "about", "approximately", and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about", "approximately", and "generally", the meanings of "about", "approximately", and "generally" can still be implied.

[0043] The semiconductor structure provided by the embodiment of the present invention uses a gate field plate to reduce the risk of the gate structure being subjected to a high electric field, and uses a source field plate to optimize the electric field distribution and effectively reduce the gate-to-drain capacitance (C gd ) and reduce the gate-to-source capacitance (C gs ), thereby reducing switching loss. Therefore, the semiconductor structure provided by the embodiment of the present invention has a breakdown voltage and a gate-to-drain capacitance (C gd ) can effectively reduce switching losses and thus improve the performance of the semiconductor structure.

[0044] Figure 1 FIG. 1 is a partial top view of an exemplary semiconductor structure 100 according to some embodiments of the present invention. Figure 1As shown, the semiconductor structure 100 includes a gate metal layer 122, a source metal layer 132, and a drain metal layer 142 disposed on a substrate 101. According to some embodiments of the present invention, the source metal layer 132 has an opening OP1 located directly above the gate metal layer 122. In some embodiments, the opening OP1 may be rectangular. It should be understood that in order to concisely describe the embodiments of the present invention and highlight its technical features, not all elements of the semiconductor structure 100 are illustrated. Figure 1 middle.

[0045] Please refer to Figure 2 . Figure 2 According to some embodiments of the present invention, Figure 1 The semiconductor structure 100 is a schematic cross-sectional view taken along the line AA' of the semiconductor structure 100. The semiconductor structure 100 includes a compound semiconductor layer 110 disposed on a substrate 101, a dielectric layer 115 disposed on the compound semiconductor layer 110, and a dielectric layer 116 disposed on the dielectric layer 115. The semiconductor structure 100 further includes a gate structure 120 disposed on the compound semiconductor layer 110, and a source structure 130 and a drain structure 140 disposed on both sides of the gate structure 120.

[0046] In some embodiments, the substrate 101 may be a doped (e.g., doped with a p-type or n-type dopant) or undoped semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, or a similar semiconductor substrate. In some embodiments, the substrate 101 may be a semiconductor-on-insulator substrate, such as a silicon on insulator (SOI) substrate. In other embodiments, the substrate 101 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an aluminum oxide substrate (Al2O3) (or sapphire substrate), or other similar substrates.

[0047] like Figure 2 As shown, the compound semiconductor layer 110 includes a buffer layer 111, a channel layer 112 disposed on the buffer layer 111, and a barrier layer 113 disposed on the channel layer 112. The buffer layer 111 can relieve the strain of the channel layer 112 subsequently formed on the buffer layer 111 to prevent defects from being formed in the channel layer 112 above. The strain is caused by the mismatch between the channel layer 112 and the substrate 101. In some embodiments, the material of the buffer layer 111 can be AlN, GaN, Al x Ga 1-xN, where 0 < x < 1, the aforementioned combination, or other similar materials. The buffer layer 111 can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), the aforementioned combination, or a similar method. It should be noted that although in the embodiment shown in Figure 2 the buffer layer 111 is a single-layer structure, the buffer layer 111 can also be a multi-layer structure (not shown) in other embodiments.

[0048] According to some embodiments of the present invention, a two-dimensional electron gas (2DEG) (not shown) is formed at the heterointerface between the channel layer 112 and the barrier layer 113. As shown in Figure 2 the semiconductor structure 100 is a high electron mobility transistor (HEMT) that uses a two-dimensional electron gas (2DEG) as the conductive carrier. In some embodiments, the channel layer 112 can be a gallium nitride (GaN) layer, and the barrier layer 113 formed on the channel layer 112 can be an aluminum gallium nitride (AlGaN) layer, where the gallium nitride layer and the aluminum gallium nitride layer can have dopants (such as n-type dopants or p-type dopants) or no dopants. Both the channel layer 112 and the barrier layer 113 can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), the aforementioned combination, or other similar methods.

[0049] Continuing to refer to Figure 2 , then, a dielectric layer 115, 116, a gate structure 120, and source and drain structures 130 and 140 located on both sides of the gate structure 120 are formed on the compound semiconductor layer 110 by a deposition process and a patterning process. Specifically, in some embodiments, the gate structure 120 includes a gate electrode 121 and a gate metal layer 122 electrically connected to the gate electrode 121. In some embodiments, the gate electrode 121 is disposed on the barrier layer 113 and buried in the dielectric layer 115, and the gate metal layer 122 is disposed on the dielectric layer 115 and covered by the dielectric layer 116. In other embodiments, an optional doped compound semiconductor layer 114 can be included between the gate electrode 12 and the barrier layer 113, and its details will be further described later.

[0050] As shown in Figure 2As shown, the source structure 130 includes a source electrode 131, a source contact 133, and a source metal layer 132. In some embodiments, the source electrode 131 is buried in the dielectric layer 115, and the source metal layer 132 is disposed on the dielectric layer 116, wherein the source electrode 131 and the source metal layer 132 are electrically connected via the source contact 133 buried in the dielectric layer 116. The potential of the source metal layer 132 electrically connected to the source electrode 131 is different from the potential of the gate metal layer 122 electrically connected to the gate electrode 121.

[0051] like Figure 2 As shown, the drain structure 140 includes a drain electrode 141, a drain contact 143, and a drain metal layer 142. In some embodiments, the drain electrode 141 is buried in the dielectric layer 115, and the drain metal layer 142 is disposed on the dielectric layer 116, wherein the drain electrode 141 and the drain metal layer 142 are electrically connected via the drain contact 143 buried in the dielectric layer 116. In some embodiments, the source electrode 131 and the drain electrode 141 located on both sides of the gate electrode 121 pass through the barrier layer 113 and contact the channel layer 112.

[0052] According to some embodiments of the present invention, the gate metal layer 122 extending from the gate electrode 121 to the drain electrode 141 and serving as a gate field plate can effectively reduce the risk of the gate structure being subjected to a high electric field. On the other hand, the source metal layer 132 extending from the gate electrode 121 to the drain electrode 141 and serving as a source field plate can optimize the electric field distribution and effectively reduce the gate-to-drain capacitance (C gd ).

[0053] In some embodiments, the material of the gate electrode 121 may be a conductive material, such as a metal, a metal nitride, or a semiconductor material. In some embodiments, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, combinations thereof, or multilayer structures thereof. The semiconductor material may be polycrystalline silicon or polycrystalline germanium. The conductive material may be formed on the blocking layer 113 by, for example, chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or other suitable deposition methods, and then the gate electrode 121 may be formed by a patterning process.

[0054] According to some embodiments of the present invention, before forming the gate electrode 121, a doped compound semiconductor layer 114 may be formed on the barrier layer 113, and then the gate electrode 121 may be formed on the doped compound semiconductor layer 114. By disposing the doped compound semiconductor layer 114 between the gate electrode 121 and the barrier layer 113, the generation of two-dimensional electron gas (2DEG) under the gate electrode 121 can be suppressed to achieve a normally-off state of the semiconductor device 100. In some embodiments, the material of the doped compound semiconductor layer 114 may be p-type doped or n-type doped gallium nitride (GaN). The step of forming the doped compound semiconductor layer 114 may include forming it at a position corresponding to the predetermined formation of the gate electrode 121 by epitaxial growth and back etching processes.

[0055] In some embodiments, the materials of the source electrode 131 and the drain electrode 141 formed on both sides of the gate electrode 121 can be selected from the materials used to form the gate electrode 121. In addition, the gate electrode 121 and the source electrode 131 and the drain electrode 141 on both sides thereof can be formed in the same process, so they are not described here in detail. In other embodiments, the gate electrode 121 and the source electrode 131 and the drain electrode 141 on both sides thereof can be formed in different processes.

[0056] In some embodiments, the gate metal layer 122, the source contact 133, the source metal layer 132, the drain contact 143, and the drain metal layer 142 may be formed by a deposition process and a patterning process, and the materials thereof include a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminide nitride (TiAlN), metal oxides, metal alloys, other suitable conductive materials, or combinations thereof.

[0057] In some embodiments, the dielectric layers 115 and 116 may include one or more single-layer or multi-layer dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials. The low-k dielectric materials may include, but are not limited to, fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. For example, the dielectric layers 115 and 116 may be formed by spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), other suitable methods or combinations thereof.

[0058] Continue to refer to Figure 2 According to some embodiments of the present invention, the dielectric layer 116 is located between the gate metal layer 122 and the source metal layer 132. The dielectric layer 116 covering the gate metal layer 122 has a dielectric layer portion 116' located directly above the gate metal layer 122 (ie, in the normal direction of the substrate 101). Figure 2 In the cross-sectional view of the semiconductor structure 100 shown in FIG. 1 , the dielectric layer portion 116 ′ located directly above the gate metal layer 122 has two side edges aligned with the gate metal layer 122 . Figure 1 In the top view, the source metal layer 132 has an opening OP1 corresponding to the gate metal layer 122. Figure 2In the cross-sectional view, the source metal layer 132 has an opening OP1 corresponding to the gate metal layer 122, and exposes the dielectric layer portion 116' directly above the gate metal layer 122. In this embodiment, the width W of the gate metal layer 122 (i.e., the width of the dielectric layer portion 116') is smaller than the width D1 of the opening OP1. The opening OP1 does not completely expose the dielectric layer portion 116', and the projections of the source metal layer 132 and the gate metal layer 122 on the substrate 101 are partially overlapped.

[0059] According to some embodiments of the present invention, the coverage of the source field plate (source metal layer 132) to the gate field plate (gate metal layer 122) can be reduced by increasing the size of the opening OP1 (eg, width D1) to reduce the gate-to-source capacitance (C gs ), thereby increasing the switching speed to reduce the switching loss. It is worth noting that the coverage of the source metal layer 132 to the gate metal layer 122 provided in the embodiment of the present invention is only exemplary and can be adjusted according to the actual product design and the required switching speed.

[0060] Please refer to Figure 3 and Figure 4 . Figure 3 FIG. 2 is a partial top view of an exemplary semiconductor structure 300 according to another embodiment of the present invention. Figure 4 is corresponding to Figure 3 It should be understood that in order to concisely describe the embodiment of the present invention and highlight its technical features, the semiconductor structure 300 is not shown in FIG. Figure 4 All elements of the semiconductor structure 300 are shown in FIG. Figure 3 middle.

[0061] Figure 3 , 4 The semiconductor structure 300 is generally similar to Figure 1 , Figure 2 The difference between the semiconductor structures 100 shown respectively is that the source metal layer 332 in the semiconductor structure 300 has an opening OP2 of a larger size.

[0062] like Figure 4In the cross-sectional schematic diagram shown, the width D2 of the opening OP2 of the source metal layer 332 is substantially equal to the width W of the gate metal layer 122 (i.e., the width of the dielectric layer portion 116'). In some embodiments, the opening OP2 completely exposes the dielectric layer portion 116', and the projections of the source metal layer 332 and the gate metal layer 122 on the substrate 101 are aligned. In this embodiment, the two sides of the opening OP2 are substantially aligned with the two sides of the gate metal layer 122. In other embodiments, the width D2 of the opening OP2 of the source metal layer 332 is greater than the width W of the gate metal layer 122 (i.e., the width of the dielectric layer portion 116') (not shown), and the opening OP2 not only completely exposes the dielectric layer portion 116', but also exposes the dielectric layer 116 next to the dielectric layer portion 116', and the projections of the source metal layer 332 and the gate metal layer 122 on the substrate 101 do not overlap at all.

[0063] exist Figure 4 In the embodiment of the present invention, the larger opening OP2 further reduces the coverage of the source field plate (source metal layer 332) relative to the gate field plate (gate metal layer 122), which can further reduce the gate-to-source capacitance (C gs ), thereby increasing the switching speed to reduce switching losses. Figure 3 , Figure 4 The switching speed of the semiconductor structure 300 shown in FIG. Figure 1 , Figure 2 The switching speed of the semiconductor structure 100 shown in FIG.

[0064] Please refer to Figure 5 and Figure 6 . Figure 5 FIG. 2 is a partial top view of an exemplary semiconductor structure 500 according to another embodiment of the present invention. Figure 6 is corresponding to Figure 5 FIG. 5 is a schematic cross-sectional view of a semiconductor structure 500 taken along the line CC'. It should be understood that in order to concisely describe the embodiment of the present invention and highlight its technical features, the Figure 6 All elements of the semiconductor structure 500 are shown in FIG. Figure 5 middle.

[0065] Figure 5 , Figure 6 The semiconductor structure 500 is generally similar to Figure 3 , Figure 4 The semiconductor structure 300 shown has the following differences: Figure 5 , Figure 6The semiconductor structure 500 shown further includes an additional source field plate. Specifically, the semiconductor structure 500 further includes a dielectric layer 616 disposed on the source metal layer 332 and the dielectric layer 116, and a source metal layer 532 disposed on the dielectric layer 616. In some embodiments, the source metal layer 532 can serve as an additional source field plate and is electrically connected to the source electrode 131 and the source metal layer 332 via the source contact 133. The potential of the source metal layers 332 and 532 electrically connected to the source electrode 131 is different from the potential of the gate metal layer 122 electrically connected to the gate electrode 121.

[0066] like Figure 6 As shown, the dielectric layer 616 is located between the source metal layer 332, the dielectric layer 116 and the source metal layer 532, wherein the dielectric layer 616 has a dielectric layer portion 616' located directly above the gate metal layer 122 and the dielectric layer portion 116'. Figure 6 In the cross-sectional view of the semiconductor structure 500 shown in FIG. 1 , the dielectric layer portion 616′ located directly above the gate metal layer 122 and the dielectric layer portion 116′ has two side edges aligned with the gate metal layer 122. In some embodiments, as shown in FIG. Figure 6 As shown, the source metal layer 532 has an opening OP3 located directly above the dielectric layer portion 616' and exposing the dielectric layer portion 616'. In this embodiment, the width W of the gate metal layer 122 (i.e., the width of the dielectric layer portions 116', 616') is greater than the width D3 of the opening OP3. The opening OP3 does not completely expose the dielectric layer portion 616', and the projections of the source metal layer 532 and the gate metal layer 122 on the substrate 101 are partially overlapped.

[0067] In the embodiment of the semiconductor structure with multiple source field plates, in addition to adjusting the coverage of the source field plate (source metal layer 332) relative to the gate field plate (gate metal layer 122), the coverage of each additional source metal layer located directly above the gate metal layer 122 relative to the gate metal layer 122 can also be further adjusted to help reduce the gate-to-source capacitance (C gs ), thereby increasing the switching speed to reduce the switching loss. It is worth noting that although only two source metal layers 332 and 532 with openings are shown in the embodiment of the present invention, the number of source metal layers, the size of the openings included therein, and the coverage of the gate metal layer 122 can be adjusted according to the actual product design and the required switching speed, and the present invention is not limited thereto.

[0068] Figure 7 FIG. 2 is a partial top view of an exemplary semiconductor structure 700 according to some other embodiments of the present invention. Figure 7As shown, the source metal layer 732 included in the semiconductor structure 700 has an opening OP4 located directly above the gate metal layer 122. In this embodiment, the opening OP4 is triangular, and its width varies linearly along the length direction of the opening OP4. Figure 7 In the figure, the section lines D-D', E-E', and F-F' are respectively drawn in the length direction of the opening OP4, wherein the directions of the section lines D-D', E-E', and F-F' are parallel to the flow direction of the electrons. In this embodiment, the section lines D-D', E-E', and F-F' may correspond to the linearly varying widths D4, D5, and D6 of the opening OP4, respectively. Figure 7 In FIG. 1 , the widths D4, D5, and D6 are all smaller than the width W of the gate metal layer 122, and the width D4 is larger than the width D5, and the width D5 is larger than the width D6. Figure 7 In the illustrated embodiment, the configuration of the opening of the source metal layer can be adjusted according to product design and required switching speed, so that the coverage of the source field plate to the gate field plate varies in different cross-sections of different electron flow directions in the semiconductor structure.

[0069] Furthermore, depending on product characteristics, the source field plate (source metal layer) may have two or more openings of different sizes and / or shapes located directly above the gate field plate (gate metal layer) (e.g. Figure 8 , Fig. 9 As shown in FIG. 1 , the coverage of the source field plate to the gate field plate varies in cross sections of different electron flow directions in the semiconductor structure. Figure 8 FIG. 8 is a partial top view of an exemplary semiconductor structure 800 according to some other embodiments of the present invention. Figure 8 As shown, the source metal layer 832 included in the semiconductor structure 800 has openings OP5 and OP6 located directly above the gate metal layer 122. In this embodiment, the openings OP5 and OP6 are trapezoids with different sizes. In some embodiments, the opening OP5 has a maximum width D7 and a minimum width D8, wherein the maximum width D7 and the minimum width D8 are both greater than the width W of the gate metal layer 122. In some embodiments, the opening OP6 has a maximum width D9 and a minimum width D10, wherein the maximum width D9 is greater than the width W of the gate metal layer 122, and the minimum width D10 is less than the width W of the gate metal layer 122.

[0070] Fig. 9 FIG. 8 is a partial top view of an exemplary semiconductor structure 900 according to some other embodiments of the present invention. Fig. 9As shown, the source metal layer 932 included in the semiconductor structure 900 has openings OP7 and OP8 located directly above the gate metal layer 122. In this embodiment, the openings OP7 and OP8 are ellipses with different sizes. In some embodiments, the short axis length D11 of the opening OP7 is greater than the width W of the gate metal layer 122. In some embodiments, the short axis length D12 of the opening OP8 is less than the width W of the gate metal layer 122.

[0071] It is worth noting that in the semiconductor structure provided in the embodiment of the present invention, the number, size, and shape of the openings located directly above the gate metal layer contained in the source metal layer are not limited to the above-mentioned embodiments. For example, various polygonal (such as pentagonal, hexagonal, or octagonal, etc.), circular, or openings with irregular arc profiles can also be applied to the semiconductor structure provided in the embodiment of the present invention. According to the actual product design and the required switching speed, the number, size, and shape of the openings described in the above different embodiments can be integrated into a single semiconductor structure to adjust the coverage of the source metal layer serving as the source field plate to the gate metal layer serving as the gate field plate.

[0072] In summary, the semiconductor structure provided by the embodiment of the present invention can reduce the risk of the gate structure being subjected to high electric fields by means of the gate field plate, and optimize the electric field distribution and reduce the gate-to-drain capacitance (C gd ), and the coverage of the source field plate to the gate field plate can be adjusted by forming an opening in the source metal layer to reduce the gate-to-source capacitance (C gs ), thereby achieving the purpose of reducing switching loss. Therefore, the semiconductor structure provided by the embodiment of the present invention has a breakdown voltage and a gate-to-drain capacitance (C gd ) can effectively reduce switching losses and thus improve the performance of the semiconductor structure.

[0073] The above summarizes a plurality of embodiments so that those skilled in the art can better understand the concepts of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: a substrate; A gate structure, disposed on the substrate, comprises: a gate electrode disposed on the substrate; and a gate metal layer electrically connected to the gate electrode and serving as a gate field plate; and A source structure and a drain structure are disposed on the substrate and located on both sides of the gate structure, wherein the source structure includes: a source electrode disposed on the substrate; a first source metal layer, electrically connected to the source electrode and extending along a direction from the gate electrode to the drain structure; a first dielectric layer disposed on the gate metal layer; The potential of the first source metal layer is different from that of the gate metal layer, and the first source metal layer at least exposes a portion of the first dielectric layer directly above the gate metal layer; a second dielectric layer disposed on the first source metal layer and the first dielectric layer; and A second source metal layer is electrically connected to the source electrode and is disposed on the second dielectric layer, wherein the second source metal layer at least exposes a portion of the second dielectric layer located directly above the gate metal layer.

2. The semiconductor structure according to claim 1, wherein: The first source metal layer completely exposes the first dielectric layer located directly above the gate metal layer.

3. The semiconductor structure according to claim 1, wherein: The source structure also includes: A plurality of source contacts, wherein the source electrode, the first source metal layer, and the second source metal layer are electrically connected to each other via the plurality of source contacts.

4. The semiconductor structure according to claim 1, wherein: Also included is a compound semiconductor layer disposed on the substrate, wherein the compound semiconductor layer includes: a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer, wherein the source structure and the drain structure are in contact with the channel layer via the source electrode and a drain electrode respectively; and A barrier layer is disposed on the channel layer.

5. The semiconductor structure according to claim 4, characterized in that The invention also comprises a doped compound semiconductor layer, wherein the doped compound semiconductor layer is located between the gate electrode and the barrier layer.

6. A semiconductor structure, characterized in that: include: a substrate; A gate structure, disposed on the substrate, comprises: a gate electrode disposed on the substrate; and a gate metal layer electrically connected to the gate electrode and serving as a gate field plate; A source structure, disposed on the substrate, comprises: a source electrode disposed on the substrate; a first source metal layer electrically connected to the source electrode and serving as a source field plate, wherein the potential of the first source metal layer is different from the potential of the gate metal layer, wherein in a top view, the first source metal layer has an opening located directly above the gate metal layer; a second source metal layer, electrically connected to the source electrode and disposed on the first source metal layer, wherein the second source metal layer has an opening located directly above the gate metal layer; and A plurality of dielectric layers are respectively disposed between the gate metal layer, the first source metal layer, and the second source metal layer; and A drain structure is disposed on the substrate.

7. The semiconductor structure according to claim 6, wherein: The width of the opening varies linearly along the length direction of the opening.

8. The semiconductor structure according to claim 6, wherein: The opening has a first width and a second width, wherein the first width is smaller than the width of the gate metal layer, and the first width is not equal to the second width.

9. The semiconductor structure according to claim 8, characterized in that The second width is smaller than the width of the gate metal layer.

10. The semiconductor structure according to claim 8, wherein: The second width is greater than a width of the gate metal layer.

11. The semiconductor structure according to claim 6, wherein: The opening has a minimum width and a maximum width, wherein the minimum width and the maximum width are both greater than the width of the gate metal layer.

12. The semiconductor structure according to claim 6, wherein: The opening is rectangular.

13. The semiconductor structure according to claim 6, wherein: The opening has an arc-shaped profile.

14. The semiconductor structure according to claim 6, wherein: The source structure also includes: A plurality of source contacts, wherein the source electrode, the first source metal layer, and the second source metal layer are electrically connected to each other via the plurality of source contacts.

15. The semiconductor structure according to claim 6, wherein: Also included is a compound semiconductor layer disposed on the substrate, wherein the compound semiconductor layer includes: a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer, wherein the source structure and the drain structure are in contact with the channel layer via the source electrode and a drain electrode respectively; and A barrier layer is disposed on the channel layer.

16. The semiconductor structure according to claim 15, wherein: The invention also comprises a doped compound semiconductor layer, wherein the doped compound semiconductor layer is located between the gate electrode and the barrier layer.

Images