A lightly doped substrate, a substrate with a selective emitter, a solar cell, and a preparation method and application thereof

Abstract

The present invention provides a lightly doped substrate, a substrate with a selective emitter, a solar cell and a preparation method and application thereof. The lightly doped substrate comprises a P-type silicon wafer layer, an N-type silicon layer, a first phosphorus silicon glass layer, an oxide layer and a second phosphorus silicon glass layer which are connected in sequence. In the subsequent heavy doping process, the lightly doped substrate of the present invention can increase the doping uniformity of the doping source on the surface of the silicon wafer on the one hand, and can reduce the square resistance of the heavily doped area on the other hand, thereby reducing the silver silicon contact resistance. The preparation method of the lightly doped substrate is simple, easy to implement and suitable for large-scale industrial production and application. The heavily doped area in the substrate with a selective emitter prepared by the lightly doped substrate has a high phosphorus content, a low and uniform square resistance of the heavily doped area, and a high light conversion efficiency.

Description

Technical Field

[0001] The invention belongs to the field of solar cells and relates to a lightly doped substrate, a substrate with a selective emitter, a solar cell and a preparation method and application thereof. Background Art

[0002] Laser doped selective emitter (LDSE) uses a laser beam to selectively irradiate the silicon surface, causing the silicon substrate to become molten. The doped atoms can quickly enter the molten silicon. When the laser beam disappears, the molten silicon cools and crystallizes, and the doped atoms enter the silicon crystal to form a heavily doped area.

[0003] Before LDSE doping, the first diffusion is performed, and the diffused phosphosilicate glass layer is the source of LDSE doping. At present, in order to ensure the efficiency of the battery, the sheet resistance of the first diffusion is relatively high, the thickness of the phosphosilicate glass layer is relatively low, and the phosphorus content is not high. As a result, during the LDSE process, the sheet resistance of the doped area is prone to unevenness, and the doping sheet resistance cannot be very low.

[0004] CN107394012A discloses a diffusion process of laser doped SE in silicon wafers. The process is to form a diffusion first phosphorus layer and a diffusion second phosphorus layer on the surface of the silicon wafer, and then add a phosphorus layer deposition process to form a phosphorus layer on the silicon surface after diffusion. The phosphorus layer not only solves the problem of insufficient PSG concentration after laser ablation, but also the phosphorus layer is easily removed in the subsequent phosphorus washing process, which can effectively solve the problem of poor ohmic contact and low filling factor caused by low PSG concentration during laser doping. However, the energy during laser doping is high, and there is no oxide layer buffer layer in the middle, which will lead to uneven doping square resistance. And the diffused second phosphorus layer may damage the doped phosphorus layer in subsequent processing, thereby affecting the uniformity of the square resistance of the doping area.

[0005] CN106206847A discloses an ultra-low concentration POCl based on a low-pressure diffusion furnace 3 The high-temperature diffusion method includes the following steps: (1) entering the boat; (2) phosphorus deposition; (3) heating up and pushing the knot; (4) cooling down and oxidizing; (5) leaving the boat; in a low-pressure environment of 50-100 mBar, low-temperature deposition and high-temperature distribution without oxygen are used to achieve ultra-low POCl 3 Concentration of phosphorus diffusion, POCl 3 The concentration is only 10% of that of the conventional process. This diffusion method can significantly increase the open circuit voltage of the battery cell and reduce the amount of carrier gas used, thereby ensuring the uniformity and stability of the square resistance. However, the uniformity and stability of the square resistance still need to be improved.

[0006] CN102945797A discloses a low-temperature, low-surface-concentration, high-square-resistance diffusion process, including a boat entry step, a deposition step, a propulsion step, and a boat exit step, wherein the reaction temperatures of the boat entry step and the deposition step are both lower than 800 degrees Celsius. Preferably, at least one of the deposition step and the propulsion step is performed in steps according to different temperatures. Further, the deposition step is divided into a first deposition step and a second deposition step; the propulsion step includes a first propulsion step and a second propulsion step. Preferably, there is an oxidation step between the boat entry step and the deposition step, and the oxidation step includes introducing oxygen into the reaction vessel. The low-temperature, low-surface-concentration, high-square-resistance diffusion process described in the invention reduces the reaction temperature in the deposition and diffusion steps relative to the traditional process, thereby reducing the surface recombination rate. At the same time, the lower diffusion temperature during the polysilicon diffusion process makes it more conducive for impurities to migrate toward the impurity absorption point, thereby improving the battery efficiency, but its battery efficiency still needs to be improved.

[0007] Therefore, it is very necessary to develop a lightly doped substrate that can subsequently increase the uniformity of the square resistance of the heavily doped region and reduce the square resistance of the heavily doped region to improve the light conversion efficiency of the solar cell. Summary of the invention

[0008] The object of the present invention is to provide a lightly doped substrate, a substrate with a selective emitter, a solar cell and a preparation method and application thereof; the lightly doped substrate can, when used in a subsequent heavy doping process, increase the doping uniformity of a doping source on the surface of a silicon wafer on the one hand, and reduce the square resistance of a heavily doped region on the other hand, thereby reducing the silver-silicon contact resistance; the preparation method of the lightly doped substrate is simple, easy to implement and suitable for large-scale industrial production and application; the substrate with a selective emitter prepared from the lightly doped substrate has a high phosphorus content in the heavily doped region, and the square resistance of the heavily doped region is low and uniform; the solar cell prepared from the substrate with a selective emitter has a high light conversion efficiency.

[0009] To achieve this object, the present invention adopts the following technical solutions:

[0010] One of the purposes of the present invention is to provide a lightly doped substrate, which includes a P-type silicon layer, an N-type silicon layer, a first phosphosilicate glass layer, an oxide layer and a second phosphosilicate glass layer connected in sequence.

[0011] In the present invention, the lightly doped substrate includes a P-type silicon wafer layer, an N-type silicon layer, a first phosphosilicate glass layer, an oxide layer and a second phosphosilicate glass layer which are connected in sequence. This is to increase the doping uniformity of the doping source on the surface of the silicon wafer during the subsequent heavy doping process, and to reduce the square resistance of the heavily doped area on the other hand, thereby reducing the silver silicon contact resistance.

[0012] In the subsequent heavy doping process, a laser beam is used to selectively irradiate the substrate surface to make the P-type silicon layer molten, and the doped atoms in the first phosphosilicate glass layer can quickly enter the molten silicon. When the laser beam disappears, the molten silicon cools and crystallizes, and the doped atoms enter the silicon crystal to form an N-type silicon layer. However, the thickness of the first phosphosilicate glass layer is relatively low and the phosphorus content is not high. In addition, the phosphorus atoms will move in all directions and are difficult to control. Therefore, it is easy to cause the problem of uneven square resistance and high square resistance in the heavily doped area. By setting an oxide layer and a second phosphosilicate glass layer on the surface of the first phosphosilicate glass layer, The second phosphosilicate glass layer has a higher phosphorus content, which can increase the phosphorus content in the heavily doped area, thereby reducing the square resistance of the heavily doped area; the oxide layer is located between the first phosphosilicate glass layer and the second phosphosilicate glass layer, and phosphorus atoms must pass through the oxide layer when diffusing. The diffusion rate of phosphorus atoms will be relatively consistent when penetrating the oxide layer, thereby increasing the uniformity of diffusion, that is, increasing the uniformity of square resistance, that is, the oxide layer plays a buffering role, alleviating the diffusion of phosphorus atoms, making the diffusion square resistance more uniform, and the oxide layer and the second phosphosilicate glass layer are easily removed in the subsequent etching process, and will not affect the square resistance of the light receiving area.

[0013] In the present invention, the thickness of the P-type silicon wafer layer is 160±20μm, for example, 140μm, 142μm, 145μm, 148μm, 150μm, 152μm, 155μm, 158μm, 160μm, 162μm, 165μm, 168μm, 170μm, 172μm, 175μm, 178μm, 180μm, etc.

[0014] In the present invention, the thickness of the N-type silicon layer is 0.3±0.2μm, for example, 0.1μm, 0.12μm, 0.15μm, 0.17μm, 0.2μm, 0.22μm, 0.25μm, 0.27μm, 0.3μm, 0.32μm, 0.35μm, 0.37μm, 0.4μm, 0.42μm, 0.45μm, 0.47μm, 0.5μm, etc.

[0015] In the present invention, the thickness of the first phosphosilicate glass layer is 20±10nm, such as 10nm, 12nm, 15nm, 17nm, 20nm, 22nm, 25nm, 27nm, 30nm, etc. When the thickness of the first phosphosilicate glass layer is less than 10nm, the square resistance of the light receiving area is too large, which easily causes abnormal silver-silicon contact; when the thickness of the first phosphosilicate glass layer is greater than 30nm, the square resistance of the light receiving area is too small, affecting the photoelectric response and causing low battery efficiency.

[0016] In the present invention, the phosphorus content in the first phosphosilicate glass layer is (5-7)×10e 20 cm -3 , for example 5×10e20 cm -3 , 5.2×10e 20 cm -3 , 5.5×10e 20 cm -3 , 5.7×10e 20 cm -3 , 6×10e 20 cm -3 、6.2×10e 20 cm -3 , 6.5×10e 20 cm -3 , 6.7×10e 20 cm -3 , 7×10e 20 cm -3 When the phosphorus content in the first phosphosilicate glass layer is higher than 7×10e 20 cm -3 , the doping amount is too much, the minority carrier recombination is serious, the photoelectric response is affected, and the efficiency is low; when the phosphorus content in the first phosphosilicate glass layer is lower than 5×10e 20 cm -3 , then the doping amount is too little, the silver-silicon contact is poor, resulting in a large contact resistance and affecting battery performance.

[0017] In the present invention, the thickness of the oxide layer is 40±20nm, such as 20nm, 22nm, 25nm, 28nm, 30nm, 32nm, 35nm, 38nm, 40nm, 42nm, 45nm, 48nm, 50nm, 52nm, 55nm, 58nm, 60nm, etc. When the thickness of the oxide layer is less than 20nm, it is easy to cause over-doping during laser doping, resulting in too small square resistance of the doped area, affecting the photoelectric response and causing low efficiency; when the thickness of the oxide layer is higher than 60nm, it is easy to make it difficult for phosphorus atoms to penetrate the oxide layer during laser doping, resulting in too large square resistance of the doped area and poor silver-silicon contact.

[0018] In the present invention, the oxide layer is a silicon oxide layer.

[0019] In the present invention, the thickness of the second phosphosilicate glass layer is 20±10nm, such as 10nm, 12nm, 15nm, 18nm, 20nm, 22nm, 25nm, 28nm, 30nm, etc. When the thickness of the second phosphosilicate glass layer is less than 10nm, the phosphorus content is too low, the laser doping is too little, and the silver-silicon contact is affected; when the thickness of the second phosphosilicate glass layer is higher than 30nm, it is easy to cause excessive doping during laser doping, resulting in too small square resistance of the doped region, affecting the photoelectric response and causing low efficiency.

[0020] In the present invention, the content of phosphorus in the second phosphosilicate glass layer is (7-9)×10e 20 cm -3 , for example 7×10e 20 cm -3 、7.2×10e 20 cm -3 , 7.5×10e 20 cm -3 , 7.7×10e 20 cm -3 , 8×10e 20 cm -3 , 8.2×10e 20 cm -3 , 8.5×10e 20 cm -3 , 8.7×10e 20 cm -3 , 9×10e 20 cm -3 When the phosphorus content in the second phosphosilicate glass layer is lower than 7×10e 20 cm -3 , the doping amount is too little, the silver-silicon contact is poor, resulting in large contact resistance and affecting battery performance; when the phosphorus content in the second phosphorus-silicon glass layer is higher than 9×10e 20 cm -3 , then the doping amount is too much, the minority carrier recombination is serious, the photoelectric response is affected, and the efficiency is low.

[0021] In the present invention, the second phosphorus silicon glass layer, as the outermost layer, can provide a large number of phosphorus atoms as the source of laser doped phosphorus atoms, and can make the square resistance of laser heavy doping uniform, and can also significantly reduce the square resistance of the laser heavy doping area and reduce the silver silicon contact resistance; and it can be easily removed in the subsequent etching process and will not affect the square resistance of the light receiving area.

[0022] A second object of the present invention is to provide a method for preparing a lightly doped substrate as described in the first object, the method for preparing the lightly doped substrate comprising:

[0023] (1) performing a first through-source deposition on the pretreated P-type silicon wafer layer to obtain a P-type silicon wafer layer having a first phosphorus-silicate glass layer on its surface;

[0024] (2) performing a push-joint treatment on the P-type silicon wafer layer having the first phosphosilicate glass layer on the surface obtained in step (1) to obtain a P-type silicon wafer layer having the N-type silicon layer and the first phosphosilicate glass layer on the surface in sequence;

[0025] (3) subjecting the P-type silicon wafer layer obtained in step (2) whose surface is sequentially covered with an N-type silicon layer and a first phosphosilicate glass layer to an oxidation annealing treatment to obtain a P-type silicon wafer layer whose surface is sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer and an oxide layer;

[0026] (4) subjecting the P-type silicon wafer layer obtained in step (3) whose surface is sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, and a P-type silicon wafer layer covered with an oxide layer to a second through-source deposition to obtain the lightly doped substrate.

[0027] The preparation method of the lightly doped substrate of the present invention is simple, low-cost, high-yield, easy to implement, and suitable for industrial large-scale production applications.

[0028] In the present invention, the temperature of the first source deposition in step (1) is 790±20°C, for example, 770°C, 772°C, 775°C, 777°C, 780°C, 782°C, 785°C, 787°C, 790°C, 792°C, 795°C, 797°C, 800°C, 802°C, 805°C, 807°C, 810°C, etc.

[0029] In the present invention, the first source deposition in step (1) is performed while simultaneously introducing nitrogen gas with a flow rate of 1000±200sccm (e.g., 800sccm, 820sccm, 850sccm, 870sccm, 900sccm, 920sccm, 950sccm, 970sccm, 1000sccm, 1020sccm, 1050sccm, 1070sccm, 1100sccm, 1120sccm, 1150sccm, 1170sccm, 1200sccm, etc.), 500±100sccm (e.g., 400sccm, 420sccm, 450sccm, It is carried out under the conditions of 470sccm, 500sccm, 520sccm, 550sccm, 570sccm, 600sccm, etc.) of oxygen and 1000±200sccm (for example, 800sccm, 820sccm, 850sccm, 870sccm, 900sccm, 920sccm, 950sccm, 970sccm, 1000sccm, 1020sccm, 1050sccm, 1070sccm, 1100sccm, 1120sccm, 1150sccm, 1170sccm, 1200sccm, etc.) of nitrogen carrying a doping source.

[0030] In the present invention, the doping source is phosphorus oxychloride.

[0031] In the present invention, the time of the first through-source deposition in step (1) is 1000±200s, such as 800s, 820s, 850s, 870s, 900s, 920s, 950s, 970s, 1000s, 1020s, 1050s, 1070s, 1100s, 1120s, 1150s, 1170s, 1200s, etc. If the through-source deposition time is less than 800s, the thickness of the deposited first phosphorus silicon glass layer is low and cannot provide sufficient phosphorus content for laser doping; if the through-source deposition time is more than 1200s, it will cause heavy doping to be formed in places where heavy doping is not required, thereby affecting the conversion efficiency of the solar cell.

[0032] In the present invention, the pre-treated P-type silicon wafer layer in step (1) is obtained by sequentially subjecting the P-type silicon wafer layer to a boat treatment and a temperature treatment.

[0033] In the present invention, the temperature of the boat treatment is 790±20℃, for example, 770℃, 772℃, 775℃, 777℃, 780℃, 782℃, 785℃, 787℃, 790℃, 792℃, 795℃, 797℃, 800℃, 802℃, 805℃, 807℃, 810℃, etc.

[0034] In the present invention, the boat entry treatment is carried out in nitrogen with a flow rate of 1000±200sccm (for example, 800sccm, 820sccm, 850sccm, 870sccm, 900sccm, 920sccm, 950sccm, 970sccm, 1000sccm, 1020sccm, 1050sccm, 1070sccm, 1100sccm, 1120sccm, 1150sccm, 1170sccm, 1200sccm, etc.).

[0035] In the present invention, the time for the boat treatment is 800±100s, for example, 700s, 720s, 750s, 780s, 800s, 820s, 850s, 870s, 900s, etc.

[0036] In the present invention, the P-type silicon wafer layer is further subjected to texturing treatment before being subjected to the boat treatment.

[0037] In the present invention, many nanometer-scale structures are formed by texturing the surface of the P-type silicon wafer layer, so that the incident light can be reflected and refracted multiple times on the silicon surface, thereby improving the short-circuit voltage and conversion efficiency of the battery.

[0038] In the present invention, the temperature of the temperature rising treatment is 790±20℃, for example, 770℃, 772℃, 775℃, 777℃, 780℃, 782℃, 785℃, 787℃, 790℃, 792℃, 795℃, 797℃, 800℃, 802℃, 805℃, 807℃, 810℃, etc.

[0039] In the present invention, the temperature increase treatment is carried out in nitrogen with a flow rate of 1000±200sccm (for example, 800sccm, 820sccm, 850sccm, 870sccm, 900sccm, 920sccm, 950sccm, 970sccm, 1000sccm, 1020sccm, 1050sccm, 1070sccm, 1100sccm, 1120sccm, 1150sccm, 1170sccm, 1200sccm, etc.).

[0040] In the present invention, the time of the temperature rising treatment is 400±100s, for example, 300s, 320s, 350s, 370s, 400s, 420s, 450s, 470s, 500s, etc.

[0041] In the present invention, the temperature of the pushing treatment in step (2) is 830±20°C, for example, 810°C, 812°C, 815°C, 817°C, 820°C, 822°C, 825°C, 827°C, 830°C, 832°C, 835°C, 837°C, 840°C, 842°C, 845°C, 847°C, 850°C, etc.

[0042] In the present invention, the push-junction treatment in step (2) is carried out in nitrogen with a flow rate of 1000±200sccm (for example, 800sccm, 820sccm, 850sccm, 870sccm, 900sccm, 920sccm, 950sccm, 970sccm, 1000sccm, 1020sccm, 1050sccm, 1070sccm, 1100sccm, 1120sccm, 1150sccm, 1170sccm, 1200sccm, etc.).

[0043] In the present invention, the time for the knot pushing treatment in step (2) is 800±100s, for example, 700s, 720s, 750s, 770s, 800s, 820s, 850s, 870s, 900s, etc.

[0044] In the present invention, the temperature of the oxidation annealing treatment in step (3) is 720±20°C, for example, 700°C, 702°C, 705°C, 707°C, 710°C, 712°C, 715°C, 717°C, 720°C, 722°C, 725°C, 727°C, 730°C, 732°C, 735°C, 737°C, 740°C, etc.

[0045] In the present invention, the oxidation annealing treatment in step (3) is carried out while a flow rate of 1000±200sccm (e.g., 800sccm, 820sccm, 850sccm, 870sccm, 900sccm, 920sccm, 950sccm, 970sccm, 1000sccm, 1020sccm, 1050sccm, 1070sccm, 1100sccm, 1120sccm, 1150sccm, 1170sccm, 1200sccm) is introduced. The reaction is carried out under the conditions of 2000±200sccm (for example, 1800sccm, 1820sccm, 1850sccm, 1870sccm, 1900sccm, 1920sccm, 1950sccm, 1970sccm, 2000sccm, 2020sccm, 2050sccm, 2070sccm, 2100sccm, 2120sccm, 2150sccm, 2170sccm, 2200sccm, etc.) of nitrogen and 2000±200sccm of oxygen.

[0046] In the present invention, the time of the oxidation annealing treatment in step (3) is 1200±100s, for example, 1100s, 1120s, 1150s, 1170s, 1200s, 1230s, 1250s, 1270s, 1300s, etc.

[0047] In the present invention, the temperature of the second source deposition in step (4) is 790±20°C, for example, 770°C, 772°C, 775°C, 777°C, 780°C, 782°C, 785°C, 787°C, 790°C, 792°C, 795°C, 797°C, 800°C, 802°C, 805°C, 807°C, 810°C, etc.

[0048] In the present invention, the second source deposition in step (4) is performed while simultaneously introducing nitrogen with a flow rate of 2000±400sccm (for example, 1600sccm, 1650sccm, 1700sccm, 1750sccm, 1800sccm, 1850sccm, 1900sccm, 1950sccm, 2000sccm, 2050sccm, 2100sccm, 2150sccm, 2200sccm, 2250sccm, 2300sccm, 2350sccm, 2400sccm, etc.), nitrogen with a flow rate of 1000±200sccm (for example, 800sccm, 820sccm, 850sccm, 870sccm, 900sccm, 920sccm, 950sccm, 970sccm, etc.), and nitrogen with a flow rate of 1000±200sccm (for example, 800sccm, 820sccm, 850sccm, 870sccm, 900sccm, 920sccm, 950sccm, 970sccm, etc.). The reaction is carried out under the conditions of 2000±400sccm (for example, 1600sccm, 1650sccm, 1700sccm, 1750sccm, 1800sccm, 1850sccm, 1900sccm, 1950sccm, 2000sccm, 2050sccm, 2100sccm, 2150sccm, 2200sccm, 2250sccm, 2300sccm, 2350sccm, 2400sccm, etc.) of oxygen and 2000±400sccm (for example, 1600sccm, 1650sccm, 1700sccm, 1750sccm, 1800sccm, 1850sccm, 1900sccm, 1950sccm, 2000sccm, 2050sccm, 2100sccm, 2150sccm, 2200sccm, 2250sccm, 2300sccm, 2350sccm, 2400sccm, etc.) of nitrogen carrying a doping source.

[0049] In the present invention, the doping source is phosphorus oxychloride.

[0050] In the present invention, the time for the second source deposition in step (4) is 2000±400s, for example, 1600s, 1650s, 1700s, 1750s, 1800s, 1850s, 1900s, 1950s, 2000s, 2050s, 2100s, 2150s, 2200s, 2250s, 2300s, 2350s, 2400s, etc.

[0051] In the present invention, the step (4) further includes unloading the preform of the P-type silicon wafer layer obtained after the second through-source deposition, the surface of which is sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, an oxide layer and a second phosphosilicate glass layer.

[0052] In the present invention, the temperature of the boat-out treatment is 720±20°C, for example, 700°C, 705°C, 710°C, 715°C, 720°C, 725°C, 730°C, 735°C, 740°C, etc.

[0053] In the present invention, the boat exit treatment is carried out in nitrogen with a flow rate of 1000±200sccm (for example, 800sccm, 820sccm, 850sccm, 870sccm, 900sccm, 920sccm, 950sccm, 970sccm, 1000sccm, 1020sccm, 1050sccm, 1070sccm, 1100sccm, 1120sccm, 1150sccm, 1170sccm, 1200sccm, etc.).

[0054] In the present invention, the time for the boat unloading treatment is 800±100s, for example, 700s, 720s, 750s, 770s, 800s, 820s, 850s, 870s, 900s, etc.

[0055] As a preferred technical solution of the present invention, the method for preparing the lightly doped substrate comprises the following steps:

[0056] A. Pre-texture the P-type silicon wafer layer to obtain a textured P-type silicon wafer layer, and then put the textured P-type silicon wafer layer into a quartz boat, and enter the diffusion furnace for boat processing at a temperature of 790±20°C and a nitrogen flow rate of 1000±200sccm. The time for the boat processing is 800±100s to obtain a boat-loaded silicon wafer;

[0057] B. Under the conditions of a temperature of 790±20° C. and a nitrogen gas flow rate of 1000±200sccm, the silicon wafer after entering the boat obtained in step A is subjected to a temperature increase treatment for a temperature increase time of 400±100s to obtain a temperature-increased silicon wafer;

[0058] C. At a temperature of 790±20° C., while introducing nitrogen gas with a flow rate of 1000±200sccm, oxygen gas with a flow rate of 500±100sccm, and nitrogen gas carrying phosphorus oxychloride with a flow rate of 1000±200sccm, the silicon wafer obtained in step B after heating is subjected to the first source deposition for a deposition time of 1000±200s to obtain a P-type silicon wafer layer having a first phosphorus silicon glass layer on the surface;

[0059] D. Under the conditions of a temperature of 830±20° C. and a nitrogen gas flow rate of 1000±200 sccm, the P-type silicon wafer layer with the first phosphosilicate glass layer on the surface obtained in step C is subjected to an oxidation push-up treatment for a time of 800±100 s to obtain a P-type silicon wafer layer with the N-type silicon layer and the first phosphosilicate glass layer on the surface in sequence;

[0060] E. Under the condition of a temperature of 720±20° C. and a nitrogen gas with a flow rate of 1000±200sccm and an oxygen gas with a flow rate of 2000±200sccm, annealing the P-type silicon wafer layer having the N-type silicon layer and the first phosphosilicate glass layer sequentially covered on the surface obtained in step D for an annealing time of 1200±200s to obtain a P-type silicon wafer layer having the N-type silicon layer, the first phosphosilicate glass layer and the oxide layer sequentially covered on the surface;

[0061] F. At a temperature of 720±20° C., while introducing nitrogen gas at a flow rate of 2000±400sccm, oxygen gas at a flow rate of 1000±200sccm, and nitrogen gas carrying phosphorus oxychloride at a flow rate of 2000±400sccm, the P-type silicon wafer layer whose surface is sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, and an oxide layer obtained in step E is subjected to a second source deposition for a deposition time of 2000±400s to obtain a preform of a P-type silicon wafer layer whose surface is sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, an oxide layer, and a second phosphosilicate glass layer;

[0062] G. Under the conditions of a temperature of 720±20°C and a nitrogen gas flow rate of 1000±200sccm, the quartz boat containing the preformed P-type silicon wafer layer obtained in step F, whose surface is sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, an oxide layer and a second phosphosilicate glass layer, is taken out of the boat for 800±100s to obtain the lightly doped substrate.

[0063] A third object of the present invention is to provide a method for preparing a substrate with a selective emitter from a lightly doped substrate as described in the first object, the method comprising the following steps:

[0064] (1) heavily doping the non-light-receiving region of the lightly doped substrate with laser to obtain a heavily doped substrate in the non-light-receiving region;

[0065] (2) Etching and cleaning the heavily doped substrate in the non-light-receiving area obtained in step (1) to remove the oxide layer and the second phosphosilicate glass layer, thereby obtaining a substrate with a selective emitter.

[0066] In the process of preparing the substrate with the selective emitter, the oxide layer and the second phosphorus silicon glass layer are removed by etching and cleaning, which will not affect the square resistance of the light receiving area of ​​the substrate with the selective emitter.

[0067] In the present invention, the doping power of the laser heavy doping in step (1) is 25±10 W, for example, 15 W, 18 W, 20 W, 22 W, 25 W, 28 W, 30 W, 32 W, 35 W, etc.

[0068] In the present invention, the doping speed of the laser heavy doping in step (1) is 20±10 m / s, for example, 10 m / s, 12 m / s, 15 m / s, 18 m / s, 20 m / s, 22 m / s, 25 m / s, 28 m / s, 30 m / s, etc.

[0069] In the present invention, the doping frequency of the laser heavy doping in step (1) is 200±100 KHz, for example, 100 KHz, 120 KHz, 150 KHz, 170 KHz, 200 KHz, 220 KHz, 250 KHz, 280 KHz, 300 KHz, etc.

[0070] The fourth object of the present invention is to provide a substrate with a selective emitter prepared by the preparation method as described in the third object.

[0071] The fifth object of the present invention is to provide a solar cell, which includes a substrate with a selective emitter as described in the fourth object.

[0072] In the present invention, the method for preparing the solar cell comprises: depositing, laser grooving and printing and sintering a substrate with a selective emitter in sequence.

[0073] In the present invention, the solar cells include single-sided solar cells and double-sided solar cells.

[0074] The sixth object of the present invention is to provide an application of the solar cell as described in the fifth object as an energy cell in a solar AC power generation device.

[0075] Compared with the prior art, the present invention has the following beneficial effects:

[0076] The lightly doped substrate of the present invention can, in the subsequent heavy doping process, increase the doping uniformity of the doping source on the surface of the silicon wafer on the one hand, and reduce the square resistance of the heavily doped area on the other hand, thereby reducing the silver-silicon contact resistance; the preparation method of the lightly doped substrate is simple, easy to implement, and suitable for large-scale industrial production applications; the phosphorus content in the heavily doped area of ​​the substrate with a selective emitter prepared by the lightly doped substrate is relatively high, so the square resistance of the heavily doped area is relatively low and uniform; the solar cell prepared by the substrate with a selective emitter has a relatively high light conversion efficiency (the light conversion efficiency is as high as 20.92%). BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 is a schematic diagram of a lightly doped substrate in Example 1 of the present invention;

[0078] Among them, 1 is a P-type silicon layer, 2 is an N-type silicon layer, 3 is a first phosphosilicate glass layer, 4 is an oxide layer, and 5 is a second phosphosilicate glass layer. DETAILED DESCRIPTION

[0079] The technical solution of the present invention is further described below by specific implementation methods. It should be understood by those skilled in the art that the embodiments are only to help understand the present invention and should not be regarded as specific limitations of the present invention.

[0080] Example 1

[0081] This embodiment provides a lightly doped substrate such as Figure 1 As shown, the lightly doped substrate includes a P-type silicon layer 1, an N-type silicon layer 2, a first phosphosilicate glass layer 3, an oxide layer 4, and a second phosphosilicate glass layer 5 connected in sequence, wherein the thickness of the P-type silicon layer 1 is 160 μm, the thickness of the N-type silicon layer 2 is 0.3 μm, the thickness of the first phosphosilicate glass layer 3 is 20 nm, and the phosphorus content in the first phosphosilicate glass layer 3 is 6×10e 20 cm -3 , the thickness of the oxide layer 4 is 40 nm, the thickness of the second phosphosilicate glass layer 5 is 20 nm, and the phosphorus content in the second phosphosilicate glass layer 5 is 8×10e 20 cm -3 .

[0082] This embodiment also provides a method for preparing a lightly doped substrate, the method comprising the following steps:

[0083] A. Boat entry: Pre-texture the P-type silicon wafer layer to obtain the textured silicon wafer, and then put the textured silicon wafer into a quartz boat, and enter the diffusion furnace for boat entry treatment at a temperature of 790°C and a nitrogen flow rate of 1000sccm. The boat entry time is 800s to obtain the P-type silicon wafer layer after boat entry;

[0084] B. Heating: After the furnace door is closed, the furnace tube is heated to 790° C., and the silicon wafer after entering the boat obtained in step A is heated under the condition of a nitrogen flow rate of 1000 sccm. The heating time is 400 s to obtain a heated P-type silicon wafer layer;

[0085] C. First source deposition: At a temperature of 790° C., while introducing nitrogen gas with a flow rate of 1000 sccm, oxygen gas with a flow rate of 500 sccm, and nitrogen gas carrying phosphorus oxychloride with a flow rate of 1000 sccm, the P-type silicon wafer layer obtained after the temperature increase in step B is subjected to the first source deposition for a deposition time of 1000 s to obtain a P-type silicon wafer layer with a first phosphosilicate glass layer deposited on the surface;

[0086] D. Pushing: Under the conditions of a temperature of 830° C. and a nitrogen gas flow rate of 1000 sccm, the P-type silicon wafer layer with the first phosphosilicate glass layer deposited on the surface obtained in step C is subjected to a push-up treatment for 800 seconds to obtain a P-type silicon wafer layer with the N-type silicon layer and the first phosphosilicate glass layer sequentially covered on the surface;

[0087] E. Oxidation: Under the condition of a temperature of 720° C. and a nitrogen gas with a flow rate of 1000 sccm and an oxygen gas with a flow rate of 2000 sccm, an oxidation annealing treatment is performed on the P-type silicon wafer layer having an N-type silicon layer and a first phosphosilicate glass layer sequentially covered on the surface obtained in step D. The oxidation annealing time is 1200 s, thereby obtaining a P-type silicon wafer layer having an N-type silicon layer, a first phosphosilicate glass layer and an oxide layer sequentially covered on the surface;

[0088] F. Second source deposition: at a temperature of 720° C., while introducing nitrogen gas with a flow rate of 2000 sccm, oxygen gas with a flow rate of 1000 sccm, and nitrogen gas carrying phosphorus oxychloride with a flow rate of 2000 sccm, the P-type silicon wafer layer with a surface sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, and an oxide layer obtained in step E is subjected to a second source deposition for a deposition time of 2000 s to obtain a preform of a P-type silicon wafer layer with a surface sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, an oxide layer, and a second phosphosilicate glass layer;

[0089] G. Boat unloading: Under the conditions of a temperature of 720° C. and a nitrogen gas flow rate of 1000 sccm, the quartz boat containing the preformed P-type silicon wafer layer obtained in step F, whose surface is sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, an oxide layer, and a second phosphosilicate glass layer, is unloaded from the boat for 800 seconds to obtain the lightly doped substrate.

[0090] This embodiment also provides a method for preparing a substrate with a selective emitter, the method comprising the following steps:

[0091] (1) The non-light-receiving region of the lightly doped substrate is heavily doped with laser, the laser heavy doping power is 25 W, the doping speed is 20 m / s, and the doping frequency is 200 kHz, to obtain a substrate with heavily doped non-light-receiving region;

[0092] (2) Etching and cleaning the heavily doped substrate in the non-light-receiving area obtained in step (1) to remove the oxide layer and the second phosphosilicate glass layer, thereby obtaining a substrate with a selective emitter.

[0093] Example 2

[0094] The present embodiment provides a lightly doped substrate, which includes a P-type silicon layer, an N-type silicon layer, a first phosphosilicate glass layer, an oxide layer, and a second phosphosilicate glass layer connected in sequence, wherein the thickness of the P-type silicon layer is 180 μm, the thickness of the N-type silicon layer is 0.1 μm, the thickness of the first phosphosilicate glass layer is 30 nm, and the phosphorus content in the first phosphosilicate glass layer is 5×10e 20 cm -3 The thickness of the oxide layer is 20 nm, the thickness of the second phosphosilicate glass layer is 10 nm, and the phosphorus content in the second phosphosilicate glass layer is 7×10e 20 cm-3 .

[0095] This embodiment also provides a method for preparing a lightly doped substrate, the method comprising the following steps:

[0096] A. Boat entry: Pre-texture the P-type silicon wafer layer to obtain the textured silicon wafer, and then put the textured silicon wafer into a quartz boat, and enter the diffusion furnace for boat entry treatment at a temperature of 770°C and a nitrogen flow rate of 1200sccm. The boat entry time is 700s to obtain the P-type silicon wafer layer after boat entry;

[0097] B. Heating: After the furnace door is closed, the furnace tube is heated to 770° C., and the silicon wafer after entering the boat obtained in step A is heated under the condition of a nitrogen gas flow rate of 1200 sccm. The heating time is 500 s to obtain a heated P-type silicon wafer layer;

[0098] C. First source deposition: At a temperature of 770° C., while introducing nitrogen gas with a flow rate of 1200 sccm, oxygen gas with a flow rate of 600 sccm, and nitrogen gas carrying phosphorus oxychloride with a flow rate of 1200 sccm, the P-type silicon wafer layer obtained after the temperature increase in step B is subjected to the first source deposition for a deposition time of 800 s to obtain a P-type silicon wafer layer with a first phosphosilicate glass layer deposited on the surface;

[0099] D. Pushing: Under the conditions of a temperature of 850° C. and a nitrogen gas flow rate of 1200 sccm, the P-type silicon wafer layer with the first phosphosilicate glass layer deposited on the surface obtained in step C is subjected to a push-up treatment for 700 seconds to obtain a P-type silicon wafer layer with the N-type silicon layer and the first phosphosilicate glass layer sequentially covered on the surface;

[0100] E. Oxidation: At a temperature of 740° C., while introducing nitrogen gas with a flow rate of 1200 sccm and oxygen gas with a flow rate of 2200 sccm, the P-type silicon wafer layer having the surface sequentially covered with the N-type silicon layer and the first phosphosilicate glass layer obtained in step D is subjected to oxidation annealing treatment for 1000 s to obtain a P-type silicon wafer layer having the surface sequentially covered with the N-type silicon layer, the first phosphosilicate glass layer and the oxide layer;

[0101] F. Second source deposition: at a temperature of 740° C., while introducing nitrogen gas with a flow rate of 1600 sccm, oxygen gas with a flow rate of 800 sccm, and nitrogen gas carrying phosphorus oxychloride with a flow rate of 1600 sccm, the P-type silicon wafer layer with a surface sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, and an oxide layer obtained in step E is subjected to a second source deposition for a deposition time of 2400 s to obtain a preform of a P-type silicon wafer layer with a surface sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, an oxide layer, and a second phosphosilicate glass layer;

[0102] G. Boat unloading: Under the conditions of a temperature of 740°C and a nitrogen gas flow rate of 1200 sccm, the quartz boat containing the preformed P-type silicon wafer layer obtained in step F, whose surface is sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, an oxide layer, and a second phosphosilicate glass layer, is unloaded from the boat for 900 seconds to obtain the lightly doped substrate.

[0103] This embodiment also provides a method for preparing a substrate with a selective emitter, the method comprising the following steps:

[0104] (1) performing laser heavy doping on the non-light-receiving region of the lightly doped substrate, wherein the laser heavy doping power is 15 W, the doping speed is 10 m / s, and the doping frequency is 100 kHz, to obtain a substrate with heavy doping on the non-light-receiving region;

[0105] (2) Etching and cleaning the heavily doped substrate in the non-light-receiving area obtained in step (1) to remove the oxide layer and the second phosphosilicate glass layer, thereby obtaining a substrate with a selective emitter.

[0106] Example 3

[0107] The present embodiment provides a lightly doped substrate, which includes a P-type silicon layer, an N-type silicon layer, a first phosphosilicate glass layer, an oxide layer, and a second phosphosilicate glass layer connected in sequence, wherein the thickness of the P-type silicon layer is 140 μm, the thickness of the N-type silicon layer is 0.5 μm, the thickness of the first phosphosilicate glass layer is 10 nm, and the phosphorus content in the first phosphosilicate glass layer is 7×10e 20 cm -3 The thickness of the oxide layer is 60 nm, the thickness of the second phosphosilicate glass layer is 30 nm, and the phosphorus content in the second phosphosilicate glass layer is 9×10e 20 cm -3 .

[0108] This embodiment also provides a method for preparing a lightly doped substrate, the method comprising the following steps:

[0109] A. Boat entry: Pre-texture the P-type silicon wafer layer to obtain the textured silicon wafer, and then put the textured silicon wafer into a quartz boat, and enter the diffusion furnace for boat entry treatment at a temperature of 810°C and a nitrogen flow rate of 800sccm. The boat entry time is 900s to obtain the P-type silicon wafer layer after boat entry;

[0110] B. Heating: After the furnace door is closed, the furnace tube is heated to 810° C., and the silicon wafer after entering the boat obtained in step A is heated under the condition of a nitrogen flow rate of 800 sccm. The heating time is 300 seconds to obtain a heated P-type silicon wafer layer;

[0111] C. First source deposition: At a temperature of 810° C., while introducing 800 sccm of nitrogen, 400 sccm of oxygen and 800 sccm of nitrogen carrying phosphorus oxychloride, the heated P-type silicon wafer layer obtained in step B is subjected to first source deposition for 1200 s to obtain a P-type silicon wafer layer with a first phosphosilicate glass layer deposited on the surface;

[0112] D. Pushing: Under the conditions of a temperature of 810° C. and a nitrogen gas flow rate of 800 sccm, the P-type silicon wafer layer with the first phosphosilicate glass layer deposited on the surface obtained in step C is subjected to a push-up treatment for 900 seconds to obtain a P-type silicon wafer layer with the N-type silicon layer and the first phosphosilicate glass layer sequentially covered on the surface;

[0113] E. Oxidation: Under the condition of a temperature of 700° C. and a nitrogen gas with a flow rate of 800 sccm and an oxygen gas with a flow rate of 1800 sccm, an oxidation annealing treatment is performed on the P-type silicon wafer layer having the N-type silicon layer and the first phosphosilicate glass layer sequentially covered on the surface obtained in step D. The oxidation annealing time is 1400 s, thereby obtaining a P-type silicon wafer layer having the N-type silicon layer, the first phosphosilicate glass layer and the oxide layer sequentially covered on the surface;

[0114] F. Second source deposition: at a temperature of 700° C., while introducing nitrogen gas with a flow rate of 2400 sccm, oxygen gas with a flow rate of 1200 sccm, and nitrogen gas carrying phosphorus oxychloride with a flow rate of 2400 sccm, the P-type silicon wafer layer obtained in step E, whose surface is sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, and an oxide layer, is subjected to a second source deposition for a deposition time of 1600 s, to obtain a preform of a P-type silicon wafer layer whose surface is sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, an oxide layer, and a second phosphosilicate glass layer;

[0115] G. Boat exit: Under the conditions of a temperature of 700° C. and a nitrogen gas flow rate of 800 sccm, the quartz boat containing the preformed P-type silicon wafer layer obtained in step F, whose surface is sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, an oxide layer, and a second phosphosilicate glass layer, is processed for 700 s to obtain the lightly doped substrate.

[0116] This embodiment also provides a method for preparing a substrate with a selective emitter, the method comprising the following steps:

[0117] (1) The non-light-receiving region of the lightly doped substrate is heavily doped with laser, the laser heavy doping power is 35 W, the doping speed is 30 m / s, and the doping frequency is 300 kHz, to obtain a substrate with heavily doped non-light-receiving region;

[0118] (2) Etching and cleaning the heavily doped substrate in the non-light-receiving area obtained in step (1) to remove the oxide layer and the second phosphosilicate glass layer, thereby obtaining a substrate with a selective emitter.

[0119] Example 4

[0120] The only difference from Example 1 is that the thickness of the first phosphosilicate glass layer is 5 nm, and the rest of the composition and preparation method are the same as those in Example 1.

[0121] Example 5

[0122] The only difference from Example 1 is that the thickness of the first phosphosilicate glass layer is 40 nm, and the rest of the composition and preparation method are the same as those of Example 1.

[0123] Example 6

[0124] The only difference from Example 1 is that the thickness of the oxide layer is 10 nm, and the rest of the composition and preparation method are the same as those of Example 1.

[0125] Example 7

[0126] The only difference from Example 1 is that the thickness of the oxide layer is 80 nm, and the rest of the composition and preparation method are the same as those of Example 1.

[0127] Example 8

[0128] The only difference from Example 1 is that the thickness of the second phosphosilicate glass layer is 5 nm, and the rest of the composition and preparation method are the same as those in Example 1.

[0129] Example 9

[0130] The only difference from Example 1 is that the thickness of the second phosphosilicate glass layer is 40 nm, and the rest of the composition and preparation method are the same as those in Example 1.

[0131] Example 10

[0132] The only difference from Example 1 is that the phosphorus content in the first phosphosilicate glass layer is 3×10e 20 cm -3 The rest of the composition and preparation method are the same as those in Example 1.

[0133] Embodiment 11

[0134] The only difference from Example 1 is that the phosphorus content in the first phosphosilicate glass layer is 9×10e 20 cm -3 The rest of the composition and preparation method are the same as those in Example 1.

[0135] Example 12

[0136] The only difference from Example 1 is that the phosphorus content in the second phosphosilicate glass layer is 5×10e 20 cm -3 The rest of the composition and preparation method are the same as those in Example 1.

[0137] Example 13

[0138] The only difference from Example 1 is that the phosphorus content in the second phosphosilicate glass layer is 11×10e 20 cm -3 The rest of the composition and preparation method are the same as those in Example 1.

[0139] Comparative Example 1

[0140] The only difference from Example 1 is that the lightly doped substrate does not include the second phosphosilicate glass layer, and the rest of the composition and preparation method are the same as those of Example 1.

[0141] Comparative Example 2

[0142] The only difference from Example 1 is that the lightly doped substrate does not include an oxide layer, and the rest of the composition and preparation method are the same as those of Example 1.

[0143] Comparative Example 3

[0144] The only difference from Example 1 is that the lightly doped substrate does not include the first phosphosilicate glass layer, and the rest of the composition and preparation method are the same as those of Example 1.

[0145] Comparative Example 4

[0146] The only difference from Example 1 is that the second phosphosilicate glass layer in the lightly doped substrate is located between the first phosphosilicate glass layer and the oxide layer, and the rest of the composition and preparation method are the same as those in Example 1.

[0147] Comparative Example 5

[0148] The only difference from Example 1 is that the positions of the first glass phosphosilicate layer and the second phosphosilicate glass layer in the lightly doped substrate are interchanged, and the rest of the composition and preparation method are the same as those in Example 1.

[0149] Comparative Example 6

[0150] The only difference from Example 1 is that the first phosphosilicate glass layer in the lightly doped substrate is located between the oxide layer and the second phosphosilicate glass layer, and the rest of the composition and preparation method are the same as those in Example 1.

[0151] The substrates with selective emitters obtained in Examples 1-13 and Comparative Examples 1-6 were used to prepare solar cells. The preparation method is exemplarily as follows:

[0152] (1) depositing an aluminum oxide film layer on the back of a substrate with a selective emitter by a vapor deposition method to obtain a substrate with an aluminum oxide film layer deposited thereon, wherein the thickness of the aluminum oxide film layer is 10 nm;

[0153] (2) depositing silicon nitride on both sides of the substrate with the aluminum oxide film layer obtained in step (1) by vapor deposition to obtain a substrate with a silicon nitride film layer, wherein the thickness of the silicon nitride film layer is 85 nm and the refractive index is 2.05;

[0154] (3) laser grooving the substrate with the silicon nitride film layer deposited thereon obtained in step (2) to obtain a substrate with laser grooves, wherein the size of the grooves is 20 μm and the depth of the grooves is 4 μm;

[0155] (4) Screen-printing the front electrode and the back electrode on the laser-grooved substrate obtained in step (3), and then sintering the substrate at a temperature of 780° C. for 20 seconds to obtain a solar cell.

[0156] The obtained solar cell was subjected to performance test, and the test results are shown in Table 1:

[0157] Table 1

[0158]

[0159] In Table 1:

[0160] The voltage (V), current (A) and fill factor (%) are the corresponding voltage, current and fill factor given in Table 1; the battery area is 245.67 square centimeters; the voltage (V) and current (A) are the voltage and current generated by the battery under 1000W light intensity irradiation, the model of the test machine used is German Halm-2400, and the model of the test software is 18-KW05; the fill factor is the ratio of the maximum output power of the battery to the product of the short-circuit current and the open-circuit voltage.

[0161] It can be seen from Table 1 that the solar cell prepared by the present invention has a high light conversion efficiency. It can be seen from the comparison between Example 1 and Examples 4-5 that when the thickness of the first phosphosilicate glass layer is too low, the silver silicon contact resistance is too large, resulting in a large series resistance and a low fill factor. When the thickness of the phosphosilicate glass layer is too high, the photoelectric response is affected, resulting in low voltage and current. It can be seen from the comparison between Example 1 and Examples 6-7 that when the thickness of the oxide layer is too low, excessive doping is caused, affecting the photoelectric response, resulting in low current and voltage. When the thickness of the oxide layer is too high, the doping amount is too small, resulting in a large series resistance. It can be seen from the comparison between Example 1 and Examples 8-9 that when the thickness of the second phosphosilicate glass layer is too low, When the thickness of the second phosphosilicate glass layer is too high, the doping amount is too much, which affects the photoelectric response and causes the voltage and current to be low. From the comparison between Example 1 and Examples 10-11, it can be seen that when the phosphorus content in the first phosphosilicate glass layer is too low, the contact resistance is too large, causing the series resistance to be large and the filling factor to be low. When the phosphorus content in the first phosphosilicate glass layer is too high, the photoelectric response is affected, causing the voltage and current to be low. From the comparison between Example 1 and Examples 12-13, it can be seen that when the phosphorus content in the second phosphosilicate glass layer is too low, the contact resistance is too large, causing the series resistance to be large and the filling factor to be low. When the phosphorus content in the glass layer is too high, the photoelectric response is affected, resulting in low voltage and current; from the comparison between Example 1 and Comparative Example 1, it can be seen that when the lightly doped substrate does not include the second phosphosilicate glass layer, the contact resistance is very large, the filling factor is seriously low, and the battery efficiency is seriously low; from the comparison between Example 1 and Comparative Example 2, it can be seen that when the lightly doped substrate does not include the oxide layer, the doping amount is excessive, and the voltage and current are seriously low; from the comparison between Example 1 and Comparative Example 3, it can be seen that when the lightly doped substrate does not include the first phosphosilicate glass layer, the silver-silicon contact of the battery is abnormal, the battery is an inefficient product, and the product is defective; from the comparison between Example 1 and Comparative Example 4, it can be seen that when the second phosphosilicate glass layer is located between the first phosphosilicate glass layer, the battery is not in good condition, and the battery is not in good condition. Since there is no buffer of the oxide layer in between the glass layer and the oxide layer, it will lead to excessive doping, low current and voltage; from the comparison between Example 1 and Comparative Example 5, it can be seen that when the positions of the first phosphosilicate glass layer and the second phosphosilicate glass layer are interchanged, there is a problem that the phosphorus content of the first phosphosilicate glass layer is high, while the phosphorus content of the second phosphosilicate glass layer is low, which may cause the final doping effect to be not very good, affecting the conversion efficiency of the battery; from the comparison between Example 1 and Comparative Example 6, it can be seen that since the oxide layer is under the two phosphosilicate glass layers, the buffering effect of the oxide layer is more obvious, which is easy to cause the square resistance after doping to be large, affecting the silver-silicon contact of the battery, resulting in low battery efficiency; therefore, the solar cell prepared by the present invention has a higher light conversion efficiency.

[0162] The applicant declares that the above is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention shall fall within the protection scope and disclosure scope of the present invention.

Claims

1. A lightly doped substrate, characterized in that: The lightly doped substrate comprises a P-type silicon layer, an N-type silicon layer, a first phosphosilicate glass layer, an oxide layer and a second phosphosilicate glass layer connected in sequence; The thickness of the first phosphosilicate glass layer is 20±10 nm; The phosphorus content in the first phosphosilicate glass layer is (5-7)×10e 20 cm -3 ; The thickness of the second phosphosilicon glass layer is 20±10 nm; The phosphorus content in the second phosphosilicate glass layer is (7-9)×10e 20 cm -3 ; The thickness of the oxide layer is 40±20 nm.

2. The lightly doped substrate according to claim 1, characterized in that: The thickness of the P-type silicon wafer layer is 160±20 μm.

3. The lightly doped substrate according to claim 1, characterized in that: The thickness of the N-type silicon layer is 0.3±0.2 μm.

4. The lightly doped substrate according to claim 1, characterized in that: The oxide layer is a silicon oxide layer.

5. The method for preparing a lightly doped substrate according to any one of claims 1 to 4, characterized in that: The method for preparing the lightly doped substrate comprises: (1) performing a first through-source deposition on the pretreated P-type silicon wafer layer to obtain a P-type silicon wafer layer having a first phosphorus-silicate glass layer on its surface; (2) performing a push-joint treatment on the P-type silicon wafer layer having the first phosphosilicate glass layer on the surface obtained in step (1) to obtain a P-type silicon wafer layer having the N-type silicon layer and the first phosphosilicate glass layer on the surface in sequence; (3) subjecting the P-type silicon wafer layer obtained in step (2) whose surface is sequentially covered with an N-type silicon layer and a first phosphosilicate glass layer to an oxidation annealing treatment to obtain a P-type silicon wafer layer whose surface is sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer and an oxide layer; (4) subjecting the P-type silicon wafer layer obtained in step (3) whose surface is sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, and a P-type silicon wafer layer covered with an oxide layer to a second through-source deposition to obtain the lightly doped substrate.

6. The preparation method according to claim 5, characterized in that: The temperature of the first through-source deposition in step (1) is 790±20°C.

7. The preparation method according to claim 5, characterized in that: The first source deposition in step (1) is carried out under the condition of simultaneously introducing nitrogen gas with a flow rate of 1000±200sccm, oxygen gas with a flow rate of 500±100sccm, and nitrogen gas carrying a doping source with a flow rate of 1000±200sccm.

8. The preparation method according to claim 7, characterized in that: The doping source is phosphorus oxychloride.

9. The preparation method according to claim 5, characterized in that: The time for the first source deposition in step (1) is 1000±200s.

10. The preparation method according to claim 5, characterized in that: The pre-treated P-type silicon wafer layer in step (1) is obtained by sequentially subjecting the P-type silicon wafer layer to a boat treatment and a temperature treatment.

11. The preparation method according to claim 10, characterized in that: The temperature of the boat processing is 790±20°C.

12. The preparation method according to claim 10, characterized in that: The boat entry process is performed in a nitrogen gas with a flow rate of 1000±200 sccm.

13. The preparation method according to claim 10, characterized in that: The time for the boat processing is 800±100s.

14. The preparation method according to claim 10, characterized in that: The P-type silicon wafer layer also includes a texturing process before the P-type silicon wafer layer is put into the boat process.

15. The preparation method according to claim 10, characterized in that: The temperature of the heating treatment is 790±20°C.

16. The preparation method according to claim 10, characterized in that: The temperature increase treatment is performed in a nitrogen gas with a flow rate of 1000±200sccm.

17. The preparation method according to claim 10, characterized in that: The time of the temperature rising treatment is 400±100s.

18. The preparation method according to claim 5, characterized in that: The temperature of the pushing treatment in step (2) is 830±20°C.

19. The preparation method according to claim 5, characterized in that: The push-knot treatment in step (2) is carried out in nitrogen gas at a flow rate of 1000±200sccm.

20. The preparation method according to claim 5, characterized in that: The time for the knot pushing treatment in step (2) is 800±100s.

21. The preparation method according to claim 5, characterized in that: The temperature of the oxidation annealing treatment in step (3) is 720±20°C.

22. The preparation method according to claim 5, characterized in that: The oxidation annealing treatment in step (3) is carried out under the condition of simultaneously introducing nitrogen gas at a flow rate of 1000±200sccm and oxygen gas at a flow rate of 2000±200sccm.

23. The preparation method according to claim 5, characterized in that: The time of the oxidation annealing treatment in step (3) is 1200±100s.

24. The preparation method according to claim 5, characterized in that: The temperature of the second through-source deposition in step (4) is 790±20°C.

25. The preparation method according to claim 5, characterized in that: The second source deposition in step (4) is carried out under the condition of simultaneously introducing nitrogen gas with a flow rate of 2000±400sccm, oxygen gas with a flow rate of 1000±200sccm and nitrogen gas carrying a doping source with a flow rate of 2000±400sccm.

26. The preparation method according to claim 25, characterized in that: The doping source is phosphorus oxychloride.

27. The preparation method according to claim 5, characterized in that: The time of the second source deposition in step (4) is 2000±400s.

28. The preparation method according to claim 5, characterized in that: The step (4) further includes taking out of the boat the preform of the P-type silicon wafer layer obtained after the second through-source deposition, the surface of which is sequentially covered with the N-type silicon layer, the first phosphosilicate glass layer, the oxide layer and the second phosphosilicate glass layer.

29. The preparation method according to claim 28, characterized in that: The temperature of the boat discharge treatment is 720±20°C.

30. The preparation method according to claim 28, characterized in that: The boat-out process is performed in nitrogen gas with a flow rate of 1000±200 sccm.

31. The preparation method according to claim 28, characterized in that: The time for the boat unloading treatment is 800±100s.

32. The preparation method according to claim 5, characterized in that: The method for preparing the lightly doped substrate comprises the following steps: A. Pre-texture the P-type silicon wafer layer to obtain a textured P-type silicon wafer layer, and then put the textured P-type silicon wafer layer into a quartz boat, and enter the diffusion furnace for boat processing at a temperature of 790±20°C and a nitrogen flow rate of 1000±200sccm. The time of the boat processing is 800±100s to obtain a silicon wafer after the boat processing; B. Under the conditions of a temperature of 790±20° C. and a nitrogen gas flow rate of 1000±200sccm, the silicon wafer after entering the boat obtained in step A is subjected to a temperature-raising treatment for a heating time of 400±100s to obtain a silicon wafer after the temperature-raising treatment; C. At a temperature of 790±20° C., while introducing nitrogen gas with a flow rate of 1000±200sccm, oxygen gas with a flow rate of 500±100sccm, and nitrogen gas carrying phosphorus oxychloride with a flow rate of 1000±200sccm, the silicon wafer obtained in step B after heating is subjected to the first source deposition for a deposition time of 1000±200s to obtain a P-type silicon wafer layer having a first phosphorus silicon glass layer on the surface; D. Under the conditions of a temperature of 830±20° C. and a nitrogen gas flow rate of 1000±200 sccm, the P-type silicon wafer layer with the first phosphosilicate glass layer on the surface obtained in step C is subjected to an oxidation push-up treatment for a time of 800±100 s to obtain a P-type silicon wafer layer with the N-type silicon layer and the first phosphosilicate glass layer on the surface in sequence; E. Under the condition of a temperature of 720±20° C. and a nitrogen gas with a flow rate of 1000±200sccm and an oxygen gas with a flow rate of 2000±200sccm, annealing the P-type silicon wafer layer having the N-type silicon layer and the first phosphosilicate glass layer sequentially covered on the surface obtained in step D for an annealing time of 1200±200s to obtain a P-type silicon wafer layer having the N-type silicon layer, the first phosphosilicate glass layer and the oxide layer sequentially covered on the surface; F. At a temperature of 720±20° C., while introducing nitrogen gas at a flow rate of 2000±400sccm, oxygen gas at a flow rate of 1000±200sccm, and nitrogen gas carrying phosphorus oxychloride at a flow rate of 2000±400sccm, the P-type silicon wafer layer whose surface is sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, and an oxide layer obtained in step E is subjected to a second source deposition for a deposition time of 2000±400s to obtain a preform of a P-type silicon wafer layer whose surface is sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, an oxide layer, and a second phosphosilicate glass layer; G. Under the conditions of a temperature of 720±20°C and a nitrogen gas flow rate of 1000±200sccm, the quartz boat containing the preformed P-type silicon wafer layer obtained in step F, whose surface is sequentially covered with an N-type silicon layer, a first phosphosilicate glass layer, an oxide layer and a second phosphosilicate glass layer, is taken out of the boat for 800±100s to obtain the lightly doped substrate.

33. A method for preparing a substrate with a selective emitter from the lightly doped substrate according to any one of claims 1 to 4, characterized in that: The method comprises the following steps: (1) heavily doping the non-light-receiving region of the lightly doped substrate with laser to obtain a heavily doped substrate in the non-light-receiving region; (2) Etching and cleaning the heavily doped substrate in the non-light-receiving area obtained in step (1) to remove the oxide layer and the second phosphosilicate glass layer, thereby obtaining a substrate with a selective emitter.

34. The method for preparing a substrate with a selective emitter from a lightly doped substrate according to claim 33, characterized in that: The doping power of the laser heavy doping in step (1) is 25±10W.

35. The method for preparing a substrate with a selective emitter from a lightly doped substrate according to claim 33, characterized in that: The doping speed of the laser heavy doping in step (1) is 20±10m / s.

36. The method for preparing a substrate with a selective emitter from a lightly doped substrate according to claim 33, characterized in that: The doping frequency of the laser heavy doping in step (1) is 200±100KHz.

37. A substrate with a selective emitter prepared according to the method according to any one of claims 34 to 36.

38. A solar cell, characterized in that: The solar cell comprises the substrate with a selective emitter as claimed in claim 37.

39. The solar cell according to claim 38, characterized in that The solar cells include single-sided solar cells and double-sided solar cells.

40. Use of the solar cell as claimed in claim 38 or 39 as an energy cell in a solar AC power generation device.

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