Circuits and methods

Abstract

The present application relates to circuits and methods. A circuit includes a transaction interface to receive data processing transactions from an upstream device, a translation circuit to access a set of address mappings between virtual memory addresses and physical memory addresses in a physical memory address space, and a control circuit to receive a memory region request from the upstream device requesting a memory region including a target virtual memory address in a virtual memory address space to be made available, initiate processing of the memory region request, and provide a response to the upstream device in accordance with the processing of the memory region request.

Description

Technical Field

[0001] The present disclosure relates to a circuit and a method. Background Art

[0002] In some circuit embodiments that use memory address translation, the device's translation can be configured so that when a translation failure occurs, the failed transaction will be paused so that software (such as an operating system) can decide how to handle it. This resolution process can be automatically initiated by the memory management unit and is invisible to the paused device. The memory management unit can then be waited for until the transaction is retried or aborted.

[0003] However, the suspend fault may lead to deadlock in some cases. As a result, general-purpose operating systems (such as Linux) generally cannot enable the suspend fault in any device (if it causes deadlock).

[0004] Another system that handles these problems is to use the ATS (Address Translation Service) and PRI (Page Request Interface) features of the PCIe (Peripheral Component Interconnect Express) protocol. Under ATS, memory address translations are obtained before a transaction is issued and are cached at the transaction initiating device or endpoint. If a translation failure occurs in response to an ATS request, the endpoint is expected (but not required) to issue a PRI request. When the memory management unit receives the PRI request, it notifies software, such as the operating system. For example, if a memory page that was previously swapped out caused a fault, the operating system can swap it in again so that the transaction can continue. The memory management unit notifies the endpoint when it receives a response from the software, and if the PRI request is successful, the endpoint is expected (but not required) to retry the ATS request.

[0005] Pause and ATS are separately enabled features and cannot be enabled at the same time. Summary of the Invention

[0006] In one example arrangement, a circuit is provided, comprising:

[0007] a transaction interface for receiving a data processing transaction from an upstream device, the data processing transaction defining a target virtual memory address in a virtual memory address space;

[0008] a translation circuit for accessing a set of address mappings between virtual memory addresses and physical memory addresses in a physical memory address space;

[0009] the conversion circuit is configured to initiate processing of the data processing transaction by a downstream device from a target physical memory address mapped from the target virtual memory address when the set of address mappings includes an address mapping for the target virtual memory address, and to provide a transaction response to the transaction interface indicating a fault condition when the set of address mappings fails to provide an address mapping for the target virtual memory address; and

[0010] control circuitry to receive a memory region request from the upstream device requesting availability of a memory region in a virtual memory address space including the target virtual memory address, initiate processing of the memory region request, and provide a response to the upstream device in dependence on the processing of the memory region request.

[0011] In another example arrangement, there is provided a circuit comprising:

[0012] a transaction interface to communicate a data processing transaction to a downstream device, the data processing transaction defining a target virtual memory address in a virtual memory address space, and to receive a transaction response indicating completion or a fault condition of the data processing transaction when conversion of the target virtual memory address to a target physical memory address fails;

[0013] control circuitry to issue a memory region request to the downstream device requesting availability of a memory region in a virtual memory address space including the target virtual memory address, and to receive a memory region request response from the downstream device;

[0014] the control circuitry is configured to selectively reissue the data processing transaction in dependence on the memory region request response received from the downstream device.

[0015] In another example arrangement, there is provided a method comprising:

[0016] receiving a data processing transaction from an upstream device, the data processing transaction defining a target virtual memory address in a virtual memory address space;

[0017] accessing a set of address mappings between virtual memory addresses and physical memory addresses in a physical memory address space;

[0018] initiating processing of the data processing transaction by a downstream device from a target physical memory address mapped from the target virtual memory address when the set of address mappings accessed by the accessing step includes an address mapping for the target virtual memory address;

[0019] providing a transaction response indicating a failure condition when the set of address mappings accessed by the accessing step fails to provide an address mapping for the target virtual memory address; and

[0020] In response to receiving a memory region request from the upstream device requesting that a memory region in a virtual memory address space including the target virtual memory address be made available, processing of the memory region request is initiated and a response is provided based on the processing of the memory region request.

[0021] In another exemplary arrangement, a method is provided, the method comprising:

[0022] transmitting a data processing transaction to a downstream device, the data processing transaction defining a target virtual memory address in a virtual memory address space;

[0023] When translation of the target virtual memory address to the target physical memory address fails, receiving a transaction response indicating completion or a failure condition of the data processing transaction;

[0024] issuing a memory region request to the downstream device requesting that a memory region in a virtual memory address space including the target virtual memory address be made available;

[0025] receiving a memory region request response from the downstream device; and

[0026] The data processing transaction is selectively reissued based on a memory region request response received from the downstream device.

[0027] Further aspects and features of the present disclosure are defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The present technology will now be further described, by way of example only, with reference to embodiments of the invention as shown in the accompanying drawings, in which:

[0029] Figure 1 schematically illustrates a circuit operating in accordance with the so-called Peripheral Component Interconnect Express (PCIe) arrangement;

[0030] Figure 2 is a schematic flow chart illustrating a method;

[0031] Figure 3 and Figure 4 is a schematic timing diagram;

[0032] Figure 5 The circuit of the example is schematically shown;

[0033] Figure 6 is a schematic flow chart illustrating an address conversion method;

[0034] Figure 7 and Figure 8 is a schematic timing diagram; and

[0035] Figure 9 and Figure 10 is a schematic flow chart illustrating each method. DETAILED DESCRIPTION

[0036] Referring now to the accompanying drawings, Figure 1 A schematic diagram illustrates circuitry operating in accordance with the so-called Peripheral Component Interconnect Express (PCIe) arrangement. In the depicted PCIe embodiment, a so-called endpoint 100 interacts with a peripheral device, such as memory 110, for example, reading data from or writing data to memory 110. The endpoint operates based on virtual addresses (VAs), while ultimately interacting with memory 110 is based on physical addresses (PAs). Therefore, in order to execute a data transaction initiated by endpoint 100, the VA must be converted to the PA.

[0037] The PCIe functionality discussed here (compared to the previously proposed Figure 1 PCIe circuits or use some PCIe functions Figure 5 ) relates to the PCIe standard from Gen 4.0 onwards (i.e., higher), as defined by the standard published at https: / / pcisig.com / specifications, the contents of which are incorporated herein by reference.

[0038] exist Figure 1 In the previously proposed arrangement, this translation is performed by the endpoint 100 itself, because before the endpoint 100 issues a data processing transaction that depends on the VA, the endpoint 100 obtains the required address translation from, for example, the memory management unit or system memory management unit (SMMU) 120 and stores the address translation in the address translation cache (ATC) 130. Therefore, it should be noted that Figure 1 In the embodiment of the present invention, it is assumed that ATS is enabled and PRI is enabled (as later combined with Figure 4 described), and therefore pausing is not enabled.

[0039] This operation is performed to pre-populate ATC 130 with the required translations before issuing data processing transactions (as a so-called "Address Translation Service" (ATS) operation). This means that data processing transactions issued by endpoint 100 have their addresses translated into the required PA using information stored in ATC 130.

[0040] like Figure 1As shown, endpoint 100 communicates with SMMU 120 via a so-called root port 140, which has a first interface 142 for conducting data processing transactions with the SMMU itself and a second interface 144 for performing ATS requests and page requests (discussed below). SMMU 120 communicates with memory 110, for example, via interconnect 150, to which other devices (such as a processing element or CPU 160) can be connected.

[0041] Figure 2 Schematically shows Figure 1 In terms of the operation of the circuit, where a translation is required in VA 200 and before a transaction is issued using that VA, VA 200 is first provided as an ATS request from endpoint 100 to SMMU 120. If the required address translation is available at step 210, it is returned to endpoint 100 and stored in ATC 130.

[0042] However, it may be the case that the required translation is not available. For example, if there is a translation failure, then in step 230, endpoint 100 uses interface 144 (which may be referred to as a page request interface or PRI in this context) to make a so-called page request. A page request is a request to the software to make available a memory page or region containing the required VA. The software may be, for example, an operating system (OS) running on CPU 160 and providing a configuration to the memory system, including translation tables and support information for SMMU 120. This "making available" process may include, for example, populating translation information at SMMU 120 and / or providing permission data to enable access to the required page.

[0043] If the required page is made available at step 240, then the translation request of endpoint 100 may be retried, causing control to transfer back to step 210. If not, then the process terminates with a failure condition.

[0044] Figure 3 3 is a schematic timing diagram illustrating the above-described operations, wherein, at step 300, endpoint 100 issues an ATS translation request to SMMU 120. Assuming the request can be serviced immediately, either by looking up in a translation lookaside buffer (TLB) or performing an operation in memory, such as a page table walk (PTW), SMMU 120 replies at stage 310 with a response containing the desired translation stored by endpoint 100 in ATC 130.

[0045] Endpoint 100 may then publish the associated data processing transformation at step 320 with the VA having been transformed into the PA.

[0046] exist Figure 4In the example of FIG10 , a translation request is again issued at stage 400, but in this case, the SMMU 120 cannot service the translation request and provides a negative response 410. This negative response prompts the endpoint 100 to issue a page request 420 to the SMMU. The SMMU responds by issuing a PRI "event" 430 to software 440, such as an operating system running on CPU 160. To prompt software 440 to process the PRI event, the SMMU may also issue an interrupt request associated with PRI event 430 to CPU 160.

[0047] Software 440 processes the PRI event and provides a PRI reply command 450 to SMMU 120, which instructs SMMU 120 to issue a PRI response 460 to endpoint 100. If the PRI response 460 is positive, indicating that the requested page is now available ( Figure 2 If a negative response is provided as PRI response 460 (a "no" outcome to step 240), endpoint 100 may take the approach of not Figure 4 Other fault handling actions shown in .

[0048] Figure 5 is a schematic diagram showing an example of a circuit according to an embodiment of the present disclosure. Figure 1 Likewise, an interconnect 500 is provided that (in this example) connects to a memory 510 and a CPU 520. Likewise, an SMMU 530 is connected to the interconnect 500. The CPU 520 may run an operating system that exercises supervisory control over the SMMU 520 and performs address translation in the system. Figure 5 The circuit can be implemented as an integrated circuit or a chip.

[0049] Endpoint 540 may be, for example, a so-called "root complex integrated endpoint" (RCiEP) (e.g., may be an on-chip device) that does not implement the PCIe protocol itself but may appear as a PCIe root complex for programming purposes, e.g., by advertising (notifying other devices) that it supports PRI and / or ATS.

[0050] However, compared with Figure 1 In contrast to the PCIe endpoint shown, endpoint 540 does not (or need not) include a cache for address translation (corresponding to Figure 1 To avoid the need to provide a cache invalidation to endpoint 540 each time a previously used translation is invalidated, in an example arrangement, control circuitry 544 of endpoint 540 may be configured to issue a notification to downstream devices that the circuitry does not include translation cache memory.

[0051] The SMMU 530 includes a transaction interface 532 for receiving data processing transactions from an upstream device (such as an endpoint 540), the data processing transactions defining a target virtual memory address (VA) in a virtual memory address space; and a translation circuit 534 for accessing a set of address mappings between VAs and PAs in a physical memory address space. For example, the translation circuit 534 may include a local cache of translations (such as a so-called translation lookaside buffer (TLB)) and / or may access translation tables in, for example, memory 510 through a so-called page table walk (PTW) process.

[0052] The translation circuit 534 is configured to: initiate processing of a data processing transaction by a downstream device (such as memory 510) according to a target PA from a target VA mapping when the set of address mappings (accessible to the translation circuit 534) includes an address mapping for the target VA; and provide a transaction response indicating a fault condition to the transaction interface when the set of address mappings fails to provide an address mapping for the target VA.

[0053] Endpoint 540 also includes a transaction interface 542 to transmit data processing transactions to downstream devices (such as SMMU 530). As described above, a data processing transaction defines a target VA. Endpoint 540 also receives a transaction response through interface 542, which indicates the completion of the data processing transaction or a fault condition when the conversion of the target VA fails.

[0054] exist Figure 5 In the context of the circuit shown, the terms "upstream" and "downstream" refer to the logical connections of devices with respect to data processing transactions. Thus, data processing transactions are issued in the direction from upstream toward downstream, and transaction responses are returned in the upstream direction.

[0055] and Figure 1 In contrast to the arrangement of , endpoint 540 provides untranslated transactions to SMMU 530. It is SMMU 520 that performs the translation and forwards the transactions via interface 536 to interconnect 500 for processing (e.g., by memory 510). Figure 1 In contrast to the PCIe arrangement of FIG, a transaction response is also provided to endpoint 540. (In a PCIe system, a transaction response need not always be provided, such as in the case where the ATC 130 has translated the data addressed in the write transaction).

[0056] therefore Figure 5The circuitry is configured to operate such that, when the conversion circuit has initiated processing of a data processing transaction by the downstream device, a transaction response is received from the downstream device and the transaction response is provided to the upstream device via the transaction interface. In other words, the downstream device is configured to communicate with the upstream device according to an interface protocol in which a response message is provided in response to each communication received from the upstream device. One embodiment of such an interface protocol is the Advanced Extensible Interface (AXI) protocol.

[0057] Reference Figure 7 , in the case where the SMMU 530 can service the VA to PA conversion without failure, at stage 700, the endpoint 540 transmits the unconverted transaction to the SMMU 530 (via interface 542 to interface 532). The SMMU 530 converts the transaction into a transaction with a PA suitable for accessing the memory 510 using the conversion circuit 534. The SMMU 530 provides the converted transaction to the interconnect 500 via output 536 at stage 710, and from the interconnect to the memory 510 for processing. The memory 510 provides a response at stage 720. For example, in the case of a data read operation, the response may be the data itself, possibly accompanied by a completion confirmation. In the case of a data write operation, the response may be a completion confirmation. Finally, at Figure 7 In stage 730 , the SMMU 530 provides a response back to the endpoint via interfaces 532 , 542 .

[0058] We will now consider the case where the SMMU 530 is unable to provide the services required to implement the VA to PA conversion required for an unconverted data transaction received from an upstream device. However, first, we will refer to Figure 6 Discuss the nature of different types of conversion failures.

[0059] Figure 6 6 is a partial schematic diagram showing some stages of the conversion of a VA to a PA. An input VA for the conversion, such as VA 600, is accompanied by so-called context information 610 that defines the context of the VA. This context may include: a definition of the address space associated with the VA, a definition of the process or thread associated with the VA, a definition of where in memory the conversion information (such as a page table) can be found, etc.

[0060] The initial stage of the conversion process is context determination (in Figure 6 ), where the context is processed or parsed to determine parameters for the conversion process ( Figure 6 For example, context determination 620 may include determining pointers to an appropriate set of page tables for use in translation step 630.

[0061] If the context determination step 620 fails, for example due to an incorrect or misconfigured SMMU 530, this is generally considered a fatal translation error that cannot be handled by a page request or similar reference to software (such as an operating system).

[0062] However, if the translation step 630 fails despite using a valid defined context, this is generally considered a translation failure, which can be handled by a page request or similar request to the operating system. For example, even if the device is operating under the AXI protocol, such a request can be a page request under the Peripheral Component Interconnect Express (PCIe) standard.

[0063] It should be noted that the question of whether a fault occurs at step 620 or step 630 is not necessarily a definitive indication of whether the fault is considered fatal. For example, a fault that occurs at step 630 (the memory system gives an error when attempting to read a page table entry) is generally considered fatal. The SMMU and / or OS may apply a set of criteria, such as predetermined criteria, regarding what types of faults constitute fatal errors.

[0064] (Finally, as Figure 6 As shown, if both steps are working correctly, the output will be PA 640. This corresponds to Figure 7 A successful conversion is shown in .)

[0065] The following scenario will now be discussed: the SMMU 530 is unable to provide translation of the VA forming part of an untranslated data transaction received from an upstream device. As described above, this may be due to a translation fault (which the operating system may correct in response to the page request) or a fatal error (such as a context determination error).

[0066] As described above, the SMMU 530 is configured to issue, and the endpoint 540 is configured to receive, a transaction response indicating a data processing transaction completion or a fault condition when translation of a target virtual memory address to a target physical memory address fails.

[0067] In response to such a fault notification, the control circuitry 544 of the endpoint 540 is configured to issue a memory region request (such as a page request) to a downstream device (e.g., the SMMU 530) requesting that a memory region in the virtual memory address space including the target VA be made available.

[0068] In some embodiments, transaction interface 542 is configured to receive the following as a transaction response from SMMU 530 indicating a fault condition:

[0069] A translation fault indication indicating that the upstream device may attempt the memory region request; or

[0070] Fatal error indication indicating that the upstream device should not attempt the memory region request.

[0071] Depending on the nature of the conversion failure, the control circuitry 544 of the endpoint may choose whether to issue a memory region request. Specifically, the control circuitry 544 may be configured to issue a memory region request to a downstream device in response to the transaction interface receiving a conversion failure indication. To achieve this, when the set of address mappings fails to provide an address mapping for the target VA, the conversion circuitry 534 is configured to provide a conversion failure indication or a fatal error indication as a transaction response, the conversion failure indication indicating that the upstream device may attempt a memory region request, and the fatal error indication indicating that the upstream device should not attempt a memory region request. The control circuitry 544 of the endpoint 540 may issue or not issue a region request based on the indication. Thus, for example, if the failure is a fatal failure, such as an inability to determine the context (as described above, see Figure 6 ), making it meaningless or not very meaningful to issue a region or page request, the control circuitry 544 of endpoint 540 may choose not to issue such a request and instead treat the situation as a fault condition. However, if the fault is at least resolvable by a region or page request, endpoint 540 may choose to issue such a request.

[0072] However, it's important to note that the distinction between fatal and conversion faults isn't just one of optimization, since it's unnecessary to issue a page request when the fault is fatal. The distinction is more important than that. A conversion fault in this context is one that causes the fault to fail due to reasons known to and / or solvable by the software, and where it's expected that the transaction will (or at least be usefully) retried once any failure is resolved. Conversely, a fatal fault is not expected to cause a transaction to be retried. If a conversion fault were to be used instead of a fatal fault, the transaction would be repeatedly retried because the software would always respond successfully to the page request.

[0073] The arrangement thus represents an embodiment of the following scenario: when the set of address mappings fails to provide an address mapping for the target virtual memory address, the translation circuit is configured to provide a translation failure indication or a fatal error indication as a transaction response, the translation failure indication indicating that the upstream device can attempt the memory region request, and the fatal error indication indicating that the upstream device should not attempt the memory region request.

[0074] Memory region or page requests are communicated from endpoint 540 to SMMU 530 (and memory region request responses in the reverse direction) via memory region or page request interface 546 at endpoint 540 and memory region or page request interface 538 at the SMMU. In the illustrated example embodiment, these interfaces are separate from transaction interfaces 532, 542, but it is noted that they may be substantially the same interface in other embodiments.

[0075] In the SMMU 530, the control circuit 539 is configured to receive a memory region request from an upstream device (such as an endpoint 540) requesting that a memory region in the virtual memory address space including the target VA be made available; initiate processing of the memory region request by the OS (e.g., by issuing a processor interrupt to the CPU 520 and providing a page or region request event to the OS being executed by the CPU 520); and provide a response to the upstream device based on the processing of the memory region request by the OS.

[0076] The resolution or result of the memory region or page request provided by the operating system may result in the requested region or page being now available (a "yes" outcome to step 240) and the data processing transaction being reissued, or the data processing transaction not being reissued (e.g., it remains unavailable (a "no" outcome to step 240). At endpoint 540, control circuitry 544 is configured to selectively reissue the data processing transaction based on the memory region request response received from the downstream device.

[0077] The timing diagram related to this process is as follows Figure 8 The process begins at stage 800 with the issuance of an untranslated data transaction from endpoint 540 that defines the target VA (associated with the address of a read, write, invalidate, or other operation). At stage 810, the transaction is routed to SMMU 530, which attempts to translate the target VA to the target PA, but Figure 8 In this case, the conversion fails and a fault response is returned by the SMMU 530 to the endpoint 540.

[0078] In response, at stage 820, control circuitry 544 of endpoint 540 selects whether to issue a page (region) request to request software (such as an OS) to make the required memory region or page available. This selection is responsive to the nature of the fault response provided at stage 810, which can be a transition fault indication, indicating that the upstream device can attempt the memory region request, or a fatal error indication, indicating that the upstream device should not attempt the memory region request. In the case of a fatal error indication, control circuitry 544 does not issue the memory region (page) request, but instead enters a fault condition. However, in the case of a transition fault indication, control circuitry 544 issues a page request via interfaces 546 and 538 at stage 830. The page request is received by SMMU 530, which causes SMMU 530 to issue a PRI event to software (such as an OS) at stage 840. The operating system ultimately responds with a PRI response at stage 850, which triggers or instructs SMMU 530 to provide a PRI response to endpoint 540 at stage 860.

[0079] Therefore, at stages 840 and 850, the control circuit 539 is configured to forward the memory region request to the operating system that controls the configuration of the conversion circuit, and forward the response received from the operating system to the upstream device. At stage 840, the control circuit can be configured to issue a processor interrupt to enable the operating system to process the memory region request.

[0080] The PRI response can be positive (yes, the page is now available) or negative. In the case of a negative response, as detected by the asterisk indication at stage 870, endpoint 540 enters a fault condition. In the case of a positive response, endpoint 540 retries the unconverted data transaction at stage 880, which then results in a corresponding Figure 7 Processing after stage 700.

[0081] In short, Figure 9 is a schematic flow chart illustrating a method, the method comprising;

[0082] (at step 900) receiving a data processing transaction from an upstream device, the data processing transaction defining a target virtual memory address in a virtual memory address space;

[0083] (at step 910) accessing a set of address mappings between virtual memory addresses and physical memory addresses in a physical memory address space;

[0084] (at step 920) when the set of address mappings accessed by the accessing step includes an address mapping for the target virtual memory address, initiating processing of the data processing transaction by the downstream device based on the target physical memory address mapped from the target virtual memory address;

[0085] (at step 930) providing a transaction response indicating a failure condition when the set of address mappings accessed by the accessing step fails to provide an address mapping for the target virtual memory address; and

[0086] (At step 940) In response to receiving a memory region request from an upstream device requesting that a memory region in a virtual memory address space including a target virtual memory address be made available, processing of the memory region request is initiated and a response is provided based on the processing of the memory region request.

[0087] Figure 10 is another schematic overview flow chart illustrating a method comprising:

[0088] (at step 1000) transmitting a data processing transaction to a downstream device, the data processing transaction defining a target virtual memory address in a virtual memory address space;

[0089] (at step 1010) receiving a transaction response indicating a data processing transaction completion or a failure condition when translation of the target virtual memory address to the target physical memory address fails;

[0090] issuing (at step 1020) a memory region request to make available a memory region in a virtual memory address space including the target virtual memory address to a downstream device;

[0091] (at step 1030) receiving a memory region request response from a downstream device; and

[0092] (At step 1040) selectively reissuing the data processing transaction based on a memory region request response received from a downstream device.

[0093] In this application, the phrase "configured to..." is used to mean that elements of a device have a configuration capable of performing a defined operation. In this context, "configuration" refers to the arrangement or manner in which hardware or software are interconnected. For example, the device may have dedicated hardware to provide the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device elements need to be modified in any way in order to provide the defined operation.

[0094] Although illustrative embodiments of the present technology have been described in detail herein with reference to the accompanying drawings, it should be understood that the present technology is not limited to those precise embodiments and that various changes, additions, and modifications may be implemented therein by those skilled in the art without departing from the scope and spirit of the present technology as defined by the appended claims. For example, features of the dependent claims may be combined in various ways with features of the independent claims without departing from the scope of the present technology.

Claims

1. A circuit, comprising: A memory management circuit is provided between an upstream device and a downstream device, and includes: a transaction interface for receiving a data processing transaction from the upstream device, the data processing transaction defining a target virtual memory address in a virtual memory address space; a translation circuit for accessing a set of address mappings between virtual memory addresses and physical memory addresses in a physical memory address space; The translation circuitry is configured to: initiate processing of the data processing transaction by the downstream device according to a target physical memory address mapped from the target virtual memory address when the set of address mappings includes an address mapping for the target virtual memory address, and provide a transaction response indicating a failure condition to the transaction interface when the set of address mappings fails to provide an address mapping for the target virtual memory address; A control circuit is configured to: receive a memory region request from the upstream device via a memory region request interface separate from the transaction interface, requesting that a memory region in a virtual memory address space including the target virtual memory address be made available, initiate processing of the memory region request, and provide a response to the upstream device based on the processing of the memory region request, wherein the control circuit is configured to: forward the memory region request to an operating system that controls the configuration of the conversion circuit, and forward the response received from the operating system to the upstream device.

2. The circuit according to claim 1, wherein When the set of address mappings fails to provide an address mapping for the target virtual memory address, the translation circuit is configured to provide a translation failure indication or a fatal error indication as the transaction response, the translation failure indication indicating that the upstream device will attempt a memory region request, and the fatal error indication indicating that the upstream device should not attempt a memory region request.

3. The circuit according to claim 1, wherein The response from the operating system indicates that the memory region is available and the data processing transaction is to be reissued, or that the data processing transaction should not be reissued.

4. The circuit according to claim 1, wherein The control circuitry is configured to issue a processor interrupt to initiate processing of the memory region request by the operating system.

5. The circuit of claim 1 , the circuit being configured to receive a transaction response from the downstream device when the conversion circuit has initiated processing of the data processing transaction by the downstream device, and to provide the transaction response to the upstream device via the transaction interface.

6. The circuit according to claim 1, wherein The memory region request is a page request according to the Peripheral Component Interconnect Express (PCIe) standard.

7. The circuit according to claim 1, wherein The circuitry is configured to communicate with the upstream device according to an interface protocol in which a response message is provided in response to each communication received from the upstream device.

8. The circuit according to claim 7, wherein The interface protocol is the Advanced Extensible Interface (AXI) protocol.

9. A circuit, comprising: Downstream equipment; a transaction interface configured to: transmit a data processing transaction to the downstream device, the data processing transaction defining a target virtual memory address in a virtual memory address space; and receive a transaction response indicating completion or a failure condition of the data processing transaction when translation of the target virtual memory address to a target physical memory address fails; as well as a control circuit configured to: issue a memory region request to the downstream device via a memory region request interface separate from the transaction interface, requesting that a memory region in a virtual memory address space including the target virtual memory address be made available, and receive a memory region request response from the downstream device; The control circuitry is configured to selectively reissue the data processing transaction based on a memory region request response received from the downstream device; Wherein, the downstream device is an address translation device, and the address translation device is configured to: translate the target virtual memory address into a target physical memory address in a physical memory address space, and start processing the data processing transaction according to the target physical memory address; and The circuit is configured to communicate with the downstream device according to an interface protocol, wherein the downstream device provides a response message in response to each communication issued by the circuit to the downstream device.

10. The circuit of claim 9, wherein: The transaction interface is configured to receive a conversion failure indication or a fatal error indication as a transaction response indicating a failure condition, the conversion failure indication indicating that the upstream device will attempt a memory region request, and the fatal error indication indicating that the upstream device should not attempt a memory region request; and The control circuitry is configured to issue the memory region request to the downstream device in response to the transaction interface receiving a translation failure indication.

11. The circuit according to claim 9, wherein The memory region response from the downstream device includes an indication that the memory region is available and the data processing transaction is to be reissued, or an indication that the data processing transaction should not be reissued.

12. The circuit according to claim 9, wherein The control circuitry is configured to issue a notification to the downstream device that the circuitry does not include a translation cache memory.

13. The circuit according to claim 9, wherein The downstream equipment includes: a translation circuit for accessing a set of address mappings between virtual memory addresses and physical memory addresses in a physical memory address space; The translation circuit is configured to: initiate processing of the data processing transaction according to the target physical memory address mapped to the target virtual memory address when the set of address mappings includes an address mapping for the target virtual memory address, and provide a transaction response indicating a translation error to the transaction interface when the set of address mappings fails to provide an address mapping for the target virtual memory address.

14. The circuit according to claim 13, wherein The downstream equipment includes: A control circuit is configured to receive a memory area request from the upstream device requesting that a memory area in a virtual memory address space including the target virtual memory address be made available, initiate processing of the memory area request, and provide the memory area request response to the upstream device based on the processing of the memory area request.

15. A method comprising: receiving, via a transaction interface, a data processing transaction from an upstream device, the data processing transaction defining a target virtual memory address in a virtual memory address space; Access a set of address mappings between virtual memory addresses and physical memory addresses in the physical memory address space; initiating processing of the data processing transaction by a downstream device based on a target physical memory address mapped from the target virtual memory address when the set of address mappings accessed by the accessing step includes an address mapping for the target virtual memory address; providing a transaction response indicating a failure condition when the set of address mappings accessed by the accessing step fails to provide an address mapping for the target virtual memory address; and in response to receiving a memory region request from the upstream device via a memory region request interface separate from the transaction interface requesting that a memory region in a virtual memory address space including the target virtual memory address be made available, initiating processing of the memory region request and providing a response based on the processing of the memory region request; Initiating processing of the memory region request includes forwarding the memory region request to an operating system that controls configuration of the conversion circuit, and forwarding a response received from the operating system to the upstream device.

16. A method comprising: transmitting a data processing transaction to a downstream device via a transaction interface, the data processing transaction defining a target virtual memory address in a virtual memory address space; When translation of the target virtual memory address to the target physical memory address fails, receiving a transaction response indicating completion or a failure condition of the data processing transaction; issuing, to the downstream device via a memory region request interface separate from the transaction interface, a memory region request to make available a memory region in a virtual memory address space including the target virtual memory address; receiving a memory region request response from the downstream device; and selectively reissuing the data processing transaction based on a memory region request response received from the downstream device; wherein the communicating step comprises communicating according to an interface protocol, wherein in response to each communication issued by the circuit to the downstream device, the downstream device provides a response message; and the method comprises: The downstream device converts the target virtual memory address into a target physical memory address in a physical memory address space, and initiates processing of the data processing transaction according to the target physical memory address.

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