Semiconductor substrate and semiconductor device

Abstract

The present invention discloses a semiconductor substrate, comprising: a dielectric insulating layer and a structured first metallization layer attached to the dielectric insulating layer; a first switching element, comprising a first load path between a first emitter terminal and a first collector terminal; a second switching element, comprising a second load path between a second emitter terminal and a second collector terminal; a first diode element, comprising a first anode terminal and a first cathode terminal; and a second diode element, comprising a second anode terminal and a second cathode terminal. The first metallization layer comprises at least five independent sections electrically insulated from each other. The first switching element, the second switching element, the first diode element, and the second diode element are arranged on the first section of the first metallization layer. The first anode terminal and the first emitter terminal are electrically coupled to the second section and the third section, and the second anode terminal and the second emitter terminal are electrically coupled to the fourth section and the fifth section.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor substrate and a semiconductor device, and more particularly, to a semiconductor device including a plurality of semiconductor substrates. Background Art

[0002] The power semiconductor module device often includes at least one semiconductor substrate arranged in a housing. A semiconductor device including a plurality of controllable semiconductor elements (e.g., two IGBTs in a half-bridge configuration) is arranged on each of the at least one substrate. Each substrate generally includes a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer, and a second metallization layer deposited on a second side of the substrate layer. For example, the controllable semiconductor element is mounted on the first metallization layer. The second metallization layer can be optionally attached to a substrate. The controllable semiconductor device is generally mounted to the semiconductor substrate by welding or sintering technology.

[0003] Conductive terminal elements are usually provided, allowing electrical contacting of the semiconductor element from outside the housing. Such conductive terminal elements often include, for example, one or more conductor rails. Since the dimensions of such power semiconductor module arrangements are usually designed to be as small as possible, high stray inductances may occur, which may have a negative impact on the operation of the semiconductor module.

[0004] There is a need for semiconductor substrates having low stray inductance and semiconductor devices including a plurality of semiconductor substrates. Summary of the invention

[0005] The semiconductor substrate comprises: a dielectric insulating layer and a structured first metallization layer attached to the dielectric insulating layer; a first switching element comprising a first load path between a first emitter terminal and a first collector terminal; a second switching element comprising a second load path between a second emitter terminal and a second collector terminal; a first diode element comprising a first anode terminal and a first cathode terminal; and a second diode element comprising a second anode terminal and a second cathode terminal. The first metallization layer comprises at least five independent sections electrically insulated from each other. The first switching element, the second switching element, the first diode element, and the second diode element are arranged on a first section of the first metallization layer, wherein the first collector terminal, the second collector terminal, the first cathode terminal, and the second cathode terminal are electrically coupled to the first section. The first anode terminal and the first emitter terminal are electrically coupled to each other and further coupled to the second section and the third section of the first metallization layer, and the second anode terminal and the second emitter terminal are electrically coupled to each other and further coupled to the fourth section and the fifth section of the first metallization layer. The second and fourth sections are arranged adjacent to each other, the third and fifth sections are arranged adjacent to each other, and the first section separates the second and fourth sections from the third and fifth sections.

[0006] The semiconductor device includes a plurality of semiconductor substrates. The plurality of semiconductor substrates are arranged in a row such that first sections of first metallization layers of the plurality of semiconductor substrates are arranged in a first row, second sections and third sections of the first metallization layers of the plurality of semiconductor substrates are arranged in a second row parallel to the first row, and fourth sections and fifth sections of the first metallization layers of the plurality of semiconductor substrates are arranged in a third row parallel to the first row and the second row.

[0007] The present invention can be better understood with reference to the following drawings and descriptions. The components in the drawings are not necessarily to scale, but rather focus on illustrating the principles of the present invention. In addition, in the drawings, similar reference numerals indicate corresponding parts throughout the different views. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional view of a power semiconductor module device.

[0009] Figure 2 A circuit arrangement according to an example is schematically shown.

[0010] Figure 3 A further circuit arrangement according to an example is schematically shown.

[0011] Figure 4 An arrangement comprising three separate power semiconductor module arrangements is schematically shown.

[0012] Figure 5 A top view of a conventional semiconductor substrate on which a plurality of semiconductor devices are mounted is schematically shown.

[0013] Figure 6 Schematically shows a plurality of Figure 5 A top view of a device of a semiconductor substrate.

[0014] Figure 7 Schematically shows a plurality of Figure 5 A three-dimensional view of a device of a semiconductor substrate.

[0015] Figure 8 A top view of a semiconductor substrate on which a plurality of semiconductor devices are mounted according to an example is schematically shown.

[0016] Fig. 9 Schematically shows a plurality of Figure 8 A top view of a device of a semiconductor substrate.

[0017] Fig.10 Schematically shows a plurality of Figure 8 A three-dimensional view of a device of a semiconductor substrate.

[0018] include Fig.11Aand Fig. 11B FIG11 schematically shows Figure 5 and Figure 8 The devices and their corresponding current directions are used for comparison.

[0019] include Fig. 12A and Fig. 12B FIG12 schematically shows a method for using Figure 5 and Figure 8 The semiconductor substrate device is implemented Figure 3 The resulting contact sheet in the first layer of the device serves as comparison.

[0020] include Fig.13A and Fig. 13B FIG13 schematically shows a method for using Figure 5 and Figure 8 The semiconductor substrate device is implemented Figure 3 The resulting contact sheet in the second layer of the device serves as a comparison.

[0021] include Fig.14A and Fig. 14B FIG14 schematically shows a method for using Figure 5 and Figure 8 The semiconductor substrate device is implemented Figure 3 The resulting contact sheet in the third layer of the device serves as a comparison.

[0022] Fig.15 Schematically shows Fig. 12A , Fig.13A and Fig.14A devices, and Figure 3 The resulting current direction in the device.

[0023] Fig.16 Schematically shows Fig. 12B , Fig. 13B and Fig. 14B devices, and Figure 3 The resulting current direction in the device.

[0024] Fig.17 Schematically shows Fig. 12A , Fig.13A and Fig.14A A device having a single half-bridge module, and Figure 2 The resulting current direction in the device.

[0025] Fig.18 Schematically shows Fig. 12B , Fig. 13B and Fig. 14B A device having a single half-bridge module, and Figure 2 The resulting current direction in the device.

[0026] Fig.19 Shown in Figure 5 The resulting current and voltage during the conduction period of the semiconductor switch in the device.

[0027] Fig. 20 Shown in Figure 8 The resulting current and voltage during the conduction period of the semiconductor switch in the device. DETAILED DESCRIPTION

[0028] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings show specific examples in which the present invention can be practiced. It is to be understood that, unless otherwise specifically noted, the features and principles described for the various examples can be combined with each other. In the specification and in the claims, designating certain elements as "first element", "second element", "third element", etc. cannot be understood as enumeration. On the contrary, such designation is only used to refer to different "elements". That is, for example, the presence of a "third element" does not require the presence of a "first element" and a "second element". The wires or electrical connections described herein may be a single conductive element, or include at least two separate conductive elements connected in series and / or in parallel. The wires and electrical connections may include metal and / or semiconductor materials and may be permanently conductive (i.e., non-convertible). The semiconductor body as described herein may be made of (doped) semiconductor material and may be a semiconductor chip or included in a semiconductor chip. The semiconductor body has an electrical connection pad and includes at least one semiconductor element having an electrode.

[0029] refer to Figure 1 , schematically shows a cross-sectional view of a power semiconductor module device 100. The power semiconductor module device 100 includes a housing 17 and a semiconductor substrate 10. The semiconductor substrate 10 includes a dielectric insulating layer 11, a (structured) first metallization layer 111 attached to the dielectric insulating layer 11, and a (structured) second metallization layer 112 attached to the dielectric insulating layer 11. The dielectric insulating layer 11 is arranged between the first and second metallization layers 111, 112.

[0030] Each of the first and second metallization layers 111, 112 may be made of or include one of the following materials: copper; copper alloy; aluminum; aluminum alloy; any other metal or alloy that remains solid during operation of the power semiconductor module device. The semiconductor substrate 10 may be a ceramic substrate, i.e., a substrate in which the dielectric insulating layer 11 is a ceramic (e.g., a thin ceramic layer). The ceramic may be made of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulating layer 11 may be made of or include one of the following materials: Al2O3, AlN, SiC, BeO, or Si3N4. For example, the substrate 10 may be, for example, a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal brazing (AMB) substrate. In addition, the substrate 10 may be an insulated metal substrate (IMS). For example, an insulated metal substrate typically includes a dielectric insulating layer 11, which includes a (filling) material such as an epoxy resin or a polyimide. For example, the material of the dielectric insulating layer 11 may be filled with ceramic particles. Such particles may include, for example, Si2O, Al2O3, AlN or BrN, and may have a diameter between about 1 μm and about 50 μm. The substrate 10 may also be a conventional printed circuit board (PCB) having a non-ceramic dielectric insulating layer 11. For example, the non-ceramic dielectric insulating layer 11 may be composed of or include a cured resin.

[0031] The semiconductor substrate 10 is arranged in a housing 17. Figure 1 In the example shown in , the semiconductor substrate 10 is arranged on a base plate 12, which forms a ground surface of a housing 17, while the housing 17 itself only includes side walls and a top cover. However, this is only an example. The housing 17 may also include a ground surface, and the semiconductor substrate 10 and the base plate 12 are arranged inside the housing 17. In some power semiconductor module devices 100, more than one semiconductor substrate 10 is arranged on a single base plate 12 or a ground surface of the housing 17.

[0032] One or more semiconductor bodies 120 may be arranged on at least one semiconductor substrate 10. Each of the semiconductor bodies 120 arranged on at least one semiconductor substrate 10 may include a diode, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a JFET (Junction Field Effect Transistor), a HEMT (High Electron Mobility Transistor), and / or any other suitable semiconductor element.

[0033] One or more semiconductor bodies 120 may form a semiconductor device on the semiconductor substrate 10. Figure 1 In FIG. 1 , only two semiconductor bodies 120 are shown by way of example. Figure 1 The second metallization layer 112 of the semiconductor substrate 10 is a continuous layer. Figure 1 In the example shown, the first metallization layer 111 is a structured layer. By "structured layer" it is meant that the first metallization layer 111 is not a continuous layer but comprises recesses between different sections of the layer. Figure 1 Such a recess is schematically shown in . In this example, the first metallization layer 111 includes three different sections. However, this is merely an example. Any other number of sections is also possible. Different semiconductor bodies 120 can be mounted to the same or different sections of the first metallization layer 111. Different sections of the first metallization layer 111 may not be electrically connected, or may be electrically connected to one or more other sections using, for example, bonding wires 13. For example, to name a few examples, the electrical connection 13 may also include a connecting plate or a conductor track. One or more semiconductor bodies 120 can be electrically and mechanically connected to the semiconductor substrate 10 via a conductive connection layer 130. For example, such a conductive connection layer can be a solder layer, a conductive adhesive layer, or a sintered metal powder (e.g., sintered silver powder) layer.

[0034] According to other examples, the second metallization layer 112 may also be a structured layer. It is also possible to completely omit the second metallization layer 112. For example, the first metallization layer 111 may also be a continuous layer.

[0035] Figure 1 The power semiconductor module device 100 shown in also includes a terminal element 14. The terminal element 14 is electrically connected to the first metallization layer 111 and provides an electrical connection between the interior and the exterior of the housing 17. The terminal element 14 may be electrically connected to the first metallization layer 111 with a first end, while a second end 141 of each of the terminal elements 14 protrudes outside the housing 17. The terminal elements 14 may be electrically contacted from the outside at the respective second ends 141 of the terminal elements 14. A first portion of the terminal element 14 may extend through the interior of the housing 17 in a vertical direction y. The vertical direction y is a direction perpendicular to a top surface of the semiconductor substrate 10, wherein the top surface of the semiconductor substrate 10 is a surface on which at least one semiconductor body 120 is mounted. However, Figure 1 The terminal elements 14 shown in FIG. 1 are merely examples. The terminal elements 14 may be implemented in any other manner and may be arranged anywhere within the housing 17. For example, one or more terminal elements 14 may be arranged close to or adjacent to the side walls of the housing 17. The terminal elements 14 may also protrude through the side walls of the housing 17 instead of through the top cover.

[0036] The semiconductor body 120 may include chip pad metallization (not specifically shown), such as source, drain, emitter, collector, anode, cathode or gate metallization. The chip pad metallization generally provides a contact surface for electrically connecting the semiconductor body 120. For example, the chip pad metallization may electrically contact the connection layer 130, the terminal element 14 or the electrical connection 13. For example, the chip pad metallization may be composed of or include a metal such as aluminum, copper, gold or silver. For example, the electrical connection 13 and the terminal element 14 may also be composed of or include a metal such as copper, aluminum, gold or silver.

[0037] Reference now Figure 2 , and as described above, for example, at least two semiconductor bodies 120 may be arranged in a semiconductor device, such as a neutral point clamped (NPC) topology (eg, a so-called NPC2, T-type, MNPC or NPC3 topology). Figure 2 is a circuit diagram of an exemplary three-level NPC2 topology. Figure 2 The NPC2 topology includes a half-bridge module 20 and a common collector module 22. For example, a typical NPC topology includes four switching elements S1, S2, S3, S4 (such as IGBTs) and four diode elements D1, D2, D3, and D4.

[0038] The half-bridge module 20 is configured to convert a DC voltage provided at an input 1, 2 of the half-bridge module 20 into an AC voltage provided at an output node 3 of the half-bridge module 20. The AC voltage may be provided to a load (not shown), for example, coupled to the output node 3 of the half-bridge module 20. The half-bridge module 20 is coupled between a first power supply node 1 configured to be operably coupled to a first potential and a second power supply node 2 configured to be operably coupled to a second potential. The first potential may be a positive potential DC+, and the second potential may be a negative potential DC-, to supply a DC voltage via the first and second power supply nodes 1, 2. The first and second power supply nodes 1, 2 form the inputs of the half-bridge module 20.

[0039] The half-bridge module 20 may include a high-side switch S1 (first switch) and a low-side switch S2 (second switch) coupled in series with each other and between a first power supply node 1 and a second power supply node 2. The half-bridge module 20 may be configured to drive a load (not specifically shown) at its output node 3. For example, the load may be an inductive load. The output node 3 is electrically connected to a common node between the high-side switch S1 and the low-side switch S2.

[0040] exist Figure 2In the circuit arrangement of the half-bridge module 20, each switch S1, S2 is implemented as an IGBT (insulated gate bipolar transistor). Each of the switches S1, S2 may include an external freewheeling diode D1, D2 coupled in parallel to the corresponding switch S1, S2. According to another example, each of the switches S1, S2 includes two or more independent switching elements (not shown) electrically coupled in parallel to each other.

[0041] Each of the first switch S1 and the second switch S2 includes a control electrode G1, G2 and a controllable load path between a first load electrode (e.g., an emitter electrode) and a second load electrode (e.g., a collector electrode). The load paths of the first switch S1 and the second switch S2 are coupled in series and between the first power supply node 1 and the second power supply node 2.

[0042] The common collector module 22 includes a third switch element S3, a fourth switch element S4, a third diode D3, and a fourth diode D4. Each of the third switch S3 and the fourth switch S4 includes a control electrode G3, G4 and a controllable load path between a first load electrode E3, E4 (e.g., an emitter electrode) and a second load electrode C3, C4 (e.g., a collector electrode). The load paths of the third switch S3 and the fourth switch S4 are coupled in series between the fourth neutral node 4 and the output node 3. In this series connection of the third switch S3 and the fourth switch S4, the second load electrode C3 of the third switch S3 is coupled to the second load electrode C4 of the fourth switch S4. The first load electrode E3 of the third switch S3 is coupled to the output node 3, and the first load electrode E4 of the fourth switch S4 is coupled to the fourth neutral node 4. The third diode element D3 is coupled in parallel to the third switch S3 between the output node 3 and the fourth switch S4, wherein the anode of the third diode element D3 is coupled to the output node 3, and the cathode of the third diode element D3 is coupled to the second load electrode C4 of the fourth switch S4. A fourth diode element D4 is coupled in parallel to the fourth switch S4 between the fourth neutral node 4 and the second load electrode C3 of the third switch S3, wherein an anode of the fourth diode element D4 is coupled to the fourth neutral node 4 and a cathode of the fourth diode element D4 is coupled to the second load electrode C3 of the third switch S3.

[0043] Figure 2 The current commutation path of the semiconductor device extends through both the half-bridge module 20 and the common collector module 22. Specifically, the commutation path may extend from the first power node 1 through the first switch S1, and further through the third switch S3 and the fourth switch S4 to the fourth neutral node 4.

[0044] A three-level NPC topology typically has a higher stray inductance than a two-level topology (the two-level topology is not specifically shown). Losses are typically increased during use of a three-level topology compared to, for example, a two-level topology.

[0045] Three-level NPC topology can usually be provided in different expansion levels. For example, Figure 3 A higher order expansion level is shown in FIG. 1 . The semiconductor device in this example comprises two half-bridge modules 20 and one common collector module 22 . The two half-bridge modules 20 are coupled in parallel between a first power supply node 1 and a second power supply node 2 . Figure 3 The individual half-bridge modules 20 correspond to Figure 2 A single half-bridge module 20, and Figure 3 The common collector module 22 corresponds to Figure 2 Common collector module 22.

[0046] For example, each of the half-bridge module and the common collector module 20, 22 can be arranged in an independent housing. That is, each half-bridge module 20 can be arranged in a housing similar to the above reference Figure 1 The housing 17 is also described. This also applies to the common collector module 22. In practice, Figure 3 The common collector module 22 can be arranged between the two half-bridge modules 20, such as Figure 4 As shown in the example, Figure 4 Schematically shows a top view of a power semiconductor module arrangement comprising three individual power semiconductor modules (three housings 17). Figure 4 In the top view of FIG. 2 , the housings of the individual modules 20 , 22 are schematically shown, wherein the second ends 141 of the respective terminal elements 14 protrude out of the housing. Figure 4 The electrical connection between the separate second ends 141 outside the housing is also schematically shown. For example, such an electrical connection can be implemented by means of a contact sheet ( Figure 4 The contact pads are not shown in the example shown).

[0047] As mentioned above Figure 1 As described, each of the modules 20 , 22 may include one or more semiconductor substrates 10 disposed in a housing 17 . Figure 52 exemplarily shows a conventional semiconductor substrate 10 that can be arranged in the housing of the common collector module 22. As described above, the semiconductor substrate 10 includes a structured first metallization layer 111. The third switch S3, the third diode element D3, the fourth switch S4, and the fourth diode element D4 are arranged on the first section 1112 of the first metallization layer 111. Specifically, the first section 1112 of the first metallization layer 111 can form a common collector of the semiconductor device. That is, the second load electrode C3 of the third switch, the second load electrode C4 of the fourth switch, the cathode of the third diode element D3, and the cathode of the fourth diode element D4 can be coupled to the first section 1112 of the first metallization layer 111. The first load electrode E3 of the third switch S3 and the anode electrode of the third diode element D3 are electrically coupled to each other and to the second section 1111 of the first metallization layer 111. The first load electrode E4 of the fourth switch S4 and the anode electrode of the fourth diode element D4 are electrically coupled to each other and to the third section 1113 of the first metallization layer 111. For example, the electrical connections between the first load electrodes E3, E4, the anode electrode and the second and third sections 1111, 1113 of the first metallization layer 111 may include one or more bonding wires 60. However, this is only an example. Alternatively, any other kind of electrical connection such as a bonding ribbon may be used.

[0048] Figure 6 exemplarily shows a power semiconductor module device including a plurality of semiconductor substrates 10 on a single substrate 12. The substrate 12 on which the plurality of semiconductor substrates 10 are mounted may be arranged in a housing ( Figure 6 For convenience, the housing is not specifically shown. Figure 6 In the example of FIG. 1 , semiconductor devices S3, D3, S4, D4 are not specifically shown. Specifically, Figure 6 The top view shown in is intended to illustrate the electrical connections between the different semiconductor modules 10 of the device. Figure 6 Such electrical connections are schematically shown as continuous lines in FIG. 1. Typically, two electrical connections are formed between the second sections 1111 of different semiconductor substrates 10, and two electrical connections are formed between the third sections 1113 of different semiconductor substrates 10.

[0049] For example, the different second and third sections 1111 , 1113 of the first metallization layer 111 can be electrically contacted by means of conductor tracks. Figure 7 First and second conductor tracks 30, 32 may be provided in order to electrically contact second sections 1111 of different semiconductor substrates 10. Third and fourth conductor tracks 34, 36 may be provided in order to electrically contact third sections 1113 of different semiconductor substrates 10.

[0050] The first and second conductor tracks 30, 32 that are in electrical contact with the same section (i.e., the second section 1111) of the independent first metallization layer 111 necessarily comprise the same electrical potential. The same also applies to the third and fourth conductor tracks 34, 36 that are in electrical contact with the third section 1113 of the independent first metallization layer 111. That is, the first and second conductor tracks 30, 32 are arranged adjacent to each other within a close distance, and the third and fourth conductor tracks 34, 36 are arranged adjacent to each other within a close distance. In other words, the distance between the first and second conductor tracks 30, 32 in the first horizontal direction x is smaller than the distance between the first conductor track 30 or the second conductor track 32 and the third conductor track 34 or the fourth conductor track 36 in the same direction. Such an arrangement in which two conductor tracks 30, 32 and 34, 36 having the same electrical potential are arranged in close proximity to each other results in a rather high stray inductance.

[0051] Figure 8 The schematic diagram for Figure 6 to Figure 7 In the present embodiment, the first metallization layer 111 includes a first section 1112, a second section 111 12 、The third section 111 32 、The fourth section 111 11 and the fifth section 111 31 . Additional Section 111 nm It is usually possible. For example, in any additional segment 111 nm However, such an optional additional section 111 nm It is not relevant to understanding the present invention and, therefore, is not specifically shown herein. Figure 5In the example shown in , the third switch S3, the third diode element D3, the fourth switch S4, and the fourth diode element D4 are arranged on the first section 1112 of the first metallization layer 111. Specifically, the first section 1112 of the first metallization layer 111 may form a common collector of the semiconductor device. That is, the second load electrode C3 of the third switch S3, the second load electrode C4 of the fourth switch S4, the cathode of the third diode element D3, and the cathode of the fourth diode element D4 may be electrically coupled to the first section 1112 of the first metallization layer 111. For example, one of the plurality of conductive connection layers 130 may be arranged between each of the switch devices S3, S4 and the diode devices D3, D4 and the first metallization layer 111. For example, the first conductive connection layer 130 may be arranged between the second load electrode C3 of the third switch S3 and the first section 1112, the second conductive connection layer 130 may be arranged between the second load electrode C4 of the fourth switch S4 and the first section 1112, the third conductive connection layer 130 may be arranged between the cathode electrode C3 of the third diode element D3 and the first section 1112, and the fourth conductive connection layer 130 may be arranged between the cathode electrode C4 of the fourth diode element D4 and the first section 1112. The first load electrode E3 of the third switch S3 and the anode electrode of the third diode element D3 are electrically coupled to each other and to the second section 1112. 12 and further electrically coupled to the third section 111 of the first metallization layer 111 32 The first load electrode E4 of the fourth switch S4 and the anode electrode of the fourth diode element D4 are electrically coupled to each other and to the fourth section 111. 11 and further electrically coupled to the fifth section 111 of the first metallization layer 111 31 .

[0052] Therefore, in Figure 8 In the example, the second segment 111 12 and the third section 111 32 are coupled to the same first potential, and the fourth section 111 11 and the fifth section 111 31 is coupled to the same second potential different from the first potential. Specifically, the second segment 111 12 and the third section 111 32 can be electrically coupled to the output node 3, and the fourth section 111 11 and the fifth section 111 31 May be electrically coupled to a fourth neutral node 4 .

[0053] Reference again Figure 5, a second section 1111 having a first potential (coupled to the output node 3) is arranged at a first end of the semiconductor substrate 10, and a third section 1113 having a second potential (coupled to the fourth neutral node 4) is arranged at a second end of the semiconductor substrate 10 opposite to the first end. Figure 5 In the device of , the first section 1112 separates the second section 1111 and the third section 1113, and thus separates the first potential and the second potential. Figure 8 In the device shown in FIG. 1 , the second section 111 having different electric potentials 12 and the fourth section 111 11 The third section 111 is arranged at the first end of the semiconductor substrate 10. 32 and the fifth section 111 31 The semiconductor substrate 10 is arranged at a second end portion opposite to the first end portion. Figure 8 The first section 1112 of the device is connected to the second section 111 at the first end of the semiconductor substrate 10 12 and the fourth section 111 11 The third section 111 at the second end of the semiconductor substrate 10 32 and the fifth section 111 31 Separate.

[0054] In this way, when a plurality of semiconductor substrates 10 are arranged adjacent to each other in a row on the base plate 12, the arrangement of the conductor tracks 30, 32, 34, 36 is combined with the above Figure 6 and Figure 7 The arrangement described is different. Now refer to Fig. 9 , schematically shown on a substrate 12 according to Figure 8 The plurality of semiconductor substrates 10 are arranged in a row on a substrate 12, such that the first sections 1112 of the first metallization layers 111 of the semiconductor substrates 10 are arranged adjacent to each other in the first row. 12 and the fourth section 111 11 Arranged adjacent to each other in a second row parallel to the first row. 12 and the fourth section 111 11 Arranged alternately in the second row. 32 and the fourth section 111 31 The third section 111 is arranged adjacent to each other in a third row parallel to the first row and the second row. 32 and the fifth section 111 31 Alternate in the third row.

[0055] The first conductor track 30 connects the second sections 111 of the plurality of semiconductor substrates 1012 The second conductor track 32 connects the fifth section 111 of the plurality of semiconductor substrates 10 to the output node 3. 31 The third conductor track 34 connects the fourth section 111 of the plurality of semiconductor substrates 10 to the fourth neutral node 4. 11 The fourth conductor track 36 connects the third sections 111 of the plurality of semiconductor substrates 10 to each other and to the fourth neutral node 4. 32 are electrically coupled to each other and to output node 3 .

[0056] Reference now Fig.10 , the first conductor rail 30 and the third conductor rail 34 having different potentials are arranged adjacent to each other at the first end of the semiconductor substrate 10. In addition, the second conductor rail 32 and the fourth conductor rail 36 having different potentials are arranged adjacent to each other at the second end of the semiconductor substrate 10 opposite to the first end. The third conductor rail 34 and the second conductor rail 32 are arranged between the first conductor rail 30 and the fourth conductor rail 36. The distance between the first conductor rail 30 and the third conductor rail 34 in the first horizontal direction x is significantly shorter than the distance between the third conductor rail 34 and the second conductor rail 32 in the same direction, for example, less than 50%, less than 30% or less than 15%. In addition, the distance between the second conductor rail 32 and the fourth conductor rail 36 in the first horizontal direction x is significantly shorter than the distance between the third conductor rail 34 and the second conductor rail 32, for example, less than 50%, less than 30% or less than 15%. The first section 1112 of the first metallization layer 111 is arranged between the third conductor rail 34 and the second conductor rail 32. That is, Figure 6 and Figure 7 Compared with the arrangement of Fig. 9 and Fig.10 In the arrangement of , conductor tracks having different potentials (ie, conductor tracks 30 and 34, and conductor tracks 32 and 36) are arranged in close proximity to each other. This significantly reduces the stray inductance of the semiconductor device.

[0057] Now referring to FIG. 11 , a schematic diagram of Figure 5 and Figure 8 The general direction of current flow in a device. Specifically, Fig.11A Schematically shows Figure 5 The current flows in the device. Fig.11A The current flow is indicated by a thick arrow in FIG. The first current flows from the third segment 1113 through the electrical connection 60 to the anode electrode of the fourth diode element D4. The current further flows through the fourth diode element D4 and through the first segment 1112 to the third switch S3. The current then flows through the third switch S3. The current then flows from the first load electrode E3 of the third switch S3 to the second segment 1111. Fig.11AIn the arrangement of FIG. 1 , no current flows through the fourth switch S4 and through the third diode element D3 . However, current flows via the first load electrode E4 of the fourth switch S4 through the electrical connection 60 electrically coupling the fourth diode element D4 to the third section 1113 .

[0058] Reference now Fig. 11B , schematically showing Figure 8 The current flows in the device. Fig. 11B The current flow in the fourth segment 111 is also shown by a thick arrow. 11 and the fifth section 111 31 The current then flows to the anode electrode of the fourth diode element D4. The current then flows through the fourth diode element D4 and further through the first section 1112 to the third switch S3. The current then flows through the third switch S3. The current then flows from the first load electrode E3 of the third switch S3 to the second section 111 12 and the third section 111 32 .exist Fig. 11B In the device, no current flows through the fourth switch S4 and through the third diode element D3. However, current flows via the first load electrode E4 of the fourth switch S4 by electrically coupling the fourth diode element D4 to the fifth section 111. 31 In addition, the current flows through the anode electrode of the third diode element D3 by electrically coupling the first load electrode E3 of the third switch S3 to the third section 111. 32 Electrical connection 60.

[0059] Each of the individual conductor tracks 30, 32, 34, 36 may include one or more taps. In the second horizontal direction z, taps of different potentials may be arranged alternately. Fig.10 is schematically shown in Fig.10 In the example of FIG. 1 , the conductor tracks 30 , 36 having a first potential are marked with a diamond pattern, while the conductor tracks 32 , 34 having a second potential are marked with a dot design. Fig.10 In the example of FIG. 1 , the first conductor track 30 and the third conductor track 34 each include two taps. The second conductor track 32 and the fourth conductor track 36 each include one tap. The taps may correspond to Figure 1 The second end portion 141 of the terminal element 14. Fig.10 In the example of FIG. 1 , the taps extend in the vertical direction y. However, this is only an example. The taps may be bent later so that they extend in the first horizontal direction x, similar to Figure 1 The second end 141 of the terminal element 14 is provided. This generally makes it easier to contact the tap. For example, each tap may include a hole. A screw can be inserted into each hole in the tap to electrically contact the conductor rail.

[0060] According to an example, one of the plurality of contact pieces can be coupled to at least one tap of the first conductor track 30, another of the plurality of contact pieces can be coupled to at least one tap of the second conductor track 32, another of the plurality of contact pieces can be coupled to at least one tap of the third conductor track 34, and another of the plurality of contact pieces can be coupled to at least one tap of the fourth conductor track 36. The contact pieces can be arranged in different layers above the housing of the power semiconductor module device. The contact pieces can be arranged parallel to the top surfaces of the plurality of semiconductor substrates 10.

[0061] FIG. 12 , FIG. 13 and FIG. 14 exemplarily show Figure 4 Different layers of the contact strips in an arrangement of , ie, in which two half-bridge modules 20 are arranged on both sides of a common collector module 22 . Fig. 12A Schematically shows the Figure 4 Used in devices Figures 5 to 7 The first layer of contact pieces of the common collector module includes two contact pieces, the first contact piece electrically contacts the taps to be connected to the output node 3, and the second contact piece electrically contacts the taps to be connected to the first power supply node 1. Fig. 12A The two contact pieces in the device are rectangular contact pieces. Figures 8 to 10 The common collector module 22, then Figure 4 The contact pads in the devices are of different types. Fig. 12B The first contact piece in this example is T-shaped, while the second contact piece is U-shaped. The T-shape of the first contact piece results from the alternating arrangement of taps of different potentials (see Fig.10 ). In FIG. 12 , the taps (or second ends 141 ) electrically coupled to corresponding contact pads are marked with circles representing holes in the taps.

[0062] The second layer may include a single third contact pad for electrically contacting those taps to be connected to the fourth neutral node 4. Fig.13A and Fig. 13B As shown in Figures 5 to 7 The common collector module 22 device (see Fig.13A ) compared to using Figures 8 to 10 The common collector module 22 (see Fig. 13B ), the size of the rectangular contact piece increases. This again stems from Figures 8 to 10 The taps are alternately arranged within the common-collector module 22.

[0063] The third layer may include another fourth contact pad for electrically contacting those taps to be connected to the second input node 2. Fig.14A (When using Figures 5 to 7 device) and Fig. 14B (When using Figures 8 to 10It can be seen that the fourth contact piece electrically contacts the half-bridge module 20, but does not electrically contact the common collector module 22. However, for different devices, the size of the fourth contact piece can still be different.

[0064] Use Figures 5 to 7 The common collector module device is compared to the use of Figures 8 to 10 The electrical contacting can be slightly more complicated when using a common collector module 22. However, the increased complexity is acceptable in terms of reduced stray inductance.

[0065] Reference now Fig.15 , in use Figures 5 to 7 The common collector module 22 is exemplarily shown Figure 3 For example, the resulting stray inductance in the upper path between the first power supply node 1 and the fourth neutral node 4 may be about 33.6 nH. For example, the resulting stray inductance in the lower path between the fourth neutral node 4 and the second input node 2 may be about 34.1 nH.

[0066] Reference now Fig.16 , in use Figures 8 to 10 The common collector module 22 is shown as an example. Figure 3 For example, the resulting stray inductance in the upper path between the first power supply node 1 and the fourth neutral node 4 may be about 14.7 nH. For example, the resulting stray inductance in the lower path between the fourth neutral node 4 and the second input node 2 may be about 15.6 nH. It can be seen that Fig.16 The stray inductance of the device is less than Fig.15 half of the stray inductance in the device.

[0067] The same applies to Fig.17 and Fig.18 device, in which Fig.17 An example is shown in which the Figures 5 to 7 The common collector module is 22 hours Figure 2 the current path in the device, and Fig.18 An example is shown in which the Figure 8 The common collector module is 22 hours Figure 2 The current path in the device. Fig.17 , the resulting stray inductance in the upper path may be about 57.7 nH, and the resulting stray inductance in the lower path may be about 58.2 nH. Fig.18 , the resulting stray inductance in the upper path is about 25.1nH, and the resulting stray inductance in the lower path can be about 26.6nH. Figures 8 to 10 The common collector module 22 can also reduce the stray inductance by at least half.

[0068] In addition, Figure 2 or Figure 3 Used in devices Figures 8 to 10 The common collector module 22, with Figures 5 to 7 Compared with the device of FIG. 1 , the turn-on characteristics of the third switch S3 and the fourth switch S4 can be improved. Fig.19 and Fig. 20 It is schematically illustrated in the graph shown in . Fig.19 According to Figure 6 Different substrates 10 of semiconductor devices schematically illustrate the collector current I c , Collector-emitter voltage V ce and the gate-emitter voltage V ge It can be seen that the scattering between different substrates is relatively large, especially for the collector current I c For the two ( Fig.19 The solid and dashed lines in the top graph of ), the collector current I c Quite low. Collector current I c Depends on the corresponding gate-emitter voltage V ge . Gate-emitter voltage V ge The switching loss in the switch is generally related to the collector current I c Therefore, with a higher collector current I c Such a substrate 10 produces higher switching losses and, therefore, generates more heat.

[0069] Fig. 20 According to Fig. 9 Different substrates 10 of semiconductor devices schematically illustrate the collector current I c , Collector-emitter voltage V ce and the gate-emitter voltage V ge It can be seen that Figure 6 Compared with the device with c .like Fig. 20 As shown in Fig. 9 The current distribution in the device is more uniform. Therefore, the switching behaviors of switches on different semiconductor substrates 10 are also more uniform.

Claims

1. A semiconductor substrate (10), comprising: A dielectric insulating layer (11) and a structured first metallization layer (111) attached to the dielectric insulating layer (11); a first switching element (S3), the first switching element (S3) comprising a first load path between a first emitter terminal (E3) and a first collector terminal (C3); a second switching element (S4), the second switching element (S4) comprising a second load path between a second emitter terminal (E4) and a second collector terminal (C4); a first diode element (D3), the first diode element (D3) comprising a first anode terminal and a first cathode terminal; as well as a second diode element (D4), the second diode element (D4) comprising a second anode terminal and a second cathode terminal, wherein The first metallization layer (111) comprises at least five independent sections (111) electrically insulated from each other. nm ), The first switching element (S3), the second switching element (S4), the first diode element (D3) and the second diode element (D4) are arranged on a first section (1112) of the first metallization layer (111), wherein the first collector terminal (C3), the second collector terminal (C4), the first cathode terminal and the second cathode terminal are electrically coupled to the first section (1112), The first anode terminal and the first emitter terminal (E3) are electrically coupled to each other and further electrically coupled to a second section (111) of the first metallization layer (111). 12 ) and the third section (111 32 ), The second anode terminal and the second emitter terminal (E4) are electrically coupled to each other and further electrically coupled to the fourth section (111) of the first metallization layer (111). 11 ) and the fifth section (111 31 ), The second section and the fourth section (111 12 ,111 11 ) are arranged adjacent to each other, The third section and the fifth section (111 32 ,111 31 ) are arranged adjacent to each other, and The first segment (1112) separates the second segment and the fourth segment (111 12 ,111 11 ) and the third section and the fifth section (111 32 ,111 31 ) separated by .

2. The semiconductor substrate (10) according to claim 1, wherein A first conductive connection layer (130) is arranged between the first collector terminal (C3) and the first section (1112); A second conductive connection layer (130) is arranged between the second collector terminal (C4) and the first section (1112); A third conductive connection layer (130) is arranged between the first cathode terminal and the first section (1112); and A fourth electrically conductive connection layer (130) is arranged between the second cathode terminal and the first section (1112).

3. The semiconductor substrate (10) according to claim 1 or 2, wherein The following electrical connection includes at least one bonding wire (60): the electrical connection electrically connects the first anode terminal and the first emitter terminal (E3) to each other and is further electrically connected to the second section (111) of the first metallization layer (111) 12 ) and the third section (111 32 ),and The following electrical connection includes at least one bonding wire (60): the electrical connection electrically connects the second anode terminal and the second emitter terminal (E4) to each other and is further electrically connected to the fourth section (111) of the first metallization layer (111) 11 ) and the fifth section (111 31 ).

4. The semiconductor substrate (10) according to claim 1 or 2, wherein: Each of the first switching element (S3) and the second switching element (S4) includes a transistor device, and wherein the transistor device is implemented as a MOSFET or an IGBT.

5. The semiconductor substrate (10) according to claim 1, wherein: The second section (111 12 ) and the third section (111 32 ) have the same first potential and are arranged at opposite ends of the semiconductor substrate (10).

6. The semiconductor substrate (10) according to claim 5, wherein: The fourth section (111 11 ) and the fifth section (111 31 ) have the same second potential and are arranged at opposite ends of the semiconductor substrate (10), wherein the second potential is different from the first potential.

7. A semiconductor device comprising a plurality of semiconductor substrates (10) according to any one of claims 1 to 6, wherein The plurality of semiconductor substrates (10) are arranged in a row, so that the first sections (1112) of the first metallization layers (111) of the plurality of semiconductor substrates (10) are arranged in a first row, and the second sections (1112) of the first metallization layers (111) of the plurality of semiconductor substrates (10) are arranged in a first row. 12 ) and the third section (111 32 ) are arranged in a second row parallel to the first row, and the fourth sections (111) of the first metallization layers (111) of the plurality of semiconductor substrates (10) are 11 ) and the fifth section (111 31 ) are arranged in a third row parallel to the first row and the second row.

8. The semiconductor device according to claim 7, wherein The second section (111) of the first metallization layer (111) of the plurality of semiconductor substrates (10) 12 ) and the third section (111 32 ) are arranged alternately within the second row; and The fourth section (111) of the first metallization layer (111) of the plurality of semiconductor substrates (10) 11 ) and the fifth section (111 31 ) are arranged alternately within the third row.

9. The semiconductor device according to claim 7 or 8, further comprising: A first conductor track (30) electrically connecting the second sections (111) of the plurality of semiconductor substrates (10) 12 ); A second conductor track (32) electrically connecting the fifth section (111) of the plurality of semiconductor substrates (10) 31 ); A third conductor track (34) electrically connecting the fourth sections (111) of the plurality of semiconductor substrates (10) 11 ); as well as A fourth conductor track (36) electrically connecting the third sections (111) of the plurality of semiconductor substrates (10) 32 ).

10. The semiconductor device according to claim 7 or 8, further comprising a substrate (12), wherein: The plurality of semiconductor substrates (10) are arranged on the base plate (12).

11. The semiconductor device according to claim 10, wherein The base plate (12) forms the bottom of the housing (17) or is arranged inside the housing (17).

12. The semiconductor device according to claim 9, wherein: Each of the first conductor track (30), the second conductor track (32), the third conductor track (34) and the fourth conductor track (36) comprises at least one tap for electrically contacting the respective conductor track (30, 32, 34, 36).

13. The semiconductor device according to claim 9, wherein: The third conductor track (34) and the second conductor track (32) are arranged between the first conductor track (30) and the fourth conductor track (36), The distance between the first conductor track (30) and the third conductor track (34) in a first horizontal direction (x) is significantly smaller than the distance between the third conductor track (34) and the second conductor track (32) in the same direction, and The distance between the second conductor track (32) and the fourth conductor track (36) in the first horizontal direction (x) is significantly smaller than the distance between the third conductor track (34) and the second conductor track (32) in the same direction.

14. The semiconductor device according to claim 13, wherein The distance between the first conductor rail (30) and the third conductor rail (34) in the first horizontal direction (x) is less than 50%, less than 30% or less than 15% of the distance between the third conductor rail (34) and the second conductor rail (32) in the same direction, and The distance between the second conductor rail (32) and the fourth conductor rail (36) in the first horizontal direction (x) is less than 50%, less than 30% or less than 15% of the distance between the third conductor rail (34) and the second conductor rail (32) in the same direction.

15. A semiconductor module, comprising: A plurality of semiconductor devices, each of the plurality of semiconductor devices comprising: a first switching element (S3), the first switching element (S3) comprising a first load path between a first emitter terminal (E3) and a first collector terminal (C3); a second switching element (S4), the second switching element (S4) comprising a second load path between a second emitter terminal (E4) and a second collector terminal (C4); a first diode element (D3) comprising a first anode terminal and a first cathode terminal; and a second diode element (D4), the second diode element (D4) comprising a second anode terminal and a second cathode terminal, wherein The first collector terminal (C3), the second collector terminal (C4), the first cathode terminal and the second cathode terminal are electrically coupled to each other, the first anode terminal and the first emitter terminal (E3) are electrically coupled to each other, and the second anode terminal and the second emitter terminal (E4) are electrically coupled to each other, and the semiconductor module further includes: a first conductor track (30) electrically coupled to the first anode terminals and the first emitter terminals (E3) of the plurality of semiconductor devices, a second conductor track (32) electrically coupled to the second anode terminals and the second emitter terminals (E4) of the plurality of semiconductor devices, a third conductor track (34) electrically coupled to the first anode terminals and the first emitter terminals (E3) of the plurality of semiconductor devices, and a fourth conductor track (36) electrically coupled to the second anode terminals and the second emitter terminals (E4) of the plurality of semiconductor devices, wherein A distance between the first conductor track (30) and the third conductor track (34) is shorter than a distance between the third conductor track (34) and the second conductor track (32), wherein the second conductor track is arranged between the third conductor track (34) and the fourth conductor track (36).

16. The semiconductor module according to claim 15, wherein: Each of the first conductor track (30), the second conductor track (32), the third conductor track (34) and the fourth conductor track (36) comprises at least one tap for electrically contacting the respective conductor track (30, 32, 34, 36). 17 . The semiconductor module according to claim 15 , further comprising a first substrate, the first substrate comprising a structured first metallization layer, wherein: The switching element and the diode element of at least a first one of the plurality of semiconductor devices are arranged on the first metallization layer.

18. The semiconductor module according to claim 17, further comprising a second substrate, the second substrate comprising a structured second metallization layer, wherein The switching element and the diode element of a second one of the plurality of semiconductor devices are arranged on the second metallization layer.

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