A current switch driver for high-speed DACs

Abstract

The present invention discloses a current switch driver suitable for high-speed DAC, which is composed of a synchronous latch circuit, a limit low crossover circuit and a current switch circuit; the synchronous latch circuit of the synchronous latch circuit inputs a sampling clock signal CLK and an input signal VIN; the synchronous latch circuit of the synchronous latch circuit inputs a synchronous latch signal D P and D N The output ends are connected to the synchronous latch signal D of the limit low crossover circuit P and D N Input terminal; Switch drive signal DS of the limiting low crossover circuit P and DS N The output ends are connected to the switch drive signal DS of the current switch circuit P and DS N The input terminal is connected; the current switch circuit outputs the output signal OUT P and OUT N The present invention can effectively reduce the switching signal amplitude and the switching signal cross point, and reduce the layout area.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a current switch driver suitable for a high-speed DAC. Background Art

[0002] With the rapid development of digital signal processing technology, electronic systems have put forward higher requirements for the speed and accuracy of D / A converters. High-speed and high-precision D / A converters are crucial components in military electronic systems. Their performance has become the bottleneck of military communications, radar, electronic countermeasures and other weapon systems. Their performance indicators directly determine the bandwidth and signal quality of wireless transmission systems.

[0003] The current steering DAC is an ideal structure for high-speed DACs, and the current switch driver is an important factor affecting the dynamic performance of high-speed DACs. The factors affecting the dynamic performance of high-speed DACs by the current switch driver are mainly the following: The first is the asynchrony of the current switch drive signal. During the transmission of the signal, the current steering DAC has inconsistent transmission line lengths and signal delays caused by parasitic capacitance in the circuit, which makes the time for the digital control signal to reach the current source switch inconsistent, which will cause burrs in the output signal and affect the dynamic performance of the DAC. The second is the clock feedthrough of the current switch drive signal. When the drive signal switches between high and low levels at high speed, the drive signal is capacitively coupled with the current switch output, causing the output voltage of the output current source to float. For DACs that do not include a correction circuit, burrs will be generated at the instant of the voltage drop on the output load resistor. The third is the simultaneous shutdown of the current switch. When the rise time and fall time of the differential drive signal are exactly the same, when the drive signal switches between high and low levels, the PMOS current switch will be turned off at the same time, causing the output current of the current source to be turned off instantly, causing burrs in the output current of the DAC. The fourth is the signal swing. Generally speaking, the signals from the previous modules are digital, and their voltage swing varies from ground to power supply voltage level. Therefore, when these signals are directly applied to the switch, the switching speed is limited and the power consumption increases.

[0004] In response to the above problems, many papers have proposed many solutions, such as adding a pre-conduction tube to the low cross-point circuit to make the output signal drop more smoothly, thereby improving the asymmetry of the switch signal, adding a signal feedthrough compensation circuit to improve the clock feedthrough effect, etc. However, this will also make the circuit more complicated. In addition, the traditional switch drive circuit adds a limiter circuit after the signal low cross-point circuit, which increases the area of ​​the circuit. Summary of the invention

[0005] The present invention aims to solve the problems of asymmetric driving switch signals, low conversion rate and excessive layout area of ​​traditional current switch drivers, and provides a current switch driver suitable for high-speed DAC, which can effectively reduce the switch signal amplitude and switch signal crossover point.

[0006] To solve the above problems, the present invention is achieved through the following technical solutions:

[0007] A current switch driver suitable for high-speed DAC, comprising a synchronous latch circuit, a limit low crossover circuit and a current switch circuit; a sampling clock signal CLK is input to an input end of the synchronous latch circuit; an input signal VIN is input to an input end of the synchronous latch circuit; a synchronous latch signal D P The output terminal of the limiter low crossover circuit is synchronously latched with the signal D P The input terminal of the synchronous latch circuit is connected; the synchronous latch signal D N The output terminal of the limiter low crossover circuit is synchronously latched with the signal D N The input terminal is connected; the switch drive signal DS of the limiting low crossover circuit P The output terminal of the current switch circuit is connected to the switch drive signal DS P The input terminal is connected; the switch drive signal DS of the limiting low crossover circuit N The output terminal of the current switch circuit is connected to the switch drive signal DS N The output signal OUT of the current switch circuit P The output terminal outputs the output signal OUT P ; Output signal OUT of the current switching circuit N The output terminal outputs the output signal OUT N .

[0008] The above-mentioned synchronous latch circuit includes PMOS transistors P1-P2, and inverters INV1-INV7; the gate of the PMOS transistor P1 is connected to the gate of the PMOS transistor P2, and forms the input end of the sampling clock signal CLK of the synchronous latch circuit; the input end of the inverter INV1 is connected to the input end of the inverter INV3, and forms the input end of the input signal VIN of the synchronous latch circuit; the output end of the inverter INV1 is connected to the source of the PMOS transistor P1 via the inverter INV2; the output end of the inverter INV3 is connected to the drain of the PMOS transistor P2; the drain of the PMOS transistor P1, the input end of the inverter INV4, the output end of the inverter INV5 and the input end of the inverter INV6 are connected; the output end of the inverter INV6 forms the synchronous latch signal D of the synchronous latch circuit PThe output terminal of the PMOS transistor P2, the output terminal of the inverter INV4, the input terminal of the inverter INV5 and the input terminal of the inverter INV7 are connected; the output terminal of the inverter INV7 forms a synchronous latch signal D of the synchronous latch circuit N The output terminal.

[0009] The above-mentioned clipping low crossover circuit includes PMOS transistors P3-P6 and NMOS transistors N1-N4; the gate of the PMOS transistor P3 is connected to the gate of the NMOS transistor N1, and forms a synchronous latch signal D of the clipping low crossover circuit. P After the drain of the PMOS transistor P3, the drain of the NMOS transistor N1, the drain of the NMOS transistor N3, and the drain and gate of the PMOS transistor P5 are connected, a switch drive signal DS is formed to form a limited low crossover circuit P The gate of the PMOS transistor P4 is connected to the gate of the NMOS transistor N2, and forms a synchronous latch signal D of the limiter low crossover circuit N the drain of the PMOS transistor P4, the drain of the NMOS transistor N2, the drain of the NMOS transistor N4, and the drain and gate of the PMOS transistor P6, forming a switch drive signal DS forming a limiter low crossover circuit N The source of the PMOS transistor P3, the source and gate of the NMOS transistor N3, the source of the PMOS transistor P4, and the source and gate of the NMOS transistor N4 are simultaneously connected to the power supply VDD; the source of the NMOS transistor N1, the source of the PMOS transistor P5, the source of the NMOS transistor N2, and the source of the PMOS transistor P6 are simultaneously connected to the ground GND.

[0010] The current switch circuit comprises PMOS transistors P7-P8, resistors R1-R2, and a current source; the gate of the PMOS transistor P7 forms a switch drive signal DS of the current switch circuit. P The source of the PMOS transistor P7 is connected to one end of the resistor R1, and forms an output signal OUT of the current switch circuit. P The gate of the PMOS transistor P8 forms a switch drive signal DS of the current switch circuit N The source of the PMOS transistor P8 is connected to one end of the resistor R2, and forms an output signal OUT of the current switch circuit. N The drain of the PMOS transistor P7 and the drain of the PMOS transistor P8 are connected to each other and then connected to the power supply VDD via a current source; the other end of the resistor R1 and the other end of the resistor R2 are grounded GND at the same time.

[0011] Compared with the prior art, the present invention has the following characteristics:

[0012] 1. It can control the switch signal to achieve both a low crossover point and a reduced amplitude.

[0013] 2. It can make the control switch signal have better symmetry and significantly reduce the output burrs.

[0014] 3. Compared with other switch drive circuits, this circuit uses fewer devices and reduces the layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of a current switch driver suitable for high-speed DAC.

[0016] Figure 2 DS is the switch drive signal for the low crossover circuit P and DS N Waveform diagram of .

[0017] Figure 3 The output signal OUT of the current switch circuit P and OUT N Waveform diagram of . DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific examples.

[0019] See also Figure 1 , a current switch driver suitable for high-speed DAC, composed of a synchronous latch circuit, a limit low crossover circuit and a current switch circuit. The sampling clock signal CLK is input to the input terminal of the synchronous latch circuit. The input signal VIN is input to the input terminal of the synchronous latch circuit. The synchronous latch signal D of the synchronous latch circuit P The output terminal of the limiter low crossover circuit is synchronously latched with the signal D P The synchronous latch signal D of the synchronous latch circuit N The output terminal of the limiter low crossover circuit is synchronously latched with the signal D N The input terminal of the limiter low crossover circuit switch drive signal DS P The output terminal of the current switch circuit is connected to the switch drive signal DS P The input terminal of the limiter low crossover circuit switch drive signal DS N The output terminal of the current switch circuit is connected to the switch drive signal DS N The output signal OUT of the current switch circuit P The output terminal outputs the output signal OUT P The output signal OUT of the current switch circuitN The output terminal outputs the output signal OUT N .

[0020] The synchronous latch circuit includes PMOS transistors P1-P2, and inverters INV1-INV7. The gate of the PMOS transistor P1 is connected to the gate of the PMOS transistor P2, and forms the input end of the sampling clock signal CLK of the synchronous latch circuit. The input end of the inverter INV1 is connected to the input end of the inverter INV3, and forms the input end of the input signal VIN of the synchronous latch circuit. The output end of the inverter INV1 is connected to the source of the PMOS transistor P1 via the inverter INV2. The output end of the inverter INV3 is connected to the drain of the PMOS transistor P2. The drain of the PMOS transistor P1, the input end of the inverter INV4, the output end of the inverter INV5 and the input end of the inverter INV6 are connected. The output end of the inverter INV6 forms the synchronous latch signal D of the synchronous latch circuit. P The source of the PMOS transistor P2, the output of the inverter INV4, the input of the inverter INV5 and the input of the inverter INV7 are connected. The output of the inverter INV7 forms a synchronous latch signal D of the synchronous latch circuit. N The output terminal.

[0021] The clipping low crossover circuit includes PMOS transistors P3-P6 and NMOS transistors N1-N4. The gate of the PMOS transistor P3 is connected to the gate of the NMOS transistor N1 and forms a synchronous latch signal D of the clipping low crossover circuit. P The drain of the PMOS transistor P3, the drain of the NMOS transistor N1, the drain of the NMOS transistor N3, and the drain and gate of the PMOS transistor P5 are connected to form a switch drive signal DS that forms a limited low crossover circuit. P The gate of the PMOS transistor P4 is connected to the gate of the NMOS transistor N2, and forms a synchronous latch signal D of the limit low crossover circuit. N The drain of the PMOS transistor P4, the drain of the NMOS transistor N2, the drain of the NMOS transistor N4, and the drain and gate of the PMOS transistor P6 are connected to form a switch drive signal DS that forms a limited low crossover circuit. N The source of the PMOS transistor P3, the source and gate of the NMOS transistor N3, the source of the PMOS transistor P4, and the source and gate of the NMOS transistor N4 are simultaneously connected to the power supply VDD. The source of the NMOS transistor N1, the source of the PMOS transistor P5, the source of the NMOS transistor N2, and the source of the PMOS transistor P6 are simultaneously connected to the ground GND.

[0022] The current switch circuit includes PMOS transistors P7-P8, resistors R1-R2, and a current source. The gate of the PMOS transistor P7 forms a switch drive signal DS of the current switch circuit. P The source of the PMOS transistor P7 is connected to one end of the resistor R1 and forms the output signal OUT of the current switch circuit. P The gate of the PMOS transistor P8 forms the switch drive signal DS of the current switch circuit. N The source of the PMOS transistor P8 is connected to one end of the resistor R2 and forms the output signal OUT of the current switch circuit. N The drain of the PMOS transistor P7 and the drain of the PMOS transistor P8 are connected to each other and then connected to the power source VDD via a current source. The other end of the resistor R1 and the other end of the resistor R2 are both grounded to GND.

[0023] The working principle of the above-mentioned current switch driver suitable for high-speed DAC is as follows:

[0024] The input terminal of the synchronous latch circuit is connected to the input signal VIN input by other modules. After the input signal VIN passes through the inverters INV1-INV3, a pair of opposite signals are formed. The opposite signals enter the PMOS transistors P1 and P2 respectively. The sampling clock CLK controls the switch conduction of the PMOS transistors P1 and P2 to synchronize the two signals. Inverters INV4 and INV5 form a synchronous latch, and then pass through inverters INV6 and INV7 respectively to output the synchronous latch signal D P and D N .

[0025] Synchronous latch signal D P and D N Entering the limiting low crossover circuit, a low crossover point is obtained, the amplitude is reduced, and a switch drive signal DS with better symmetry is output. P and DS N When the synchronous latch signal D P is logic level "1", synchronous latch signal D N When the logic level is "0", NMOS transistor N1 is turned on, PMOS transistor P3 remains off, and most of the current flows from VDD through NMOS transistor N3 and NMOS transistor N1 to the ground, pulling the output to a low level. P is logic level "0", synchronous latch signal D N When the logic level is "1", the NMOS transistor N1 is turned off, the PMOS transistor P3 is turned on, and most of the current flows from VDD through the PMOS transistor P3 and the PMOS transistor P5 to the ground, pulling the output to a high level.

[0026] Switch drive signal DS P and DS N Entering the current switching circuit, the switch driving signal DS P and DS N Control the on and off of PMOS transistors P7 and P8 to output the current of the current source and obtain the output signal OUT P and OUT N .

[0027] for Figure 1 A current switch driver suitable for high-speed DAC is shown, NMOS tubes N1-N4 are NMOS tubes with a standard voltage of 1.8V, PMOS tubes P1-P8 are PMOS transistors with a standard voltage of 1.8V, and are designed using a 0.18μm process.

[0028] When the input signal VIN cycle is 4ns, the high level is 1.8v, the low level is 0v square wave signal, the sampling clock signal CLK cycle is 2ns, the high level is 1.8v, the low level is 0v, and the power supply voltage is 1.8v, the switch drive signal DS of the limit low crossover circuit P and DS N The waveform is as Figure 2 As shown, the output signal OUT of the current switch circuit P and OUT N The waveform is as Figure 3 As shown. Figure 2 It can be seen that the signal amplitude drops to 1.18V, the low crossover point of the switch signal is 389.9mv, and the switch signal has good symmetry. Figure 3 It can be seen that the output current glitch is improved.

[0029] It should be noted that, although the embodiments of the present invention described above are illustrative, they are not intended to limit the present invention, and therefore the present invention is not limited to the above specific embodiments. Without departing from the principles of the present invention, any other embodiments obtained by those skilled in the art under the guidance of the present invention are deemed to be within the protection of the present invention.

Claims

1. A current switch driver suitable for high-speed DAC, characterized in that: It consists of a synchronous latch circuit, a limit low crossover circuit and a current switch circuit; The sampling clock signal CLK is input into the input terminal of the sampling clock signal CLK of the synchronous latch circuit; The input terminal of the synchronous latch circuit receives the input signal VIN; Synchronous latch signal D of synchronous latch circuit P The output terminal of the limiter low crossover circuit is synchronously latched with the signal D P The input terminal of the synchronous latch circuit is connected; the synchronous latch signal D N The output terminal of the limiter low crossover circuit is synchronously latched with the signal D N The input terminal connection of The switch drive signal DS of the limiting low crossover circuit P The output terminal of the current switch circuit is connected to the switch drive signal DS P The input terminal is connected; the switch drive signal DS of the limiting low crossover circuit N The output terminal of the current switch circuit is connected to the switch drive signal DS N The input terminal connection of The clipping low crossover circuit includes PMOS transistors P3-P6 and NMOS transistors N1-N4; the gate of the PMOS transistor P3 is connected to the gate of the NMOS transistor N1, and forms a synchronous latch signal D of the clipping low crossover circuit. P After the drain of the PMOS transistor P3, the drain of the NMOS transistor N1, the drain of the NMOS transistor N3, and the drain and gate of the PMOS transistor P5 are connected, a switch drive signal DS is formed to form a limited low crossover circuit P The gate of the PMOS transistor P4 is connected to the gate of the NMOS transistor N2, and forms a synchronous latch signal D of the limiter low crossover circuit N the drain of the PMOS transistor P4, the drain of the NMOS transistor N2, the drain of the NMOS transistor N4, and the drain and gate of the PMOS transistor P6, forming a switch drive signal DS forming a limiter low crossover circuit N The source of the PMOS transistor P3, the source and gate of the NMOS transistor N3, the source of the PMOS transistor P4, and the source and gate of the NMOS transistor N4 are simultaneously connected to the power supply VDD; the source of the NMOS transistor N1, the source of the PMOS transistor P5, the source of the NMOS transistor N2, and the source of the PMOS transistor P6 are simultaneously connected to the ground GND; The output signal OUT of the current switch circuit P The output terminal outputs the output signal OUT P ; Output signal OUT of the current switching circuit N The output terminal outputs the output signal OUT N .

2. A current switch driver suitable for high-speed DAC according to claim 1, characterized in that: The synchronous latch circuit includes PMOS transistors P1-P2 and inverters INV1-INV7; The gate of the PMOS transistor P1 is connected to the gate of the PMOS transistor P2 and forms an input terminal of the sampling clock signal CLK of the synchronous latch circuit; The input end of the inverter INV1 is connected to the input end of the inverter INV3 and forms the input end of the input signal VIN of the synchronous latch circuit; The output end of the inverter INV1 is connected to the source of the PMOS transistor P1 via the inverter INV2; the output end of the inverter INV3 is connected to the drain of the PMOS transistor P2; The drain of the PMOS transistor P1, the input end of the inverter INV4, the output end of the inverter INV5 and the input end of the inverter INV6 are connected; the output end of the inverter INV6 forms a synchronous latch signal D of the synchronous latch circuit. P The output terminal; The source of the PMOS transistor P2, the output end of the inverter INV4, the input end of the inverter INV5 and the input end of the inverter INV7 are connected; the output end of the inverter INV7 forms a synchronous latch signal D of the synchronous latch circuit. N The output terminal.

3. A current switch driver suitable for high-speed DAC according to claim 1, characterized in that: The current switch circuit includes PMOS transistors P7-P8, resistors R1-R2, and a current source; The gate of the PMOS transistor P7 forms a switch drive signal DS of the current switch circuit. P The source of the PMOS transistor P7 is connected to one end of the resistor R1, and forms an output signal OUT of the current switch circuit. P The output terminal; The gate of the PMOS transistor P8 forms a switch drive signal DS of the current switch circuit. N The source of the PMOS transistor P8 is connected to one end of the resistor R2, and forms an output signal OUT of the current switch circuit. N The output terminal; The drain of the PMOS transistor P7 is connected to the drain of the PMOS transistor P8 and then connected to the power source VDD via a current source; The other end of the resistor R1 and the other end of the resistor R2 are both connected to the ground GND.

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