Buried three-dimensional metal-oxide field effect transistor and preparation method thereof

Abstract

The present invention provides a buried three-dimensional metal-oxide field effect transistor and a preparation method, the preparation method comprising: 1) providing a semiconductor substrate, etching at least one groove in the semiconductor substrate; 2) forming a gate dielectric layer on the surface of the groove and the surface of the semiconductor substrate, forming a gate electrode layer on the gate dielectric layer, and etching the gate electrode layer and the gate dielectric layer to form a gate structure, the gate structure intersecting the groove; 3) forming a source region and a drain region in the semiconductor substrate on both sides of the gate structure, the groove connecting or overlapping the source region and the drain region. The present invention forms a groove under the gate between the source region and the drain region, changes the channel of the gate from two-dimensional to three-dimensional, can increase the gate channel width without changing the channel length, and improve the device performance of the MOSFET.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor integrated circuit design and manufacture, and in particular relates to a buried three-dimensional metal-oxide field effect transistor and a preparation method thereof. Background Art

[0002] As the size of the device decreases, when the MOS tube channel is shortened to a certain extent, the short channel effect will appear, which is mainly manifested in the velocity saturation of the carriers in the MOS tube channel. When the MOS tube channel is long and the electric field is small, the carrier velocity is proportional to the electric field, that is, the carrier mobility is a constant. However, when the channel electric field intensity is very high, the carrier velocity will tend to saturation due to the scattering effect. The general short channel effect includes:

[0003] 1) The threshold voltage changes with the decrease of channel length and the narrowing of channel length. For short channel MOS devices, the threshold voltage decreases as the channel length decreases; for narrow channel MOS devices, the threshold voltage increases as the channel width decreases.

[0004] 2) The channel electric field increases as the channel becomes shorter, resulting in a mobility modulation effect, which saturates the carrier velocity, and reduces the saturated drain-source voltage and saturated drain current compared to the theoretical values ​​of a long channel.

[0005] 3) Subthreshold characteristics deteriorate, for example: short channel and narrow channel effects that affect threshold voltage. When the channel length is reduced to a certain extent, the proportion of the depletion region of the source and drain junctions in the entire channel increases, and the amount of charge required to form an inversion layer on the silicon surface under the gate decreases, so the threshold voltage decreases. At the same time, the charge in the part of the depletion region in the substrate that is laterally widened along the channel width increases the threshold voltage. When the channel width is reduced to the same order of magnitude as the depletion layer width, the increase in threshold voltage becomes very significant. The threshold voltage of short channel devices is very sensitive to changes in channel length. Mobility field-related effect and carrier velocity saturation effect. Under low fields, the mobility is a constant, and the carrier velocity increases linearly with the electric field. Under high fields, the mobility decreases, and the carrier velocity reaches saturation and is no longer related to the electric field. The impact of velocity saturation on the device is that the drain saturation current is greatly reduced, and the relationship between the saturation current and the gate voltage is no longer a near-square relationship in long channel devices, but a linear relationship. Hot carrier effect that affects device life As the device size enters the deep submicron channel length range, the electric field strength inside the device increases with the decrease in device size. In particular, there is a strong electric field near the drain junction. Carriers gain higher energy in this strong electric field and become hot carriers. Hot carriers can easily cross the Si-SiO 2Potential barriers are injected into the oxide layer, accumulating continuously, changing the threshold voltage and affecting the device life; in the depletion region near the drain, they collide with the lattice to generate electron-hole pairs. For NMOS tubes, the electrons generated by the collision form additional leakage current, and the holes are collected by the substrate to form substrate current, making the total current the sum of the saturated leakage current and the substrate current. The larger the substrate current, the more collisions occur in the channel, and the more serious the corresponding hot carrier effect. The hot carrier effect is one of the basic factors that limit the maximum operating voltage of the device.

[0006] 4) Subthreshold characteristics degrade, device clamping is continuous, and subthreshold leakage current makes the off-state characteristics of MOSFET devices worse, and static power consumption increases. In dynamic circuits and storage cells, it may also cause confusion in the logic state. Therefore, the drain-induced barrier lowering effect caused by the short channel becomes a basic physical effect that determines the size limit of short-channel MOS devices.

[0007] In order to improve device performance, the industry usually uses high-K / metal gate to reduce gate thickness and increase saturation current; or to prepare fin field-effect transistors to increase channel surface area. Today, research on technologies below 40 nanometers is concentrated in the field of high metal gates, which have complex processes and are difficult to manufacture. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a buried three-dimensional metal-oxide field effect transistor and a preparation method thereof, so as to increase the gate channel width without changing the channel length, thereby improving the device performance of the MOSFET.

[0009] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for preparing a buried three-dimensional metal-oxide field effect transistor, the preparation method comprising the steps of: 1) providing a semiconductor substrate and etching at least one trench in the semiconductor substrate; 2) forming a gate dielectric layer on the surface of the trench and the surface of the semiconductor substrate, forming a gate electrode layer on the gate dielectric layer, and etching the gate electrode layer and the gate dielectric layer to form a gate structure; 3) forming a source region and a drain region in the semiconductor substrate on both sides of the gate structure, and both sides of the trench extend into the source region and the drain region; the lower end of the gate structure is filled in the trench, and the upper end of the gate structure intersects with the trench.

[0010] Optionally, the semiconductor substrate comprises a silicon substrate, and step 1) further comprises the step of annealing the silicon substrate in a hydrogen atmosphere to round the top and bottom corners of the trench.

[0011] Optionally, the gate dielectric layer includes a stack of one or both of a silicon dioxide layer and a silicon oxynitride layer, and the gate electrode layer includes a doped polysilicon layer.

[0012] Optionally, the gate dielectric layer includes a high-k dielectric layer, and the gate electrode layer includes a metal layer.

[0013] Optionally, the ion doping type of the source region and the drain region is n-type, and the ion doping type of the semiconductor substrate between the source region and the drain region is p-type.

[0014] Optionally, the ion doping type of the source region and the drain region is p-type, and the ion doping type of the semiconductor substrate between the source region and the drain region is n-type.

[0015] Optionally, the number of the grooves is not less than 2, the grooves are arranged in parallel, and the grooves are connected to or overlapped with the source region and the drain region.

[0016] The present invention also provides a buried three-dimensional metal-oxide field effect transistor, comprising: a semiconductor substrate, in which at least one trench is formed; a gate structure, comprising a gate dielectric layer formed on the surface of the trench and the surface of the semiconductor substrate, and a gate electrode layer formed on the gate dielectric layer; a source region and a drain region, formed in the semiconductor substrate on both sides of the gate structure, and both sides of the trench extend into the source region and the drain region; the lower end of the gate structure is filled in the trench, and the upper end of the gate structure intersects with the trench.

[0017] Optionally, the top corner and the bottom corner of the groove are rounded.

[0018] Optionally, the gate dielectric layer includes a stack of one or both of a silicon dioxide layer and a silicon oxynitride layer, and the gate electrode layer includes a doped polysilicon layer.

[0019] Optionally, the gate dielectric layer includes a high-k dielectric layer, and the gate electrode layer includes a metal layer.

[0020] Optionally, the ion doping type of the source region and the drain region is n-type, and the ion doping type of the semiconductor substrate between the source region and the drain region is p-type.

[0021] Optionally, the ion doping type of the source region and the drain region is p-type, and the ion doping type of the semiconductor substrate between the source region and the drain region is n-type.

[0022] Optionally, the number of the grooves is not less than 2, the grooves are arranged in parallel, and the grooves are connected to or overlapped with the source region and the drain region.

[0023] As described above, the buried three-dimensional metal-oxide field effect transistor and the preparation method of the present invention have the following beneficial effects:

[0024] The present invention forms a groove under the gate between the source region and the drain region, changes the gate channel from two-dimensional to three-dimensional, and can increase the gate channel width without changing the channel length, thereby improving the device performance of MOSFET.

[0025] After the trench etching is completed, the present invention uses high-temperature hydrogen annealing to round the corners, which can effectively eliminate the stress at the corners and improve the stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 to Figure 7 It is a schematic structural diagram showing the steps of the method for preparing a buried three-dimensional metal-oxide field effect transistor according to the present invention, wherein: Figure 6 Display as Figure 7 Schematic diagram of the cross-sectional structure at A-A'.

[0027] Component number description

[0028] 101 Semiconductor Substrate

[0029] 102 Isolation Structure

[0030] 103 Photoresist pattern

[0031] 104 Groove

[0032] 105 Round Corner

[0033] 106 gate dielectric layer

[0034] 107 gate electrode layer

[0035] 108 Source Area

[0036] 109 Leakage Area DETAILED DESCRIPTION

[0037] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0039] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0040] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0041] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0042] like Figure 1 to Figure 7 As shown, this embodiment provides a method for preparing a buried three-dimensional metal-oxide field effect transistor, the preparation method comprising the steps of:

[0043] like Figure 1 to Figure 4 As shown, step 1) is first performed to provide a semiconductor substrate 101 and to etch at least one trench 104 in the semiconductor substrate 101 .

[0044] The semiconductor substrate 101 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, a SOI substrate, a GOI substrate, a III-V group substrate, etc., and a suitable semiconductor material may be selected according to the actual needs of the device, and is not limited here. In this specific implementation, the substrate is a single crystal silicon substrate.

[0045] like Figure 1 As shown, an isolation structure 102, such as a shallow trench isolation structure, a local field oxide layer isolation structure, etc., can be first formed in the semiconductor substrate 101 to facilitate isolation between subsequent devices. The semiconductor substrate 101 can also first form a required well region (not shown) according to the type of MOS device.

[0046] When etching the groove 104, a photoresist pattern 103 may be firstly formed on the semiconductor substrate 101 by a photolithography process, such as Figure 2As shown, a dry etching process is then used to etch a groove 104 in the semiconductor substrate 101, as shown in FIG. Figure 3 As shown, of course, different etching processes can be used according to different aspect ratios of the trench 104, and the selection needs to be made according to actual needs.

[0047] It should be noted that the vertical depth of the trench 104 can be adjusted according to the device requirements, and the width of the trench 104 can also be adjusted according to the device requirements. For example, the depth of the trench 104 can be 10nm to 100nm, etc., and the width can be 5nm to 50nm, etc. The length of the trench 104 is set so that it is at least connected to the source region 108 and the drain region 109 formed subsequently, or partially or completely overlaps.

[0048] After etching the trench 104, in this embodiment, the step of annealing the silicon substrate in a hydrogen atmosphere to round the top and bottom corners of the trench 104 is also included. Figure 4 After the trench 104 is etched, the present invention uses high temperature hydrogen annealing to make the top and bottom corners become rounded corners 105, which can effectively eliminate the stress at the corners and improve the stability of the device, such as improving the performance of the device such as the breakdown voltage.

[0049] like Figure 5 As shown, step 2 is then performed to form a gate dielectric layer 106 on the surface of the trench 104 and the surface of the semiconductor substrate 101, a gate electrode layer 107 is formed on the gate dielectric layer 106, and the gate electrode layer 107 and the gate dielectric layer 106 are etched to form a gate structure, which intersects the trench 104.

[0050] In this embodiment, the gate dielectric layer 106 includes a stack of one or both of a silicon dioxide layer and a silicon oxynitride layer, and the gate electrode layer 107 includes a doped polysilicon layer.

[0051] In addition, in this embodiment, gate sidewalls may also be formed on both sides of the gate structure to protect the gate structure and further improve the isolation effect between the gate structure and the source and drain regions.

[0052] like Figure 6 and Figure 7 As shown, Figure 6 Display as Figure 7 Finally, step 3) is performed to form a source region 108 and a drain region 109 in the semiconductor substrate 101 on both sides of the gate structure, and the trench 104 is connected to or overlapped with the source region 108 and the drain region 109. Specifically, Figure 6 and Figure 7As shown, the lower end of the gate structure is filled in the trench 104 , and the upper end of the gate structure intersects the trench 104 .

[0053] Specifically, the gate structure is used as a mask to perform a self-aligned ion implantation process and an annealing process to form a source region 108 and a drain region 109 in the semiconductor substrate 101 at both sides of the gate structure.

[0054] In this embodiment, the ion doping type of the source region 108 and the drain region 109 is n-type, and the ion doping type of the semiconductor substrate 101 between the source region 108 and the drain region 109 is p-type.

[0055] like Figure 6 and Figure 7 As shown, this embodiment further provides a buried three-dimensional metal-oxide field effect transistor, the field effect transistor comprising: a semiconductor substrate 101, wherein at least one trench 104 is formed in the semiconductor substrate 101; a gate structure, comprising a gate dielectric layer 106 formed on the surface of the trench 104 and the surface of the semiconductor substrate 101 and a gate electrode layer 107 formed on the gate dielectric layer 106, wherein the gate structure intersects the trench 104; a source region 108 and a drain region 109 are formed in the semiconductor substrate 101 on both sides of the gate structure, and the trench 104 is connected to or overlaps with the source region 108 and the drain region 109. Specifically, as Figure 6 and Figure 7 As shown, the lower end of the gate structure is filled in the trench 104 , and the upper end of the gate structure intersects the trench 104 .

[0056] The semiconductor substrate 101 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, a SOI substrate, a GOI substrate, a III-V group substrate, etc., and a suitable semiconductor material may be selected according to the actual needs of the device, and is not limited here. In this specific implementation, the substrate is a single crystal silicon substrate.

[0057] like Figure 6 As shown, an isolation structure 102, such as a shallow trench isolation structure, a local field oxide layer isolation structure, etc., can be first formed in the semiconductor substrate 101 to facilitate isolation between subsequent devices. The semiconductor substrate 101 can also first form a required well region (not shown) according to the type of MOS device.

[0058] The top corner and the bottom corner of the groove 104 are rounded corners 105, so as to effectively eliminate the stress at the corners and improve the stability of the device, such as improving the performance of the device such as the breakdown voltage.

[0059] The gate dielectric layer 106 includes a stack of one or both of a silicon dioxide layer and a silicon oxynitride layer, and the gate electrode layer 107 includes a doped polysilicon layer.

[0060] In this embodiment, the ion doping type of the source region 108 and the drain region 109 is n-type, and the ion doping type of the semiconductor substrate 101 between the source region 108 and the drain region 109 is p-type.

[0061] The present invention forms a groove 104 below the gate between the source region 108 and the drain region 109, changing the gate channel from two-dimensional to three-dimensional, thereby increasing the gate channel width without changing the channel length and improving the device performance of the MOSFET.

[0062] Example 2

[0063] like Figure 6-7 As shown, this embodiment provides a buried three-dimensional metal-oxide field effect transistor and a preparation method thereof, wherein the basic structure and preparation method thereof are as in Embodiment 1, wherein the difference from Embodiment 1 is that: the number of the grooves 104 is not less than 2, the grooves 104 are arranged in parallel, and the grooves 104 are connected to or overlapped with the source region 108 and the drain region 109. By providing a plurality of grooves 104, this embodiment can further increase the gate channel width compared to Embodiment 1.

[0064] Example 3

[0065] like Figure 6-7 As shown, this embodiment provides a buried three-dimensional metal-oxide field effect transistor and a preparation method thereof, wherein the basic structure and preparation method thereof are as in Embodiment 1, wherein the difference from Embodiment 1 is that the gate dielectric layer 106 comprises a high-k dielectric layer, and the gate electrode layer 107 comprises a metal layer. This embodiment adopts a high-k metal gate structure, which can increase the physical thickness of the gate dielectric while keeping the gate capacitance unchanged, thereby achieving the purpose of reducing the gate leakage current and improving the reliability of the device.

[0066] Example 4

[0067] like Figure 6-7 As shown, this embodiment provides a buried three-dimensional metal-oxide field effect transistor and a preparation method, whose basic structure and preparation method are as in Example 1, wherein the difference from Example 1 is that the ion doping type of the source region 108 and the drain region 109 is p-type, and the ion doping type of the semiconductor substrate 101 between the source region 108 and the drain region 109 is n-type.

[0068] As described above, the buried three-dimensional metal-oxide field effect transistor and the preparation method of the present invention have the following beneficial effects:

[0069] The present invention forms a groove under the gate between the source region and the drain region, changes the gate channel from two-dimensional to three-dimensional, and can increase the gate channel width without changing the channel length, thereby improving the device performance of MOSFET.

[0070] After the trench etching is completed, the present invention uses high-temperature hydrogen annealing to round the corners, which can effectively eliminate the stress at the corners and improve the stability of the device.

[0071] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0072] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a buried three-dimensional metal-oxide field effect transistor, characterized in that: The preparation method comprises the steps of: 1) providing a semiconductor substrate, and etching at least one trench in the semiconductor substrate; 2) forming a gate dielectric layer on the surface of the trench and the surface of the semiconductor substrate, forming a gate electrode layer on the gate dielectric layer, and etching the gate electrode layer and the gate dielectric layer to form a gate structure; 3) forming a source region and a drain region in the semiconductor substrate on both sides of the gate structure, wherein both sides of the trench extend into the source region and the drain region; the lower end of the gate structure is filled in the trench, and the lower end of the gate structure extends into the source region and the drain region along the trench, and the upper end of the gate structure and the lower end of the gate structure are cross-shaped when viewed from a top view.

2. The method for preparing a buried three-dimensional metal-oxide field effect transistor according to claim 1, characterized in that: The semiconductor substrate comprises a silicon substrate, and step 1) further comprises the step of annealing the silicon substrate in a hydrogen atmosphere to round the top and bottom corners of the trench.

3. The method for preparing a buried three-dimensional metal-oxide field effect transistor according to claim 1, characterized in that: The gate dielectric layer includes a stack of one or both of a silicon dioxide layer and a silicon oxynitride layer, and the gate electrode layer includes a doped polysilicon layer.

4. The method for preparing a buried three-dimensional metal-oxide field effect transistor according to claim 1, characterized in that: The gate dielectric layer includes a high-k dielectric layer, and the gate electrode layer includes a metal layer.

5. The method for preparing a buried three-dimensional metal-oxide field effect transistor according to claim 1, characterized in that: The ion doping type of the source region and the drain region is n-type, and the ion doping type of the semiconductor substrate between the source region and the drain region is p-type.

6. The method for preparing a buried three-dimensional metal-oxide field effect transistor according to claim 1, characterized in that: The ion doping type of the source region and the drain region is p-type, and the ion doping type of the semiconductor substrate between the source region and the drain region is n-type.

7. The method for preparing a buried three-dimensional metal-oxide field effect transistor according to claim 1, characterized in that: The number of the grooves is not less than 2, the grooves are arranged in parallel, and the grooves overlap with the source region and the drain region.

8. A buried three-dimensional metal-oxide field effect transistor, characterized in that: include: a semiconductor substrate having at least one trench formed therein; A gate structure, comprising a gate dielectric layer formed on the surface of the trench and the surface of the semiconductor substrate and a gate electrode layer formed on the gate dielectric layer; The source region and the drain region are formed in the semiconductor substrate on both sides of the gate structure, and both sides of the trench extend into the source region and the drain region; the lower end of the gate structure is filled in the trench, and the lower end of the gate structure extends into the source region and the drain region along the trench, and the upper end of the gate structure and the lower end of the gate structure are cross-shaped when viewed from a top view.

9. The buried three-dimensional metal-oxide field effect transistor according to claim 8, characterized in that: The top corner and bottom corner of the groove are rounded.

10. The buried three-dimensional metal-oxide field effect transistor according to claim 8, characterized in that: The gate dielectric layer includes a stack of one or both of a silicon dioxide layer and a silicon oxynitride layer, and the gate electrode layer includes a doped polysilicon layer.

11. The buried three-dimensional metal-oxide field effect transistor according to claim 8, characterized in that: The gate dielectric layer includes a high-k dielectric layer, and the gate electrode layer includes a metal layer.

12. The buried three-dimensional metal-oxide field effect transistor according to claim 8, characterized in that: The ion doping type of the source region and the drain region is n-type, and the ion doping type of the semiconductor substrate between the source region and the drain region is p-type.

13. The buried three-dimensional metal-oxide field effect transistor according to claim 8, characterized in that: The ion doping type of the source region and the drain region is p-type, and the ion doping type of the semiconductor substrate between the source region and the drain region is n-type.

14. The buried three-dimensional metal-oxide field effect transistor according to claim 8, characterized in that: The number of the grooves is not less than 2, the grooves are arranged in parallel, and the grooves overlap with the source region and the drain region.

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