VDMOS device, control circuit, battery management chip and electrical device

Abstract

This disclosure provides a VDMOS device for controlling the charging and discharging current of a battery, comprising: a substrate of a first conductivity type; an epitaxial layer disposed on the substrate and of the first conductivity type; a first cell structure region including cell structures formed in the epitaxial layer to form a charging MOSFET serving as a charging switch; a second cell structure region including cell structures formed in the epitaxial layer to form a discharging MOSFET serving as a discharging switch; and a third cell structure region including cell structures formed in the epitaxial layer to form a sampling MOSFET, the sampling MOSFET being used to collect the current flowing through the charging MOSFET and the discharging MOSFET. This disclosure also provides a control circuit, a battery management chip, and an electrical device.

Description

Technical Field

[0001] This disclosure relates to a VDMOS device, a control circuit, a battery management chip, and an electrical device. Background Technology

[0002] When controlling the charging and discharging of batteries such as lithium batteries, it is necessary to measure the charging and discharging current for safety and battery life. An external resistor is typically required to detect the charging and discharging current.

[0003] In the prior art, when an external sensing resistor is used to detect the charging current and discharging current (for example, the sensing resistor is connected in series with the charging / discharging switch in the current loop), the sensing resistor needs to be connected in series in the current loop. This results in a large power consumption of the sensing resistor when the charging / discharging current is relatively large.

[0004] Alternatively, the current can be detected by the on-resistance of the charge / discharge switch. However, this on-resistance must be large enough to acquire a sufficiently large detection voltage for detection. If the on-resistance is large, the power consumption of the charge / discharge switch will inevitably be large as well.

[0005] In addition, regarding filtration protection, Figure 19 An overcurrent protection circuit for lithium battery protection in the prior art is presented.

[0006] During normal battery discharge, the voltage at the output OD and OC ports of the protection switch drive circuit is typically around VDD, 5V, or 15V. OD and OC are connected to the gates (G) of MOSFETs M1 and M2, respectively. At this time, M1 and M2 operate in the linear region, and the drain (D) and source (S) of M1 and M2 are equivalent to a single on-resistance with a resistance value of R. ON Discharge current I dsg The current flows from terminal P- to terminal B-, with a higher voltage at terminal P-. When the voltage difference (I) between terminal P- and terminal B- is detected... dsg *R ON When a certain threshold is reached, the OD voltage changes from VDD to B-, while OC remains at VDD potential, thus opening the discharge switch M1. Similarly, during normal battery charging, the gates (G) of M1 and M2 are at the battery voltage VDD. Current flows from the B- terminal to the P- terminal. The voltage at the P- terminal is lower, and when the voltage difference (I) between the B- and P- terminals reaches a certain threshold, the discharge switch M1 opens. chg *R ON When a certain limit is reached, the OC voltage changes from VDD to B-, while OD maintains the VDD potential, thus disconnecting the charging switch M2.

[0007] However, the on-resistance of MOSFETs M1 and M2 is related to battery temperature and battery voltage. If overcurrent is determined solely by detecting the voltage difference between the B- and P- terminals, the error will exceed ±30%.

[0008] In addition, existing technologies also include methods for detecting the drain-source voltage V of MOSFETs M1 and M2. DS A scheme for sampling charging and discharging current.

[0009] Based on the basic principle of sampling the charging and discharging current according to the on-resistance of the MOSFET, as follows: Figure 20 The diagram shows (using NMOS as an example; the principle is the same for PMOS, so it will not be repeated here).

[0010] I g This refers to the current flowing from the VCC voltage to the NMOS gate (G). Because the NMOS gate is in a high-resistance state, the current is short-circuited, therefore I... g All flow to R g Then V GS =I g *R g . When I g *R g =0 or <V TH (NMOS turn-on threshold voltage), NMOS is off, and because of the high impedance state, it is in an un-turned state. When I g *R g >V TH (NMOS turn-on threshold voltage), the NMOS transistor turns on and begins to conduct current. When I g *R g >V DS (NMOS source-drain voltage difference), I g *R g >V TH NMOS operates in the deep linear region, and is essentially a voltage-controlled resistor. Its on-resistance is related to V. GS The relationship is: R on =1 / [μ n *C ox *W*(V GS -V TH ) / L], where μ n C represents the mobility of charge carriers. ox V is the gate unit capacitance. TH The threshold voltage for NMOS, V GS Let I be the gate-source voltage, W be the channel width of the NMOS transistor, and L be the channel length of the NMOS transistor. Then, when there is a current I... ds When current flows through a MOSFET switch, the voltage difference V between the drain (D) and source (S) is... DS =Ids *R on =I ds / [μ n *C ox *(W / L)*(V GS -V TH )).

[0011] As can be seen from the above formula, by detecting the source-drain voltage difference V of the MOSFET switch... DS The charging / discharging current is sampled. However, there is a problem with directly sampling the charging / discharging current using the on-resistance of the charging / discharging MOSFET switch:

[0012] 1. The electron mobility μ of discrete MOSFET switches cannot be known in advance. n Width-to-length ratio (W / L), threshold turn-on voltage (V) TH Gate unit capacitance C ox Therefore, even if the source-drain voltage difference V is accurately measured... DS It is also impossible to accurately determine the magnitude of the charging and discharging current because I ds =V DS *μ n *C ox *(W / L)*(V GS -V TH The parameters mentioned above are usually the process and design parameters of discrete MOSFET manufacturers and are generally not disclosed to the public.

[0013] 2. Electron mobility μ n Threshold turn-on voltage V TH Gate unit capacitance C ox Because the on-resistance changes with temperature, the resistance of a MOSFET switch also changes with temperature. In other words, the on-resistance of the same MOSFET switch differs at different temperatures. This means that at the same temperature, the same source-drain voltage difference V... DS Because the resistance of the MOSFET switch changes with temperature, it is impossible to obtain the charging and discharging current at all different temperatures by measuring the resistance of the MOSFET at a single temperature point.

[0014] 3. Electron mobility μ of discrete MOSFET switches of the same type from the same or different batches n Threshold turn-on voltage V TH Gate unit capacitance C oxThese variations are inherent, typically exhibiting a Gaussian distribution, due to manufacturing process variations. In other words, the on-resistance of the same type of discrete MOSFET switches from the same or different batches may differ. Therefore, it is impossible to measure the resistance of a single MOSFET beforehand to obtain the on-resistance of the same type of discrete MOSFET switches from the same or different batches.

[0015] Given the problems existing in the current technology, the technical problem to be solved is how to detect the charging and discharging current of the battery with high accuracy. Summary of the Invention

[0016] To address one of the aforementioned technical problems, this disclosure provides a VDMOS device, a control circuit, a battery management chip, and an electrical device.

[0017] According to one aspect of this disclosure, a VDMOS device, the VDMOS being used to control the charging current and discharging current of a battery, includes:

[0018] Substrate, wherein the substrate is of a first conductivity type;

[0019] An epitaxial layer, wherein the epitaxial layer is disposed on the substrate and is of a first conductivity type;

[0020] A first cell structure region, comprising cell structures formed in the epitaxial layer to form a charging MOSFET used as a charging switch;

[0021] The second cell structure region, comprising cell structures formed in the epitaxial layer, constitutes a discharge MOSFET serving as a discharge switch; and

[0022] The third cell structure region includes cell structures formed in the epitaxial layer to constitute a sampling MOSFET for acquiring the current flowing through the charging MOSFET and the discharging MOSFET.

[0023] According to at least one embodiment of this disclosure, the ratio of the number of cell structures in the third cell structure region to the number of cell structures in the first cell structure region and the second cell structure region is 1:K, where K≥2.

[0024] According to at least one embodiment of the present disclosure, the charging MOSFET and the discharging MOSFET are configured such that their drains are connected.

[0025] According to at least one embodiment of the present disclosure, the number of the third cell structure region and the number of the sampling MOSFET is one, and the source of the sampling MOSFET is configured to be connected to the source of the charging MOSFET or the source of the discharging MOSFET, and the drain of the sampling MOSFET is configured as a sampling terminal for the charging current or the discharging current.

[0026] According to at least one embodiment of this disclosure, the number of the third cell structure region and the number of the sampling MOSFETs are two, and one sampling MOSFET is connected to the drain of the other sampling MOSFET, and the source of one of the two sampling MOSFETs is configured to be connected to the source of the charging MOSFET or the source of the discharging MOSFET, and the source of the other sampling MOSFET is configured as a sampling terminal for the charging current or the discharging current.

[0027] According to at least one embodiment of the present disclosure, a well resistor structure is further included to form a well resistor, one end of which is configured to be connected to the source of the other sampling MOSFET, and the other end of which is configured to be connected to the source of the discharge MOSFET or the source of the charging MOSFET, and one end of the well resistor is configured as a sampling terminal for the discharge current or the charging current.

[0028] According to at least one embodiment of this disclosure, the number of the third cell structure region and the sampling MOSFET is four, wherein...

[0029] Of the four sampling MOSFETs, one sampling MOSFET is connected to the drain of the other sampling MOSFET, the source of the first sampling MOSFET is configured to be connected to the source of the charging MOSFET, and the source of the second sampling MOSFET is configured as a charging current sampling terminal; and

[0030] Of the other two of the four sampling MOSFETs, one sampling MOSFET is connected to the drain of the other sampling MOSFET, the source of the sampling MOSFET is configured to be connected to the source of the discharge MOSFET, and the source of the other sampling MOSFET is configured to be a discharge current sampling terminal.

[0031] According to at least one embodiment of this disclosure, two well resistor structures are further included to form two well resistors. The number of the third cell structure region and the sampling MOSFETs is two, and one sampling MOSFET is connected to the drain of the other sampling MOSFET. The source of the one sampling MOSFET is configured to be connected to one end of the well resistor, and the other end of the one well resistor is configured to be connected to the source of the charging MOSFET. One end of the other well resistor is configured to be connected to the source of the other sampling MOSFET, and the other end of the other well resistor is configured to be connected to the source of the discharging MOSFET. One end of the one well resistor is a charging current sampling terminal, and one end of the other well resistor is a discharging current sampling terminal.

[0032] According to at least one embodiment of this disclosure, each cell structure includes:

[0033] Two trenches, each containing a gate oxide layer, polysilicon, and a dielectric layer on top of the polysilicon;

[0034] A first well region, having a second conductivity type, is located between the two trenches and above the epitaxial layer; and

[0035] A heavily doped region, which is located above the first well region and between the two trenches, and the heavily doped region is of a first conductivity type.

[0036] According to at least one embodiment of this disclosure, each cell structure includes:

[0037] Two trenches are provided in each trench, including a gate oxide layer, a control gate, a shield gate, a first dielectric layer and a second dielectric layer. The control gate is located above the shield gate and is separated by the first dielectric layer, and the second dielectric layer is located above the control gate.

[0038] A first well region, having a second conductivity type, is located between the two trenches and above the epitaxial layer; and

[0039] A heavily doped region, which is located above the first well region and between the two trenches, and the heavily doped region is of a first conductivity type.

[0040] According to another aspect of this disclosure, a charge / discharge control circuit includes a VDMOS device as described above, which charges and discharges the battery through a first connection terminal and a second connection terminal. The charging and discharging are controlled by controlling a charge / discharge switch composed of the charging MOSFET and the discharging MOSFET. The charging MOSFET and the discharging MOSFET are connected in series in the current path between the battery and the first connection terminal or between the battery and the second connection terminal. The sampling MOSFET and / or well resistor in the VDMOS device constitute the detection unit of the control circuit. The control circuit further includes:

[0041] A comparison unit, wherein a first input terminal of the comparison unit is connected to a voltage related to the voltage of a first terminal of the detection unit, a second input terminal of the comparison unit is connected to a voltage related to the voltage of a first terminal of the charge / discharge switch, and a second terminal of the detection unit is connected to a second terminal of the charge / discharge switch; and

[0042] A control logic unit controls the charging MOSFET and the discharging MOSFET based on the comparison result output by the comparison unit.

[0043] The impedance ratio between the on-resistance value of the charge / discharge switch and the on-resistance value of the detection unit remains constant.

[0044] According to at least one embodiment of this disclosure, the current ratio between the current flowing through the charge / discharge switch and the current flowing through the detection unit remains constant.

[0045] According to at least one embodiment of this disclosure, the current ratio between the current flowing through the charge / discharge switch and the current flowing through the detection unit is independent of the system voltage and system temperature.

[0046] According to at least one embodiment of this disclosure, when the discharge current is controlled,

[0047] The source of the sampling MOSFET of the detection unit is connected to the source of the discharge MOSFET, the drain of the sampling MOSFET is connected to a constant current that is independent of voltage and temperature, and the discharge current flows from the charging MOSFET to the discharge MOSFET.

[0048] According to at least one embodiment of this disclosure, when the voltage on the source side of the charging MOSFET is greater than the voltage on the drain side of the sampling MOSFET, the comparison result of the comparison unit is flipped, and the control logic unit controls the discharge MOSFET to be turned off.

[0049] According to at least one embodiment of this disclosure, when the charging current is controlled,

[0050] The source of the sampling MOSFET is connected to the source of the charging MOSFET, the drain of the sampling MOSFET is connected to a constant current that is independent of voltage and temperature, and a discharge current flows from the discharge MOSFET to the charging MOSFET.

[0051] According to at least one embodiment of this disclosure, when the voltage on the source side of the discharge MOSFET is greater than the voltage on the drain side of the sampling MOSFET, the comparison result of the comparison unit is flipped, and the control logic unit controls the charging MOSFET to be turned off.

[0052] According to at least one embodiment of this disclosure, it further includes a mirror circuit and a comparator.

[0053] With the discharge current controlled, the source of the sampling MOSFET is connected to the source of the discharge MOSFET, the drain of the sampling MOSFET is connected to a mirror circuit, the voltage on the drain side of the sampling MOSFET is set to be equal to the voltage on the source side of the charging MOSFET, and the discharge current flows from the charging MOSFET to the discharge MOSFET.

[0054] When the voltage at the source side of the charging MOSFET is greater than the voltage at the drain side of the sampling MOSFET, the comparison result of the comparator is flipped, and the mirror circuit is controlled to mirror the current flowing through the sampling MOSFET to generate a mirror current. The voltage generated based on the mirror current is input to the first input terminal of the comparator, and the reference voltage is input to the second input terminal of the comparator. The comparison result of the comparator is used to control the control logic unit to turn off the discharge MOSFET.

[0055] According to at least one embodiment of this disclosure, it further includes a mirror circuit and a comparator.

[0056] With the charging current controlled, the source of the sampling MOSFET is connected to the source of the charging MOSFET, the drain of the sampling MOSFET is connected to a mirror circuit, the voltage on the drain side of the sampling MOSFET is set to be equal to the voltage on the source side of the discharging MOSFET, and the charging current flows from the discharging MOSFET to the charging MOSFET.

[0057] When the voltage on the source side of the discharge MOSFET is greater than the voltage on the drain side of the sampling MOSFET, the comparison result of the comparator is flipped, and the mirror circuit is controlled to mirror the current flowing through the sampling MOSFET to generate a mirror current. The voltage generated based on the mirror current is input to the first input terminal of the comparator, and the reference voltage is input to the second input terminal of the comparator. The comparison result of the comparator is used to enable the control logic unit to control the charging MOSFET to turn off.

[0058] According to at least one embodiment of this disclosure, in the case where the detection unit includes a well resistor and a sampling MOSFET,

[0059] When the discharge current is controlled, the connection point of the well resistor and the sampling MOSFET is connected to the first input terminal of the comparison unit, and the second input terminal of the comparison unit is connected to the reference voltage generated based on the source-side voltage of the discharge MOSFET. When the voltage at the first input terminal of the comparison unit is greater than the voltage at the second input terminal, the comparison result of the comparison unit is flipped, and the control logic unit controls the discharge MOSFET to be turned off.

[0060] According to at least one embodiment of this disclosure, the value of the well resistor is much smaller than the on-resistance of the sampling MOSFET.

[0061] According to at least one embodiment of this disclosure, in the case where the detection unit includes a well resistor and a sampling MOSFET,

[0062] When the charging current is controlled, and the connection point of the well resistor and the sampling MOSFET is connected to the first input terminal of the comparison unit, and the second input terminal of the comparison unit is connected to the reference voltage generated based on the source-side voltage of the charging MOSFET, when the voltage at the first input terminal of the comparison unit is greater than the voltage at the second input terminal, the comparison result of the comparison unit is flipped, and the control logic unit controls the charging MOSFET to be turned off.

[0063] According to at least one embodiment of this disclosure, the value of the well resistor is much smaller than the on-resistance of the sampling MOSFET.

[0064] According to another aspect of this disclosure, a battery management chip includes the charge / discharge control circuit described above.

[0065] According to at least one embodiment of this disclosure, the charging / discharging switch is also included.

[0066] According to another aspect of this disclosure, an electrical device includes:

[0067] The battery management chip mentioned above; and

[0068] The battery is used to power other components of the electrical device, and the battery management chip is used to manage the battery. Attached Figure Description

[0069] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0070] Figure 1 A schematic diagram of a VDMOS device according to an embodiment of the present disclosure is shown.

[0071] Figure 2 A circuit diagram of a VDMOS device according to an embodiment of the present disclosure is shown.

[0072] Figure 3 A schematic diagram of an application of a VDMOS device according to an embodiment of the present disclosure is shown.

[0073] Figure 4 A schematic diagram of a VDMOS device according to an embodiment of the present disclosure is shown.

[0074] Figure 5 A circuit diagram of a VDMOS device according to an embodiment of the present disclosure is shown.

[0075] Figure 6 A schematic diagram of an application of a VDMOS device according to an embodiment of the present disclosure is shown.

[0076] Figure 7 A schematic diagram of an application of a VDMOS device according to an embodiment of the present disclosure is shown.

[0077] Figure 8 A schematic diagram of a VDMOS device according to an embodiment of the present disclosure is shown.

[0078] Figure 9 A circuit diagram of a VDMOS device according to an embodiment of the present disclosure is shown.

[0079] Figure 10 A schematic diagram of an application of a VDMOS device according to an embodiment of the present disclosure is shown.

[0080] Figure 11 A schematic diagram of an application of a VDMOS device according to an embodiment of the present disclosure is shown.

[0081] Figure 12A schematic diagram of a VDMOS device according to an embodiment of the present disclosure is shown.

[0082] Figure 13 A schematic diagram of an application of a VDMOS device according to an embodiment of the present disclosure is shown.

[0083] Figure 14 A schematic diagram of an application of a VDMOS device according to an embodiment of the present disclosure is shown.

[0084] Figure 15 A schematic diagram of a VDMOS device according to an embodiment of the present disclosure is shown.

[0085] Figure 16 A circuit diagram of a VDMOS device according to an embodiment of the present disclosure is shown.

[0086] Figure 17 A schematic diagram of an application of a VDMOS device according to an embodiment of the present disclosure is shown.

[0087] Figure 18 A schematic diagram of a VDMOS device according to an embodiment of the present disclosure is shown.

[0088] Figure 19 A schematic diagram of a battery management system according to the prior art is shown.

[0089] Figure 20 A schematic diagram of the on-resistance of a prior art NMOS transistor is shown. Detailed Implementation

[0090] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0091] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0092] Unless otherwise stated, the exemplary implementations / embodiments shown are to be understood as providing exemplary features of various details that provide ways in which the technical concepts of this disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of various implementations / embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of this disclosure.

[0093] The use of crosshairs and / or shading in the accompanying drawings is generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities between the illustrated components, or any other characteristics, properties, etc., of the components. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0094] When a component is referred to as being "on" or "above" another component, "connected to," or "joined to" another component, the component may be directly on, directly connected to, or directly joined to the other component, or there may be intermediate components. However, when a component is referred to as being "directly on" another component, "directly connected to," or "directly joined to" another component, there are no intermediate components. Therefore, the term "connection" can refer to a physical connection, an electrical connection, etc., and may or may not have intermediate components.

[0095] For descriptive purposes, this disclosure may use spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side (e.g., in a “sidewall”)” to describe the relationship between one component and another component as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, a component described as “below” or “under” another component or feature would subsequently be positioned “above” said other component or feature. Thus, the exemplary term “below” can encompass both “above” and “below” orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0096] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, parts, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, parts, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0097] According to embodiments of this disclosure, a VDMOS device with integrated current sampling function is provided.

[0098] Figure 1 A VDMOS device with current sampling function according to a first embodiment of the present disclosure is shown.

[0099] like Figure 1 As shown, the VDMOS device 100 may include: a substrate 102, an epitaxial layer 104, and a cell structure, wherein each cell structure includes a gate oxide layer 106, a polysilicon layer 108, a dielectric layer 110, a first well region 112, a second well region 114, and a heavily doped region 116.

[0100] The substrate 102 can be a silicon wafer, and it is a substrate of a first conductivity type. An epitaxial layer 104, also of the first conductivity type, is fabricated on the substrate 102. Multiple cell structures are formed in the epitaxial layer 104, each cell structure including two trenches. A gate oxide layer 106, polysilicon 108, and a dielectric layer 110 are disposed in each trench. The gate oxide layer 106 is located outside the polysilicon 108, and the dielectric layer 110 is disposed on top of the polysilicon 108.

[0101] A second well region 114 is provided above the epitaxial layer 104 and between the two trenches. The second well region 114 is of a second conductivity type. A heavily doped region 116 is provided above the second well region 114. The doping concentration of the heavily doped region 116 is higher than that of the epitaxial layer 104, and the heavily doped region 116 is of a first conductivity type.

[0102] A first well region 112 is provided on the outer side of each of the two trenches, wherein the first well region 112 has a conductivity type of the second conductivity type.

[0103] Furthermore, a source electrode 118 can be drawn from the heavily doped region 116. A drain electrode 120 is provided on the other side of the substrate 102.

[0104] like Figure 1 As shown, the VDMOS device can integrate a charging MOSFET MD, a discharging MOSFET MC, a first sampling MOSFET MS1, a second sampling MOSFET MS2, a third sampling MOSFET MS3, and a fourth sampling MOSFET MS4.

[0105] The charging MOSFET MD and the discharging MOSFET MC can each include multiple cell structures. The first sampling MOSFET MS1, the second sampling MOSFET MS2, the third sampling MOSFET MS3, and the fourth sampling MOSFET MS4 can each include one or more cell structures. The ratio of the number of cell structures of the first sampling MOSFET MS1, the second sampling MOSFET MS2, the third sampling MOSFET MS3, and the fourth sampling MOSFET MS4 to the number of cell structures of the charging MOSFET MD and the discharging MOSFET MC can be 1:K, where K is greater than or equal to 1.

[0106] The structure of this VDMOS device allows for the adjustment of the ratio of current flowing through the sampling MOSFETs MS1-MS4 and the charge / discharge switches MD and MS by changing the number of cells, thereby achieving accurate current sampling.

[0107] Figure 1 The VDMOS device structure shown corresponds to Figure 2 The application circuit shown can be used for the charging and discharging control of batteries in a battery management system.

[0108] like Figure 2 As shown, in the application circuit, MD is used as the discharge MOSFET, MC is used as the charging MOSFET, MS1 and MS2 are used as the discharge current sampling branches, and MS3 and MS4 are used as the charging current sampling branches.

[0109] Figure 3 This illustrates how the application circuit is used in a battery management system. The charge / discharge control unit may include a detection unit consisting of MS3 and MS4, as well as a resistor R2 and a comparator CMP2.

[0110] During discharge, the discharge current Idsg flows from the P- terminal to the B- terminal.

[0111] The first input of comparator CMP2 is connected to a voltage related to the detection result of the detection unit, and the second input is connected to a reference voltage VREF2. The detection voltage generated based on the detection current Idsg / K obtained from MS3 and MS4 and the resistance value of resistor R2 is compared with the reference voltage VREF2. When the voltage at the first input of comparator CMP2 is greater than the voltage at the second input, the comparison result of comparator CMP2 flips, and the control logic unit controls the discharge switch MD to open. MOSFET MD is turned off by outputting a control signal OD through the drive unit. For example, when the OD voltage changes from VDD to B-, OC remains at the VDD potential.

[0112] MOSFETs MS3 and MS4 are the same type of MOSFET as MOSFETs MD and MC. The ratio of the on-resistance of MOSFETs MS3 and MS4 to that of MOSFETs MD and MC is constant at K:1.

[0113] When MOSFET MD is turned off, the current flowing through MOSFET MD and MC is VREF2 / R2*K. Since VREF2 and R2 are fixed values, and K is a constant ratio, these three values ​​will not change when the system voltage and temperature change. Therefore, the current flowing through MOSFET MD and MC will not change, meaning that the detected discharge current will not change with voltage or temperature.

[0114] During charging, the charging current Ichg flows from terminal B- to terminal P-.

[0115] The first input of comparator CMP1 is connected to a voltage related to the detection result of the detection unit, and the second input is connected to a reference voltage VREF1. The detection voltage generated based on the detection current Ichg / K obtained from MS1 and MS2 and the resistance value of resistor R1 is compared with the reference voltage VREF1. When the voltage at the first input of comparator CMP1 is greater than the voltage at the second input, the comparison result of comparator CMP1 flips, and the control logic unit controls the MOSFET MC to turn off. MOSFET MC is turned off by outputting a control signal OC through the drive unit. For example, when the OC voltage changes from VDD to P-, OD remains at the VDD potential.

[0116] MOSFETs MS1 and MS2 are the same type of MOSFETs as MOSFETs MD and MC. The ratio of the on-resistance of MOSFETs MS1 and MS2 to that of MOSFETs MD and MC is constant at K:1.

[0117] When MOSFET MC is turned off, the current flowing through MOSFET MD and MC is VREF1 / R1*K. Since VREF1 and R1 are fixed values, and K is a constant ratio, these three values ​​will not change when the system voltage and temperature change. Therefore, the current flowing through MOSFET MD and MC will not change, meaning that the detected charging current will not change with voltage or temperature.

[0118] Figure 4 A VDMOS device with current sampling function according to a second embodiment of the present disclosure is shown.

[0119] like Figure 4 As shown, the VDMOS device 100 may include: a substrate 102, an epitaxial layer 104, and a cell structure, wherein each cell structure includes a gate oxide layer 106, a polysilicon layer 108, a dielectric layer 110, a first well region 112, a second well region 114, and a heavily doped region 116.

[0120] The substrate 102 can be a silicon wafer, and it is a substrate of a first conductivity type. An epitaxial layer 104, also of the first conductivity type, is fabricated on the substrate 102. Multiple cell structures are formed in the epitaxial layer 104, each cell structure including two trenches. A gate oxide layer 106, polysilicon 108, and a dielectric layer 110 are disposed in each trench. The gate oxide layer 106 is located outside the polysilicon 108, and the dielectric layer 110 is disposed on top of the polysilicon 108.

[0121] A second well region 114 is provided above the epitaxial layer 104 and between the two trenches. The second well region 114 is of a second conductivity type. A heavily doped region 116 is provided above the second well region 114. The doping concentration of the heavily doped region 116 is higher than that of the epitaxial layer 104, and the heavily doped region 116 is of a first conductivity type.

[0122] A first well region 112 is provided on the outer side of each of the two trenches, wherein the first well region 112 has a conductivity type of the second conductivity type.

[0123] Furthermore, a source electrode 118 can be drawn from the heavily doped region 116. A drain electrode 120 is provided on the other side of the substrate 102.

[0124] like Figure 4 As shown, the VDMOS device can integrate a charging MOSFET MD, a discharging MOSFET MC, and a first sampling MOSFET MS1.

[0125] The charging MOSFET MD and the discharging MOSFET MC can each include multiple cell structures, and the first sampling MOSFET MS1 includes one or more cell structures. The ratio of the number of cell structures of the first sampling MOSFET MS1 to the number of cell structures of the charging MOSFET MD and the discharging MOSFET MC can be 1:K, where K is greater than or equal to 1.

[0126] The structure of this VDMOS device allows for the adjustment of the ratio of current flowing through the sampling MOSFET MS1 and the charge / discharge switches MD and MS by changing the number of cells, thereby achieving accurate current sampling.

[0127] Figure 4 The VDMOS device structure shown corresponds to Figure 5 The application circuit shown can be used for the charging and discharging control of batteries in a battery management system.

[0128] like Figure 5 As shown, in the application circuit, MD is used as the discharge MOSFET, MC is used as the charging MOSFET, and MS1 is used as the charging current sampling branch.

[0129] Figure 6 It shows Figure 4 The application of the VDMOS device structure shown is illustrated.

[0130] This application is used to control overcurrent during battery charging.

[0131] The charge / discharge control unit may include a detection unit composed of MOSFET MS1 and a comparator. The second input terminal of the comparator is connected to a voltage related to the voltage at the second terminal of the detection unit, and the first input terminal of the comparator is connected to a voltage related to the voltage at the second terminal of the charge / discharge switch. The first terminal of the detection unit is connected to the first terminal of the charge / discharge switch. The charge / discharge switch consists of a charging MOSFET MC and a discharging MOSFET MD.

[0132] In this embodiment, the source of the MOSFET M1 in the detection unit is connected to a constant current Idc, which is independent of the system voltage and temperature. The charging current Ichg flows from the second terminal of the charge / discharge switch (shown in the figure as the right end of the discharge switch, i.e., the negative terminal B- of the battery) to the first terminal P-. When the voltage at the second terminal of the charge / discharge switch is greater than the detection voltage of the detection unit, the comparator's comparison result flips, and the control logic unit controls the charging MOSFET MC to turn off.

[0133] Specifically, a constant current Idc can be generated inside the chip. This constant current Idc is independent of the system voltage and temperature, and generates a voltage Vb across MOSFET MS1. Since MOSFETs MD, MC, and MS1 are of the same type, even if the system temperature or voltage changes, the sum of the equivalent on-resistance of MOSFET MS1 and the equivalent on-resistances of MOSFETs MD and MC can remain a constant value K:1.

[0134] The comparator is used to compare voltage Vb and voltage VB- (voltage at terminal B-). When VB- is greater than Vb, the comparator's output signal flips, and after receiving the flip signal, the control logic unit outputs a control signal OC through the drive unit to turn off the charging MOSFET. For example, when the OC voltage changes from VDD to P-, the OD voltage remains at VDD.

[0135] When the charging MOSFET is turned off, the current flowing through MOSFET MD and MC is Idc*K. Since Idc is a constant current and K is a constant ratio, these two constant values ​​will not change when the system voltage and temperature change. Therefore, the current flowing through MOSFET MD and MC will not change, meaning that the detected charging overcurrent will not change with voltage or temperature.

[0136] As a variant of this embodiment, two or more sampling MOSFETs can also be used, so the VDMOS device structure can be modified accordingly.

[0137] According to a third embodiment of this disclosure, a sampling MOSFET may also be provided only on the discharge MOSFET side for detecting the discharge current, for example, with... Figure 5 The principle is the same, except that it includes the sampling MOSFET on the MD side of the discharge MOSFET.

[0138] Figure 7 An application example including a sampling MOSFET is shown.

[0139] This example is used to control battery discharge overcurrent.

[0140] The charge / discharge control unit may include a detection unit composed of a sampling MOSFET and a comparator. The first input terminal of the comparator is connected to a voltage related to the voltage at the first terminal of the detection unit, and the second input terminal of the comparator is connected to a voltage related to the voltage at the first terminal of the charge / discharge switch. The second terminal of the detection unit is connected to the second terminal of the charge / discharge switch. The charge / discharge switch consists of a charging MOSFET and a discharging MOSFET.

[0141] In this embodiment, the detection unit is a sampling MOSFET. The source of the sampling MOSFET is connected to the second terminal of the charge / discharge switch (the right terminal of the discharge switch, i.e., the negative terminal B- of the battery, is shown in the figure). The drain of the sampling MOSFET of the detection unit is connected to a constant current Idc, which is independent of the voltage and temperature of the system.

[0142] The discharge current Idsg flows from the first terminal of the charge / discharge switch (shown in the figure as the negative terminal connected to an external charger or external load, i.e., the P- terminal) to the second terminal. When the voltage at the first terminal of the charge / discharge switch is greater than the voltage on the drain side of the sampling MOSFET of the detection unit, the comparison result of the comparator flips, and the control logic unit controls the discharge MOSFET to turn off.

[0143] Specifically, a constant current Idc can be generated inside the chip. This constant current Idc is independent of the system voltage and temperature, and it generates a voltage Va (the voltage at the drain terminal of the sampling MOSFET) across the sampling MOSFET. Since the charge / discharge switch and the sampling MOSFET are the same type of MOSFET, even if the system temperature or voltage changes, the sum of the equivalent on-resistance of the sampling MOSFET and the equivalent on-resistance of the charge / discharge switch can remain a constant value K:1.

[0144] The comparator is used to compare voltage Va and voltage VP- (the voltage at the P- terminal). When VP- is greater than Va, the comparator's output signal flips, and after receiving the flip signal, the control logic unit outputs a control signal OD through the drive unit to turn off the discharge MOSFET. For example, when the OD voltage changes from VDD to B-, the OC voltage remains at VDD.

[0145] When the discharge MOSFET is turned off, the current flowing through the charge / discharge switch is Idc*K. Since Idc is a constant current and K is a constant ratio, these two constant values ​​will not change when the system voltage and temperature change. Therefore, the current flowing through the charge / discharge switch will not change, meaning that the detected discharge overcurrent will not change with voltage or temperature.

[0146] Figure 8 A VDMOS device structure according to a fourth embodiment of this disclosure is shown. (and) Figure 4 The difference in the device structure shown is the addition of a well resistor R. Compared to... Figure 4 The same parts will not be described again here. The well resistor structure includes a second well region 114 disposed in the epitaxial layer 104, which is of a second conductivity type. Furthermore, a heavily doped region 116 is disposed in the second well region 114, the doping concentration of the heavily doped region 116 being higher than that of the epitaxial layer 104, and the heavily doped region 116 being of a first conductivity type.

[0147] Figure 9 for Figure 8 The circuit diagram corresponding to the VDMOS device structure shown is shown. Figure 10 This demonstrates a practical application of the VDMOS device.

[0148] This practical application is used to control overcurrent during battery discharge. The discharge current Idsg flows from the P- terminal to the B- terminal.

[0149] The charge / discharge control unit may include a detection unit consisting of two sampling MOSFETs and a resistor R, and a comparator.

[0150] The first input terminal of the comparator is connected to a voltage related to the voltage at the second terminal of the detection unit. The first input terminal of the comparator is also connected to a voltage related to the voltage at the first terminal of the charge / discharge switch. The first terminal of the detection unit is connected to the first terminal of the charge / discharge switch. The charge / discharge switch consists of a charging MOSFET MC and a discharging MOSFET MD.

[0151] The detection unit includes a resistor R connected in series with MOSFETs MS1 and MS2. The number of MOSFETs connected in series can be one or more, for example, it can be in the form of a single MOSFET or multiple MOSFETs.

[0152] When the discharge current is controlled, one end of the resistor of the detection unit is connected to the second terminal of the charge / discharge switch, and the other end is connected to one end of the MOSFET of the detection unit and the other end is connected to the first terminal of the charge / discharge switch. The connection point between the resistor and the MOSFET of the detection unit is connected to the first input terminal of the comparator. The second input terminal of the comparator is connected to a reference voltage generated based on the voltage of the second terminal of the charge / discharge switch. When the voltage of the first input terminal of the comparator is greater than the voltage of the second input terminal, the comparison result of the comparator flips, and the control logic unit controls the discharge MOSFET to turn off.

[0153] The resistance of the detection unit is much smaller than the on-resistance of the MOSFET of the detection unit.

[0154] For example, refer to Figure 10It includes two sampling MOSFETs connected in series. The source of one sampling MOSFET is connected to the P- terminal, and its drain is connected to the drain of the other sampling MOSFET. The source of the other sampling MOSFET is connected to one end of a resistor R, and the other end of the 533e resistor is connected to the B- terminal. The connection point of the other sampling MOSFET and the resistor R is connected to one input terminal of a comparator, and the other input terminal of the comparator is connected to a reference voltage Vref generated based on VB- (the voltage at the B- terminal). This reference voltage Vref can be generated based on VB- through a voltage generation unit DC (e.g., a voltage with VB- as a reference zero potential, which can be generated internally by the chip).

[0155] The sampling MOSFET and the charge / discharge switch are of the same type. The ratio of the sum of the on-resistances of the sampling MOSFET to the on-resistance of the charge / discharge switch is constant at K:1. To ensure accuracy, the resistance Re of the resistor R is set to be much smaller than the sum of the on-resistances of the sampling MOSFET. The voltage Ve at the connection point of the sampling MOSFET is compared with Vref. When Ve is greater than Vref, the comparator flips. The logic control unit can then control the drive unit based on this flip signal, outputting a control signal OD to turn off the discharge MOSFET. For example, when the OD voltage changes from VDD to B-, the OC voltage remains at VDD.

[0156] When the discharge MOSFET is turned off, the current flowing through the charge / discharge switch is Vref / Re*K. Since Vref and Re are fixed values, and K is a constant ratio, these three values ​​will not change when the system voltage and temperature change. Therefore, the current flowing through the charge / discharge switch will not change, meaning that the detected discharge overcurrent will not change with voltage or temperature.

[0157] According to a fifth embodiment of this disclosure, a VDMOS device structure is also provided. The difference between this fifth embodiment and the fourth embodiment is that MOSFETs MS1 and MS2 and the resistor are disposed on one side of the discharge MOSFET.

[0158] Figure 11 This illustrates the application of the VDMOS device. It is used for controlling overcurrent during battery charging. The charging current Ichg flows from the B- terminal to the P- terminal.

[0159] The charge / discharge control unit may include a detection unit consisting of a sampling MOSFET and a resistor, and a comparator.

[0160] The first input terminal of the comparator is connected to a voltage related to the voltage at the second terminal of the detection unit. The first input terminal of the comparator is also connected to a voltage related to the voltage at the first terminal of the charge / discharge switch. The first terminal of the detection unit is connected to the first terminal of the charge / discharge switch. The charge / discharge switch consists of a charging MOSFET and a discharging MOSFET.

[0161] The detection unit includes a resistor R connected in series with a sampling MOSFET. The number of the sampling MOSFETs connected in series can be one or more, for example, it can be in the form of a single sampling MOSFET or multiple sampling MOSFETs.

[0162] When the charging current is controlled, one end of the resistor of the detection unit is connected to the first terminal of the charge / discharge switch, and the other end is connected to one end of the sampling MOSFET of the detection unit and the other end is connected to the second terminal of the charge / discharge switch. The connection point between the resistor of the detection unit and the sampling MOSFET is connected to the first input terminal of the comparator. The second input terminal of the comparator is connected to a reference voltage generated based on the voltage of the second terminal of the charge / discharge switch. When the voltage of the first input terminal of the comparator is greater than the voltage of the second input terminal, the comparison result of the comparator flips, and the control logic unit controls the charging MOSFET to turn off.

[0163] The resistance of the detection unit is much smaller than the on-resistance of the sampling MOSFET of the detection unit.

[0164] For example, refer to Figure 11 This includes two sampling MOSFETs connected in series. The source of one sampling MOSFET is connected to the B- terminal, and its drain is connected to the drain of the other sampling MOSFET. The source of the other MOSFET is connected to one end of a resistor R, and the other end of the resistor R is connected to the P- terminal. The connection point between the MOSFET and the resistor is connected to one input of a comparator, and the other input of the comparator is connected to a reference voltage Vref generated based on VP- (the voltage at the P- terminal). This reference voltage Vref can be generated based on VP- through a voltage generation unit (e.g., a voltage with VP- as a reference zero potential, which can be generated internally within the chip).

[0165] The sampling MOSFET and the charge / discharge switch are the same type of MOSFET. The ratio of the on-resistance of the sampling MOSFET to that of the charge / discharge switch is constant at K:1. To ensure accuracy, the resistance Rf is set to be much smaller than the on-resistance of the sampling MOSFET. The voltage Vf at the connection point between the sampling MOSFET and the resistor is compared with Vref. When Vf is greater than Vref, the comparator flips. The logic control unit can then use this flip signal to control the drive unit, which outputs a control signal OC to turn off the charging MOSFET. For example, when the OC voltage changes from VDD to VP-, the OD voltage remains at VDD.

[0166] When the charging MOSFET is turned off, the current flowing through the charge / discharge switch is Vref / Rf*K. Since Vref and Rf are fixed values, and K is a constant ratio, these three values ​​will not change when the system voltage and temperature change. Therefore, the current flowing through the charge / discharge switch will not change, meaning that the detected charging overcurrent will not change with voltage or temperature.

[0167] Figure 12 A VDMOS device structure according to a sixth embodiment of the present disclosure is shown.

[0168] The device structure is similar to Figure 4 The difference in the device structure shown is that it includes two sampling MOSFETs.

[0169] Figure 13 It shows Figure 12 The VDMOS device structure shown is used for overcurrent control during battery charging. The charging current Ichg flows from the B- terminal to the P- terminal.

[0170] The charge / discharge control unit may include a detection unit and a comparator.

[0171] The first input terminal of the comparator is connected to a voltage related to the voltage at the second terminal of the detection unit. The first input terminal of the comparator is also connected to a voltage related to the voltage at the first terminal of the charge / discharge switch. The first terminal of the detection unit is connected to the first terminal of the charge / discharge switch. The charge / discharge switch consists of a charging MOSFET MC and a discharging MOSFET MD.

[0172] In this embodiment, the comparator is an operational amplifier, and a detection resistor is connected in series between the second input terminal and the output terminal of the operational amplifier. One end of the NMOS MOSFET of the comparator is connected to the second input terminal of the operational amplifier, and the other end of the NMOS MOSFET of the comparator is connected to the second terminal of the charge / discharge switch. The first input terminal of the operational amplifier is connected to the first terminal of the charge / discharge switch.

[0173] The current value of the charging current or the discharging current is obtained by using the voltage generated by the detection resistor and the resistance value of the detection resistor.

[0174] The following will refer to Figure 11 A detailed description is provided. The detection unit may include sampling MOSFETs MS1 and MS2. Sampling MOSFETs MS1 and MS2 can be the same type of MOSFET as the charging MOSFET MC and the discharging MOSFET MD.

[0175] The source of MOSFET MS1 is connected to the P- terminal, and its drain is connected to the drain of MOSFET MS2. The source of MOSFET MS2 is connected to one input terminal of the operational amplifier. The gate of NMOS MOSFET MS1 is connected to the control signal OC, and the gate of MOSFET MS2 is connected to the control signal OD. The other input terminal of the operational amplifier is connected to the B- terminal.

[0176] MOSFET MS1 and the discharge MOSFET MD are the same type of MOSFET, and MOSFET MS2 and the charge MOSFET MC are the same type of MOSFET. Therefore, even if the temperature or voltage changes, the ratio of the series equivalent on-resistance of sampling MOSFETs MS1 and MS2 to the series equivalent on-resistance of charging MOSFET MC and discharge MOSFET MD remains a constant value K:1. Thus, the current flowing through the sampling MOSFETs and the current flowing through the charge / discharge switch remain constant at 1:K.

[0177] During charging, the external charger is connected between the battery's positive output terminal (P+) and negative output terminal (P-). The charging current from the external charger to the battery pack is Ichg*(1+1 / K). The current flowing through the charge / discharge switch is Ichg, while the current flowing through the sampling MOSFET is Ichg / K.

[0178] The operational amplifier can make the source voltage of MOSFET MS1 the same as the voltage of the negative terminal B- of the battery. The voltage of the negative terminal B- of the battery pack is the system ground point, so V(B-) = 0.

[0179] Because of the negative feedback of the operational amplifier, the voltage at the negative input terminal of the operational amplifier, i.e., the source terminal voltage of MOSFET MS1, is the same as the voltage at the negative terminal P- of the battery output.

[0180] Furthermore, because the input impedance of the operational amplifier is approximately infinite, all the current from the sampling MOSFET flows into the sampling resistor R (whose resistance is Rh).

[0181] Thus, the output voltage V of the operational amplifier sns =Rh*Ichg / K+V(B-)=Rh*Ichg / K. Because V sns The value can be obtained by the subsequent voltage sampling circuit. Rh is a pre-designed circuit value, so as to accurately obtain the magnitude of the charging current Ichg flowing through the charging and discharging switch, thus not being affected by the system voltage or temperature.

[0182] According to a seventh embodiment of this disclosure, a VDMOS device structure is also provided.

[0183] The difference between this device structure and the device structure of the sixth embodiment is that the two sampling MOSFETs are located on the discharge MOSFET side.

[0184] Figure 14 A schematic diagram of an application according to this embodiment is shown. It is used for controlling battery charging overcurrent. The discharge current Idsg flows from the P- terminal to the B- terminal.

[0185] The charge / discharge control unit may include a detection unit and a comparator.

[0186] The first input terminal of the comparator is connected to a voltage related to the voltage at the second terminal of the detection unit. The first input terminal of the comparator is also connected to a voltage related to the voltage at the first terminal of the charge / discharge switch. The first terminal of the detection unit is connected to the first terminal of the charge / discharge switch. The charge / discharge switch is a charge / discharge switch.

[0187] In this embodiment, the comparator is an operational amplifier, and a detection resistor is connected in series between the second input terminal and the output terminal of the operational amplifier. One end of the MOSFET of the detection unit is connected to the second input terminal of the operational amplifier, and the other end of the MOSFET of the detection unit is connected to the second terminal of the charge / discharge switch. The first input terminal of the operational amplifier is connected to the first terminal of the charge / discharge switch.

[0188] The current value of the charging current or the discharging current is obtained by using the voltage generated by the detection resistor and the resistance value of the detection resistor.

[0189] The following will refer to Figure 14 A detailed description is provided. The detection unit may include sampling MOSFETs MS1 and MS2. Sampling MOSFETs MS1 and MS2 can be the same type of MOSFET, namely charging MOSFET MC and discharging MOSFET MD. The source of MOSFET MS1 is connected to the B- terminal, and its drain is connected to the drain of MOSFET MS2. The source of MOSFET MS2 is connected to one input terminal of an operational amplifier. The gate of MOSFET MS1 is connected to the control signal OC, and the gate of MOSFET MS2 is connected to the control signal OD. The other input terminal of the operational amplifier is connected to the P- terminal.

[0190] The principle of this implementation method will be explained in detail below.

[0191] When charging, an external load is connected between the battery's positive output terminal P+ and negative output terminal P-, and its resistance is R. Load Thus, the battery discharge current Idsg is [V(P+) - V(P-)] / R Load .

[0192] The operational amplifier ensures that the source voltage of MOSFET MS1 is the same as the voltage at the negative P-terminal of the battery output. NMOSMOSFET MS1 is the same type of MOSFET as the discharge MOSFET, and NMOSMOSFET MS2 is the same type of MOSFET as the charge MOSFET. Therefore, even with changes in temperature or voltage, the ratio of the series equivalent on-resistance of MOSFET MS1 and MOSFET MS2 to the series equivalent on-resistance of MOSFET MD and MOSFET MS remains constant at K:1. Thus, the current flowing through MOSFET MS1 and MOSFET MS2 remains constant at 1:K compared to the current flowing through MOSFET MD and MOSFET MS.

[0193] Because of the negative feedback of the operational amplifier, the source voltage of the negative input terminal of the operational amplifier, i.e., MOSFET MS1, is the same as the negative P-terminal voltage of the battery output.

[0194] Because the input impedance of the operational amplifier is approximately infinite, the current in MOSFET MS1 and MOSFET MS2 flows entirely into the sampling resistor R (resistance value Rg).

[0195] Thus, the output voltage V of the operational amplifier sns =Rg*Idsg / k+V(P-). V(P-) is the voltage at the P- terminal.

[0196] V(P-)=V(B-)+Idsg*(R on1 +R on2 V(B-) is the voltage at terminal B-, R on1 R is the equivalent resistance of the MOSFET MD. on2 This is the equivalent resistance of the MOSFET MS.

[0197] The B- terminal is the ground terminal of the battery, so V(B-) can be considered as the "ground" point of the system, therefore V(B-) = 0.

[0198] Thus, V(P-)=Idsg*(R) on1 +R on2 ).

[0199] V sns =Rg*Idsg / K+V(P-)=Rg*Idsg / K+Idsg*(R on1 +R on2 )

[0200] =Idsg*[(Rg / K+(R on1 +R on2 )).

[0201] Typically, Rg / K >> (R on1 +R on2 Therefore, the above equation can be equivalent to V. sns =Idsg*Rg / K, Idsg=K*V sns / Rg.

[0202] V sns The value can be obtained by the subsequent voltage sampling circuit. Rg is a pre-designed circuit value, so as to accurately obtain the magnitude of the discharge current Idsg flowing through the charge and discharge switch, so as not to be affected by the system voltage or temperature.

[0203] Figure 15 A VDMOS device structure according to an eighth embodiment of the present disclosure is shown.

[0204] The difference between this device structure and the device structure in the first embodiment is the addition of two sensing resistors, Rsns1 and Rsns2. The specific implementation of the sensing resistors Rsns1 and Rsns2 can be found, for example, in [reference needed]. Figure 8 The relevant descriptions will not be repeated here.

[0205] Figure 16 It shows the relationship with Figure 15 The circuit diagram corresponding to the VDMOS device structure.

[0206] Figure 17 It shows Figure 15 VDMOS device structure and Figure 16 The circuit shown is used in the following configuration. The charge / discharge control unit may include detection units composed of MS1 and MS2, resistors Rsns1 and Rsns3, and comparators CMP1 and CMP2, etc. The resistance values ​​of Rsns1 to Rsns6 can be equal. MOSFETs MD and MC constitute the discharge MOSFET and charge MOSFET, respectively.

[0207] The control principle of charging and discharging in this embodiment is similar to that in the first embodiment, and will not be repeated here.

[0208] MOSFETs MS1 and MS2 are the same type of MOSFET as MOSFETs MD and MC. The ratio of the on-resistance of MOSFETs MS1 and MS2 to that of MOSFETs MD and MC is constant at K:1, and the ratio of their cell counts is 1:K. MOSFETs MS1 and MS2 can have the same cell count, and MOSFETs MD and MC can also have the same cell count.

[0209] During discharge, when MOSFET MD is turned off, the current flowing through MOSFET MD and MC is VREF2 / Rsns6*K. Since VREF2 and Rsns6 are fixed values, and K is a constant ratio, these three values ​​will not change when the system voltage and temperature change. Therefore, the current flowing through MOSFET MD and MC will not change, meaning that the detected discharge current will not change with voltage or temperature.

[0210] During charging, when MOSFET MC is off, the current flowing through MOSFET MD and MC is VREF1 / Rsns4*K. Since VREF1 and Rsns4 are fixed values, and K is a constant ratio, these three values ​​will not change when the system voltage and temperature change. Therefore, the current flowing through MOSFET MD and MC will not change, meaning that the detected charging current will not change with voltage or temperature.

[0211] Figure 18 A VDMOS device structure according to a ninth embodiment of the present disclosure is shown. The difference between this device structure and the first embodiment is that the cell structures are all replaced with SGT MOSFET structures. The VDMOS device 200 may include: a substrate 202, an epitaxial layer 204, and cell structures, wherein each cell structure includes a gate oxide layer 206, a dielectric layer 210, a first well region 112, a second well region 214, and a heavily doped region 216. It may also include a source electrode 218 and a drain electrode 220.

[0212] In this embodiment, Figure 1 The polysilicon 108 shown is replaced by a shielding gate 2081 and a control gate 2082, which are separated by a dielectric layer 210.

[0213] Thus, the VDMOS device structure of this embodiment can also achieve the functions of the above embodiments. Furthermore, for other embodiments besides the first embodiment, their cell structure can be replaced with the cell structure shown in the ninth embodiment, and the same functions can be achieved. Further details will not be provided here.

[0214] Alternatively, the structure of the SGT MOSFET can be replaced with that of the LDMOS.

[0215] According to the present disclosure, a battery management chip includes the above-described charge / discharge control circuit and the charge / discharge switch.

[0216] According to this disclosure, an electrical device includes: a battery management chip as described above; and a battery for supplying power to other components of the electrical device, and the battery management chip for managing the battery.

[0217] According to the VDMOS structure disclosed herein, the ratio of the charging / discharging circuit current to the sampling branch current is achieved by adjusting the number of cells of the charging / discharging power transistor and the sampling transistor, thereby realizing accurate current sampling. At the same time, due to process compatibility, the sampling transistor and the power transistor can be integrated together to achieve the purpose of current sampling. Furthermore, the sampling can be achieved by integrating the resistor and sampling the voltage across the integrated resistor. From an application perspective, this can greatly increase the system integration, avoid the problem of large size, and reduce the system cost.

[0218] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0219] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0220] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A charge / discharge control circuit, the control circuit including a VDMOS device for controlling the charging current and discharging current of a battery, characterized in that, The VDMOS device includes: Substrate, wherein the substrate is of a first conductivity type; An epitaxial layer, wherein the epitaxial layer is disposed on the substrate and is of a first conductivity type; A first cell structure region, comprising cell structures formed in the epitaxial layer to constitute a charging MOSFET; The second cell structure region includes cell structures formed in the epitaxial layer to constitute a discharge MOSFET; and The third cell structure region includes cell structures formed in the epitaxial layer to constitute a sampling MOSFET, which is used to collect the current flowing through the charging MOSFET and the discharging MOSFET. The ratio of the number of cell structures in the third cell structure region to the number of cell structures in the first and second cell structure regions is 1:K, where K≥2; The control circuit charges and discharges the battery through the first connection terminal and the second connection terminal. The charging MOSFET and the discharging MOSFET constitute a charge-discharge switch connected in series in the current path between the battery and the first connection terminal or between the battery and the second connection terminal. The control circuit also includes: A comparison unit, wherein a first input terminal of the comparison unit is connected to a first terminal of the detection unit, a second input terminal of the comparison unit is connected to a first terminal of the charge / discharge switch, and a second terminal of the detection unit is connected to a second terminal of the charge / discharge switch; and A control logic unit that controls the charging MOSFET and the discharging MOSFET based on the comparison result output by the comparison unit; The number of the third cell structure region and the sampling MOSFET is one, and the source of the sampling MOSFET is configured to be connected to the source of the charging MOSFET or the source of the discharging MOSFET, and the drain of the sampling MOSFET is configured as a sampling terminal for the charging current or the discharging current. The VDMOS device further includes a well resistor structure to form a well resistor. One end of the well resistor is configured to be connected to the source of the sampling MOSFET, and the other end of the well resistor is configured to be connected to the source of the discharge MOSFET or the source of the charging MOSFET. One end of the well resistor is configured as a sampling terminal for the discharge current or the charging current. The sampling MOSFET and the well resistor constitute the detection unit of the control circuit. The value of the well resistor is much smaller than the on-resistance of the sampling MOSFET; The current ratio between the current flowing through the charge / discharge switch and the current flowing through the detection unit is independent of the system voltage and system temperature.

2. The charging and discharging control circuit as described in claim 1, characterized in that, The charging MOSFET and the discharging MOSFET are configured such that their drains are connected.

3. The charging and discharging control circuit as described in claim 1, characterized in that, The third cell structure region and the number of the sampling MOSFETs are two, and one sampling MOSFET is connected to the drain of the other sampling MOSFET. The source of one of the two sampling MOSFETs is configured to be connected to the source of the charging MOSFET or the source of the discharging MOSFET, and the source of the other sampling MOSFET is configured as a sampling terminal for the charging current or the discharging current.

4. The charging and discharging control circuit as described in claim 1, characterized in that, The number of the third cell structure region and the sampling MOSFETs is four, among which Of the four sampling MOSFETs, one sampling MOSFET is connected to the drain of the other sampling MOSFET, the source of the sampling MOSFET is configured to be connected to the source of the charging MOSFET, and the source of the other sampling MOSFET is configured as a charging current sampling terminal. as well as Of the four sampling MOSFETs, one sampling MOSFET is connected to the drain of the other sampling MOSFET, the source of the sampling MOSFET is configured to be connected to the source of the discharge MOSFET, and the source of the other sampling MOSFET is configured to be a discharge current sampling terminal.

5. The charge / discharge control circuit as described in claim 3, characterized in that, The VDMOS device further includes two well resistor structures to form two well resistors. The source of one sampling MOSFET is configured to be connected to one end of one well resistor, and the other end of the one well resistor is configured to be connected to the source of the charging MOSFET. One end of the other well resistor is configured to be connected to the source of the other sampling MOSFET, and the other end of the other well resistor is configured to be connected to the source of the discharging MOSFET. One end of one well resistor is the charging current sampling terminal, and one end of the other well resistor is the discharging current sampling terminal. The sampling MOSFET and the well resistor constitute the detection unit of the control circuit.

6. The charge / discharge control circuit as described in any one of claims 1 to 5, characterized in that, Each cell structure includes: Two trenches, each containing a gate oxide layer, polysilicon, and a dielectric layer on top of the polysilicon; The first well region is of the second conductivity type and is located outside the two trenches; A second well region, having a second conductivity type, is located above the epitaxial layer and between the two trenches; and A heavily doped region, which is located above the second well region and between the two trenches, is of a first conductivity type.

7. The charge / discharge control circuit as described in any one of claims 1 to 5, characterized in that, Each cell structure includes: Two trenches are provided in each trench, including a gate oxide layer, a control gate, a shield gate, a first dielectric layer and a second dielectric layer. The control gate is located above the shield gate and is separated by the first dielectric layer, and the second dielectric layer is located above the control gate. The first well region is of the second conductivity type and is located outside the two trenches; A second well region, having a second conductivity type, is located above the epitaxial layer and between the two trenches; and A heavily doped region, which is located above the first well region and between the two trenches, and the heavily doped region is of a first conductivity type.

8. The charge / discharge control circuit according to any one of claims 1 to 5, characterized in that, The impedance ratio between the on-resistance value of the charge / discharge switch and the on-resistance value of the detection unit remains constant.

9. The charge / discharge control circuit according to any one of claims 1 to 5, characterized in that, The current ratio between the current flowing through the charge / discharge switch and the current flowing through the detection unit remains constant.

10. The charge / discharge control circuit according to any one of claims 1 to 5, characterized in that, With the discharge current controlled, The source of the sampling MOSFET of the detection unit is connected to the source of the discharge MOSFET, the drain of the sampling MOSFET is connected to a constant current that is independent of voltage and temperature, and the discharge current flows from the charging MOSFET to the discharge MOSFET.

11. The charge / discharge control circuit as described in claim 10, characterized in that, When the voltage on the source side of the charging MOSFET is greater than the voltage on the drain side of the sampling MOSFET, the comparison result of the comparison unit is flipped, and the control logic unit controls the discharge MOSFET to turn off.

12. The charge / discharge control circuit according to any one of claims 1 to 5, characterized in that, With the charging current controlled, The source of the sampling MOSFET is connected to the source of the charging MOSFET, the drain of the sampling MOSFET is connected to a constant current that is independent of voltage and temperature, and a discharge current flows from the discharge MOSFET to the charging MOSFET.

13. The charge / discharge control circuit according to any one of claims 1 to 5, characterized in that, When the voltage on the source side of the discharge MOSFET is greater than the voltage on the drain side of the sampling MOSFET, the comparison result of the comparison unit is flipped, and the control logic unit controls the charging MOSFET to be turned off.

14. The charge / discharge control circuit according to any one of claims 1 to 5, characterized in that, It also includes mirror circuits and comparators. With the discharge current controlled, the source of the sampling MOSFET is connected to the source of the discharge MOSFET, the drain of the sampling MOSFET is connected to a mirror circuit, the voltage on the drain side of the sampling MOSFET is set to be equal to the voltage on the source side of the charging MOSFET, and the discharge current flows from the charging MOSFET to the discharge MOSFET. When the voltage at the source side of the charging MOSFET is greater than the voltage at the drain side of the sampling MOSFET, the comparison result of the comparator is flipped, and the mirror circuit is controlled to mirror the current flowing through the sampling MOSFET to generate a mirror current. The voltage generated based on the mirror current is input to the first input terminal of the comparator, and the reference voltage is input to the second input terminal of the comparator. The comparison result of the comparator is used to enable the control logic unit to control the discharge MOSFET to turn off.

15. The charge / discharge control circuit according to any one of claims 1 to 5, characterized in that, It also includes mirror circuits and comparators. With the charging current controlled, the source of the sampling MOSFET is connected to the source of the charging MOSFET, the drain of the sampling MOSFET is connected to a mirror circuit, the voltage on the drain side of the sampling MOSFET is set to be equal to the voltage on the source side of the discharging MOSFET, and the charging current flows from the discharging MOSFET to the charging MOSFET. When the voltage on the source side of the discharge MOSFET is greater than the voltage on the drain side of the sampling MOSFET, the comparison result of the comparator is flipped, and the mirror circuit is controlled to mirror the current flowing through the sampling MOSFET to generate a mirror current. The voltage generated based on the mirror current is input to the first input terminal of the comparator, and the reference voltage is input to the second input terminal of the comparator. The comparison result of the comparator is used to enable the control logic unit to control the charging MOSFET to turn off.

16. The charge / discharge control circuit as described in claim 1, characterized in that, When the discharge current is controlled, the connection point of the well resistor and the sampling MOSFET is connected to the first input terminal of the comparison unit, and the second input terminal of the comparison unit is connected to the reference voltage generated based on the source-side voltage of the discharge MOSFET. When the voltage at the first input terminal of the comparison unit is greater than the voltage at the second input terminal, the comparison result of the comparison unit is flipped, and the control logic unit controls the discharge MOSFET to be turned off.

17. The charge / discharge control circuit as described in claim 1, characterized in that, When the charging current is controlled, and the connection point of the well resistor and the sampling MOSFET is connected to the first input terminal of the comparison unit, and the second input terminal of the comparison unit is connected to the reference voltage generated based on the source-side voltage of the charging MOSFET, when the voltage at the first input terminal of the comparison unit is greater than the voltage at the second input terminal, the comparison result of the comparison unit is flipped, and the control logic unit controls the charging MOSFET to be turned off.

18. A battery management chip, characterized in that, Includes the charge / discharge control circuit as described in any one of claims 1 to 17.

19. An electrical device, characterized in that, include: The battery management chip as described in claim 18; as well as The battery is used to power other components of the electrical device, and the battery management chip is used to manage the battery.

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