Flexible Printed Circuit Board

Abstract

A flexible printed circuit board comprises: a conductive layer, the conductive layer comprising a first signal line, a first ground plane, and a second ground plane. A first shielding via extends from a third ground plane to a fourth ground plane and extends through the first ground plane to electrically connect the first ground plane, the third ground plane, and the fourth ground plane. A second shielding via extends from the third ground plane to the fourth ground plane. The first ground plane, the second ground plane, the third ground plane, the fourth ground plane, the first shielding via, and the second shielding via together circumferentially surround the first signal line to minimize electromagnetic interference to the first signal line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 62 / 616,821, filed on January 12, 2018, and entitled “Flexible Printed Circuit Board,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates generally to flexible printed circuit boards, and more particularly to a flexible printed circuit board for transmitting high frequency signals. Summary of the invention

[0004] A flexible printed circuit board is disclosed, which includes: a conductive layer, which includes a first signal line, a first ground plane, and a second ground plane; a first ground plane layer, which includes a third ground plane; a second ground plane layer, which includes a fourth ground plane; and a first shielding via, which extends from the third ground plane to the fourth ground plane and extends through the first ground plane to electrically connect the first ground plane, the third ground plane, and the fourth ground plane; and a second shielding via, which extends from the third ground plane to the fourth ground plane and extends through the second ground plane to electrically connect the second ground plane, the third ground plane, and the fourth ground plane, the first ground plane, the second ground plane, the third ground plane, the fourth ground plane, the first shielding via, and the second shielding via together circumferentially surround the first signal line to minimize electromagnetic interference to the first signal line.

[0005] In one aspect, the signal line is located between the first ground plane and the second ground plane.

[0006] In one aspect, the first signal line is located between the third ground plane and the fourth ground plane.

[0007] In one aspect, the first signal line is located between the first shielding via and the second shielding via.

[0008] In one aspect, the impedance of the first signal line is between 45 ohms and 55 ohms.

[0009] In one aspect, the impedance of the first signal line is between about 49 ohms and about 51 ohms.

[0010] In one aspect, the impedance of the first signal line is between 67.5 ohms and 82.5 ohms.

[0011] In one aspect, the impedance of the first signal line is about 75 ohms.

[0012] In one aspect, the impedance of the first signal line is between 90 ohms and 110 ohms.

[0013] In one aspect, the impedance of the first signal line is about 100 ohms.

[0014] In one aspect, the flexible printed circuit board includes a first dielectric plane located between a first signal line and a third ground plane.

[0015] In one aspect, the first dielectric plane has a thickness of about 0.004 inches.

[0016] In one aspect, the flexible printed circuit board includes a second dielectric plane located between the first signal line and the fourth ground plane.

[0017] In one aspect, the second dielectric plane has a thickness of about 0.003 inches.

[0018] In one aspect, the total thickness of the conductive layer, the first ground plane layer, the second ground plane layer, the first dielectric plane, and the second dielectric plane is about 0.0094 inches.

[0019] In one aspect, the first ground plane, the second ground plane, and the first signal line have a thickness of approximately 0.001 inches.

[0020] In one aspect, the third ground plane has a thickness of approximately 0.007 inches.

[0021] In one aspect, the fourth ground plane has a thickness of approximately 0.007 inches.

[0022] In one aspect, a flexible printed circuit board includes: a second signal line, a fifth ground plane, and a sixth ground plane located at a conductive layer, the second signal line being separated from and different from the first signal line; a seventh ground plane located at the first ground plane layer; an eighth ground plane located at the second ground plane layer; a third shielding via extending from the seventh ground plane to the eighth ground plane and extending through the fifth ground plane to electrically connect the fifth ground plane, the seventh ground plane, and the eighth ground plane; and a fourth shielding via extending from the seventh ground plane to the eighth ground plane and extending through the sixth ground plane to electrically connect the sixth ground plane, the seventh ground plane, and the eighth ground plane, the fifth ground plane, the sixth ground plane, the seventh ground plane, the eighth ground plane, the second shielding via, and the third shielding via together circumferentially surround the second signal line to minimize electromagnetic interference to the second signal line.

[0023] In one aspect, the second shielding via and the third shielding via are located between the first signal line and the second signal line.

[0024] In one aspect, the second ground plane and the fifth ground plane are located between the first signal line and the second signal line.

[0025] In one aspect, the flexible printed circuit board includes a dielectric plane located between the third ground plane and the seventh ground plane at the first ground plane layer to electromagnetically isolate the third ground plane and the seventh ground plane.

[0026] In one aspect, the flexible printed circuit board includes a dielectric plane located between the second ground plane and the fifth ground plane at the conductive layer to electromagnetically isolate the second ground plane from the fifth ground plane.

[0027] In one aspect, the flexible printed circuit board includes a dielectric plane located between a fourth ground plane and an eighth ground plane at the second ground plane layer to electromagnetically isolate the fourth ground plane and the eighth ground plane.

[0028] A method for manufacturing a flexible printed circuit board is disclosed, the method comprising: providing a conductive layer, the conductive layer comprising a first signal line, a first ground plane, and a second ground plane; providing a first ground plane layer, the first ground plane layer comprising a third ground plane; providing a second ground plane layer, the second ground plane layer comprising a fourth ground plane; and stitching a first shielding via, the first shielding via extending from the third ground plane to the fourth ground plane and extending through the first ground plane to electrically connect the first ground plane, the third ground plane, and the fourth ground plane; and stitching a second shielding via, the second shielding via extending from the third ground plane to the fourth ground plane and extending through the second ground plane to electrically connect the second ground plane, the third ground plane, and the fourth ground plane, the first ground plane, the second ground plane, the third ground plane, the fourth ground plane, the first shielding via, and the second shielding via together circumferentially surround the first signal line to minimize electromagnetic interference to the first signal line.

[0029] In one aspect, the method further includes positioning the signal line between the first ground plane and the second ground plane.

[0030] In one aspect, the method further includes positioning the first signal line between the third ground plane and the fourth ground plane.

[0031] In one aspect, the method further includes disposing a first signal line between the first shielding via and the second shielding via.

[0032] In one aspect, the impedance of the first signal line is between 47.5 ohms and 52.5 ohms.

[0033] In one aspect, the impedance of the first signal line is between about 49 ohms and about 51 ohms.

[0034] In one aspect, the impedance of the first signal line is between 67.5 ohms and 82.5 ohms.

[0035] In one aspect, the impedance of the first signal line is about 75 ohms.

[0036] In one aspect, the impedance of the first signal line is between 90 ohms and 110 ohms.

[0037] In one aspect, the impedance of the first signal line is about 100 ohms.

[0038] In one aspect, the method further includes providing a first dielectric plane between the first signal line and the third ground plane.

[0039] In one aspect, the first dielectric plane has a thickness of about 0.004 inches.

[0040] In one aspect, the method further includes providing a second dielectric plane between the first signal line and the fourth ground plane.

[0041] In one aspect, the second dielectric plane has a thickness of about 0.003 inches.

[0042] In one aspect, the total thickness of the conductive layer, the first ground plane layer, the second ground plane layer, the first dielectric plane, and the second dielectric plane is about 0.0094 inches.

[0043] In one aspect, the first ground plane, the second ground plane, and the first signal line have a thickness of approximately 0.001 inches.

[0044] In one aspect, the third ground plane has a thickness of approximately 0.007 inches.

[0045] In one aspect, the fourth ground plane has a thickness of approximately 0.007 inches.

[0046] In one aspect, the method also includes: setting a second signal line, a fifth ground plane and a sixth ground plane at the conductive layer, the second signal line being separated from and different from the first signal line; setting a seventh ground plane at the first ground plane layer; setting an eighth ground plane at the second ground plane layer; stitching a third shielding via, the third shielding via extending from the seventh ground plane to the eighth ground plane and extending through the fifth ground plane to electrically connect the fifth ground plane, the seventh ground plane and the eighth ground plane; and stitching a fourth shielding via, the fourth shielding via extending from the seventh ground plane to the eighth ground plane and extending through the sixth ground plane to electrically connect the sixth ground plane, the seventh ground plane and the eighth ground plane, the fifth ground plane, the sixth ground plane, the seventh ground plane, the eighth ground plane, the second shielding via and the third shielding via together circumferentially surround the second signal line to minimize electromagnetic interference to the second signal line.

[0047] In one aspect, the method further includes positioning a second shielding via and a third shielding via between the first signal line and the second signal line.

[0048] In one aspect, the method further includes positioning a second ground plane and a fifth ground plane between the first signal line and the second signal line.

[0049] In one aspect, the method further includes positioning a dielectric plane between the third ground plane and the seventh ground plane at the first ground plane layer to electromagnetically isolate the third ground plane and the seventh ground plane.

[0050] In one aspect, the method further includes positioning a dielectric plane between the second ground plane and the fifth ground plane at the conductive layer to electromagnetically isolate the second ground plane from the fifth ground plane.

[0051] In one aspect, the method further includes positioning a dielectric plane between the fourth ground plane and the eighth ground plane at the second ground plane layer to electromagnetically isolate the fourth ground plane and the eighth ground plane. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The foregoing summary of the invention as well as the following detailed description of embodiments of the invention will be better understood when read in conjunction with the accompanying drawings of exemplary embodiments. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.

[0053] In the attached picture:

[0054] Figure 1 is a partial cross-section of a flexible printed circuit board according to an exemplary embodiment of the present invention;

[0055] Figure 2is a partial cross-section of a flexible printed circuit board according to an exemplary embodiment of the present invention;

[0056] Figure 3 is a flow chart of a method for manufacturing a flexible printed circuit board according to an exemplary embodiment of the present invention;

[0057] Figure 4 is a partial cross-section of a flexible printed circuit board according to an exemplary embodiment of the present invention; and

[0058] Figure 5 is a conceptual top cross-section of a flexible printed circuit board according to an exemplary embodiment of the present invention; and

[0059] Figure 6 yes Figure 5 An enlarged view of a portion of. DETAILED DESCRIPTION

[0060] In high-frequency applications that require many different radio frequency (RF) signals, such as radio or video transmission systems, coaxial cables can be used as signal lines. There are many advantages to using coaxial cables. For example, coaxial cables can be used to minimize electromagnetic interference (i.e., crosstalk) between signal lines. However, to achieve these desired effects, coaxial cables can be bulky, making them unsuitable for use in applications that require compact signal lines.

[0061] Flexible printed circuit boards (FPCBs) can be preferred over coaxial cables because FPCBs are more compact. FPCBs are a combination of different substrates that are laminated together to form a circuit. However, in order to use FPCBs and maintain a compact design, signal lines must be placed close to each other. Unfortunately, when signal lines on an FPCB are placed close to each other, there can be electromagnetic interference between the signal lines that causes signal degradation. Therefore, there is a need to have a compact signal line configuration that also minimizes electromagnetic interference. When printing or performing photolithography, tolerances can be more easily controlled.

[0062] In one embodiment of the present invention, a FPCB having multiple signal lines includes one or more ground planes positioned around each signal line on the same and / or different layers of the FPCB. The ground planes can be electrically connected by stitching vias. Once the ground planes are electrically connected, an electromagnetic shield (or Faraday cage) circumferentially surrounding the signal lines can be formed to protect the signal lines from electromagnetic interference from external sources.

[0063] Referring to the drawings in detail, wherein like reference numerals refer to like elements throughout, Figures 1 to 6 1 and 2, a flexible printed circuit board (FPCB) 10 and an FPCB 20, a method 30 of manufacturing the FPCB, an FPCB 40, and a cable 50 according to an exemplary embodiment of the present invention are respectively shown.

[0064] Figure 1 1 shows a cross section of an FPCB 10 according to an exemplary embodiment of the present invention. The FPCB 10 may include a conductive layer 100. The conductive layer 100 may include a signal line 104, a side ground plane 103a, and / or a side ground plane 103b.

[0065] The signal line 104 can be configured to transmit an electrical signal (e.g., an RF signal or a video signal). In some embodiments, the electrical signal can exceed 100 MHz. At these frequencies, the electrical signal can experience signal quality attenuation and degradation due to exposure to any electromagnetic interference. Electromagnetic interference can have a greater impact at higher frequency signals than at lower frequency signals. As used herein, attenuation can refer to any decrease in signal strength. The effects of attenuation and degradation of signal quality can be mitigated by using an FPCB with selected materials for each layer and traces with tighter variations (such as trace width, trace height, and trace spacing) than coaxial cables.

[0066] Side ground plane 103a and side ground plane 103b may be located on opposite sides of signal line 104. Side ground plane 103a and / or side ground plane 103b may be configured as an electromagnetic shield to electrically isolate signal line 104 from external sources (eg, other signal lines).

[0067] The signal line, side ground plane 103a, and / or side ground plane 103b may each be approximately 0.001 inches thick.

[0068] The FPCB 10 may include a top ground plane 102 and / or a bottom ground plane 106. The top ground plane 102 and / or the bottom ground plane 106 may be configured as an electromagnetic shield to electrically isolate the signal line 104 from external sources. The top ground plane 102 and / or the bottom ground plane 106 may be flexible with a bending radius as tight as 0.5 inches. The top ground plane 102 and / or the bottom ground plane 106 may be 0.5 ounce copper. The top ground plane 102 and / or the bottom ground plane 106 may be 1.0 ounce copper.

[0069] The side ground plane 103 a , the side ground plane 103 b , and the signal line 104 may be located between the top ground plane 102 and the bottom ground plane 106 .

[0070] The FPCB 10 may include a dielectric layer 101 and a dielectric layer 105. The dielectric layer 101 and the dielectric layer 105 may be configured to electrically insulate the signal line 104 from the ground planes 102, 103a, 103b, 106 to prevent a short circuit of the signal line 104. The dielectric layer 101 and / or the dielectric layer 105 may be an adhesive. The dielectric layer 101 and / or the dielectric layer 105 may be a flexible laminate. The dielectric layer 101 may be approximately 0.004 inches thick. The dielectric layer 105 may be approximately 0.003 inches thick. The signal line 104 may be located between the dielectric layer 101 and the dielectric layer 105.

[0071] The signal line 104, the dielectric layer 101, and the dielectric layer 105 can be connected using an acrylic adhesive 107. The acrylic adhesive 107 can be located between the signal line 104 and the side ground planes 103a and 103b, and is configured to electrically insulate the signal line 104 from the side ground planes 103a and 103b. The vias can be shielded vias or stitched vias that extend between two or more layers and connect the two or more layers, and can be used to shield electromagnetic interference or connect ground planes, as discussed in further detail below. In some embodiments, the vias are formed after the layers are formed (e.g., by drilling). In some embodiments, the cross-section of the via is circular, but in other embodiments, the cross-section of the via can be square or triangular.

[0072] FPCB 10 may include shielding vias 108a and shielding vias 108b. Shielding vias 108a and / or shielding vias 108b may be sections of conductive materials extending between two parallel layers to electrically couple the layers together. Shielding vias 108a and / or shielding vias 108b may have a cross-sectional diameter less than or equal to 0.100 inches, and in some embodiments have a cross-sectional diameter less than or equal to 0.0078 inches. Shielding vias 108a and / or shielding vias 108b may have a cross-sectional diameter less than 50% of the width of the narrowest layer through which the via passes. In some embodiments, shielding vias 108a and / or shielding vias 108b may have a cross-sectional diameter between 0.100 inches and 0.050 inches. In some embodiments, shielding vias 108a may have a cross-sectional diameter different from that of shielding vias 108b. The shielding vias 108a and / or the shielding vias 108b may be substantially perpendicular to the two parallel layers connected by the vias 108a to 108b. The shielding vias 108a and / or the shielding vias 108b may be inserted into the FPCB 10 after the layers are formed, as discussed in further detail below. For example, the shielding vias 108a and / or the shielding vias 108b may be strip lines sewn into the FPCB 10.

[0073] The FPCB 10 may include stitching vias 130a and / or stitching vias 130b, which may connect two or more ground systems to create a common ground between the two ground systems, thereby reducing phase changes between two or more signal lines and / or preventing any of the ground systems from acting as a transmission line segment itself. The stitching vias 130a and / or stitching vias 130b may be sections of conductive material extending between two parallel ground layers to electrically couple the ground layers together. The stitching vias 130a and / or stitching vias 130b may have a diameter of 0.100 inches, and in some embodiments, a diameter of 0.0078 inches. The stitching vias 130a and / or stitching vias 130b may be substantially perpendicular to the two ground layers. The stitching vias 130a and / or stitching vias 130b may be inserted into the FPCB 10 after layer formation, as discussed in further detail below. For example, the stitching vias 130 a to 130 b may be strip lines stitched into the FPCB 10 .

[0074] In some embodiments, the FPCB 10 may not include any shielding vias and stitching vias. In some embodiments, the FPCB 10 may include only shielding vias. In some embodiments, the FPCB 10 may include only stitching vias.

[0075] The shielding via 108a can be configured to electrically connect the top ground plane 102, the side ground plane 103a, and the bottom ground plane 106 to surround at least a portion of the signal line 104. The shielding via 108b can electrically connect the top ground plane 102, the side ground plane 103b, and the bottom ground plane 106. The shielding via 108a and / or the shielding via 108b can be flexible. The shielding via 108a, the shielding via 108b, the side ground plane 103a, the side ground plane 103b, the top ground plane 102, and / or the bottom ground plane 106 can circumferentially surround the signal line 104 to minimize electromagnetic interference (e.g., crosstalk) between the signal line 104 and external sources.

[0076] The FPCB 10 may include a top inner cover layer 110 and a bottom inner cover layer 111. The top inner cover layer 110 and / or the bottom inner cover layer 111 may be configured to cover the top ground plane 102, the bottom ground plane 106, and the shielding vias 108a, 108b. The top inner cover layer 110 and / or the bottom inner cover layer 111 may be an acrylic adhesive. The top inner cover layer 110 and / or the bottom inner cover layer 111 may be 0.001 inches thick. The FPCB 10 may include a top outer cover layer 109 and a bottom outer cover layer 112. The top outer cover layer 109 may be configured to cover the top inner cover layer 110. The bottom outer cover layer 112 may be configured to cover the bottom inner cover layer 111. The top outer cover layer 109 and / or the bottom outer cover layer 112 may be a polyimide film (e.g., a KAPTON film). The top outer cover layer 109 and / or the bottom outer cover layer 112 may be 0.001 inches thick.

[0077] The FPCB 10 may include a top prepreg layer 115 and a bottom prepreg layer 116. The basic materials that may be needed to build a multilayer board may include copper foil, a prepreg (pre-impregnated bonding sheet), and an inner core. In some embodiments, the prepreg is a fiber material pre-impregnated with a specific synthetic resin, which can be used in the manufacture of reinforced plastics. The top prepreg layer 115 and / or the bottom prepreg layer 116 may be 0.005 inches thick. The top prepreg layer 115 may contact the top cover layer 109. The bottom prepreg layer 116 may contact the bottom cover layer 112. The FPCB 10 may include a top laminate layer 113 and a bottom laminate layer 114. The top laminate layer 113 and the bottom laminate layer 114 may include a high-performance FR406.008 0 / H epoxy resin material. The top laminate layer 113 and / or the bottom laminate layer 114 may be 0.008 inches thick. The top laminate layer 113 may be in contact with the top prepreg layer 115. The bottom laminate layer 114 may be in contact with the bottom prepreg layer 116. The FPCB 10 may include through vias 117, 118, 119, and 120. The through vias 117, 118, 119, and 120 may include pads located in corresponding positions on different layers of the FPCB 10, which may provide electrical connections between components.

[0078] Figure 2 A cross section of an exemplary FPCB 20 according to one embodiment of the present invention is shown. Figure 2 The FPCB 20 shown in FIG. Figure 1 The FPCB 10 shown in FIG. 1 is similar to the FPCB 10 shown in FIG. 1 , but also includes additional signal lines and corresponding structures, as described in more detail below.

[0079] FPCB 20 may include signal line 204, separate and distinct from signal line 104. Signal line 204 may be configured to transmit an electrical signal (e.g., an RF signal or a video signal). In some embodiments, the electrical signal may exceed 100 MHz. In some embodiments of the present invention, FPCB 20 may include 4, 8, 16, 32, 64, and / or N signal lines, where N is an integer.

[0080] The FPCB 20 may include a side ground plane 203a, a side ground plane 203b, a top ground plane 202, and a bottom ground plane 206. The side ground plane 203a, the side ground plane 203b, the top ground plane 202, and / or the bottom ground plane 206 may include features similar to the side ground plane 103a, the side ground plane 103b, the top ground plane 102, and the bottom ground plane 106, respectively.

[0081] In some embodiments, signal line 104 is electrically separated from signal line 204 by gaps between channels. In some embodiments, dielectric layer 210 can be located between top ground plane 102 and top ground plane 202. In some embodiments, dielectric layer 212 can be located between side ground plane 103b and side ground plane 203a. In some embodiments, dielectric layer 214 can be located between bottom ground plane 106 and bottom ground plane 206. In some embodiments, signal line 104 can be located between dielectric layers 231a-231b. In some embodiments, signal line 204 can be located between dielectric layers 231c-231d.

[0082] The FPCB 20 may include a shielding via 208a and / or a shielding via 208b. The shielding via 208a and / or the shielding via 208b may include Figure 1 The side ground plane 203a, the side ground plane 203b, the top ground plane 202, the bottom ground plane 206, the shielding via 208a and the shielding via 208b can be configured to minimize electromagnetic interference between the signal line 204 and an external source (e.g., the signal line 104).

[0083] The FPCB 20 may include a stitching via 230a and / or a stitching via 230b that may connect two or more ground systems to create a common ground between the two ground systems and thereby reduce phase variation between two or more signal lines and / or prevent any of the ground systems from acting as a transmission line segment itself. The stitching via 230a and / or the stitching via 130b may include a stitching via 230a and / or a stitching via 130b that may connect two or more ground systems to create a common ground between the two ground systems and thereby reduce phase variation between the two or more signal lines and / or prevent any of the ground systems from acting as a transmission line segment itself. Figure 1 The stitching via 130a and / or the stitching via 130b have similar features.

[0084] In some embodiments, the FPCB 20 includes a plurality of vias including shielding vias 208a-208b and stitching vias 230a-230b and are spaced apart and, in some embodiments, staggered along the axial direction of the FPCB 20 on both sides of the signal line 104. The distance between each via in the axial direction may be based on or a function of the frequency of the electrical signal propagating through the signal line 204. In some embodiments, the distance between each via in the axial direction may be inversely proportional to the frequency of the electrical signal, such that as the frequency of the electrical signal increases, the distance between each via in the axial direction may decrease.

[0085] In some embodiments, the rigid-flexible printed circuit board may include an FPCB 20. The rigid-flexible printed circuit board may include a rigid end. The rigid end may include one or more plugs. The FPCB 20 may be located between the rigid ends of the rigid-flexible printed circuit board.

[0086] In some embodiments, the FPCB 20 is configured to meet one or more design standards. Examples of design standards may include IPC-2221B, IPC-2223, IPC-4101E, IPC-4204B, and IPC6013D, all of which are incorporated herein in their entirety.

[0087] : Is the basic design standard for all documents in the IPC-2220 series. This standard establishes general requirements for the design of printed boards and other forms of component mounting or interconnection structures (whether single-sided, double-sided or multi-sided).

[0088] : Establishes specific requirements for the design of flexible printed boards and the form of component mounting and interconnect structures. The flexible materials used in the structure consist of insulating films, reinforced and / or non-reinforced dielectrics combined with metallic materials. Revision D provides new design guidance and requirements for material selection and construction, selective (button) plating, minimum bending for flexible circuits with covers, impedance and capacitance control, unsupported edge conductors / fingers, and copper-filled vias / microvias.

[0089] : Covers the requirements for basic materials which are referred to as laminates or prepregs and are listed in the specification sheets which are included at the end of the body. These can be used primarily for electronic interconnects in rigid and multilayer printed boards. The document includes 65 individual specification sheets which can be searched using keywords. These keywords allow users of this document to find materials that are similar in nature but have specific different properties that require fine tuning of their laminate and / or prepreg selection.

[0090] : Establishes a classification system, qualification, and quality performance requirements for flexible metal-clad dielectric materials to be used in the manufacture of flexible printed boards. This standard includes 12 specification sheets resulting from various combinations of copper foil cladding, polymer-based dielectrics selected from polyester, polyimide, liquid crystal polymer, and at least nine polymer adhesives and tack-free binders. The end result of these material combinations provides the industry with suitable clad flexible dielectrics for use in the manufacture of flexible printed board interconnects. IPC-4204B also addresses how to utilize legacy designs, which refer to earlier, obsolete material names.

[0091] : Covers qualification and performance requirements for flexible printed boards designed for IPC-2221 and IPC-2223. Flexible printed boards can be single-sided, double-sided, multi-layer, or rigid-flex multi-layer. All of these constructions can include stiffeners, PTHs, microvias, and blind / buried vias. IPC-6013D includes new and updated requirements for finishing, rigid-to-flex transition areas, deformation anomalies including wrinkles, creases, and straw-type voids, marking, registration (annular rings), conductor thickness reduction, dielectric removal in holes, resin smearing, copper-filled microvias, and selective (button) hole plating.

[0092] In one aspect, the FPCB 10 for transmitting high frequency signals can be configured to minimize the change of the impedance of discrete targets. Examples of impedance targets can include 50 ohms, 75 ohms and / or 100 ohms. The selection of impedance targets can be based on attenuation, power and voltage requirements. In some embodiments, the FPCB 10 can be configured to maintain impedance values ​​of 50 ohms + / - 10%, 75 ohms + / - 10% and 100 ohms + / - 10%.

[0093] In one aspect, the FPCB 10 for transmitting high frequency signals can be configured to maintain the electrical (phase) length of the flexible cable within a target of (+ / -) 1 electrical degree within a frequency range (e.g., 67 MHz to 300 MHz frequency). The phase length or electrical length of a cable (flexible cable, coaxial cable, etc.) can depend on several factors, including material composition and construction.

[0094] There are several types of phase matching requirements and associated tolerances that are commonly used in FPCB 10. Examples include:

[0095] Relative Phase: Group-matched phase—all cable components are matched to each other;

[0096] Absolute Phase: Phase matched to electrical length - as with mechanical standards, this electrical length in degrees or time is determined by the customer;

[0097] Phase matching to standard: All cables are matched to a standard. This standard can be established by a previous batch or provided by the customer;

[0098] Phase offset matching: One or more cables are provided with a defined phase offset compared to each of the other cable components.

[0099] In one aspect, the FPCB 10 can minimize the variation in velocity propagation to achieve a desired phase match. In one aspect, the FPCB 10 can be a delivery system that provides precision and control for the phase length of parallel transmission lines while complying with regulatory guidelines.

[0100] Figure 3 A method 30 of manufacturing a FPCB (eg, the FPCB 10 ) according to an exemplary embodiment of the present invention is illustrated.

[0101] In steps 301 to 315, the flexible layers 2 to 4 may be laminated together and drilled. Via holes (eg, stitching vias or shielding vias) may be plated.

[0102] In step 301 , a flexible copper clad laminate (FCCL) may be baked. In some embodiments, the FCCL may be the dielectric layer 101 . In some embodiments, the FCCL may be the dielectric layer 106 .

[0103] In step 302, the FCCL may be chemically cleaned and micro-etched.

[0104] In step 303, the FCCL may be laminated with photoresist, exposed, and developed.

[0105] In step 304, the FCCL may be etched and photoresist stripped.

[0106] In step 305, automated optical inspection may be performed.

[0107] In step 306 , a bonding layer may be fabricated. Layer 2 and layer 4 may be laminated with the bonding layer. In some embodiments, layer 2 may be dielectric layer 101 , and layer 4 may be dielectric layer 105 .

[0108] In step 306a, the bonding layer may be manufactured by lamination. In some embodiments, the bonding layer may be the top ground plane 102 or the bottom ground plane 106.

[0109] In step 306b, the bonding layer may be laser routed, drilled, or die cut.

[0110] In step 307, the vias may have holes that may be drilled, deburred, and plasma treated.

[0111] In step 308, the stitching holes may be metalized.

[0112] In step 309 , the via hole may be cleaned and micro-etched.

[0113] In step 310 , vias may be laminated, printed, and the photosensitive plating resist may be developed.

[0114] In step 311, the photoresist may be plated and etched into holes.

[0115] In step 312, the photosensitive plating resist may be stripped.

[0116] In step 313, the base copper may be etched.

[0117] In step 314, the sacrificial metal etch resist may be stripped.

[0118] In step 315, a cover layer may be fabricated for layer 2 and layer 4. The cover layer may be laminated to layer 2 and layer 4. In some embodiments, the cover layer may be cover layers 109-112.

[0119] In step 315a, cover layers 2 and 4 may be laminated.

[0120] In step 315b, cover layers 2 and 4 may be laser routed, drilled, and die cut.

[0121] In steps 316 to 321, hardboard layers 1 and 5 may be manufactured. In some embodiments, hardboard layers 1 and 5 are top laminate layer 113 and bottom laminate layer 114, respectively.

[0122] In step 316, hardboard layers 1 and 5 may be a glass reinforced copper clad laminate that may be baked.

[0123] In step 317, the hardboard layers 1 and 5 may be chemically cleaned and micro-etched.

[0124] In step 318, the photoresist may be laminated, exposed, and developed.

[0125] In step 319, the copper may be etched and the photoresist may be stripped.

[0126] In step 320, an automated optical inspection of the hardboard layers 1 and 5 may be performed.

[0127] In step 321, a window may be routed for the flexible area of ​​the FPCB.

[0128] In step 322, prepreg layers may be fabricated by routing windows in a no-flow prepreg. In some embodiments, the prepreg layers are a top prepreg layer 115 and a bottom prepreg layer 116.

[0129] In steps 323 to 343 , the rigid-flex printed circuit board may be assembled.

[0130] In step 323, the inner layers 2 to 4 may be oxidized. In some embodiments, the inner layers are labeled Figure 1 101 to 112 of the.

[0131] In step 324, the flexible layers, stacks, and no-flow prepregs may be combined. In some embodiments, the flexible layers are layers 2 to 4. In some embodiments, the laminate layers are top stack 113 and bottom stack 114. In some embodiments, the prepreg layers are top prepreg layer 115 and bottom prepreg layer 116.

[0132] In step 325, final lamination may be performed.

[0133] In step 326, the vias may be drilled, deburred, and plasma treated. In some embodiments, the vias are vias 117-120.

[0134] In step 327, the via holes may be metallized.

[0135] In step 328, the copper may be cleaned and microetched.

[0136] In step 329, the photosensitive plating resist may be laminated, printed, and developed.

[0137] In step 330, copper and sacrificial metal etch resist may be pattern plated.

[0138] In step 331, the resist may be stripped and plated.

[0139] In step 332, the base copper may be drilled with non-plated vias and etched.

[0140] In step 333, the copper and sacrificial metal etch resist may be stripped.

[0141] In step 334, the vias may be cleaned, solder mask applied, exposed, and developed.

[0142] In step 335, the FPCB may be baked.

[0143] In step 336, nomenclature may be applied.

[0144] In step 337, the FPCB may be baked.

[0145] In step 338, an Electroless Nickel Immersion Gold (ENIG) process is applied to the FPCB.

[0146] In step 339, the FPCB may be subjected to final microsectioning.

[0147] In step 340, the flexible area may be laser routed.

[0148] In step 341, the hardboard area may be mechanically routed.

[0149] In step 342, the FPCB may undergo final inspection and electrical testing.

[0150] In step 343, the FPCB may be packaged and prepared for shipment.

[0151] Now refer to Figure 4 , shows a cross section of an FPCB 40 according to an exemplary embodiment of the present invention.

[0152] In some embodiments, the FPCB 40 may forgo including vias, such as Figure 1 In some embodiments, the ground trace of FPCB 40 is wide enough and the thickness of the dielectric layer is thin enough to achieve EMI shielding. In some embodiments, the ground trace can be less than or equal to 0.045 inches. In some embodiments, one or more dielectric layers have a thickness less than or equal to 0.001 inches.

[0153] FPCB 40 may include a conductive layer 400. Conductive layer 400 may include a copper layer 402 having a width of 0.001 inches. Conductive layer 400 may include a signal line 404, a side ground plane 403a, and / or a side ground plane 403b. In some embodiments, conductive layer 400 may include a plurality of signal lines and side ground planes similar to signal line 404, side ground plane 403a, and / or side ground plane 403b. Signal line 404 may be configured to transmit an electrical signal (e.g., an RF signal or a video signal). In some embodiments, the electrical signal may exceed 100 MHz. Signal line 404 may have a width of about 0.0039 inches. Side ground plane 403a and / or side ground plane 403b may have a width that is about 10 times the width of signal line 404. In some embodiments, side ground plane 403a and / or side ground plane 403b may have a width of about 0.045 inches. Side ground plane 403a and / or side ground plane 403b can be located on the opposite side of signal line 404 and can be configured as electromagnetic shielding to electrically isolate signal line 404 from external sources (e.g., other signal lines). The distance between signal line 404 and side ground plane 403a or side ground plane 403b is about 0.0153 inches. A portion of copper layer 402 can be arranged between signal line 404 and side ground plane 403a or side ground plane 403b and have a width of 0.0153 inches. Side ground plane 403a and side ground plane 403b can have a width of 0.0055 inches. Another portion of copper layer 402 can be located outside side ground plane 403a or side ground plane 403b and can have a width of about 0.0145 inches. Signal line 404, side ground plane 403a and / or side ground plane 403b can be about 0.001 inches thick.

[0154] The FPCB 40 may include a top dielectric layer 401 and a bottom dielectric layer 405. The top dielectric layer 401 and the bottom dielectric layer 105 may be configured to electrically insulate the signal line 404 from other ground planes to prevent short circuits of the signal line 404. The top dielectric layer 401 may have a width of 0.003 inches. The bottom dielectric layer 405 may have a width of 0.005 inches. The top dielectric layer 401 and / or the bottom dielectric layer 405 may include a film layer. In another embodiment, the top dielectric layer 401 may be approximately 0.004 inches thick. In another embodiment, the bottom dielectric layer 405 may be approximately 0.003 inches thick. The top dielectric layer 401 and / or the bottom dielectric layer 405 may be an adhesive. The top dielectric layer 401 and / or the bottom dielectric layer 405 may be a flexible laminate.

[0155] Conductive layer 400 may be located between dielectric layer 401 and dielectric layer 405. Conductive layer 400 and top dielectric layer 401 may be connected using acrylic adhesive 407. Acrylic adhesive 407 may be located between conductive layer 400 and top dielectric layer 401 to adhere conductive layer 400 to dielectric layer 405. Acrylic adhesive 407 may be 0.002 inches thick.

[0156] The FPCB 40 may include a top copper layer 420 disposed on the dielectric layer 401. The copper layer 420 may include a top space 414 and / or a top space 406. The FPCB 40 may include a bottom copper layer 422. The bottom copper layer 422 may include a bottom space 413 and / or a bottom space 408. In some embodiments, the top space 414, the top space 406, the bottom space 413 and / or the bottom space 408 may all have a width of 0.0045 inches. The space or spacing may affect the electrical properties of the FPCB. The spacing and material may control the impedance, capacitance, attenuation and other electrical properties of the FPCB 40. For example, by changing or adjusting, the spacing, impedance, capacitance, attenuation and other electrical properties of the FPCB 40 may also be changed. The side ground plane 403a, the side ground plane 403b, the top copper layer 420 and / or the bottom copper layer 422 may circumferentially surround the signal line 404 to minimize electromagnetic interference between the signal line 404 and an external source.

[0157] The FPCB 40 may include a top inner cover layer 410 and a bottom inner cover layer 411. The top inner cover layer 410 and / or the bottom inner cover layer 411 may be configured to cover the top copper layer 420 and / or the bottom copper layer 422, respectively. The top inner cover layer 410 and / or the bottom inner cover layer 411 may be an acrylic adhesive. The top inner cover layer 410 and / or the bottom inner cover layer 411 may be 0.001 inches thick.

[0158] The FPCB 10 may include a top outer cover layer 409 and a bottom outer cover layer 412. The top outer cover layer 409 may be configured to cover the top inner cover layer 410. The bottom outer cover layer 412 may be configured to cover the bottom inner cover layer 411. The top outer cover layer 409 and / or the bottom outer cover layer 412 may be a polyimide film (e.g., a KAPTON film). The top outer cover layer 409 and / or the bottom outer cover layer 412 may be 0.001 inches thick.

[0159] In some embodiments, FPCB 40 may include 2, 4, 8, 16, 32, 64 and / or N signal lines, where N is an integer. In these embodiments, at least some portions of FPCB 40 are repeated for each signal line and attached to the right or left side of FPCB 40, separated by spaces (e.g., spaces 406, 408, 413, 414).

[0160] Now refer to Figure 5 , showing an exemplary embodiment of the present invention along Figure 4 A to A' is a top cross-section of the cable 50. When the cable 50 is Figure 4 When the FPCB 40 is included, the cable 50 may include other FPCBs, including FPCB 10 and FPCB 20. The cable 50 may include a first connector 502 and / or a second connector 504. The cable 50 may include one or more signal lines (e.g., signal line 404) and / or protection traces (e.g., ground traces 403a to 403b) extending from the first connector 502 to the second connector 504. The first connector 502 and / or the second connector 504 may be a rigid printed circuit board. The first connector 502 and / or the second connector 504 may include one or more connector elements (e.g., pins, wires, contacts, zero insertion force connectors, etc.), which electrically connect the cable 50 to an external electrical device, so that when the first connector 502 and the second connector 504 are connected to the first external device and the second external device, respectively, the electrical signal can be transmitted from the first external device to the second external device through the cable 50.

[0161] Each of the signal line and / or the guard trace can be centered on the connector pitch and perpendicular to the connector pitch. As used herein, the connection pitch can refer to the distance between at least two connector contacts (such as the second connector 504) of a connector (such as the second connector 504). Figure 6 A center line extending between contacts 505a to 505b) shown in FIG.

[0162] In some embodiments, the connector pitch, shielding, and retention features can be based on the system design and application. In some embodiments, the pitch of the one or more signal lines and the pitch of the one or more guard traces can be uniform. The pitch of the one or more signal lines and / or the one or more guard traces is based on the connector, impedance, dielectric strength, and / or current carrying requirements of the application. In some embodiments, the cable 50 may include staggered vias to separate the guard traces from the top and bottom ground planes (e.g., Figure 1 , Figure 2 and Figure 4The guard trace is implemented as an isolated ground plane located on both the top and bottom layers of the FPCB to separate each signal line, maintain electromagnetic communication between external devices, and minimize crosstalk. In some embodiments, the cable 50 may include a ground plane loop (such as Figure 6 ) to further isolate the signal lines (e.g., signal line 504) by surrounding the corresponding signal lines into a semicircle or arc, and thereby provide crosstalk shielding within the contact. In some embodiments, connector 502 and / or connector 504 can be coupled to one or more ground planes to shield the connectors from electromagnetic interference.

[0163] In one embodiment, the spacing between one or more shielding vias 108a and shielding vias 108b has been calculated to minimize grounding effects while maximizing manufacturability. The shielding via stitching length may be less than or equal to 1 / 4 wavelength, less than or equal to 1 / 8 wavelength, or less than or equal to 1 / 20 wavelength. In one embodiment, the wavelength is equal to about 60% of the free space velocity (commonly measured as the propagation velocity and referred to as the propagation velocity) of electromagnetic radiation propagating through the FPCB dielectric divided by the applied fundamental frequency.

[0164] In some embodiments, the cable 50 may include a signal line having an impedance of 50 ohms. The signal line may have a width of 0.004 inches and a height of 0.005 inches (eg, approximately 36 AWG). The cable 50 may include a layer of 0.5 ounce copper. The cable 50 may include a pitch of 0.5 mm.

[0165] When two signals are transmitted through the cable 50, the signals will be out of phase due to the variation in material, spacing, length and width of the traces caused by manufacturing defects. In order to reduce the phase difference, the variation in material, spacing, length and width of the traces is minimized so that the impedance between the signals is similar, and thus the electrical length is similar so that the signals are within one electrical degree of each other. An electrical degree may refer to 1 / 360 of the period of a signal passing through a signal line. Electrical length may refer to the number of wavelengths of a signal required to pass through a signal line of a cable having a physical length.

[0166] As described above, due to manufacturing process variations of the cable 50, the electrical length may be different for the signal lines. In some embodiments, the physical length of the FPCB of the cable used for at least one signal line may be adjusted (e.g., lengthened or used with a delay circuit or an equalization circuit) so that the electrical lengths of at least two signal lines on the cable 50 are substantially similar. For certain RF applications, the two signal lines may be substantially similar if they are at least one of the following: within a few electrical degrees of each of the two signal lines. Adjusting the physical length of the FPCB to reduce the variation in electrical length between the signal lines to within a few electrical degrees is a better controlled manufacturing process using the FPCB than coaxial cable.

[0167] Alternative Embodiments

[0168] In some embodiments, a flexible printed circuit board (e.g., FPCB 10) may include a conductive layer (e.g., conductive layer 100), which may include a first signal line (e.g., signal line 104), a first ground plane (e.g., ground plane 103a), and a second ground plane (e.g., ground plane 103b). The first ground plane layer (e.g., ground plane layer 120) may include a third ground plane (e.g., ground plane 102). The second ground plane layer (e.g., ground plane layer 122) may include a fourth ground plane (e.g., ground plane 106). The first shielding via (e.g., shielding via 108a) may extend from the third ground plane to the fourth ground plane through the first ground plane to electrically connect the first ground plane, the third ground plane, and the fourth ground plane. The second shielding via (e.g., shielding via 108b) may extend from the third ground plane to the fourth ground plane through the second ground plane to electrically connect the second ground plane, the third ground plane, and the fourth ground plane. The first ground plane, the second ground plane, the third ground plane, the fourth ground plane, the first shielding via, and the second shielding via may together circumferentially surround the first signal line to minimize electromagnetic interference to the first signal line.

[0169] In some embodiments, the signal line may be located between the first ground plane and the second ground plane. In some embodiments, the first signal line may be located between the third ground plane and the fourth ground plane. In some embodiments, the signal line may be located between the first shielding via and the second shielding via.

[0170] In some embodiments, the impedance of the first signal line can be between 47.5 ohms and 52.5 ohms. In some embodiments, the impedance of the first signal line can be between 49 ohms and 51 ohms. In other embodiments, the impedance of the first signal line can be between 45 ohms and 55 ohms, wherein the target center of the distribution is at 50 ohms. In one aspect, the impedance of the first signal line is between 67.5 ohms and 82.5 ohms. In one aspect, the impedance of the first signal line is about 75 ohms. In one aspect, the impedance of the first signal line is between 90 ohms and 110 ohms. In one aspect, the impedance of the first signal line is about 100 ohms. By using an FPCB with certain materials for each layer, and by using photolithography, tighter geometries such as trace width variations, trace height variations, and trace spacing variations can be achieved, which minimizes impedance variations and results in better signal quality compared to coaxial cables.

[0171] In some embodiments, the flexible printed circuit board further includes a first dielectric plane (e.g., dielectric plane 101) located between the signal line and the third ground plane. In some embodiments, the first dielectric plane has a thickness of about 0.004 inches. In some embodiments, the flexible printed circuit board further includes: a second dielectric plane (e.g., dielectric plane 105) located between the signal line and the fourth ground plane. In some embodiments, the second dielectric plane has a thickness of about 0.003 inches. In some embodiments, the total thickness of the conductive layer, the first ground plane layer, the second ground plane layer, the first dielectric plane, and the second dielectric plane is about 0.0094 inches. In some embodiments, the first ground plane, the second ground plane, and the first signal line have a thickness of about 0.001 inches. In some embodiments, the third ground plane may have a thickness of about 0.007 inches. In some embodiments, the fourth ground plane may have a thickness of about 0.007 inches.

[0172] In some embodiments, the flexible printed circuit board may include a second signal line (e.g., signal line 204), a fifth ground plane (e.g., ground plane 203a), and a sixth ground plane (e.g., ground plane 203b) located at a conductive layer (e.g., conductive layer 100), the second signal line being separated from and different from the first signal line. The flexible printed circuit board may include a seventh ground plane (e.g., ground plane 202) located at the first ground plane layer. The flexible printed circuit board may include an eighth ground plane (e.g., ground plane 206) located at the second ground plane layer. The flexible printed circuit board may include a third shielding via (e.g., shielding via 208a) extending from the seventh ground plane to the eighth ground plane and extending through the fifth ground plane to electrically connect the fifth ground plane, the seventh ground plane, and the eighth ground plane. The flexible printed circuit board may include a fourth shielding via (e.g., shielding via 208b) extending from the seventh ground plane to the eighth ground plane and extending through the sixth ground plane to electrically connect the sixth ground plane, the seventh ground plane, and the eighth ground plane. In some embodiments, the fifth ground plane, the sixth ground plane, the seventh ground plane, the eighth ground plane, the second shielding via, and the third shielding via together circumferentially surround the second signal line to minimize electromagnetic interference to the second signal line.

[0173] In some embodiments, the second shielding via and the third shielding via are located between the first signal line and the second signal line. In some embodiments, the second ground plane and the fifth ground plane are located between the first signal line and the second signal line. In some embodiments, the flexible printed circuit board further includes a dielectric plane (e.g., dielectric plane 210) located between the third ground plane and the seventh ground plane at the first ground plane layer to electromagnetically isolate the third ground plane from the seventh ground plane. In some embodiments, the flexible printed circuit board further includes a dielectric plane (e.g., dielectric plane 212) located between the second ground plane and the fifth ground plane at the conductive layer to electromagnetically isolate the second ground plane from the fifth ground plane. In some embodiments, the flexible printed circuit board further includes a dielectric plane (e.g., dielectric plane 214) located between the fourth ground plane and the eighth ground plane at the second ground plane layer to electromagnetically isolate the fourth ground plane from the eighth ground plane.

[0174] In some embodiments, a method for manufacturing a flexible printed circuit board (e.g., FPCB 10) includes providing a conductive layer (e.g., conductive layer 100) including a first signal line (e.g., signal line 104), a first ground plane (e.g., ground plane 103a), and a second ground plane (e.g., ground plane 103b). The method may include providing a first ground plane layer (e.g., ground plane layer 120) including a third ground plane (e.g., top ground plane 102). The method may include providing a second ground plane layer (e.g., bottom ground plane layer 122) including a fourth ground plane (e.g., bottom ground plane 106). The method may include stitching a first shielding via (e.g., shielding via 108a) extending from the third ground plane to the fourth ground plane and extending through the first ground plane to electrically connect the first ground plane, the third ground plane, and the fourth ground plane. The method may include stitching a second shielding via (e.g., shielding via 108b) extending from the third ground plane to the fourth ground plane and extending through the second ground plane to electrically connect the second ground plane, the third ground plane, and the fourth ground plane. The first ground plane, the second ground plane, the third ground plane, the fourth ground plane, the first shielding via, and the second shielding via may together circumferentially surround the first signal line to minimize electromagnetic interference to the first signal line.

[0175] Those skilled in the art will recognize that the exemplary embodiments shown and described above may be changed without departing from the broad inventive concept thereof. Therefore, it is to be understood that the present invention is not limited to the exemplary embodiments shown and described, but is intended to cover modifications within the spirit and scope of the present invention as defined by the claims. For example, the specific features of the exemplary embodiments may or may not be part of the claimed invention, and the features of the disclosed embodiments may be combined. Unless otherwise specified herein, the terms "one", "an" and "the" are not limited to one element, but should be interpreted as meaning "at least one". As used herein, the term "approximately" or "about" may refer to + or -10% of the referenced value. For example, "approximately 9" is understood to include 8.2 and 9.9.

[0176] It is to be understood that at least some of the figures and descriptions of the present invention have been simplified to focus on elements relevant to a clear understanding of the present invention, while other elements that a person of ordinary skill in the art would recognize may also comprise a part of the present invention have been eliminated for the sake of clarity. However, because these elements are well known in the art and because they do not necessarily contribute to a better understanding of the present invention, a description of these elements is not provided herein.

[0177] Further, to the extent that the method does not rely on the specific order of the steps indicated herein, the specific order of the steps should not be construed as limiting the claims. Claims directed to the method of the present invention should not be limited to performing its steps in the order written, and those skilled in the art can readily recognize that the steps can be changed and still remain within the spirit and scope of the present invention.

Claims

1. A flexible printed circuit board, comprising: a conductive layer comprising a first signal line, a first ground plane, and a second ground plane, wherein a contact is located at an end of the first signal line, and the first signal line is isolated by a ground plane loop, the ground plane loop is adjacent to the contact and surrounds the first signal line in a semicircle or an arc; a first ground plane layer, the first ground plane layer comprising a third ground plane; a second ground plane layer, the second ground plane layer comprising a fourth ground plane; and a first shielding via extending from the third ground plane to the fourth ground plane and through the first ground plane to electrically connect the first ground plane, the third ground plane, and the fourth ground plane; a second shielding via extending from the third ground plane to the fourth ground plane and through the second ground plane to electrically connect the second ground plane, the third ground plane, and the fourth ground plane; and a stitching via extending from the third ground plane to the fourth ground plane to electrically connect the third ground plane and the fourth ground plane, The first ground plane, the second ground plane, the third ground plane, the fourth ground plane, the first shielding via and the second shielding via together circumferentially surround the first signal line to minimize electromagnetic interference between the first signal line and a second signal line located in the flexible printed circuit board, and the second signal line is separated from the first signal line and different from the first signal line.

2. The flexible printed circuit board according to claim 1, wherein: The first signal line is located between the first ground plane and the second ground plane.

3. The flexible printed circuit board according to claim 1, wherein: The first signal line is located between the third ground plane and the fourth ground plane.

4. The flexible printed circuit board according to claim 1, wherein: The first signal line is located between the first shielding via and the second shielding via.

5. The flexible printed circuit board according to claim 1, wherein: The impedance of the first signal line is between 45 ohms and 55 ohms.

6. The flexible printed circuit board according to claim 1, wherein: The impedance of the first signal line is between about 49 ohms and about 51 ohms.

7. The flexible printed circuit board according to claim 1, further comprising: A first dielectric plane is located between the first signal line and the third ground plane.

8. The flexible printed circuit board according to claim 1, further comprising: A second dielectric plane is located between the first signal line and the fourth ground plane.

9. The flexible printed circuit board according to claim 1, further comprising: a fifth ground plane and a sixth ground plane located at the conductive layer; a seventh ground plane, the seventh ground plane being located at the first ground plane layer; an eighth ground plane, the eighth ground plane being located at the second ground plane layer; a third shielding via extending from the seventh ground plane to the eighth ground plane and extending through the fifth ground plane to electrically connect the fifth ground plane, the seventh ground plane, and the eighth ground plane; as well as a fourth shielding via extending from the seventh ground plane to the eighth ground plane and extending through the sixth ground plane to electrically connect the sixth ground plane, the seventh ground plane, and the eighth ground plane, The fifth ground plane, the sixth ground plane, the seventh ground plane, the eighth ground plane, the second shielding via and the third shielding via together circumferentially surround the second signal line to minimize electromagnetic interference to the second signal line.

10. The flexible printed circuit board according to claim 9, wherein: The second shielding via and the third shielding via are located between the first signal line and the second signal line.

11. The flexible printed circuit board according to claim 9, wherein: The second ground plane and the fifth ground plane are located between the first signal line and the second signal line.

12. The flexible printed circuit board according to claim 9, further comprising a dielectric plane located between the third ground plane and the seventh ground plane at the first ground plane layer to electromagnetically isolate the third ground plane and the seventh ground plane.

13. The flexible printed circuit board according to claim 9, further comprising a dielectric plane located between the second ground plane and the fifth ground plane at the conductive layer to electromagnetically isolate the second ground plane from the fifth ground plane.

14. The flexible printed circuit board according to claim 9, further comprising a dielectric plane located between the fourth ground plane and the eighth ground plane at the second ground plane layer to electromagnetically isolate the fourth ground plane from the eighth ground plane.

15. A method for manufacturing a flexible printed circuit board, the method comprising: providing a conductive layer, the conductive layer comprising a first signal line, a first ground plane and a second ground plane, wherein a contact is located at an end of the first signal line and the first signal line is isolated by a ground plane loop, the ground plane loop being adjacent to the contact and surrounding the first signal line in a semicircle or an arc; providing a first ground plane layer, the first ground plane layer comprising a third ground plane; providing a second ground plane layer, the second ground plane layer comprising a fourth ground plane; and stitching a first shielding via extending from the third ground plane to the fourth ground plane and extending through the first ground plane to electrically connect the first ground plane, the third ground plane, and the fourth ground plane; stitching a second shielding via extending from the third ground plane to the fourth ground plane and extending through the second ground plane to electrically connect the second ground plane, the third ground plane, and the fourth ground plane; and stitching a stitching via extending from the third ground plane to the fourth ground plane to electrically connect the third ground plane and the fourth ground plane, The first ground plane, the second ground plane, the third ground plane, the fourth ground plane, the first shielding via and the second shielding via together circumferentially surround the first signal line to minimize electromagnetic interference between the first signal line and a second signal line located in the flexible printed circuit board, and the second signal line is separated from the first signal line and different from the first signal line.

16. The method for manufacturing a flexible printed circuit board according to claim 15, further comprising: The first signal line is positioned between the first ground plane and the second ground plane.

17. The method for manufacturing a flexible printed circuit board according to claim 15, further comprising: The first signal line is positioned between the third ground plane and the fourth ground plane.

18. The method for manufacturing a flexible printed circuit board according to claim 15, further comprising: The first signal line is disposed between the first shielding via and the second shielding via.

19. The method for manufacturing a flexible printed circuit board according to claim 15, wherein: The impedance of the first signal line is between 45 ohms and 55 ohms.

20. The method for manufacturing a flexible printed circuit board according to claim 15, wherein: The impedance of the first signal line is between about 49 ohms and about 51 ohms.

21. The method for manufacturing a flexible printed circuit board according to claim 15, further comprising: A first dielectric plane is disposed between the first signal line and the third ground plane.

22. The method for manufacturing a flexible printed circuit board according to claim 15, further comprising: A second dielectric plane is disposed between the first signal line and the fourth ground plane.

23. The method for manufacturing a flexible printed circuit board according to claim 15, further comprising: Disposing a fifth ground plane and a sixth ground plane at the conductive layer; Disposing a seventh ground plane at the first ground plane layer; Disposing an eighth ground plane at the second ground plane layer; stitching a third shielding via, the third shielding via extending from the seventh ground plane to the eighth ground plane and extending through the fifth ground plane to electrically connect the fifth ground plane, the seventh ground plane, and the eighth ground plane; as well as stitching a fourth shielding via extending from the seventh ground plane to the eighth ground plane and extending through the sixth ground plane to electrically connect the sixth ground plane, the seventh ground plane, and the eighth ground plane, The fifth ground plane, the sixth ground plane, the seventh ground plane, the eighth ground plane, the second shielding via and the third shielding via together circumferentially surround the second signal line to minimize electromagnetic interference to the second signal line.

24. The method for manufacturing a flexible printed circuit board according to claim 23, further comprising: The second shielding via and the third shielding via are positioned between the first signal line and the second signal line.

25. The method for manufacturing a flexible printed circuit board according to claim 23, further comprising: The second ground plane and the fifth ground plane are positioned between the first signal line and the second signal line.

26. The method for manufacturing a flexible printed circuit board according to claim 23, further comprising: A dielectric plane is positioned between the third ground plane and the seventh ground plane at the first ground plane layer to electromagnetically isolate the third ground plane from the seventh ground plane.

27. The method for manufacturing a flexible printed circuit board according to claim 23, further comprising: A dielectric plane is positioned between the second ground plane and the fifth ground plane at the conductive layer to electromagnetically isolate the second ground plane from the fifth ground plane.

28. The method for manufacturing a flexible printed circuit board according to claim 23, further comprising: A dielectric plane is positioned between the fourth ground plane and the eighth ground plane at the second ground plane layer to electromagnetically isolate the fourth ground plane from the eighth ground plane.

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