Clock monitoring circuit and integrated circuit comprising a clock monitoring circuit

Abstract

A clock monitoring circuit and an integrated circuit including the clock monitoring circuit, the clock monitoring circuit including a first duty cycle detector that detects a change in a duty cycle of a clock signal based on a first upper limit voltage and a first lower limit voltage, a second duty cycle detector that detects a change in a duty cycle of a monitoring clock signal based on a second upper limit voltage and a second lower limit voltage, and a first frequency detector that detects a change in a frequency of the clock signal using the second upper limit voltage and the second lower limit voltage.

Description

[0001] Cross-references to related applications

[0002] Priority is claimed in accordance with 35 USC §119 for Korean Patent Application No. 10-2019-0069557, filed with the Korean Intellectual Property Office on June 12, 2019, the entire contents of which are incorporated herein by reference. Background Technology

[0003] The inventive concept of this article relates to clock monitoring circuits, and more specifically, to clock monitoring circuits and integrated circuits including such clock monitoring circuits.

[0004] Electronic circuits and devices typically include power management integrated circuits (ICs) that convert input voltages received from external sources to supply source voltages. The power management IC receives the input voltage and, based on the received input voltage, provides various source voltages suitable for the internal operation of the electronic circuit / device.

[0005] Various semiconductor devices, including power management integrated circuits, use clock signals for switching operations. These clock-based semiconductor devices may require control to maintain a specific clock frequency and duty cycle. Summary of the Invention

[0006] An embodiment of the present invention provides a clock monitoring circuit and an integrated circuit including the clock monitoring circuit, which detects changes in the duty cycle and frequency of a clock signal to detect abnormal states of the clock signal.

[0007] An embodiment of the present invention provides a clock monitoring circuit, comprising: a first duty cycle detector that detects changes in the duty cycle of a clock signal using a first upper limit voltage and a first lower limit voltage; a second duty cycle detector that detects changes in the duty cycle of the monitored clock signal using a second upper limit voltage and a second lower limit voltage; and a first frequency detector that detects frequency changes of the clock signal using a second upper limit voltage and a second lower limit voltage. The first upper limit voltage has a level as high as a first upper limit level relative to the voltage corresponding to the duty cycle of the clock signal, and the first lower limit voltage has a level as low as a first lower limit level relative to the voltage corresponding to the duty cycle of the clock signal. The second upper limit voltage has a level as high as a second upper limit level relative to the voltage corresponding to the duty cycle of the monitored clock signal, and the second lower limit voltage has a level as low as a second lower limit level relative to the voltage corresponding to the duty cycle of the monitored clock signal.

[0008] Embodiments of the present inventive concept also provide an integrated circuit including a clock monitoring circuit for monitoring a characteristic of a clock signal, the clock monitoring circuit including a first duty cycle detector that generates and outputs a first duty cycle detection signal based on a change in a duty cycle of a first clock signal by using a first upper limit voltage and a first lower limit voltage, a second duty cycle detector that generates and outputs a second duty cycle detection signal based on a change in a duty cycle of a monitoring clock signal by using a second upper limit voltage and a second lower limit voltage, and a first frequency detector that outputs a first frequency detection signal based on a change in a frequency of the first clock signal by using the second upper limit voltage and the second lower limit voltage. The first upper limit voltage has a level as high as a first upper limit level with respect to a voltage corresponding to the duty cycle of the first clock signal, and the first lower limit voltage has a level as low as a first lower limit level with respect to the voltage corresponding to the duty cycle of the first clock signal. The second upper limit voltage has a level as high as a second upper limit level with respect to a voltage corresponding to the duty cycle of the monitoring clock signal, and the second lower limit voltage has a level as low as a second lower limit level with respect to the voltage corresponding to the duty cycle of the monitoring clock signal.

[0009] Embodiments of the present inventive concept also provide an integrated circuit including a clock generator that generates a clock signal and a clock monitoring circuit that monitors a duty cycle and a frequency of the clock signal. The clock monitoring circuit includes a first duty cycle detector that detects a change in the duty cycle of the clock signal, a second duty cycle detector that detects a change in the duty cycle of the monitoring clock signal, a first frequency detector that detects a change in the frequency of the clock signal, and a second frequency detector that detects a change in the frequency of the monitoring clock signal. The second frequency detector detects the change in the frequency of the monitoring clock signal by using a first upper limit voltage and a first lower limit voltage that are both generated by the first duty cycle detector. The first frequency detector detects the change in the frequency of the clock signal by using a second upper limit voltage and a second lower limit voltage that are both generated by the second duty cycle detector. BRIEF DESCRIPTION OF DRAWINGS

[0010] Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, and by reference to the drawings in which:

[0011] Figure 1 A block diagram of a clock monitoring circuit according to an example embodiment of the present inventive concept is shown;

[0012] Figure 2 A block diagram of a first duty cycle detector included in a clock monitoring circuit according to an example embodiment of the present inventive concept is shown;

[0013] Figure 3 A circuit diagram of a first duty cycle detector included in a clock monitoring circuit according to an example embodiment of the present inventive concept is shown;

[0014] Figure 4A 、 Figure 4B and Figure 4C shows a timing diagram describing the operation of a first duty cycle detector included in a clock monitoring circuit according to example embodiments of inventive concepts;

[0015] Figure 5 shows a block diagram of a first duty cycle detector included in a clock monitoring circuit according to example embodiments of inventive concepts;

[0016] Figure 6 shows a block diagram of a first frequency detector included in a clock monitoring circuit according to example embodiments of inventive concepts;

[0017] Figure 7 shows a circuit diagram of a first frequency detector included in a clock monitoring circuit according to example embodiments of inventive concepts;

[0018] Figure 8A 、 Figure 8B and Figure 8C shows a timing diagram describing the operation of a first frequency detector included in a clock monitoring circuit according to example embodiments of inventive concepts;

[0019] Figure 9 shows a block diagram of an integrated circuit describing example embodiments of inventive concepts;

[0020] Figure 10 shows a block diagram of an integrated circuit describing another example embodiment of inventive concepts; and

[0021] Figure 11 shows a block diagram of an electronic device describing example embodiments of inventive concepts. DETAILED DESCRIPTION

[0022] As is conventional in the art to which the inventive concepts pertain, embodiments can be described and illustrated in terms of blocks that perform one or more functions. These blocks, which can be referred to herein as units or modules, among others, are physically implemented by analog and / or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, and the like and can optionally be driven by firmware and / or software. For example, circuitry constituting a block can be embodied in one or more semiconductor chips, or on a substrate such as a printed circuit board. The circuitry constituting a block can be implemented by specialized hardware or a processor such as one or more programmed microprocessors and associated circuitry, or a combination of specialized hardware and a processor executing software that performs some of the functions of the block. Each block of an embodiment can be physically separated into two or more interacting and discrete blocks without departing from the scope of the inventive concepts. Likewise, blocks of an embodiment can be physically combined into a more complex block without departing from the scope of the inventive concepts.

[0023] Figure 1 A block diagram of a clock monitoring circuit 10 according to an example embodiment of the inventive concepts is shown.

[0024] Referring to Figure 1 The clock monitoring circuit 10 can include a first duty cycle detector 100_1, a second duty cycle detector 100_2, a first frequency detector 200_1, and a second frequency detector 200_2. The second frequency detector 200_2 is optional. The first duty cycle detector 100_1 can be a circuit for detecting a change in a duty cycle of the clock signal CLK, and the first frequency detector 200_1 can be a circuit for detecting a change in a frequency of the clock signal CLK. The second duty cycle detector 100_1 can be a circuit for detecting a change in a duty cycle of the monitoring clock signal CLK_M, and the second frequency detector 200_2 can be a circuit for detecting a change in a frequency of the monitoring clock signal CLK_M.

[0025] In an example embodiment, the monitoring clock signal CLK_M can be a signal that is a standard of the clock signal CLK. For example, a duty cycle (e.g., 50%) of the monitoring clock signal CLK_M can be a reference duty cycle of the clock signal CLK, and a frequency of the monitoring clock signal CLK_M can be a reference frequency of the clock signal CLK. Accordingly, the clock monitoring circuit 10 can detect whether a degree of change in the duty cycle of the clock signal CLK with respect to the duty cycle of the monitoring clock signal CLK_M is greater than an upper limit or less than a lower limit, and can detect whether a degree of change in the frequency of the clock signal CLK with respect to the frequency of the monitoring clock signal CLK_M is greater than an upper limit or less than a lower limit.

[0026] The first duty cycle detector 100_1 can output a first duty cycle detection signal DRR1 based on a change in a duty cycle of the clock signal CLK. In an example embodiment, the first duty cycle detection signal DRR1 can include a first signal DRRH1 and a second signal DRRL1. The first signal DRRH1 can be a signal having a logic level changed when the duty cycle of the clock signal CLK is greater than an upper limit, and the second signal DRRL1 can be a signal having a logic level changed when the duty cycle of the clock signal CLK is less than a lower limit. Alternatively, in an example embodiment, the first duty cycle detection signal DRR1 can be configured as a single signal, and can be a signal having a logic level changed when the duty cycle of the clock signal CLK is greater than the upper limit or less than the lower limit.

[0027] The first duty cycle detector 100_1 can generate a voltage corresponding to the duty cycle of the clock signal CLK. The first duty cycle detector 100_1 can generate a first upper limit voltage BH1 having a level as high as a first upper limit level with respect to the voltage corresponding to the duty cycle of the clock signal CLK, and can generate a first lower limit voltage BL1 having a level as low as a first lower limit level with respect to the voltage corresponding to the duty cycle of the clock signal CLK. In an example embodiment, the first upper limit level and the first lower limit level can have the same value, but are not limited thereto, and can have different values.

[0028] The second duty cycle detector 100_2 can output a second duty cycle detection signal DRR2 based on a change in a duty cycle of the monitoring clock signal CLK_M. In an example embodiment, the second duty cycle detection signal DRR2 can include a first signal DRRH2 and a second signal DRRL2. The first signal DRRH2 can be a signal having a logic level changed when the duty cycle of the monitoring clock signal CLK_M is greater than an upper limit, and the second signal DRRL2 can be a signal having a logic level changed when the duty cycle of the monitoring clock signal CLK_M is less than a lower limit. Alternatively, in an example embodiment, the second duty cycle detection signal DRR2 can be configured as a single signal, and can be a signal having a logic level changed when the duty cycle of the monitoring clock signal CLK_M is greater than the upper limit or less than the lower limit.

[0029] The second duty cycle detector 100_2 can generate a voltage corresponding to the duty cycle of the monitoring clock signal CLK_M. The second duty cycle detector 100_2 can generate a second upper limit voltage BH2, which has a level as high as a second upper limit level relative to the voltage corresponding to the duty cycle of the monitoring clock signal CLK_M, and can generate a second lower limit voltage BL2, which has a level as low as a second lower limit level relative to the voltage corresponding to the duty cycle of the monitoring clock signal CLK_M. In an example embodiment, the second upper limit level can have the same value as the first upper limit level, and the second lower limit level can have the same value as the first lower limit level. However, the inventive concept is not limited to this, and the second upper limit level can have a value different from the first lower limit level, and the second lower limit level can have a value different from the first lower limit level. In an example embodiment, the second upper limit level and the second lower limit level can have the same value, but are not limited to this, and can have different values.

[0030] The first frequency detector 200_1 can output a first frequency detection signal FR1 based on the frequency change of the clock signal CLK. In an example embodiment, the first frequency detection signal FR1 can be a signal with a logic level that changes when the frequency of the clock signal CLK is greater than an upper limit or less than a lower limit.

[0031] The first frequency detector 200_1 can receive a second upper limit voltage BH2 and a second lower limit voltage BL2 from the second duty cycle detector 100_2. The first frequency detector 200_1 can detect frequency changes in the clock signal CLK and can generate a first frequency detection signal FR1 using the second upper limit voltage BH2 and the second lower limit voltage BL2. In an example embodiment, the first frequency detector 200_1 can generate a frequency detection voltage corresponding to the frequency of the clock signal CLK and can compare the frequency detection voltage with the second upper limit voltage BH2 and the second lower limit voltage BL2 to generate the first frequency detection signal FR1.

[0032] The second frequency detector 200_2 can output a second frequency detection signal FR2 based on the frequency change of the monitoring clock signal CLK_M. In an example embodiment, the second frequency detection signal FR2 can be a signal with a logic level that changes when the frequency of the monitoring clock signal CLK_M is greater than an upper limit or less than a lower limit.

[0033] The second frequency detector 200_2 can receive a first upper limit voltage BH1 and a first lower limit voltage BL1 from the first duty cycle detector 100_1. The second frequency detector 200_2 can detect frequency changes in the monitoring clock signal CLK_M and can generate a second frequency detection signal FR2 using the first upper limit voltage BH1 and the first lower limit voltage BL1. In an example embodiment, the second frequency detector 200_2 can generate a frequency detection voltage corresponding to the frequency of the monitoring clock signal CLK_M and can compare the frequency detection voltage with the first upper limit voltage BH1 and the first lower limit voltage BL1 to generate the second frequency detection signal FR2.

[0034] The clock monitoring circuit 10 according to the present invention can preferentially detect duty cycle changes of each of the clock signal CLK and the monitoring clock signal CLK_M, and can subsequently detect frequency changes of each of the clock signal CLK and the monitoring clock signal CLK_M, thereby detecting abnormal states of each of the clock signal CLK and the monitoring clock signal CLK_M. Specifically, the clock monitoring circuit 10 can detect frequency changes of each of the clock signal CLK and the monitoring clock signal CLK_M by using a first upper limit voltage BH1, a first lower limit voltage BL1, a second upper limit voltage BH2, and a second lower limit voltage BL2 (each of which is used to detect duty cycle changes of each of the clock signal CLK and the monitoring clock signal CLK_M), thereby detecting all duty cycle and frequency changes of each of the clock signal CLK and the monitoring clock signal CLK_M. Therefore, the clock monitoring circuit 10 can detect cases where the duty cycle and frequency of each of the clock signal CLK and the monitoring clock signal CLK_M are outside the normal range (normal range, e.g., the range between the lower and upper limits), and thus can monitor the clock signal CLK and the monitoring clock signal CLK_M.

[0035] Figure 2 A block diagram is shown of a first duty cycle detector 100_1 included in a clock monitoring circuit 10 according to an exemplary embodiment of the present invention.

[0036] refer to Figure 2 The first duty cycle detector 100_1 may include a low-level detector 110, a high-level detector 120, a boundary voltage generator 130, and a comparator circuit 140. Figure 2 Similar to the first duty cycle detector 100_1, Figure 1 The second duty cycle detector 100_2 may include a low-level detector, a high-level detector, a boundary voltage generator, and a comparator circuit. The following description of the components of the first duty cycle detector 100_1 can be applied to the components of the second duty cycle detector 100_2.

[0037] The low-level detector 110 can receive a clock signal CLK and can generate and output an off-duty width voltage VCLKL corresponding to the length of the low-level period (off-time period) of the clock signal CLK. For example, the low-level detector 110 can generate an off-duty width voltage VCLKL such that the level of the off-duty width voltage VCLKL increases as the low-level period increases.

[0038] The high-level detector 120 can receive a clock signal CLK and can generate and output an on-duty voltage VCLKH corresponding to the length of the high-level period (on-time period) of the clock signal CLK. For example, the high-level detector 120 can generate an on-duty voltage VCLKH such that the level of the on-duty voltage VCLKH increases as the high-level period increases.

[0039] Boundary voltage generator 130 can receive the non-operating width voltage VCLKL from low-level detector 110 and can generate a first upper limit voltage BH1 and a first lower limit voltage BL1. In this case, the first upper limit voltage BH1 can have a level as high as a first upper limit level relative to the non-operating width voltage VCLKL, and the first lower limit voltage BL1 can have a level as low as a first lower limit level relative to the non-operating width voltage VCLKL. In an example embodiment, the first upper limit level and the first lower limit level can have the same value.

[0040] Comparator circuit 140 can receive the operating width voltage VCLKH from high-level detector 120, and can receive the first upper limit voltage BH1 and the first lower limit voltage BL1 from boundary voltage generator 130. Comparator circuit 140 can compare the operating width voltage VCLKH with the first upper limit voltage BH1, and can compare the operating width voltage VCLKH with the first lower limit voltage BL1, thereby generating a first duty cycle signal DRR1.

[0041] In an example embodiment, the first duty cycle signal DRR1 may include a first signal DRRH1 and a second signal DRRL1. For example, when the operating width voltage VCLKH is higher than the first upper limit voltage BH1, the comparator circuit 140 may output the first signal DRRH1 with a first logic level (e.g., high level), and when the operating width voltage VCLKH is equal to or lower than the first upper limit voltage BH1, the comparator circuit 140 may output the first signal DRRH1 with a second logic level (e.g., low level). Furthermore, when the operating width voltage VCLKH is lower than the first lower limit voltage BL1, the comparator circuit 140 may output the second signal DRRL1 with a first logic level, and when the operating width voltage VCLKH is equal to or higher than the first lower limit voltage BL1, the comparator circuit 140 may output the second signal DRRL1 with a second logic level.

[0042] Figure 3 A circuit diagram is shown including a first duty cycle detector 100_1 in a clock monitoring circuit 10 according to an example embodiment, and is based on... Figure 2 The circuit diagram of the example embodiment shown is shown in the figure.

[0043] refer to Figure 3 The first duty cycle detector 100_1 may include a low-level detector 110, a high-level detector 120, a boundary voltage generator 130, and a comparator circuit 140. Figure 1 The second duty cycle detector 100_2 may include a low-level detector, a high-level detector, a boundary voltage generator, and a comparator circuit, and the following description of the components of the first duty cycle detector 100_1 may be applied to the components of the second duty cycle detector 100_2.

[0044] The low-level detector 110 may include a transistor Ta that is turned on based on a clock signal CLK, a capacitor Ca that is charged or discharged based on the clock signal CLK, and a low-pass filter including a resistor Rx and a capacitor Cx. The capacitor Ca may be connected to a current source IB, and the current source IB may be connected to a source voltage VDD.

[0045] During the low-level period of the clock signal CLK, transistor Ta can be turned off, and capacitor Ca can be charged by current source IB. The voltage CLKS of capacitor Ca can gradually increase during the low-level period of the clock signal CLK. On the other hand, during the high-level period of the clock signal CLK, transistor Ta can be turned on, and the voltage CLKS of capacitor Ca can be 0V. Therefore, the voltage CLKS of capacitor Ca can be a sawtooth wave with the same period as the period of the clock signal CLK. As the low-level period of the clock signal CLK increases, the charging time of capacitor Ca can increase, and therefore the maximum value of the voltage CLKS of capacitor Ca can increase.

[0046] A low-pass filter including resistor Rx and capacitor Cx can receive the voltage CLKS of capacitor Ca and output the average value of the voltage CLKS of capacitor Ca during the period of clock signal CLK as the non-working width voltage VCLKL. The non-working width voltage VCLKL of clock signal CLK can satisfy the following equation (1).

[0047] [Equation 1]

[0048]

[0049] Here, IB represents the current level of the current source IB connected to capacitor Ca, TS represents the period of the clock signal CLK, DL represents the ratio of the low-level period (off-time period) of the clock signal CLK to the period TS, and Ca represents the capacitance of capacitor Ca. Therefore, as the low-level period increases, the level of the non-operating width voltage VCLKL can increase.

[0050] The high-level detector 120 may include an inverter 121 for an inverted clock signal CLK, a transistor Tab that is turned on based on the inverted clock signal CLKb, a capacitor Cab that is charged or discharged based on the inverted clock signal CLKb, and a low-pass filter including a resistor Rxb and a capacitor Cxb. The capacitor Cab may be connected to a current source IBb, and the current source IBb may be connected to the source voltage VDD.

[0051] During the low-level period of the clock inversion signal CLKb (i.e., the high-level period of the clock signal CLK), transistor Tab can be turned off, and capacitor Cab can be charged by current source IBb. The voltage CLKSb of capacitor Cab can gradually increase during the high-level period of the clock signal CLK.

[0052] On the other hand, during the high-level period of the clock inversion signal CLKb (i.e., the low-level period of the clock signal CLK), transistor Tab can be turned on, and the voltage CLKSb of capacitor Cab can be 0V. Therefore, the voltage CLKSb of capacitor Cab can be a sawtooth wave with the same period as the period of the clock signal CLK, and the maximum value of the voltage CLKSb of capacitor Cab can increase as the high-level period of the clock signal CLK increases.

[0053] A low-pass filter including resistor Rxb and capacitor Cxb can receive the voltage CLKSb of capacitor Cab and output the average value of the voltage CLKSb of capacitor Cab during the period of clock signal CLKb as the working width voltage VCLKH. The working width voltage VCLKH can satisfy the following equation (2).

[0054] [Equation 2]

[0055]

[0056] Here, IBb represents the current level of the current source IBb connected to capacitor Cab, TS represents the period of the clock signal CLK, DH represents the ratio of the high-level period (on-time period) of the clock signal CLK to the period TS (i.e., duty cycle), and Cab represents the capacitance of capacitor Cab. Therefore, as the high-level period of the clock signal CLK increases, the level of the operating width voltage VCLKH can increase.

[0057] In the example embodiment, except for the inverter 121, the components of the high-level detector 120 can be the same as those of the low-level detector 110, and can have the same characteristics. That is, the transistor Tab of the high-level detector 120 can be configured to have the same size as the transistor Ta of the low-level detector 110, the capacitor Cab of the high-level detector 120 can have the same capacitance as the capacitor Ca of the low-level detector 110, and the current level of the current source IBb of the high-level detector 120 can be the same as the current level of the current source IB of the low-level detector 110. Furthermore, in the example embodiment, the low-pass filter of the high-level detector 120 can be configured to have the same characteristics as the low-pass filter of the low-level detector 110.

[0058] The boundary voltage generator 130 may include an operational amplifier 131, multiple resistors R1, R2 and R3, and a current source IBC. The first upper limit voltage BH1 and the first lower limit voltage BL1 can satisfy the following equation (3).

[0059] [Equation 3]

[0060] BH1=VCLKL+IBC·R3

[0061] BL1=VCLKL-IBC·R2

[0062] Here, IBC represents the current level of the current source IBC, and R2 and R3 represent the resistance values ​​of resistors R2 and R3. When the resistance values ​​of resistors R2 and R3 are the same, each of the first upper limit voltage BH1 and the first lower limit voltage BL1 can have a difference equal to the same level relative to the non-operating width voltage VCLKL. That is, the first upper limit level and the first lower limit level can be the same. By adjusting the resistance values ​​R2 and R3 of the boundary voltage generator 130, the levels of each of the first upper limit voltage BH1 and the first lower limit voltage BL1 can be adjusted, and the upper and lower limits of the duty cycle of the clock signal CLK can be set.

[0063] Comparator circuit 140 may include a first comparator 141 and a second comparator 143. The first comparator 141 may receive a working width voltage VCLKH from a high-level detector 120 and a first upper limit voltage BH1 from a boundary voltage generator 130. The first comparator 141 may output a comparison result obtained by comparing the working width voltage VCLKH and the first upper limit voltage BH1 as a first signal DRRH1. For example, when the working width voltage VCLKH is higher than the first upper limit voltage BH1, the first comparator 141 may output the first signal DRRH1 with a first logic level (e.g., high level), and when the working width voltage VCLKH is lower than the first upper limit voltage BH1, the first comparator 141 may output the first signal DRRH1 with a second logic level (e.g., low level).

[0064] The second comparator 143 can receive the operating width voltage VCLKH from the high-level detector 120 and the first lower limit voltage BL1 from the boundary voltage generator 130. The second comparator 143 can output the comparison result obtained by comparing the operating width voltage VCLKH and the first lower limit voltage BL1 as a second signal DRRL1. For example, when the operating width voltage VCLKH is higher than the first lower limit voltage BL1, the second comparator 143 can output the second signal DRRL1 with a second logic level, and when the operating width voltage VCLKH is lower than the first lower limit voltage BL1, the second comparator 143 can output the second signal DRRL1 with a first logic level.

[0065] The first comparator 141 and the second comparator 143 can be configured to use time lag or voltage lag in the comparison operation. For example, instead of outputting the first signal DRRH1 at the first logic level as soon as the operating width voltage VCLKH becomes higher than the first upper limit voltage BH1, the first comparator 141 can output the first signal DRRH1 with the first logic level when the operating width voltage VCLKH is higher than the first upper limit voltage BH1 for a predetermined duration. Similarly, instead of outputting the second signal DRRL1 at the first logic level as soon as the operating width voltage VCLKH becomes lower than the first lower limit voltage BL1, the second comparator 143 can output the second signal DRRL1 with the first logic level when the operating width voltage VCLKH is lower than the first lower limit voltage BL1 for a predetermined duration.

[0066] exist Figure 3 The diagram illustrates a circuit configuration of a first duty cycle detector 100_1 according to an exemplary embodiment. However, the clock monitoring circuit 10 conceived according to the present invention is not limited thereto, and the first duty cycle detector 100_1 can be implemented in various circuit configurations.

[0067] The first duty cycle detector 100_1 according to the present invention can detect the duty cycle change of the clock signal CLK by using the non-operating width voltage VCLKL and the operating width voltage VCLKH, both of which pass through their respective low-pass filters. Therefore, compared to detecting the duty cycle change of the clock signal CLK by using the maximum value of the voltage CLKS of capacitor Ca of low-level detector 110 or the maximum value of the voltage CLKSb of capacitor Cab of high-level detector 120, power consumption can be reduced. In other words, in the first duty cycle detector 100_1, since the average voltage of the voltage CLKS of capacitor Ca of low-level detector 110 is used, a high-speed comparator is not required during the detection of duty cycle changes by the clock monitoring circuit 10, and power consumption can be reduced. Therefore, the clock monitoring circuit 10 can be applied to low-power systems.

[0068] Figure 4A , Figure 4B and Figure 4C A timing diagram illustrating the operation of a first duty cycle detector 100_1 included in a clock monitoring circuit 10 according to an exemplary embodiment of the present invention is shown. Figures 4A-4C The operation of the first duty cycle detector 100_1 will be described in the following section, but the same description can be applied to other detectors. Figure 1 The operation of the second duty cycle detector 100_2. Figures 4A-4C For ease of description, it can be assumed that the elements of the high-level detector 120, excluding the inverter 121, have the same characteristics as the elements of the low-level detector 110, but the inventive concept is not limited thereto.

[0069] refer to Figure 3 and Figure 4A The clock signal CLK can have a period TS and a duty cycle of 50%. The length of the high-level period DS of the clock signal CLK can be the same as the length of the low-level period of the clock signal CLK.

[0070] The voltage CLKS of capacitor Ca in low-level detector 110 and the voltage CLKSb of capacitor Cab in high-level detector 120 can both be sawtooth waves with the same period TS as the period of clock signal CLK. The voltage CLKS of capacitor Ca in low-level detector 110 can be a sawtooth wave, where the sawtooth is formed during the low-level period of clock signal CLK. Conversely, the voltage CLKSb of capacitor Cab in high-level detector 120 can be a sawtooth wave, where the sawtooth is formed during the high-level period of clock signal CLK.

[0071] The first upper limit voltage BH1 can have a level that is higher than the non-working width voltage VCLKL by a first upper limit level dh1, and the first lower limit voltage BL1 can have a level that is lower than the non-working width voltage VCLKL by a first lower limit level dl1. In an example embodiment, the first upper limit level dh1 and the first lower limit level dl1 can have the same value.

[0072] The components of the high-level detector 120, excluding the inverter 121, can have the same characteristics as the components of the low-level detector 110, and therefore, the non-operating width voltage VCLKL and the operating width voltage VCLKH can have substantially the same value. Thus, the operating width voltage VCLKH can have a value between the first upper limit voltage BH1 and the first lower limit voltage BL1.

[0073] The comparator circuit 140 can output a first duty cycle detection signal DRR1, which includes a first signal DRRH1 having a second logic level (e.g., low level) and a second signal DRRL1 having a second logic level.

[0074] refer to Figure 3 and Figure 4B The clock signal CLK can have a period TS and a reduced duty cycle (e.g., 30% duty cycle). Therefore, the length of the high-level period DS_d of the clock signal CLK can be shorter than the length of the low-level period of the clock signal CLK.

[0075] The voltage CLKS of capacitor Ca in low-level detector 110 can be a sawtooth wave, where the sawtooth is formed during the low-level period of clock signal CLK. Conversely, the voltage CLKSb of capacitor Cab in high-level detector 120 can also be a sawtooth wave, where the sawtooth is formed during the high-level period of clock signal CLK. Since the length of the high-level period DS_d of clock signal CLK is shorter than the length of the low-level period of clock signal CLK, the maximum value of the voltage CLKS of capacitor Ca in low-level detector 110 can be greater than the maximum value of the voltage CLKSb of capacitor Cab in high-level detector 120.

[0076] and Figure 4A Compared to the non-operating width voltage VCLKL Figure 4B The non-operating width voltage VCLKL can be increased, and simultaneously, the first upper limit voltage BH1 and the first lower limit voltage BL1 can be increased. On the other hand, with Figure 4A Compared to the operating width voltage VCLKH. Figure 4B The operating width voltage VCLKH can be reduced and can have a value less than the first lower limit voltage BL1. The comparator circuit 140 can output a first duty cycle detection signal DRR1, which includes a first signal DRRH1 with a second logic level (e.g., low level) and a second signal DRRL1 with a first logic level (e.g., high level).

[0077] refer to Figure 3 and Figure 4C The clock signal CLK can have a period TS and can have an increased duty cycle (e.g., 70% duty cycle). Therefore, the length of the high-level period DS_i of the clock signal CLK can be longer than the length of the low-level period of the clock signal CLK.

[0078] The voltage CLKS of capacitor Ca in low-level detector 110 can be a sawtooth wave, where the sawtooth is formed during the low-level period of clock signal CLK. Conversely, the voltage CLKSb of capacitor Cab in high-level detector 120 can also be a sawtooth wave, where the sawtooth is formed during the high-level period of clock signal CLK. Since the length of the high-level period DS_i of clock signal CLK is longer than the length of the low-level period of clock signal CLK, the maximum value of the voltage CLKS of capacitor Ca in low-level detector 110 can be less than the maximum value of the voltage CLKSb of capacitor Cab in high-level detector 120.

[0079] and Figure 4A Compared to the non-operating width voltage VCLKL Figure 4C The non-operating width voltage VCLKL can be reduced, and simultaneously, the first upper limit voltage BH1 and the first lower limit voltage BL1 can be reduced. On the other hand, withFigure 4A Compared to the operating width voltage VCLKH. Figure 4C The operating width voltage VCLKH can be increased and can have a value greater than the first upper limit voltage BH1. The comparator circuit 140 can output a first duty cycle detection signal DRR1, which includes a first signal DRRH1 with a first logic level and a second signal DRRL1 with a second logic level.

[0080] refer to Figures 4A-4C The first duty cycle detector 100_1 can detect situations where the clock signal CLK does not maintain a 50% duty cycle, and thus increases to above the upper limit or decreases to below the lower limit. When the difference between the duty cycle of the clock signal CLK and 50% increases, the probability that a portion of the clock signal CLK is not transmitted may increase. The clock monitoring circuit 10 according to the present invention can perform monitoring to ensure that the duty cycle of the clock signal CLK is maintained at 50%, thereby enhancing the operational performance of the integrated circuit of the clock monitoring circuit 10.

[0081] Figure 5 An example embodiment of the invention is shown. Figure 1 A block diagram of the first duty cycle detector 100_1a included in the clock monitoring circuit 10.

[0082] refer to Figure 5 The first duty cycle detector 100_1a may include a low-level detector 110a, a high-level detector 120a, a boundary voltage generator 130a, and a comparator circuit 140a. Figure 1 The second duty cycle detector 100_2 may also include, for example, Figure 5 The low-level detector, high-level detector, boundary voltage generator, and comparator circuitry shown are illustrated, and the description of the components of the first duty cycle detector 100_1a can be applied to the components of the second duty cycle detector 100_2. The low-level detector 110a of the first duty cycle detector 100_1a can be implemented as such... Figure 3 The circuit of the low-level detector 110 of the first duty cycle detector 100_1 shown is illustrated, and the high-level detector 120a can be implemented as such Figure 3 The circuit of the high-level detector 120 shown.

[0083] The low-level detector 110a can receive a clock signal CLK and can generate and output a non-working width voltage VCLKL corresponding to the length of the low-level period of the clock signal CLK. For example, the low-level detector 110a can generate a non-working width voltage VCLKL such that the level of the non-working width voltage VCLKL increases as the low-level period increases.

[0084] The high-level detector 120a can receive the clock signal CLK and generate and output a working width voltage VCLKH corresponding to the length of the high-level period of the clock signal CLK. For example, the high-level detector 120a can generate a working width voltage VCLKH such that the level of the working width voltage VCLKH increases as the high-level period increases.

[0085] Boundary voltage generator 130a can receive the operating width voltage VCLKH from the high-level detector 120a and can generate a first upper limit voltage BH1a and a first lower limit voltage BL1a. In this case, the first upper limit voltage BH1a can have a level as high as the first upper limit level from the operating width voltage VCLKH, and the first lower limit voltage BL1a can have a level as low as the first lower limit level relative to the operating width voltage VCLKH. In an example embodiment, the first upper limit level and the first lower limit level can have the same value.

[0086] Comparator circuit 140a can receive the non-operating width voltage VCLKL from low-level detector 110a, and can receive the first upper limit voltage BH1a and the first lower limit voltage BL1a from boundary voltage generator 130a. Comparator circuit 140a can compare the non-operating width voltage VCLKL with the first upper limit voltage BH1a, and can compare the non-operating width voltage VCLKL with the first lower limit voltage BL1a, thereby generating a first duty cycle signal DRR1a.

[0087] In an example embodiment, the first duty cycle signal DRR1a may include a first signal DRRH1a and a second signal DRRL1a. For example, when the non-working width voltage VCLKL increases with the length of the low-level period of the clock signal CLK and the non-working width voltage VCLKL is higher than the first upper limit voltage BH1a, the comparator circuit 140a may output the second signal DRRL1a with a first logic level (e.g., a high level). On the other hand, when the non-working width voltage VCLKL is equal to or lower than the first upper limit voltage BH1a, the comparator circuit 140a may output the second signal DRRL1a with a second logic level (e.g., a low level).

[0088] When the non-operating width voltage VCLKL decreases as the length of the low-level period of the clock signal CLK decreases and the non-operating width voltage VCLKL is lower than the first lower limit voltage BL1a, the comparator circuit 140a can output a first signal DRRH1a with a first logic level. On the other hand, when the non-operating width voltage VCLKL is equal to or higher than the first lower limit voltage BL1a, the comparator circuit 140a can output a first signal DRRH1a with a second logic level.

[0089] Figure 6 A block diagram of a first frequency detector 200_1 included in a clock monitoring circuit 10 according to an exemplary embodiment of the present invention is shown.

[0090] refer to Figure 6 The first frequency detector 200_1 may include a frequency extractor 210 and a comparator circuit 220. Figure 1 The second frequency detector 200_2 may include a frequency extractor and a comparator circuit, and the following description of the elements of the first frequency detector 200_1 may be applied to the elements of the second frequency detector 200_2.

[0091] Frequency extractor 210 can receive a clock signal CLK and generate a frequency detection voltage VCLKF corresponding to the frequency of the clock signal CLK. In an example embodiment, frequency extractor 210 can generate a frequency detection voltage VCLKF such that the level of the frequency detection voltage VCLKF increases as the frequency of the clock signal CLK decreases, that is, as the period of the clock signal CLK increases. Alternatively, in an example embodiment, frequency extractor 210 can generate a frequency detection voltage VCLKF such that the level of the frequency detection voltage VCLKF increases as the frequency of the clock signal CLK increases.

[0092] The comparator circuit 220 can obtain the second duty cycle detector (e.g., Figure 1 (100_2) receives a second upper limit voltage BH2 and a second lower limit voltage BL2. Both the second upper limit voltage BH2 and the second lower limit voltage BL2 can be used to detect a monitoring clock signal (e.g., Figure 1 The voltage generated by the change in the duty cycle of CLK_M.

[0093] In an example embodiment, the second upper limit voltage BH2 may have a relative relationship with the monitoring clock signal (e.g., Figure 1 The second upper limit voltage BL2 can be as high as the second lower limit voltage BL2 relative to the voltage corresponding to the duty cycle of the monitoring clock signal CLK_M (e.g., the non-working width voltage corresponding to the length of the low-level period or the working width voltage corresponding to the length of the high-level period), and the second lower limit voltage BL2 can be as low as the second lower limit voltage relative to the voltage corresponding to the duty cycle of the monitoring clock signal CLK_M. Both the second upper limit voltage BL2 and the second lower limit voltage BL2 can be boundary values ​​used by the second duty cycle detector 100_2 to detect changes in the duty cycle of the monitoring clock signal CLK_M.

[0094] Comparator circuit 220 can compare the frequency detection voltage VCLKF with a second upper limit voltage BH2 and a second lower limit voltage BL2 to generate a first frequency detection signal FR1. In an example embodiment, when the frequency detection voltage VCLKF has a level between the second upper limit voltage BH2 and the second lower limit voltage BL2, comparator circuit 220 can output the first frequency detection signal FR1 with a first logic level (e.g., high level). Furthermore, when the frequency detection voltage VCLKF is higher than the second upper limit voltage BH2 or lower than the second lower limit voltage BL2, comparator circuit 220 can output the first frequency detection signal FR1 with a second logic level (e.g., low level).

[0095] Figure 7 A circuit diagram of a first frequency detector 200_1 included in a clock monitoring circuit 10 according to an example embodiment is shown, and it is based on... Figure 6 The circuit diagram of the example embodiment shown is shown in the figure.

[0096] refer to Figure 7 The first frequency detector 200_1 may include a frequency extractor 210 and a comparator circuit 220. Figure 1 The second frequency detector 200_2 may include a frequency extractor and a comparator circuit, and the following description of the circuit elements of the first frequency detector 200_1 may be applied to the circuit elements of the second frequency detector 200_2.

[0097] The low-level detector 110 may include a transistor Tf that is turned on based on a clock signal CLK, a capacitor Cf that is charged or discharged based on the clock signal CLK, and a low-pass filter including a resistor Rxf and a capacitor Cxf. The capacitor Cf may be connected to a current source IBf, and the current source IBf may be connected to a source voltage VDD.

[0098] During the low-level period of the clock signal CLK, transistor Tf can be turned off, and capacitor Cf can be charged by current source IBf. The voltage CLKSf across capacitor Cf can gradually increase during the low-level period of the clock signal CLK. Conversely, during the high-level period of the clock signal CLK, transistor Tf can be turned on, and the voltage CLKSf across capacitor Cf can be 0V. The voltage CLKSf across capacitor Cf can be a sawtooth wave with the same period as the clock signal CLK, and the maximum value of the voltage CLKSf across capacitor Cf can increase as the low-level period of the clock signal CLK increases.

[0099] A low-pass filter including resistor Rxf and capacitor Cxf can receive the voltage CLKSf of capacitor Cf and output the average value of the voltage CLKSf of capacitor Cf during the period of clock signal CLK as the frequency detection voltage VCLKF. The frequency detection voltage VCLKF can satisfy the following equation (4).

[0100] [Equation 4]

[0101]

[0102] Here, IBf represents the current level of the current source IBf connected to capacitor Cf, TS represents the period of clock signal CLK, DL represents the ratio of the low-level period of clock signal CLK to the period TS, and Cf represents the capacitance of capacitor Cf. Therefore, when the duty cycle of the frequency detection voltage VCLKF is constant, the level of the frequency detection voltage VCLKF can increase as the period TS of clock signal CLK increases, that is, it increases as the frequency of clock signal CLK decreases.

[0103] In an example embodiment, the elements of the frequency extractor 210 may have elements that are compatible with a low-level detector (e.g., Figure 3 The characteristics of the frequency extractor 210 are the same as those of the low-level detector 110. That is, the transistor Tf of the frequency extractor 210 can be configured to be the same as the transistor Ta of the low-level detector 110, the capacitance Cf of the frequency extractor 210 can be the same as the capacitance Ca of the low-level detector 110, and the current level of the current source IBf of the frequency extractor 210 can be the same as the current level of the current source IB of the low-level detector 110. Furthermore, in the example embodiment, the low-pass filter of the frequency extractor 210 can have the same characteristics as the low-pass filter of the low-level detector 110.

[0104] However, in Figure 7 In the circuit configuration of the frequency extractor 210, it can be assumed that each of the second upper limit voltage BH2 and the second lower limit voltage BL2 input to the comparator circuit 220 is derived from a source having… Figure 2 The second duty cycle detector 100_2, as shown in the configuration, is provided. The second upper limit voltage BH2 and the second lower limit voltage BL2 input to each comparator circuit 220 are provided by... Figure 5 In the case of the second duty cycle detector 100_2 provided in the configuration shown, the circuit elements of the frequency extractor 210 can have the same characteristics as the high-level detector (e.g., Figure 3 The characteristics of the components of (120) are the same. That is, the frequency extractor 210 may also include an inverter and may use the clock inversion signal CLKb.

[0105] Comparator circuit 220 may include a first comparator 221, a second comparator 223, and a NOR gate 225. However, the NOR gate 225 may be merely an example, and comparator circuit 220 conceived according to the present invention may include an XOR gate instead of the NOR gate 225, and may be implemented as various circuits.

[0106] The first comparator 221 can receive the frequency detection voltage VCLKF from the frequency extractor 210, and can also receive it from the second duty cycle detector (e.g., Figure 1 The first comparator 221 receives the second upper limit voltage BH2. It compares the frequency detection voltage VCLKF with the second upper limit voltage BH2 and outputs a comparison result signal FRH1. For example, when the frequency detection voltage VCLKF is higher than the second upper limit voltage BH2, the first comparator 221 can output a comparison result signal FRH1 with a first logic level (e.g., high level), and when the frequency detection voltage VCLKF is equal to or lower than the second upper limit voltage BH2, the first comparator 221 can output a comparison result signal FRH1 with a second logic level (e.g., low level).

[0107] The second comparator 223 can receive the frequency detection voltage VCLKF from the frequency extractor 210 and the second lower limit voltage BL2 from the second duty cycle detector 100_2. The second comparator 223 can compare the frequency detection voltage VCLKF with the second lower limit voltage BL2 and output a comparison result signal FRL1. For example, when the frequency detection voltage VCLKF is equal to or higher than the second lower limit voltage BL2, the second comparator 223 can output a comparison result signal FRL1 with a second logic level; and when the frequency detection voltage VCLKF is lower than the second lower limit voltage BL2, the second comparator 223 can output a comparison result signal FRL1 with a first logic level.

[0108] NOR gate 225 can receive the comparison result signal FRH1 from the first comparator 221 and the comparison result signal FRL1 from the second comparator 223. When both the comparison result signal FRH1 output from the first comparator 221 and the comparison result signal FRL1 output from the second comparator 223 have a second logic level, NOR gate 225 can output a first frequency detection signal FR1 with a first logic level. Therefore, when the frequency detection voltage VCLKF has a level between the second upper limit voltage BH2 and the second lower limit voltage BL2, the first frequency detection signal FR1 with a first logic level can be output.

[0109] On the other hand, when either the comparison result signal FRH1 output from the first comparator 221 or the comparison result signal FRL1 output from the second comparator 223 has a first logic level, the NOR gate 225 can output a first frequency detection signal FR1 with a second logic level. Therefore, when the frequency detection voltage VCLKF is higher than the second upper limit voltage BH2 or lower than the second lower limit voltage BL2, the first frequency detection signal FR1 with a second logic level can be output.

[0110] The first frequency detector 200_1 according to the present invention can use a low-pass filter to detect a frequency voltage VCLKF using the average value of the voltage CLKSf of the capacitor Cf with frequency extractor 210, and therefore, a relatively slow comparator (e.g., first comparator 221 and second comparator 223) can be used. Therefore, the frequency extractor in the comparison example where the maximum value of the voltage CLKSf of the capacitor Cf is used to detect frequency changes requires a comparator with a relatively fast speed, but the first frequency detector 200_1 according to the present invention can reduce the power consumption of the first frequency detector 200_1 by using a comparator with a relatively slow speed.

[0111] Figure 8A , Figure 8B and Figure 8C This is a timing diagram illustrating the operation of a first frequency detector 200_1 included in a clock monitoring circuit 10 according to an exemplary embodiment of the present invention.

[0112] exist Figures 8A-8C The operation of the first frequency detector 200_1 will be described in the following section, but the same description can be applied to other frequencies. Figure 1 The operation of the second frequency detector 200_2. It can be assumed that... Figure 1 The second duty cycle detector 100_2 is configured to be with Figure 3 The circuit shown is the same as that of the first duty cycle detector 100_1.

[0113] refer to Figure 7 and Figure 8A The period TS_M of the monitoring clock signal CLK_M and the period TS of the clock signal CLK can be the same. Furthermore, both the monitoring clock signal CLK_M and the clock signal CLK can have a 50% duty cycle. Therefore, the length of each of the high-level periods DS_M and DS of the monitoring clock signal CLK_M and the clock signal CLK can be the same as the length of each of the low-level periods of the monitoring clock signal CLK_M and the clock signal CLK.

[0114] The voltage CLKSM of the capacitor included in the low-level detector of the second duty cycle detector 100_2 can be charged or discharged according to the control based on the monitoring clock signal CLK_M. For example, the capacitor can be charged when the monitoring clock signal CLK_M is low, and the capacitor can be discharged when the monitoring clock signal CLK_M is high.

[0115] The capacitor voltage CLKSM can be a sawtooth wave with the same period TS_M as the monitoring clock signal CLK_M, and the sawtooth can be formed during the low-level period of the monitoring clock signal CLK_M. The non-operating monitoring voltage VCLKLM can be the average value of the capacitor voltage CLKSM during the period TS_M of the monitoring clock signal CLK_M.

[0116] The voltage CLKSf of capacitor Cf in frequency extractor 210 can be a sawtooth wave with the same period TS as the period of clock signal CLK. The voltage CLKSf of capacitor Cf in frequency extractor 210 can be a sawtooth wave in which the sawtooth is formed during the low-level period of clock signal CLK.

[0117] When the low-level detector of the second duty cycle detector 100_2 and the frequency extractor 210 are configured with the same circuitry, the non-operation monitoring voltage VCLKLM and the frequency detection voltage VCLKF can be approximately the same. Therefore, the frequency detection voltage VCLKF can have a value between the second upper limit voltage BH2 and the second lower limit voltage BL2. In this case, the second upper limit voltage BH2 can have a higher level than the non-operation monitoring voltage VCLKLM (the second upper limit level dh2), and the second lower limit voltage BL2 can have a lower level than the non-operation monitoring voltage VCLKLM (the second lower limit level dl2). In the example embodiment, the second upper limit level dh2 and the second lower limit level dl2 can have the same value.

[0118] The comparator circuit 220 can output a first frequency detection signal FR1 with a first logic level (e.g., high level).

[0119] refer to Figure 7 and Figure 8B The period TSd of the clock signal CLK can be shorter than the period TS_M of the monitoring clock signal CLK_M. In other words, the frequency of the clock signal CLK can be higher than the frequency of the monitoring clock signal CLK_M. The length of the high-level period DSd of the clock signal CLK can be shorter than... Figure 8A The high-level period DS of the clock signal CLK shown is shorter.

[0120] As the period TSd of the clock signal CLK shortens, the maximum value of the voltage CLKSf across the capacitor Cf of the frequency extractor 210 can decrease, and the level of the frequency detection voltage VCLKF can decrease. Therefore, the frequency detection voltage VCLKF can become lower than the second lower limit voltage BL2, and the comparator circuit 220 can output a first frequency detection signal FR1 with a second logic level (e.g., low level).

[0121] refer to Figure 7 and Figure 8C The period TS_i of the clock signal CLK can be longer than the period TS_M of the monitoring clock signal CLK_M. In other words, the frequency of the clock signal CLK can be lower than the frequency of the monitoring clock signal CLK_M. The length of the high-level period DSi of the clock signal CLK can be longer than... Figure 8A The high-level period DS of the clock signal CLK shown is longer.

[0122] As the period TSi of the clock signal CLK increases, the maximum value of the voltage CLKSf across the capacitor Cf of the frequency extractor 210 can increase, and the level of the frequency detection voltage VCLKF can increase. Therefore, the frequency detection voltage VCLKF can become higher than the second upper limit voltage BH2, and the comparator circuit 220 can output a first frequency detection signal FR1 with a second logic level.

[0123] refer to Figures 8A-8C The frequency of the clock signal CLK can be associated with various operating speeds of the integrated circuit including the clock monitoring circuit 10, and therefore, the clock signal CLK can be generated in the integrated circuit to have a predetermined frequency. The first frequency detector 200_1 can detect excessive increases or decreases in the frequency of the clock signal CLK, and can detect abnormal states of each of the clock signal CLK and the monitoring clock signal CLK_M.

[0124] Figure 9 A block diagram illustrating an example embodiment of an integrated circuit 1000 according to a concept of the present invention is shown.

[0125] refer to Figure 9 The integrated circuit 1000 may include a clock monitoring circuit 10, a clock generator 20, and control logic 30. The clock generator 20 may generate clock signals CLK1 and CLK2. For example, the clock generator 20 may include a first oscillator 20_1 and a second oscillator 20_2.

[0126] exist Figure 9 The diagram shows that clock generator 20 outputs two different clock signals CLK1 and CLK2, but the number of clock signals generated by clock generator 20 can be modified in various ways.

[0127] In an example embodiment, integrated circuit 1000 may be a power management integrated circuit (PMIC) that can receive an input voltage from an external source and provide multiple output voltages to the PMIC, each of which is suitable for driving multiple consumers. In an example embodiment, integrated circuit 1000 may be implemented using various semiconductor devices.

[0128] The first oscillator 20_1 can generate a first clock signal CLK1 with a first frequency, and the second oscillator 20_2 can generate a second clock signal CLK2 with a second frequency. In this case, the first frequency can be different from the second frequency. Figure 9 The diagram shows two oscillators, but the integrated circuit 1000 according to the present invention may include three or more oscillators.

[0129] The clock monitoring circuit 10 can detect duty cycle changes and frequency changes of at least one of the first clock signal CLK1 and the second clock signal CLK2. For example, the clock monitoring circuit 10 can detect duty cycle changes and frequency changes of the first clock signal CLK1 by using a monitoring clock signal CLK_M. The clock monitoring circuit 10 can output a first duty cycle signal DRR1 based on the duty cycle change of the first clock signal CLK1, and output a first frequency detection signal FR1 based on the frequency change of the first clock signal CLK1. Furthermore, the clock monitoring circuit 10 can also output a second duty cycle signal DRR2 based on the duty cycle change of the monitoring clock signal CLK_M, and output a second frequency detection signal FR2 based on the frequency change of the monitoring clock signal CLK_M. In an example embodiment, the clock monitoring circuit 10 may be... Figure 1 The clock monitoring circuit 10, and may include Figure 6 The first frequency detector 200_1 and at least one of the following: Figure 2 The first duty cycle detector 100_1 and Figure 5 The first duty cycle detector 100_1a.

[0130] Control logic 30 can receive a first clock signal CLK1 from the first oscillator 20_1 and a second clock signal CLK2 from the second oscillator 20_2. Control logic 30 can receive a first duty cycle signal DRR1, a second duty cycle signal DRR2, a first frequency detection signal FR1, and a second frequency detection signal FR2 from the clock monitoring circuit 10.

[0131] Control logic 30 can determine the duty cycle and frequency changes of the first clock signal CLK1 based on the first duty cycle signal DRR1, the second duty cycle signal DRR2, the first frequency detection signal FR1, and the second frequency detection signal FR2. For example, when receiving the first duty cycle signal DRR1, which includes a first signal DRRH1 with a second logic level (e.g., low) and a second signal DRRL1 with a first logic level (e.g., high), control logic 30 can determine that the duty cycle of the first clock signal CLK1 is less than the lower limit. Alternatively, for example, when receiving the first duty cycle signal DRR1, which includes a first signal DRRH1 with a first logic level and a second signal DRRL1 with a second logic level, control logic 30 can determine that the duty cycle of the first clock signal CLK1 is greater than the upper limit. Furthermore, for example, when receiving the first frequency detection signal FR1 with a second logic level, control logic 30 can determine that the frequency of the first clock signal CLK1 is greater than the upper limit or less than the lower limit.

[0132] In an example embodiment, when an excessive change is determined in at least one of the duty cycle and frequency of the first clock signal CLK1, the control logic 30 may restore the first clock signal CLK1.

[0133] Control logic 30 can determine the frequency change of the second clock signal CLK2 based on the first frequency detection signal FR1 and the second frequency detection signal FR2. For example, control logic 30 can determine the frequency change of the second clock signal CLK2 based on the relationship between the first frequency and the second frequency. Alternatively, for example, control logic 30 can determine the frequency change of the second clock signal CLK2 based on the relationship between the frequency of the monitoring clock signal CLK_M and the second frequency.

[0134] Figure 10 A block diagram illustrating an example embodiment of an integrated circuit 1000' according to a concept of the present invention is shown.

[0135] refer to Figure 10 Integrated circuit 1000' may include clock monitoring circuit 10', phase-locked loop (PLL) 20_3, and control logic 30'. In an example embodiment, integrated circuit 1000' may be a PMIC. In an example embodiment, integrated circuit 1000' may be implemented using various semiconductor devices.

[0136] PLL 20_3 can receive a reference clock to generate multiple clock signals (e.g., a first clock signal CLK1 and a second clock signal CLK2). In this case, the first frequency can be different from the second frequency.

[0137] The clock monitoring circuit 10' can detect duty cycle changes and frequency changes of at least one of the first clock signal CLK1 and the second clock signal CLK2. For example, the clock monitoring circuit 10' can detect duty cycle changes and frequency changes of the first clock signal CLK1 by using a monitoring clock signal CLK_M. The clock monitoring circuit 10' can output a first duty cycle signal DRR1 based on the duty cycle change of the first clock signal CLK1, and output a first frequency detection signal FR1 based on the frequency change of the first clock signal CLK1. Furthermore, the clock monitoring circuit 10' can also output a second duty cycle signal DRR2 based on the duty cycle change of the monitoring clock signal CLK_M, and output a second frequency detection signal FR2 based on the frequency change of the monitoring clock signal CLK_M. In an example embodiment, the clock monitoring circuit 10' may be... Figure 1 The clock monitoring circuit 10, and may include Figure 6 The first frequency detector 200_1 and at least one of the following: Figure 2 The first duty cycle detector 100_1 and Figure 5 The first duty cycle detector 100_1a.

[0138] Control logic 30' can receive the first clock signal CLK1 and the second clock signal CLK2 from PLL 20_3. Control logic 30' can receive the first duty cycle signal DRR1, the second duty cycle signal DRR2, the first frequency detection signal FR1, and the second frequency detection signal FR2 from clock monitoring circuit 10'.

[0139] Control logic 30' can determine the duty cycle change and frequency change of the first clock signal CLK1 based on the first duty cycle signal DRR1, the second duty cycle signal DRR2, the first frequency detection signal FR1, and the second frequency detection signal FR2. In an example embodiment, when an excessive change in at least one of the duty cycle and frequency of the first clock signal CLK1 is determined, control logic 30' can restore the first clock signal CLK1.

[0140] Control logic 30' can determine the frequency change of the second clock signal CLK2 based on the first frequency detection signal FR1 and the second frequency detection signal FR2. For example, control logic 30' can determine the frequency change of the second clock signal CLK2 based on the relationship between the first clock signal CLK1 and the second clock signal CLK2 (e.g., the relationship between the first frequency and the second frequency).

[0141] Figure 11 A block diagram illustrating an example embodiment of an electronic device 2000 according to a concept of the present invention is shown.

[0142] refer to Figure 11The electronic device 2000 may include a PMIC 2100, an application processor (AP) 2200, an input device 2300, a display 2400, a memory 2500, and a battery 2600. For example, the electronic device 2000 may be a device included in a vehicle, or it may be a smartphone, personal computer (PC), tablet PC, netbook computer, e-reader, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player, etc. Furthermore, the electronic device 2000 may be a wearable device such as an electronic bracelet or electronic necklace.

[0143] The PMIC 2100 can be powered by the battery 2600 and can manage the power of the AP 2200, input device 2300, display 2400, or memory 2500. In an example embodiment, the PMIC 2100 may include... Figure 9 Integrated circuit 1000 and Figure 10 At least one of the integrated circuits 1000'.

[0144] AP 2200 can control the overall operation of electronic device 2000. Specifically, AP 2200 can display data stored in memory 2500 on display 2400 based on input signals generated by input device 2300. For example, input device 2300 can be implemented using a keypad, keyboard, or pointing device such as touchpad or computer mouse.

[0145] As described above, exemplary embodiments have been disclosed in the accompanying drawings and specification. While the concept of the invention has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, it should be understood that various modifications and other equivalent embodiments can be implemented by those skilled in the art. Consequently, the spirit and scope of the invention should be defined by the claims.

Claims

1. A clock monitoring circuit, comprising: The first duty cycle detector is configured to detect changes in the duty cycle of a clock signal and generate a first duty cycle detection signal indicating changes in the duty cycle of the clock signal. The first duty cycle detector is also configured to output a first upper limit voltage and a first lower limit voltage corresponding to the first duty cycle detection signal. The second duty cycle detector is configured to detect changes in the duty cycle of the monitoring clock signal and generate a second duty cycle detection signal indicating changes in the duty cycle of the monitoring clock signal. The second duty cycle detector is also configured to output a second upper limit voltage and a second lower limit voltage corresponding to the second duty cycle detection signal. and A first frequency detector is configured to receive the clock signal, the second upper limit voltage, and the second lower limit voltage, and to detect frequency changes of the clock signal based on the second upper limit voltage and the second lower limit voltage. Wherein, the first upper limit voltage has a level as high as a first upper limit level relative to the voltage corresponding to the duty cycle of the clock signal, and the first lower limit voltage has a level as low as a first lower limit level relative to the voltage corresponding to the duty cycle of the clock signal, and The second upper limit voltage has a level as high as a second upper limit level relative to the voltage corresponding to the duty cycle of the monitoring clock signal, and the second lower limit voltage has a level as low as a second lower limit level relative to the voltage corresponding to the duty cycle of the monitoring clock signal.

2. The clock monitoring circuit according to claim 1 further includes a second frequency detector, the second frequency detector being configured to receive the monitoring clock signal, the first upper limit voltage and the first lower limit voltage, and to detect frequency changes of the monitoring clock signal based on the first upper limit voltage and the first lower limit voltage.

3. The clock monitoring circuit according to claim 1, wherein, The first duty cycle detector includes: A low-level detector is configured to generate a non-operating width voltage corresponding to the length of the low-level period of the clock signal; A high-level detector is configured to generate an operating width voltage corresponding to the length of the high-level period of the clock signal; A boundary voltage generator, configured to receive the non-operating width voltage and generate the first upper limit voltage and the first lower limit voltage; and A comparator circuit is configured to compare the operating width voltage with the first upper limit voltage and the first lower limit voltage to generate and output a first duty cycle detection signal.

4. The clock monitoring circuit according to claim 3, wherein, The low-level detector includes: A capacitor having a first terminal and a second terminal, wherein, during a low-level period of the clock signal, the voltage across the first terminal and the second terminal increases; and A low-pass filter configured to generate the non-operating width voltage using the voltage across the first and second terminals of the capacitor.

5. The clock monitoring circuit according to claim 1, wherein, The first duty cycle detector includes: A low-level detector is configured to generate a non-operating width voltage corresponding to the low-level period of the clock signal; A high-level detector is configured to generate a working width voltage corresponding to the high-level period of the clock signal; A boundary voltage generator, configured to receive the operating width voltage and generate the first upper limit voltage and the first lower limit voltage; and A comparator circuit is configured to compare the non-operating width voltage with the first upper limit voltage and the first lower limit voltage to generate and output a first duty cycle detection signal.

6. The clock monitoring circuit according to claim 1, wherein, The first frequency detector includes: A frequency extractor is configured to generate a frequency detection voltage corresponding to the frequency of the clock signal; and A comparator circuit is configured to compare the frequency detection voltage with a second upper limit voltage and a second lower limit voltage to generate and output a frequency detection signal corresponding to the frequency change of the clock signal.

7. The clock monitoring circuit according to claim 6, wherein, The frequency extractor includes: A capacitor having a first terminal and a second terminal, wherein, during a low-level period of the clock signal, the voltage across the first terminal and the second terminal increases; and A low-pass filter configured to generate the frequency detection voltage using the voltage across the first and second terminals of the capacitor.

8. The clock monitoring circuit according to claim 1, wherein, The first upper limit level and the first lower limit level have the same value.

9. The clock monitoring circuit according to claim 1, wherein, The first upper limit level and the second upper limit level have the same value.

10. An integrated circuit including a clock monitoring circuit for monitoring the characteristics of a clock signal, The clock monitoring circuit includes: The first duty cycle detector is configured to detect changes in the duty cycle of the first clock signal and generate a first duty cycle detection signal indicating changes in the duty cycle of the first clock signal. The first duty cycle detector is also configured to output a first upper limit voltage and a first lower limit voltage corresponding to the first duty cycle detection signal. The second duty cycle detector is configured to detect changes in the duty cycle of the monitoring clock signal and generate a second duty cycle detection signal indicating changes in the duty cycle of the monitoring clock signal. The second duty cycle detector is also configured to output a second upper limit voltage and a second lower limit voltage corresponding to the second duty cycle detection signal. and A first frequency detector is configured to receive a first clock signal, a second upper limit voltage, and a second lower limit voltage, and to output a first frequency detection signal based on the frequency change of the first clock signal based on the second upper limit voltage and the second lower limit voltage. Wherein, the first upper limit voltage has a level as high as a first upper limit level relative to the voltage corresponding to the duty cycle of the first clock signal, and the first lower limit voltage has a level as low as a first lower limit level relative to the voltage corresponding to the duty cycle of the first clock signal, and The second upper limit voltage has a level as high as a second upper limit level relative to the voltage corresponding to the duty cycle of the monitoring clock signal, and the second lower limit voltage has a level as low as a second lower limit level relative to the voltage corresponding to the duty cycle of the monitoring clock signal.

11. The integrated circuit according to claim 10, further comprising: A first oscillator is configured to generate the first clock signal; and The second oscillator is configured to generate a second clock signal having a frequency different from that of the first clock signal. The clock monitoring circuit is configured to receive the first clock signal from the first oscillator.

12. The integrated circuit of claim 11, further comprising control logic configured to determine the frequency change of the second clock signal based on the first clock signal and the first frequency detection signal.

13. The integrated circuit of claim 10, further comprising a phase-locked loop (PLL) configured to generate a plurality of clock signals having different frequencies. in, The clock monitoring circuit is configured to receive the first clock signal from the plurality of clock signals from the PLL.

14. The integrated circuit according to claim 10, wherein, The integrated circuit includes a power management integrated circuit (PMIC) configured to provide power to an external location.

15. The integrated circuit according to claim 10, wherein, The clock monitoring circuit further includes a second frequency detector, which is configured to receive the monitoring clock signal, the first upper limit voltage, and the first lower limit voltage, and output a second frequency detection signal based on the frequency change of the monitoring clock signal based on the first upper limit voltage and the first lower limit voltage.

16. The integrated circuit according to claim 10, wherein, The first duty cycle detector includes: A low-level detector is configured to output a non-operating width voltage corresponding to the length of the low-level period of the first clock signal; A high-level detector is configured to output a working width voltage corresponding to the length of the high-level period of the first clock signal; A boundary voltage generator, configured to generate the first upper limit voltage and the first lower limit voltage from the non-operating width voltage; and The comparator circuit is configured to compare the operating width voltage with the first upper limit voltage and the first lower limit voltage to output the first duty cycle detection signal.

17. The integrated circuit according to claim 10, wherein, The first duty cycle detector includes: A low-level detector is configured to generate a non-operating width voltage corresponding to the length of the low-level period of the first clock signal; A high-level detector is configured to generate a working width voltage corresponding to the length of the high-level period of the first clock signal; A boundary voltage generator, configured to generate the first upper limit voltage and the first lower limit voltage from the operating width voltage; and The comparator circuit is configured to compare the non-operating width voltage with the first upper limit voltage and the first lower limit voltage to output the first duty cycle detection signal.

18. The integrated circuit according to claim 10, wherein, The first frequency detector includes: A frequency extractor is configured to generate a frequency detection voltage corresponding to the frequency of the first clock signal; and A comparator circuit is configured to compare the frequency detection voltage with a second upper limit voltage and a second lower limit voltage to generate and output the first frequency detection signal.

19. An integrated circuit, comprising: A clock generator, configured to generate clock signals; and A clock monitoring circuit is configured to monitor the duty cycle and frequency of the clock signal. The clock monitoring circuit includes: The first duty cycle detector is configured to detect changes in the duty cycle of a clock signal and generate a first duty cycle detection signal indicating changes in the duty cycle of the clock signal. The first duty cycle detector is also configured to output a first upper limit voltage and a first lower limit voltage corresponding to the first duty cycle detection signal. The second duty cycle detector is configured to detect changes in the duty cycle of the monitoring clock signal and generate a second duty cycle detection signal indicating changes in the duty cycle of the monitoring clock signal. The second duty cycle detector is also configured to output a second upper limit voltage and a second lower limit voltage corresponding to the second duty cycle detection signal. A first frequency detector is configured to receive the clock signal, the second upper limit voltage, and the second lower limit voltage, and based on the second upper limit voltage and the second lower limit voltage, output a first frequency detection signal based on the frequency change of the clock signal; and The second frequency detector is configured to receive the monitoring clock signal, the first upper limit voltage, and the first lower limit voltage, and output a second frequency detection signal based on the frequency change of the monitoring clock signal based on the first upper limit voltage and the first lower limit voltage.

20. The integrated circuit according to claim 19, wherein, The first upper limit voltage has a level as high as a first upper limit level relative to the voltage corresponding to the duty cycle of the clock signal, and the first lower limit voltage has a level as low as a first lower limit level relative to the voltage corresponding to the duty cycle of the clock signal. The second upper limit voltage has a level as high as a second upper limit level relative to the voltage corresponding to the duty cycle of the monitoring clock signal, and the second lower limit voltage has a level as low as a second lower limit level relative to the voltage corresponding to the duty cycle of the monitoring clock signal.

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