Storage system and method of controlling operation of nonvolatile memory device

Abstract

The present application relates to a storage system and a method for controlling the operation of a non-volatile memory device. The method includes monitoring a plurality of data streams having different stream identifiers to determine a stream data characteristic of each of the plurality of data streams, determining a plurality of operating conditions based on a plurality of operating environments, and determining one of the plurality of operating conditions as a stream operating condition for each of the plurality of data streams based on the stream data characteristic of each of the plurality of data streams.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2019-0071596 filed on June 17, 2019, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments relate to semiconductor integrated circuits, and more particularly, to a memory device supporting multiple-stream and a method of controlling operations of a nonvolatile memory device. Background Art

[0004] There are many different types of nonvolatile memory devices, each with constituent memory cells that operate according to different principles. For example, the memory cells of a flash memory device store data associated with multiple threshold voltage distributions, while the memory cells of a resistive memory device store data according to multiple resistance value distributions. In either case, each respective "distribution" represents a corresponding logical state for the stored data.

[0005] Once data is written (or programmed) to a nonvolatile memory cell, the data can be read by determining whether the selected (or target) memory cell is turned on or off when a specific read voltage is applied. Thus, one or more read voltages will be defined according to a profile intended to characterize the stored data.

[0006] During or after programming a memory cell, its intended distribution may change or be distorted due to a number of events or conditions including, for example, charge leakage, program disturb, read disturb, word and / or bit line coupling, temperature variations, voltage variations, memory cell degradation, etc. In extreme cases, the intended distribution may become shifted and / or widened such that a "read fail" occurs.

[0007] When a read failure occurs, some nonvolatile memory devices may perform a different type of read operation (i.e., a read operation with a different read sequence) than the read operation that caused the read failure. However, it is not easy to set a read sequence that correctly accounts for the many events and conditions that may have changed the distribution of data being read. Therefore, as changes in current operating conditions are evaluated or identified according to an acceptable read sequence, the "read latency" (i.e., the period of time required to read the stored data) may increase, and the performance of the nonvolatile memory device may decrease as its read latency increases. Summary of the Invention

[0008] Some example embodiments may provide a memory device that efficiently supports multi-streaming and a method of controlling an operation of a nonvolatile memory device.

[0009] According to an example embodiment, a method of controlling an operation of a nonvolatile memory device includes monitoring a plurality of data streams having different stream identifiers to determine a stream data characteristic of each of the plurality of data streams, determining a plurality of operating conditions based on a plurality of operating environments, respectively, and determining one of the plurality of operating conditions as a stream operating condition for each of the plurality of data streams based on the stream data characteristic of each of the plurality of data streams.

[0010] According to an example embodiment, a method for controlling the operation of a nonvolatile memory device that exchanges multiple data streams with a memory controller (each of the multiple data streams is identified by a corresponding one of multiple stream identifiers) includes monitoring at least one of a data retention characteristic and a read disturb characteristic of each of the multiple data streams, determining multiple read sequences based on multiple operating environments, the multiple read sequences having different combinations of multiple read operations, the multiple read operations having different read voltage sets or different read times, and determining at least one of a hold read sequence or a disturb read sequence among the multiple read sequences as a stream operation condition for each of the multiple data streams. In the hold read sequence, a read operation having a read voltage set corresponding to a case where the data retention characteristic is degraded is first performed. In the disturb read sequence, a read operation having a read voltage set corresponding to a case where the read disturb characteristic is degraded is first performed.

[0011] According to an example embodiment, a storage system that processes multiple data streams (each of the multiple data streams is identified by a corresponding one of a plurality of stream identifiers) includes a nonvolatile memory device including a memory cell array in which a plurality of nonvolatile memory cells are arranged, and a controller configured to store a plurality of operating conditions corresponding to a plurality of operating environments, respectively, to monitor stream data characteristics for each of the multiple data streams, and to determine a stream operating condition corresponding to each of the multiple data streams among the multiple operating conditions based on the stream data characteristics of each of the multiple data streams.

[0012] A storage device supporting multi-streaming and a method of controlling operations of a nonvolatile memory device according to example embodiments may improve performance of a nonvolatile memory device and a storage device including the nonvolatile memory device by setting streaming operation conditions suitable for streaming data characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0014] Figure 1 is a flowchart illustrating a method of controlling an operation of a nonvolatile memory device according to example embodiments.

[0015] Figure 2 is a block diagram illustrating a storage system according to example embodiments.

[0016] Figure 3 is a diagram illustrating an example transfer of multi-stream data to be written to a storage device, as requested by a host device.

[0017] Figure 4 This is a diagram showing an address mapping table of the flash translation layer (FTL).

[0018] Figure 5 is a diagram illustrating an example embodiment of a flow control table of a flow manager included in a nonvolatile memory device according to example embodiments.

[0019] Figure 6 It is shown that the Figure 5 FIG. 1 is a diagram of an example embodiment of flow data characteristics in a flow control table of FIG.

[0020] Figure 7 is a block diagram illustrating a nonvolatile memory device according to example embodiments.

[0021] Figure 8 is a block diagram illustrating an example embodiment of a memory cell array included in a nonvolatile memory device according to example embodiments.

[0022] Figure 9 It shows Figure 8 Circuit diagram of the equivalent circuit of the memory block in .

[0023] Figure 10 is a flowchart illustrating a method of controlling an operation of a nonvolatile memory device according to example embodiments.

[0024] Figure 11 and 12 is a diagram for describing changes in threshold voltage distribution of memory cells.

[0025] Figure 13 is a diagram illustrating a read sequence according to an example embodiment.

[0026] Figure 14 is a diagram showing an example format of a command transmitted from a host device to a storage device, and Figure 15 It is shown that the Figure 14 Figure 1 shows an example format of the lowest double word in a command.

[0027] Figure 16 is a diagram illustrating an example read sequence according to an example embodiment.

[0028] Figure 17 It shows that according to Figure 16 Flowchart of a method for reading data from a reading sequence.

[0029] Figure 18 is a diagram illustrating a plurality of read sequences according to example embodiments.

[0030] Figure 19 is a block diagram illustrating an example of a read sequence controller in a nonvolatile memory device according to example embodiments.

[0031] Figure 20 is a flowchart illustrating a method of controlling a read sequence of a nonvolatile memory device according to example embodiments.

[0032] Figure 21 is a diagram for describing a predetermined read voltage and an optimal read voltage.

[0033] Figure 22 、 Figure 23 and Figure 24 is a diagram illustrating a read sequence according to an example embodiment.

[0034] Figure 25 is a timing diagram showing an example of a read process of a nonvolatile memory device, and Figure 26 Is used to describe the Figure 25 A graph showing the reading time of the reading process.

[0035] Figure 27 、 Figure 28 and Figure 29 is a diagram illustrating a valley search method according to example embodiments.

[0036] Figure 30 is a diagram for describing an example of a 2-bit soft decision read operation, and Figure 31 is a diagram for describing an example of a 3-bit soft decision read operation.

[0037] Figure 32 is a diagram illustrating an example embodiment of a unit characteristic table of a stream manager included in a nonvolatile memory device according to example embodiments.

[0038] Figure 33 is a diagram for describing program operation conditions according to example embodiments, and Figure 34 is a diagram for describing erase operation conditions according to example embodiments. DETAILED DESCRIPTION

[0039] Various example embodiments will be described more fully below with reference to the accompanying drawings, in which some example embodiments are shown. In the accompanying drawings, like numbers refer to like elements. Repetitive descriptions may be omitted.

[0040] Figure 1 is a flowchart illustrating a method of controlling an operation of a nonvolatile memory device according to example embodiments.

[0041] refer to Figure 1 In a storage device including a nonvolatile memory device that exchanges multi-stream data (or multiple data streams) with a storage controller using multiple stream identifiers, stream data characteristics are monitored for each of the multiple stream identifiers (S100). The stream data characteristics may be monitored continuously and in real time. In some example embodiments, the stream data characteristics to be monitored may include a data retention characteristic indicating a duration for which data stored in a memory cell is maintained and a read disturb characteristic indicating state distortion of a memory cell due to repeated read operations.

[0042] A plurality of operating conditions corresponding to a plurality of operating environments are determined (S200). The operating environment can be changed and determined based on various factors that affect the operation of the non-volatile memory device. For example, the operating environment can be determined based on factors such as operating temperature, degree of memory cell degradation, user scenario, and characteristics of data used by the application. The operating environment may change when at least one of the factors changes. As described below, the plurality of operating conditions may include a plurality of read sequences, a plurality of programming conditions, or a plurality of erase operation conditions.

[0043] Based on the stream data characteristics, a plurality of stream operating conditions corresponding to the plurality of stream identifiers are determined from among the plurality of operating conditions (S300). The stream operating conditions may be optimized for the corresponding stream data characteristics.

[0044] In this way, the performance of the nonvolatile memory device and the storage device including the nonvolatile memory device can be improved by setting streaming operation conditions suitable for the characteristics of streaming data.

[0045] Figure 2 is a block diagram illustrating a storage system according to example embodiments.

[0046] refer to Figure 2, the storage system 10 may include a storage controller 20 and a storage device 30. The storage device 30 may include at least one non-volatile memory device NVM. The storage device 30 may include a flash memory or a flash memory-based data storage medium (such as a memory card and a universal serial bus (USB) memory). In an example embodiment, the storage system 10 may include a solid state drive (SSD).

[0047] The memory device 30 can perform read operations, erase operations, and program operations or write operations under the control of the memory controller 20. The memory device 30 can receive commands CMD, addresses ADDR, and data DATA from the memory controller 20 through input / output lines to perform such operations. In addition, the memory device 30 can receive control signals CTRL from the memory controller 20 through control lines and receive power PWR from the memory controller 20 through power lines.

[0048] According to an example embodiment, the storage device 30 may include a stream manager STMNG. Figure 1 As described above, the stream manager STMNG may monitor stream data characteristics for each of the plurality of stream identifiers, and determine a plurality of stream operating conditions respectively corresponding to the plurality of stream identifiers from among the plurality of operating conditions based on the monitored stream data characteristics.

[0049] Figure 3 is a diagram illustrating an example transfer of multi-stream data to be written to a storage device, as requested by a storage controller.

[0050] refer to Figure 3 , since there is a signal channel between the storage controller 20 and the storage device 30, it is difficult to simultaneously transmit multi-stream data (or multiple data streams) to the storage device 30. The write request to the storage device 30 can be executed in units of, for example, multiple segments that can form one stream. In the case where multiple stream data are requested to be written (write-requested), the write command for each segment can include a multi-stream index or stream identifier STID. The present invention is not limited to this. In an example embodiment, the write request to the storage device 30 can be executed in units of multiple blocks or pages that can form one stream.

[0051] like Figure 3As shown, it can be assumed that a host (not shown) runs an application in multiple threads, and the application generates a write request associated with four stream data (or data streams) driven by a storage controller 20 connected to the host. Each of a plurality of stream identifiers STID (for example, STID=1, 2, 3, or 4) can be assigned to each of a plurality of stream data (or a plurality of data streams) ST1, ST2, ST3, and ST4. The storage device 30 can store the data requested to be written based on the plurality of stream identifiers STID. For example, the storage device 30 can store data with the same stream identifier STID in the same memory area (for example, in the same memory block corresponding to the unit of the erase operation). Therefore, the efficiency of operations such as garbage collection, sequential reading, or sequential writing can be improved.

[0052] Figure 4 FIG. 1 is a diagram showing an address mapping table of the flash translation layer.

[0053] refer to Figure 4 , the storage controller 20 can operate based on the address mapping table AMT, which includes mapping information between the logical address LOGADD of the host device and the physical address PHYADD of the non-volatile memory device in the storage device 30. For example, according to the mapping information of the address mapping table AMT, the logical address LA1 is mapped to the physical address PAa, and the logical address LA2 is mapped to the physical address PAb. The flash translation layer, as the firmware of the storage controller 20, can use the address mapping table AMT to determine the physical address of the non-volatile memory device corresponding to the logical address requested by the host device, and vice versa.

[0054] Figure 5 is a diagram illustrating an example embodiment of a flow control table of a flow manager included in a storage device according to an example embodiment.

[0055] refer to Figure 5 , the stream control table SDCT may include mapping information between the stream identifier STID, the logical address LOGADD, the stream data characteristics STDC and the stream operation condition SOPCON. Figure 2 The stream manager STMNG can monitor the stream data characteristics STDC (for example, STDC=SCH1 or SCH2) for each of multiple stream identifiers STID (for example, STID=1 or 2), and determine multiple stream operating conditions SOPCON (for example, SOPCON=OCa or OCb) corresponding to the multiple stream identifiers STID respectively among the multiple operating conditions based on the stream data characteristics STDC.

[0056] Figure 6 It is shown that the Figure 5 FIG. 1 is a diagram of an example embodiment of flow data characteristics in a flow control table of FIG.

[0057] refer to Figure 6 The stream data characteristics STDC monitored by the stream manager STMNG may include a programming time point TMPGM when data is programmed in the nonvolatile memory device, a read count RDC, the number of memory cells in a weak hold state NCR, the number of memory cells in a weak read disturbance state NCD, and a plurality of average read wait times m(LAT) respectively corresponding to a plurality of read sequences.

[0058] In some example embodiments, the stream manager STMNG may determine data retention characteristics for each of a plurality of streams by monitoring a programming-reading interval time between a programming time point TMPGM when data is written to a non-volatile memory device and a reading time point when data is read from the non-volatile memory device, where each of the plurality of streams is identified by a corresponding one of a plurality of stream identifiers.

[0059] In some example embodiments, the stream manager STMNG may determine a data retention characteristic for each of a plurality of data streams by monitoring a number NCR of memory cells in a weak retention state among a plurality of memory cells in a plurality of states of a non-volatile memory device, each of the plurality of data streams being identified by a corresponding one of a plurality of stream identifiers, wherein the weak retention state corresponds to at least one of the plurality of states.

[0060] In some example embodiments, the stream manager STMNG may determine the read disturb characteristic for each of the plurality of stream identifiers by monitoring a read count RDC indicating the number of times data is read since the data was written in the nonvolatile memory device.

[0061] In some example embodiments, the stream manager STMNG may determine a read disturbance characteristic of each of a plurality of streams by monitoring a number NCD of memory cells in a weak read disturbance state among a plurality of memory cells in a plurality of states of a non-volatile memory device, each of the plurality of streams being identified by a corresponding one of a plurality of stream identifiers, wherein the weak read disturbance state corresponds to at least one of the plurality of states.

[0062] In some example embodiments, the stream manager STMNG may monitor, for each of a plurality of stream identifiers, a plurality of average read latencies m(LAT) respectively corresponding to a plurality of read sequences, and may select a primary read sequence from among the plurality of read sequences as a stream operation condition. The primary read sequence corresponds to a read sequence having a minimum average read latency from among the plurality of average read latencies m(LAT).

[0063] Figure 6 The factors shown are non-limiting examples, and example embodiments are not limited thereto. For example, the stream data characteristics STDC may include a programming temperature when data is written to the non-volatile memory device. In this case, the stream manager STMNG may determine appropriate stream operating conditions by monitoring the difference between the programming temperature and the read temperature when data is read from the non-volatile memory device.

[0064] Figure 7 is a block diagram illustrating a nonvolatile memory device according to example embodiments.

[0065] refer to Figure 7 , the memory device 30 includes a nonvolatile memory device including a memory cell array 100 , a page buffer circuit 410 , a data input / output circuit 420 , an address decoder 430 , a control circuit 450 , and a voltage generator 460 .

[0066] The memory cell array 100 is coupled to the address decoder 430 through a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. In addition, the memory cell array 100 is coupled to the page buffer circuit 410 through a plurality of bit lines BL.

[0067] The memory cell array 100 may include a plurality of memory cells coupled to a plurality of word lines WL and a plurality of bit lines BL. In some example embodiments, the memory cell array 100 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional structure (or a vertical structure). In this case, the memory cell array 100 may include a plurality of NAND strings vertically oriented such that at least one memory cell is located above another memory cell.

[0068] The control circuit 450 receives a command (signal) CMD and an address (signal) ADDR from the memory controller 20, which may also be referred to as a memory controller. The control circuit 450 may control the erase, program, and read operations of the non-volatile memory device 30 based on the command signal CMD and the address signal ADDR. For example, the control circuit 450 may generate a control signal CTL for controlling the voltage generator 460 based on the command signal CMD, may generate a page buffer control signal PBC for controlling the page buffer circuit 410, and may generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 450 may provide the row address R_ADDR to the address decoder 430 and provide the column address C_ADDR to the data input / output circuit 420.

[0069] The address decoder 430 may be coupled to the memory cell array 100 through a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. During a programming operation or a read operation, the address decoder 430 may determine one of the plurality of word lines WL as a selected word line based on a row address R_ADDR, and determine the remaining word lines of the plurality of word lines WL other than the selected word line as unselected word lines. In addition, during a programming operation or a read operation, the address decoder 430 may determine one of the plurality of string selection lines SSL as a selected string selection line based on a row address R_ADDR, and determine the remaining word lines of the plurality of string selection lines SSL other than the selected string selection line as unselected string selection lines.

[0070] The voltage generator 460 may generate a word line voltage VWL that may be required for the operation of the memory cell array 100 of the nonvolatile memory device 30 based on the control signal CTL. The voltage generator 460 may receive power PWR from the memory controller 20. The word line voltage VWL may be applied to a plurality of word lines WL through the address decoder 430.

[0071] The page buffer circuit 410 may be coupled to the memory cell array 100 through a plurality of bit lines BL. The page buffer circuit 410 may include a plurality of buffers. The page buffer circuit 410 may temporarily store data to be programmed into a selected page or data read out from a selected page of the memory cell array 100.

[0072] The data input / output circuit 420 may be coupled to the page buffer circuit 410 via the data line DL. During a program operation, the data input / output circuit 410 may receive program data DATA received from the host device via the memory controller 20 and provide the program data DATA to the page buffer circuit 410 based on the column address C_ADDR received from the control circuit 450. During a read operation, the data input / output circuit 420 may provide read data DATA that has been read from the memory cell array 100 and stored in the page buffer circuit 410 to the host device via the memory controller 20 based on the column address C_ADDR received from the control circuit 450.

[0073] According to an example embodiment, the control circuit 450 may include a stream manager STMNG. The stream manager STMNG may monitor stream data characteristics for each of a plurality of stream identifiers and determine a plurality of stream operating conditions corresponding to the plurality of stream identifiers, respectively, from among a plurality of operating conditions based on the monitored stream data characteristics.

[0074] Figure 8 is a block diagram illustrating an example embodiment of a memory cell array included in a nonvolatile memory device according to example embodiments, and Figure 9 It shows Figure 8 Circuit diagram of the equivalent circuit of the memory block in .

[0075] like Figure 8 As shown, the memory cell array 100 includes a plurality of memory blocks BLK1 to BLKz. Figure 7 The address decoder 430 in the memory block BLK1 to BLKz selects the memory blocks BLK1 to BLKz. For example, the address decoder 430 may select a specific memory block BLK corresponding to the block address among the memory blocks BLK1 to BLKz.

[0076] Figure 9 The memory block BLKi may be formed in a three-dimensional structure (or vertical structure) on a substrate. For example, a plurality of NAND strings or cell strings included in the memory block BLKi may be formed in a first direction D1 (i.e., perpendicular to the upper surface of the substrate) perpendicular to the second direction D2 and the third direction D3.

[0077] refer to Figure 9 , the memory block BLKi includes NAND strings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the NAND strings NS11 to NS33 includes a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST. Figure 9 , each of the NAND strings NS11 to NS33 is shown as including eight memory cells MC1 to MC8. However, example embodiments are not limited thereto. In some example embodiments, each of the NAND strings NS11 to NS33 may include any number of memory cells.

[0078] Each string select transistor SST can be connected to a corresponding string select line (one of SSL1 to SSL3). A plurality of memory cells MC1 to MC8 can be connected to a plurality of gate lines GTL1 to GTL8, respectively. The gate lines GTL1 to GTL8 can be word lines, and some of the gate lines GTL1 to GTL8 can be dummy word lines. Each ground select transistor GST can be connected to a corresponding ground select line (one of GSL1 to GSL3). Each string select transistor SST can be connected to a corresponding bit line (e.g., one of BL1, BL2, and BL3), and each ground select transistor GST can be connected to a common source line CSL.

[0079] Word lines (eg, WL1) having the same height (ie, level) may be commonly connected, and ground selection lines GSL1 to GSL3 and string selection lines SSL1 to SSL3 may be separated. Figure 9, the memory block BLKi is illustrated as being coupled to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3. However, example embodiments are not limited thereto.

[0080] Figure 10 is a flowchart illustrating a method of controlling an operation of a nonvolatile memory device according to example embodiments.

[0081] refer to Figure 10 In a storage device including a nonvolatile memory device that exchanges multi-stream data with a storage controller using multiple stream identifiers, at least one of a data retention characteristic and a read disturbance characteristic can be monitored for each of the multiple data streams (S110). A plurality of read sequences corresponding to different combinations of multiple read operations can be determined, wherein the multiple read operations have different read voltage sets or different read times (S210). A retention read sequence or a disturbance read sequence can be determined as each of the multiple stream operation conditions corresponding to the multiple stream identifiers among the multiple operation conditions (S310). A read operation having a read voltage set corresponding to a case where the data retention characteristic is degraded can be performed first according to the retention read sequence. A read operation having a read voltage set corresponding to a case where the read disturbance characteristic is degraded can be performed first according to the retention read sequence.

[0082] In the following, reference will be made to Figures 11 to 31 Further description Figure 10 An example embodiment of a method of

[0083] Figure 11 and Figure 12 is a diagram for describing changes in threshold voltage distribution of memory cells.

[0084] exist Figure 11 and Figure 12 , the horizontal axis indicates the threshold voltage VTH, and the vertical axis indicates the number of memory cells having the threshold voltage VTH. Figure 11 shows the change in threshold voltage distribution according to the degradation of data retention characteristics, and Figure 12 The change of the threshold voltage distribution according to the degradation of the read disturbance characteristic is shown. Figure 11 and 12 , only two adjacent states Si and Si+1 in multiple threshold voltage distributions and a read voltage Vr used to determine one of states Si and Si+1 are shown. Typically, each memory cell can have one of 2n states corresponding to n bits, where n is a natural number. In this case, 2n-1 read voltages are required to determine the 2n states, and these 2n-1 read voltages can be referred to as a read voltage set.

[0085] like Figure 11 As shown, according to the data retention characteristics related to data retention capability, the initial states Si and Si+1 can be changed or shifted to the retained degraded states RSi and RSi+1 having a lower threshold voltage distribution. In this case, it is necessary to adjust the read voltage VR used to determine one of the initial states Si and Si+1 to the read voltage VRr used to determine the retained degraded states RSi and RSi+1.

[0086] like Figure 12 As shown, according to the read disturbance characteristics associated with repeated data reading, the initial states Si and Si+1 can be changed or shifted to the disturbance-degraded states DSi and DSi+1 having a higher threshold voltage distribution. In this case, it is necessary to adjust the read voltage VR used to determine one of the initial states Si and Si+1 to the read voltage VRd used to determine one of the disturbance-degraded states DSi and DSi+1.

[0087] Figure 13 is a diagram illustrating a read sequence according to an example embodiment.

[0088] refer to Figure 13 , the first read sequence RSEQ1, the second read sequence RSEQ2, and the third read sequence RSEQ3 can have different combinations of multiple read operations (e.g., first to fourth read operations ROP1 to ROP4). For example, the first read operation ROP1 can have a first read voltage set, the second read operation can have a second read voltage set suitable for degradation of data retention characteristics, the third read operation ROP3 can have a third read voltage set suitable for degradation of read disturbance characteristics, and the fourth read operation ROP4 can have a fourth read voltage set suitable for changes in operating temperature. The first read sequence RSEQ1 can be a predetermined default read sequence regardless of the operating environment.

[0089] When the stream manager STMNG determines that the data retention characteristic has degraded for a stream identifier, the stream manager STMNG may determine the second read sequence RSEQ2 as the stream operation condition for the corresponding stream identifier. In this way, the stream manager STMNG may monitor the data retention characteristic for each of the plurality of stream identifiers and select a retention read sequence (i.e., the second read sequence RSEQ2) from among the plurality of read sequences RSEQ1 to RSEQ4 as the stream operation condition, so that a read operation ROP2 having a read voltage set corresponding to the condition of the data retention characteristic degradation may be first performed according to the retention read sequence.

[0090] When the stream manager STMNG determines that the read disturb characteristic has degraded for a stream identifier, the stream manager STMNG may determine the third read sequence RSEQ3 as the stream operation condition for the corresponding stream identifier. In this way, the stream manager STMNG may monitor the read disturb characteristic for each of the plurality of stream identifiers and select an interfering read sequence (i.e., the third read sequence RSEQ3) from among the plurality of read sequences RSEQ1 to RSEQ4 as the stream operation condition, so that a read operation ROP3 having a read voltage set corresponding to the condition of the degraded read disturb characteristic may be first performed according to the interfering read sequence.

[0091] Figure 14 is a diagram showing an example format of a command transmitted from a storage controller to a storage device, and Figure 15 It is shown that the Figure 14 Figure 17 shows an example format of the lowest double word in the command. Figure 14 and 15 The format can be used for standard commands specified in the NVMe standard.

[0092] refer to Figure 14 , each command may have a predetermined size, such as 64 bytes. Figure 14 In the , the lowest double word CDW0 can be commonly used for all commands. The double word corresponds to four bytes. The namespace identifier (NSID) field can specify the namespace ID to which the command is applied. If the namespace ID is not used for the command, the NSID field can be cleared to 0h. Bytes 08 to 15 can be reserved. The metadata pointer (MPTR) field can be valid and used only when the command includes metadata. The physical region page (PRP) entry field can specify the data used by the command. The above double words CDW10 to CDW15 can have a specific usage for each command.

[0093] refer to Figure 15, the lowest double word CDW0 can have a predetermined size, for example, four bytes. Important information can be concentrated in the first byte (BYTE=0). Bits B0 to B3 of the first byte (BYTE=0) can include the access frequency ACCFRQ for the memory area of ​​the address range requested for access. In other words, information about the write request frequency or the read request frequency can be included in bits B0 to B3 of the first byte (BYTE=0). Bits B4 and B5 of the first byte (BYTE=0) can include information about the access latency ACCLAT. The access latency for the requested data can be defined by the values ​​of bits B4 and B5 of the first byte (BYTE=0). Bit B6 of the first byte (BYTE=0) can indicate whether the corresponding command is one of the sequential commands. For example, when the value of bit B6 is "1", the corresponding command can be one of the sequential commands, and when the value of bit B6 is "0", information about the sequential command may be unavailable. Bit B7 of the first byte (BYTE=0) can indicate whether the data requested for access is compressed. For example, when the value of the B7 bit is '1', data may be compressed, and when the value of the B7 bit is '1', information on data compression may be unavailable.

[0094] In some example embodiments, the stream identifier STID may be included in the second byte (BYTE=1). In other example embodiments, the stream identifier STID may be included in reserved bytes (BYTE=2 and 3).

[0095] In some example embodiments, the stream manager STMNG may determine stream data characteristics for each of the plurality of stream identifiers STID based on access information (e.g., access frequency ACCFRQ) in a command transmitted from a storage controller to a storage device or a non-volatile memory device.

[0096] Figure 16 is a diagram illustrating an example read sequence according to an example embodiment.

[0097] refer to Figure 16 , each read sequence RSEQ may include a plurality of read operations ROP1 ˜ROPk having respective read times tRD1 ˜tRDk different from each other.

[0098] There is a trade-off between the length of the read time and the accuracy of the corresponding read operation. In other words, a read operation with a shorter read time may have a higher probability of a read failure result, while a read operation with a longer read time may have a higher probability of a successful read operation result. Therefore, each read sequence RSEQ may be set so that a read operation with a shorter read time will be executed before a read operation with a longer read time, for example Figure 16 shown.

[0099] The read latency associated with the selected read sequence corresponds to the sum of the read times of the read operations performed before valid data is obtained. Figure 16 In the example shown, if valid data is obtained through the first read operation ROP1, the read wait time tLAT1 corresponds to the first read time tRD1, if valid data is obtained through the second read operation ROP2, the read wait time tLAT2 corresponds to the sum tRD1+tRD2 of the first read time tRD1 and the second read time tRD2, if valid data is obtained through the third read operation ROP3, the read wait time tLAT3 corresponds to the sum tRD1+tRD2+tRD3 of the first read time tRD1, the second read time tRD2 and the third read time tRD3, and if valid data is obtained through the last read operation ROPk, the read wait time tLATk corresponds to the sum tRD1+tRD2+…+tRDk of all read times tRD1~tRDk.

[0100] Figure 17 It shows that according to Figure 16 Flowchart of a method for reading data from a reading sequence.

[0101] refer to Figure 17 , according to the set read sequence RSET, the first read operation ROP1 (S11) with the highest priority is executed. Figure 16 As in the example of FIG. 1 , it is assumed that each read operation is performed in conjunction with ECC decoding. Therefore, when the error(s) in the read data are determined to be correctable by ECC decoding ( S12 = Yes), the first read time tRD1 of the first read operation ROP1 is determined to be the read latency tLAT1 ( S13 ). Therefore, since the error(s), if any, are correctable, valid data is obtained, and the read sequence RSEQ ends.

[0102] However, when the error(s) are uncorrectable (S12=No), the second read operation ROP2 of the next priority is executed (S21). Similarly, if the error(s) generated in the read data (if any) are determined to be correctable by ECC decoding (S22=Yes), the sum of the read times tRD1+tRD2 of the first and second read operations ROP1 and ROP2 is determined as the read latency tLAT2 (S23).

[0103] However, if the error(s) are uncorrectable (S22=No), the third read operation ROP3 of the next priority is executed (S31). Similarly, if the error(s) in the read data (if any) are determined to be correctable by ECC decoding (S32=Yes), the sum of the read times tRD1+tRD2+tRD3 of the first read operation ROP1, the second read operation ROP2, and the third read operation ROP3 is determined as the read latency tLAT3 (S33).

[0104] In this manner, as long as valid data is not obtained by executing a read operation with a higher priority, the various read operations are sequentially executed until the last read operation ROPk is executed (S41). Therefore, finally, if the error(s) in the read data (if any) are determined to be correctable by ECC decoding (S42=Yes), the sum of the read times tRD1+tRD2+…+tRDk of all read operations ROP1-ROPk is determined as the read latency tLATk (S43).

[0105] However, if valid data is not obtained through the last read operation ROPk, it is determined that the current read operation is determined to be a failure ( S50 ) (ie, a read failure occurs), and the read sequence RSEQ ends.

[0106] For example, according to Figure 2 In the operating environment of the storage device 30, valid data can be obtained in the first read operation ROP1. Therefore, the read latency can be minimized by using the read sequence shown, so that the entire read operation can be performed with the minimum read latency, or valid data can be obtained in a read operation after the first read operation is performed. Therefore, a second and possibly subsequent read operations with their respective priorities can be performed. This will significantly increase the read latency of the entire read operation. In the example embodiment, a storage device 30 that is less used may output valid data in the first read operation ROP1. However, a storage device 30 that has degraded due to frequent use may output valid data in a read operation after the first read operation is performed, which results in an increase in read latency.

[0107] According to example embodiments, performance of a nonvolatile memory device may be improved by setting a plurality of read sequences and determining an optimal read sequence among the set read sequences for each of the stream identifiers.

[0108] Figure 18 is a diagram illustrating a plurality of read sequences according to example embodiments.

[0109] Figure 18FIG. 0 shows non-limiting examples of two read sequences of three or more read operations that may be set according to example embodiments. As described above, each of the first read sequence RSEQ1 and the second read sequence RSEQ2 may be set such that a read operation with a shorter read time is performed before a read operation with a longer read time. For example, the read times of the read operations ROP11, ROP12, and ROP13 in the first read sequence RSEQ1 may satisfy the relationship tRD11 < tRD12 < tRD13, and the read times of the read operations ROP21, ROP22, and ROP23 in the second read sequence RSEQ2 may satisfy the relationship tRD21 < tRD22 < tRD23.

[0110] In some example embodiments, the first read sequence RSEQ1 may be set such that a first read operation ROP1 with a first read time tRD11 is first performed in the first read sequence RSEQ1, and the second read sequence RSEQ2 may be set such that a second read operation ROP21 with a second read time tRD21 longer than the first read time tRD11 is first performed in the second read sequence RSEQ2. As the probability of successful reading of the first read operation ROP11 increases, the first read sequence RSEQ1 is more suitable than the second read sequence RSEQ2. Conversely, as the probability of successful reading of the first read operation ROP11 decreases, the second read sequence RSEQ2 is more suitable than the first read sequence RSEQ1.

[0111] Figure 19 FIG. 7 is a block diagram showing an example of a read sequence controller in a non-volatile memory device according to an example embodiment.

[0112] Referring Figure 19 to FIG. 12, the read sequence controller 600 includes a latency detector 620, an average latency calculator 630, a sequence selection rate (SSR) determiner 640, a read sequence (RSEQ) selector 650, and a number provider 660. In an example embodiment, the read sequence controller 600 may be included in Figure 2 the stream manager STMNG.

[0113] Whenever the selected read sequence is completed, the latency detector 620 may provide the current read latency tLATj of the selected read sequence based on the timing signal TM and the stream identifier STID. For example, the timing signal TM may include a signal indicating a timing point when a raw read command is generated or received and a signal indicating a timing point when it is determined that the reading is successful by ECC decoding.

[0114] The average latency calculator 630 may provide an average latency m(tLATj) of the selected read sequence based on the current read latency tLATj and the selection signal SEL. A read sequence corresponding to the current read latency tLATj may be selected based on the selection signal SEL to update the average latency m(tLATj) of the corresponding read sequence using the current read latency tLATj.

[0115] The SSR determiner 640 can adjust the sequence selectivity SSRi based on the average wait times corresponding to the read sequences, respectively. For example, when three read sequences RSEQ1, RSEQ2, and RSEQ3 are set, the SSR determiner 640 can provide three sequence selectivity rates SSR1, SSR2, and SSR3. The SSR determiner 140 can determine a main read sequence among the read sequences so that the main read sequence can correspond to the read sequence with the minimum average wait time among the average wait times, and set the sequence selectivity of the main read sequence to be greater than the sequence selectivity of the other read sequences.

[0116] For example, in the early stages of using a nonvolatile memory device, a first read sequence RSE1 may have the minimum average latency and may be set as the primary read sequence. If the minimum value of the sequence selectivity is 0.05 for monitoring at least the read latency, the sequence selectivity may be determined as SSR1 = 0.90, SSR2 = 0.05, and SSR3 = 0.05. If operating conditions change and the primary read sequence is changed from the first read sequence RSEQ1 to the second read sequence RSEQ2, the sequence selectivity may be adjusted to SSR1 = 0.05, SSR2 = 0.90, and SSR3 = 0.05.

[0117] The RSEQ selector 650 can generate a selection signal SEL indicating which read sequence is currently selected and executed. For example, when SSR1=0.90, SSR2=0.05, and SSR3=0.05, the RSEQ selector generates the selection signal SEL so that the first read sequence RSEQ1 can be selected 90 times out of 100, the second read sequence RSEQ2 can be selected 5 times out of 100, and the third read sequence RSEQ3 can be selected 5 times out of 100. The selection signal SEL can be provided by the stream manager STMNG described above, and the stream manager STMNG can select an appropriate read sequence for each stream identifier STID based on the selection signal SEL.

[0118] In some example embodiments, the RSEQ selector 150 may irregularly select a read sequence based on the random number RN and the sequence selection rate SSRi.

[0119] Figure 20is a flowchart illustrating a method of controlling a read sequence of a nonvolatile memory device according to example embodiments.

[0120] refer to Figure 20 Initialize the sequence selection rates SSRi corresponding to the read sequences RSEQi (S710). According to the change of the operating conditions, each time a read sequence is executed, the initialized sequence selection rates SSRi are adjusted or maintained.

[0121] Based on the current sequence selection rate SSRi, a read sequence is selected from the read sequences RSEQi (S310), and the selected read sequence RSEQj is executed each time (S320, S330, S340). Figure 3 As described above, after the read sequence RSEQj ends, the current read latency tLATj of the selected read sequence RSEQj is provided (S510). The corresponding average latency m(tLATj) is updated using the provided current read latency tLATj (S520). Based on the average latency m(tLAT1), m(tLAT2), and m(tLAT3), it is determined whether the operating condition has changed (S720). When the operating condition is determined to have changed (S720: Yes), the sequence selectivity SSRi is adjusted (S730) to reflect or compensate for the change in the operating condition. When the operating condition is determined to have not changed (S720: No), the sequence selectivity SSRi is maintained.

[0122] When the operation of the nonvolatile memory device is completed (S910: Yes), the current sequence selection rate SSRi and the current average waiting time m(tLATi) may be stored in the memory controller or the nonvolatile memory device. When the operation of the nonvolatile memory device is not completed (S910: No), the above process is repeated based on the adjusted or maintained sequence selection rate SSRi.

[0123] In this way, each time a read sequence is executed, the read latency can be monitored, and the sequence selection rate can be adjusted based on the monitoring result to improve the performance of the non-volatile memory device.

[0124] Figure 21 is a diagram for describing a predetermined read voltage and an optimal read voltage.

[0125] Figure 21The threshold voltage distributions for two adjacent states Si and Si+1 in a flash memory device are shown as an example. The optimal read voltage Vop is the read voltage that minimizes the number of error bits among the data bits read simultaneously. The optimal read voltage Vop corresponds to the valley, i.e., the intersection of the threshold voltage distributions for the two states Si and Si+1. When the distributions shift and / or widen due to changes in operating conditions, a difference may occur between the predetermined read voltage and the optimal read voltage. As the difference increases, the bit error rate (BER) or the probability of a read failure also increases.

[0126] When the predetermined voltage is included in the first voltage range R1, errors in the read data can be corrected by ECC decoding using hard decision (HD). When the predetermined voltage is included in the second voltage range R2, errors in the read data can be corrected by ECC decoding using soft decision (SD). Figure 30 and Figure 31 HD and SD are further described.

[0127] When there are too many bit errors in the read data and the predetermined read voltage is outside the second range R2, valid data may not be obtained through ECC decoding. When valid data is not obtained through the previous read operation based on the predetermined read voltage, a valley search operation may be performed to determine the optimal read voltage Vop, and then the read operation may be performed again based on the optimal read voltage. Such a valley search operation and a read operation based on the optimal read voltage may be referred to as a voltage compensation read operation. In some example embodiments, each of the read sequences may include a read operation based on the predetermined read voltage with a higher priority and at least one voltage compensation read operation with a lower priority, such as Figure 22 、 Figure 23 and Figure 24 shown.

[0128] Figure 22 、 Figure 23 and Figure 24 is a diagram illustrating a read sequence according to an example embodiment.

[0129] refer to Figure 22 The first read sequence RSEQ1 may include first to sixth read operations ROP11 to ROP16 arranged according to respective priorities. The first, second, and third read operations ROP11, ROP12, and ROP13 may be based on predetermined read voltages, and the fourth, fifth, and sixth read operations ROP14, ROP15, and ROP16 may be voltage compensation read operations.

[0130] As described above, a read operation with a shorter read time can be executed before a read operation with a longer read time. In other words, the shorter the read time, the higher the priority of the read operation. The first read operation ROP11 with the shortest read time (i.e., the first read time tRD11) can be executed first, the second read operation ROP12 with a second read time tRD12 longer than the first read time tRD11 can be executed after the first read operation ROP11, and the sixth read operation ROP16 with the longest read time tRD16 can be executed last.

[0131] Each of the first and second read operations ROP11 and ROP12 may be a hard decision (HD) read operation that reads hard decision data using a predetermined read voltage and performs ECC decoding based on the hard decision data. Figure 25 and Figure 26 Described in more detail, the first read operation ROP11 may be a fast read operation DEF(F) based on a predetermined read voltage, and the second read operation ROP12 may be a normal read operation DEF(N) based on a predetermined read voltage.

[0132] The third read operation ROP13 can be a soft decision (SD) read operation, which reads out hard decision data using a predetermined read voltage, provides reliability information of the hard decision data using multiple read voltages around the predetermined read voltage, and performs ECC decoding based on the hard decision data and the reliability information.

[0133] The fourth, fifth, and sixth read operations ROP14, ROP15, and ROP16 may be voltage compensation read operations including valley search operations VS1, VS2, and VS3, respectively, and a read operation based on the detected optimal read voltage. The valley search operations VS1, VS2, and VS3 may be implemented differently to have different search times and different read accuracies.

[0134] refer to Figure 23 The second read sequence RSEQ2 may include first to fourth read operations ROP21 to ROP24 arranged according to respective priorities. The first and second read operations ROP21 and ROP22 may be based on predetermined read voltages, and the third and fourth read operations ROP23 and ROP24 may be voltage compensation read operations.

[0135] refer to Figure 24 , the third read sequence RSEQ3 may include first, second, and third read operations ROP31, ROP32, and ROP33 arranged according to respective priorities. The first read operation ROP31 may be based on a predetermined read voltage, and the second and third read operations ROP32 and ROP33 may be voltage compensation read operations.

[0136] For example, the BER can be set for a relatively low range of operating environments. Figure 22 The first read sequence RSEQ1 can be set for an operating environment with a BER in the middle range. Figure 23 The second read sequence RSEQ2 can be set for an operating environment with a relatively high BER range. Figure 24 In this way, the performance of the nonvolatile memory device can be improved by setting a plurality of read sequences corresponding to different operating environments and adaptively controlling the read sequences.

[0137] Figure 25 is a timing diagram showing an example of a read process (ie, a read operation) of a nonvolatile memory device, and Figure 26 Is used to describe the Figure 25 A graph showing the reading time of the reading process.

[0138] refer to Figure 25 When the discharge signal DIS is activated to a logic high level during the discharge period t0-t1, the bit line voltage Vr is initialized to the ground voltage. When the precharge signal PRE is activated to a logic low level during the precharge period t1-t2, the bit line voltage Vr is charged with the precharge voltage. When the precharge signal PRE is deactivated to a logic high level during the develop period t2-t3, the precharge voltage is blocked and the bit line voltage Vr decreases, where the bit line is connected to the ground voltage through the resistance element of the selected memory cell. The voltage VF1 of the bit line coupled to the off cell with a relatively high resistance value decreases slowly, while the voltage VF0 of the bit line coupled to the on cell with a relatively low resistance value decreases quickly.

[0139] When the sense enable signal SEN is activated to a logic high level during the sensing period t3 ˜ t4 , the bit line voltage VF1 or VF0 is compared with the read voltage VRD, and a data bit stored in a selected memory cell may be read.

[0140] Figure 26 Shown Figure 22 The data read time may include a discharge time tDIS, a precharge time tPRE, a development time tDEV, and a latch or read time tSEN. As the precharge time tPRE or the development time tDEV increases, the accuracy or reliability of the read data can be improved. Figure 26As shown, the sum of the precharge time tPRE(F) and the development time tDEV(F) of the first read operation ROP11 may be shorter than the sum of the precharge time tPRE(N) and the development time tDEV(N) of the second read operation ROP12 .

[0141] Figure 27 、 Figure 28 and Figure 29 is a schematic diagram illustrating a valley search method according to example embodiments.

[0142] refer to Figure 27 The first valley search method VS1 can be performed by referring to the shift table and testing a plurality of read voltages V1 to V4 having a higher valley probability using a blind search scheme.

[0143] refer to Figure 28 The second valley search method VS2 can be performed by scanning the distribution around the valley using a plurality of read voltages V1 to V5 and modeling the second-order curve MD. The voltage corresponding to the vertex of the modeled curve MD can be determined as the optimal read voltage.

[0144] refer to Figure 29 , the third valley search method may be performed by searching for a valley point using a plurality of read voltages V1 to V8 at relatively narrow intervals. A voltage corresponding to the minimum number of cells may be determined as an optimal voltage.

[0145] The first valley search method VS1 requires the shortest search time but has the lowest accuracy. In contrast, the third valley search method VS3 requires the longest search time but has the highest accuracy. In this way, various valley search methods or operations VS1, VS2, and VS3 with different search times and accuracies can be used to set the reference Figure 9 、 Figure 10 and Figure 11 Described read sequences RSEQ1, RSEQ2, and RSEQ3.

[0146] Figure 30 is a diagram for describing an example of a 2-bit soft decision read operation, and Figure 31 is a diagram for describing an example of a 3-bit soft decision read operation.

[0147] For example, Figure 30As shown, a nonvolatile memory device may perform a 2-bit soft decision read operation. The 2-bit soft decision read operation may include three read operations using three voltages V1, V2, and V3 at regular intervals. For example, the three voltages V1, V2, and V3 may include a first voltage V1 having a predetermined reference level for determining one of a first state Si corresponding to data "1" and a second state Si+1 corresponding to data "0," a second voltage V2 having a predetermined level lower than the first voltage V1, and a third voltage V3 having a predetermined level higher than the first voltage V1. In some example embodiments, the data 710 read using the first voltage V1 having the reference level may be hard decision data 710 read through a hard decision read operation, and the 2-bit soft decision read operation may use the hard decision data 710 read through the hard decision read operation without applying the first voltage V1 having the reference level. By performing a predetermined logical operation (e.g., an XNOR operation 730) (or encoding) on ​​the data read using the second voltage V2 and the data read using the third voltage V3, a 2-bit soft decision read operation can generate soft decision data 720 having reliability information of the hard decision data 710. Each bit of the soft decision data 720 can represent the reliability level of the corresponding bit of the hard decision data 710. For example, a bit with a value of "1" in the soft decision data 720 can indicate that the corresponding bit of the hard decision data 710 has a first reliability, and a bit with a value of "0" in the soft decision data 720 can indicate that the corresponding bit of the hard decision data 710 has a second reliability. In an example embodiment, the first reliability can indicate "more reliable" than the second reliability. In other words, the hard decision data 710 with the first reliability can be relatively more reliable than the hard decision data 710 with the second reliability.

[0148] In other examples, such as Figure 31As shown, the nonvolatile memory device can perform a 3-bit soft decision read operation. The 3-bit soft decision read operation may include seven read operations using seven voltages V1, V2, V3, V4, V5, V6, and V7 at regular intervals. For example, the seven voltages V1, V2, V3, V4, V5, V6, and V7 may include the three voltages V1, V2, and V3 used in the 2-bit soft decision read operation, and may further include a fourth voltage V4 lower than the second voltage V2, a fifth voltage V5 between the second voltage V2 and the first voltage V1, a sixth voltage V6 between the first voltage V1 and the third voltage V3, and a seventh voltage V7 higher than the third voltage V3. In some example embodiments, the data 710 read using the first voltage V1 may be hard decision data 710 read using a hard decision read operation. The data 720 read using the second and third voltages V2 and V3 may be the most significant bit (MSB) soft decision data 720 corresponding to the soft decision data 720 read using the 2-bit soft decision read operation. By performing a predetermined logic operation (e.g., an XNOR operation 750) (or encoding) on ​​the data read using the fourth voltage V4, the fifth voltage V5, the sixth voltage V6, and the seventh voltage V7, a 3-bit soft decision read operation can generate least significant bit (LSB) soft decision data 740. Each of the two-bit soft decision data 720 and 740 can represent the reliability of the corresponding bit of the hard decision data 710. For example, each of the soft decision data 720 and 740 with a value of "11" can represent that the corresponding bit of the hard decision data 710 has a first reliability, each of the soft decision data 720 and 740 with a value of "10" can represent that the corresponding bit of the hard decision data 710 has a second reliability, each of the soft decision data 720 and 740 with a value of "00" can represent that the corresponding bit of the hard decision data 710 has a third reliability, and each of the soft decision data 720 and 740 with a value of "01" can represent that the corresponding bit of the hard decision data 710 has a fourth reliability. In an exemplary embodiment, the first reliability, the second reliability, the third reliability, and the fourth reliability can be increasingly unreliable in the order listed.

[0149] Figure 32 is a diagram illustrating an example embodiment of a unit characteristic table of a stream manager included in a nonvolatile memory device according to example embodiments.

[0150] refer to Figure 32 The cell characteristic table CCT may include mapping information between a physical address PHYADD of a nonvolatile memory device and a degradation characteristic MCLC of a memory cell. The physical address PHYADD may be an address of a memory block corresponding to a unit of an erase operation, or an address of a page corresponding to a unit of a write operation and a read operation.

[0151] The stream manager STMNG may monitor the degradation characteristic MCLC for each of the physical addresses PA1 and PA2 and determine the above-mentioned stream operating conditions corresponding to the stream identifiers, respectively, based on the degradation characteristics CCH1 and CCH2. In some example embodiments, the degradation characteristics CCH1 and CCH2 may be the number of program-erase (PE) cycles of the corresponding physical addresses PA1 and PA2.

[0152] Figure 33 is a diagram for describing program operation conditions according to example embodiments, and Figure 34 is a diagram for describing erase operation conditions according to example embodiments.

[0153] The aforementioned operating conditions may include program operating conditions and / or erase operating conditions.

[0154] refer to Figure 33 The threshold voltage distribution or state of the memory cells may be changed according to different programming operation conditions. The different programming operation conditions may include different programming voltages, different program verification voltages, or different programming times.

[0155] exist Figure 33 In the embodiment, the first case CS1 corresponds to a stream identifier having a first degree of degradation in an operating environment (such as data retention characteristics, read disturbance characteristics, program-erase cycles, etc.), and the second case CS2 corresponds to a stream identifier having a second degree of degradation (less than the first degree of degradation). When the degradation is relatively large, a larger interval of program verification voltages VPV11-VPV14 can be used to program states S11-S14 having a larger read margin. Conversely, when the degradation is relatively small, a smaller interval of program verification voltages VPV21-VPV24 can be used to program states S21-S24 having a smaller read margin.

[0156] refer to Figure 34 The threshold voltage distribution or state of the memory cells may be changed according to different erase operation conditions. The different erase operation conditions may include different erase voltages, different erase verification voltages, or different erase times.

[0157] exist Figure 34 In the embodiment of the present invention, the first case CS1 corresponds to a relatively less degraded stream identifier of an operating environment (such as data retention characteristics, read disturbance characteristics, program-erase cycles, etc.). The second case CS2 corresponds to a relatively more degraded stream identifier. When the degradation is relatively small, a higher erase verify voltage VERS1 can be used to implement an erase state of a relatively high threshold voltage distribution. Conversely, when the degradation is relatively large, a lower erase verify voltage VERS2 can be used to implement an erase state of a relatively low threshold voltage distribution.

[0158] As described above, a storage device supporting multi-stream and a method of controlling operation of a nonvolatile memory device according to example embodiments may improve performance of a nonvolatile memory device and a storage device including the nonvolatile memory device by setting streaming operation conditions suitable for streaming data characteristics.

[0159] The concepts of the present invention can be applied to any electronic device and system that supports multi-streaming. For example, the concepts of the present invention can be applied to devices such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), universal flash storage (UFS), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptops, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0160] The foregoing illustrates example embodiments and should not be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the inventive concept.

Claims

1. A method of controlling an operation of a non-volatile memory device, the method comprising: Receive multiple commands and multiple data streams, where Each command in the plurality of commands has a corresponding one of a plurality of flow identifiers, and each data flow in the plurality of data flows is assigned to a corresponding one of the plurality of flow identifiers; monitoring the plurality of data streams using control circuitry, the control circuitry tracking each data stream in the plurality of data streams and associating a single corresponding one of a plurality of stream data characteristics with each data stream in the plurality of data streams such that each data stream in the plurality of data streams is associated with a single one of the plurality of stream data characteristics; accessing, by the control circuit, a flow control table comprising a plurality of entries, each entry comprising a corresponding one of the plurality of flow identifiers, a corresponding one of the plurality of flow data characteristics, and a corresponding one of a plurality of operating conditions, to determine, by the control circuit, a corresponding one of the plurality of operating conditions as a flow operating condition for each of the plurality of data flows, wherein the plurality of operating conditions are respectively determined based on the plurality of operating environments; as well as writing first data of each of the plurality of data streams to the nonvolatile memory device or reading second data of each of the plurality of data streams from the nonvolatile memory device using a corresponding one of the operation conditions according to types of the plurality of commands, wherein the types of the plurality of commands include write commands or read commands, wherein data of each of the plurality of data streams associated with the same stream identifier is written to a first identical memory block of the nonvolatile memory device or is read from a second identical memory block of the nonvolatile memory device, and Wherein the same flow identifier is stored in the control circuit.

2. The method according to claim 1, wherein Described monitoring described multiple data streams comprises: A data retention characteristic of each of the plurality of data streams or a read disturb characteristic of each of the plurality of data streams is monitored.

3. The method according to claim 2, further comprising: monitoring a data retention characteristic of each of the plurality of data streams, The data retention characteristic of each data stream among the multiple data streams corresponds to a programming-reading interval time between a programming time point when data of a corresponding data stream among the multiple data streams is written to the non-volatile memory device and a reading time point when data of the corresponding data stream is read from the non-volatile memory device.

4. The method according to claim 2, further comprising: monitoring a data retention characteristic of each of the plurality of data streams, Wherein, monitoring the data retention characteristic of each data stream in the plurality of data streams comprises: A number of memory cells in a hold weak state among a plurality of memory cells of the nonvolatile memory device is monitored.

5. The method according to claim 2, further comprising: monitoring a data retention characteristic of each of the plurality of data streams, Wherein, monitoring the read disturbance characteristic includes: monitoring a read count for each of the plurality of data streams, and The read count of each of the plurality of data streams indicates the number of times the data corresponding to each of the plurality of data streams has been read since the data was written into the nonvolatile memory device.

6. The method according to claim 2, in, Monitoring a read disturb characteristic of each of the plurality of data streams, wherein monitoring the read disturb characteristic comprises: A number of memory cells in a read disturb weak state among a plurality of memory cells of the nonvolatile memory device is monitored.

7. The method according to claim 1, wherein Described monitoring described multiple data streams comprises: The stream data characteristics of each of the plurality of data streams are determined based on access information included in a command associated with a corresponding one of the plurality of data streams.

8. The method according to claim 1, wherein Determining the plurality of operating conditions comprises: A plurality of read sequences respectively corresponding to different combinations of a plurality of read operations having different sets of read voltages or different read times are determined.

9. The method according to claim 8, wherein Described monitoring described multiple data streams comprises: monitoring the plurality of data flows to determine a data retention characteristic of each of the plurality of data flows as its flow data characteristic, and Wherein, determining one of the multiple operating conditions as the stream operating condition of each of the multiple data streams includes: A retention read sequence is selected as the flow operation condition among the plurality of read sequences, wherein in the retention read sequence, in response to the data retention characteristic being determined to be degraded, a read operation having a read voltage set is first performed.

10. The method according to claim 8, wherein Described monitoring described multiple data streams comprises: monitoring the plurality of data streams to determine a read disturb characteristic of each of the plurality of data streams as its stream data characteristic, and Wherein, determining one of the multiple operating conditions as the stream operating condition of each of the multiple data streams includes: A disturb read sequence is selected as the flow operation condition among the plurality of read sequences, wherein in the disturb read sequence, in response to the read disturb characteristic being determined to be degraded, a read operation having a read voltage set is first performed.

11. The method according to claim 8, wherein Described monitoring described multiple data streams comprises: monitoring the plurality of data streams to determine, for each of the plurality of data streams, a plurality of average read latencies corresponding to the plurality of read sequences, respectively; and Wherein, determining one of the multiple operating conditions as the stream operating condition of each of the multiple data streams includes: A main read sequence is selected as the stream operation condition among the plurality of read sequences, the main read sequence corresponding to a read sequence having a minimum average read latency among the plurality of average read latency times.

12. The method according to claim 8, wherein The plurality of read sequences include a first read sequence and a second read sequence, The first read sequence includes a first read operation with a first read time, and the first read operation is performed first in the first read sequence. The second read sequence includes a second read operation having a second read time longer than the first read time, and the second read operation is performed first in the second read sequence.

13. The method according to claim 12, wherein: Each of the first read operation and the second read operation is a hard decision read operation.

14. The method according to claim 12, wherein: The first read operation is a hard decision read operation, and the second read operation is a soft decision read operation.

15. The method of claim 1, further comprising: monitoring degradation characteristics of memory cells of each of a plurality of memory blocks or each of a plurality of pages in the nonvolatile memory device, each of the memory blocks corresponding to a unit of erase operation and each of the pages corresponding to a unit of write operation or read operation; in, Determining one of the plurality of operating conditions as a stream operating condition for each of the plurality of data streams comprises: The stream operating condition is determined based on the degradation characteristic of the memory cell.

16. The method according to claim 1, wherein Determining one of the plurality of operating conditions as a stream operating condition for each of the plurality of data streams comprises at least one of: determining a plurality of program operation conditions having different program voltages, different program verification voltages, or different program times; and A plurality of erase operation conditions having different erase voltages, different erase verify voltages, or different erase times are determined.

17. The method according to claim 1, wherein Described monitoring described multiple data streams comprises: A difference between a programming temperature when data of each of the plurality of data streams is written to the nonvolatile memory device and a read temperature when the data is read from the nonvolatile memory device is monitored.

18. A method of controlling operation of a nonvolatile memory device that exchanges a plurality of data streams with a memory controller, each of the plurality of data streams being identified by a corresponding one of a plurality of stream identifiers, the method comprising: At least one of a data retention characteristic from a plurality of data retention characteristics and a read disturb characteristic from a plurality of read disturb characteristics for each of the plurality of data streams is determined using control circuitry of a nonvolatile memory device, the control circuitry of the nonvolatile memory device monitoring at least one of the following to determine the data retention characteristic from the plurality of data retention characteristics: a program-read interval time between a programming time point when data of a corresponding data stream among the plurality of data streams is written to the nonvolatile memory device and a reading time point when data of the corresponding data stream among the plurality of data streams is read from the nonvolatile memory device; and a number of memory cells in a weak hold state among a plurality of memory cells of the nonvolatile memory device, and To determine a read disturb characteristic from the plurality of read disturb characteristics, at least one of the following is monitored: a read count indicating the number of times the data has been read since the data was written to the nonvolatile memory device; and the number of memory cells in a read disturb weak state among a plurality of memory cells of the nonvolatile memory device, accessing, by the control circuit, a flow control table including a plurality of entries, each entry including a corresponding one of the plurality of flow identifiers, at least one of a data retention characteristic and a read disturb characteristic of each of the plurality of data flows, and a corresponding read sequence of a plurality of read sequences, to determine at least one of a retention read sequence and a disturb read sequence among the plurality of read sequences as a flow operation condition for each of the plurality of data flows, in, The multiple reading sequences are determined based on multiple operating environments respectively, wherein each of the plurality of read sequences is formed by a plurality of read operations that are different from one another in terms of a read voltage set or a read time, and has a different combination of the plurality of read operations, In the retention read sequence, a first read operation is performed at the beginning of the retention read sequence, wherein the first read operation has a read voltage set for the data retention characteristic when the data retention characteristic is determined to be degraded in determining the data retention characteristics among the plurality of data retention characteristics, and In the interference read sequence, a second read operation is performed at the beginning of the interference read sequence, wherein the second read operation has a second read voltage set for the read interference characteristic when the read interference characteristic is determined to be degraded in determining the read interference characteristics among the plurality of read interference characteristics.

19. The method according to claim 18, further comprising: monitoring degradation characteristics of memory cells of the nonvolatile memory device for each of a plurality of memory blocks or each of a plurality of pages, each of the plurality of memory blocks corresponding to a unit of erase operation and each of the plurality of pages corresponding to a unit of write operation or a unit of read operation; and An operating condition of at least one of the retention read sequence and the disturbance read sequence in the plurality of read sequences is determined based on the degradation characteristics of the memory cell with respect to each memory block in the plurality of memory blocks or each page in the plurality of pages.

20. A storage system for processing multiple data streams, the storage system comprising: A nonvolatile memory device includes: a memory cell array in which a plurality of nonvolatile memory cells are arranged; and Controller, including flow control table, in, The flow control table includes a plurality of entries, each entry including a corresponding one of a plurality of flow identifiers, a corresponding one of a plurality of flow data characteristics, and a corresponding one of a plurality of operation conditions, and Wherein, the controller is configured as follows: issuing a plurality of commands and a plurality of data streams, wherein each command of the plurality of commands has a corresponding one of the plurality of stream identifiers and each data stream of the plurality of data streams is assigned to a corresponding one of the plurality of stream identifiers; tracking each data stream of the plurality of data streams and associating a single corresponding stream data characteristic of a plurality of stream data characteristics with each data stream of the plurality of data streams; accessing the flow control table to determine a corresponding one of the plurality of operating conditions as a flow operating condition for each of the plurality of data flows; and writing data of each of the plurality of data streams to the nonvolatile memory device using the determined corresponding one of the operating conditions, wherein data of each data stream associated with the same stream identifier in the plurality of data streams is written to the same storage block of the non-volatile memory device, and The same flow identifier is stored in the controller.

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