Semiconductor device and method for manufacturing semiconductor device

Abstract

Embodiments of the present disclosure relate to a semiconductor device having an insulated gate field effect transistor and a manufacturing method of the semiconductor device. In a cell region EFR defined in a first region on one main surface side of a semiconductor substrate (SUB), an insulated gate type field effect transistor (MFET) is formed; in a gate pad region GPR defined in the first region, a buffer region SNR forming a buffer circuit SNC is defined. In the first region and a second region, a first deep trench and a second deep trench are formed spaced apart from each other, and at least one width of a plurality of second deep trenches formed in the second region is smaller than a width of a first deep trench formed in the second region.

Description

[0001] Cross-references to related applications

[0002] Japanese Patent Application No. 2019-113133, filed on June 18, 2019, including the specification, drawings and abstract, the disclosure of which is incorporated herein by reference in its entirety. Background Technology

[0003] This invention relates to semiconductor devices and methods for manufacturing semiconductor devices, and is applicable to semiconductor devices, for example, those having trench gate power MOSFETs.

[0004] Insulated-gate field-effect transistors (such as trench-gate power MOSFETs (metal-oxide-semiconductor field-effect transistors)) are known as power switching semiconductor devices.

[0005] In this type of semiconductor device, when the parasitic diode of the insulated-gate field-effect transistor (IGFET) is restored, the parasitic inductance of the circuitry within the semiconductor device can cause a surge voltage between the source and drain electrodes. Additionally, when the IGFET operates from on to off, the parasitic inductance generates a surge voltage between the source and drain electrodes. This surge voltage can lead to breakdown of the IGFET or other semiconductor devices.

[0006] To reduce such surge voltages, a buffer circuit is incorporated into the semiconductor device. The buffer circuit consists of a resistor and a capacitor connected in series. The series-connected resistor and capacitor are electrically connected between the drain and source electrodes of the trench-gate power MOSFET.

[0007] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2017-143188

[0008] Patent document 1 discloses a semiconductor device with a buffer circuit having a resistor and a capacitor formed in a designated buffer region of a semiconductor substrate. Summary of the Invention

[0009] The purpose of these embodiments is to improve the reliability of semiconductor devices with insulated gate field-effect transistors.

[0010] Other objects and novel features will become apparent from the description and drawings of the invention.

[0011] The semiconductor device according to an embodiment includes a semiconductor substrate; an insulated-gate field-effect transistor formed in a first region of the semiconductor substrate; and a buffer circuit formed in a second region different from the first region, the buffer circuit having a resistor and a capacitor. In a plan view of the first main surface side of the first region, the semiconductor device has a plurality of first deep trenches arranged in an island-like pattern spaced apart from each other. In a plan view of the first main surface side of the second region, the semiconductor device has a plurality of second deep trenches arranged in an island-like pattern spaced apart from each other. Here, in the plan view of the first main surface side of the first region, the width of at least one of the plurality of second deep trenches is smaller than the width of at least one of the plurality of first deep trenches.

[0012] A method for manufacturing a semiconductor device according to an embodiment includes the following steps: preparing a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; forming an insulated-gate field-effect transistor in a first region of the semiconductor substrate and forming a buffer circuit having a resistor and a capacitor in a second region different from the first region; forming a plurality of first deep trenches arranged in an island-like spaced-apart arrangement; and forming a plurality of second deep trenches arranged in an island-like spaced-apart arrangement from the first main surface toward the substrate in the second region in the first region. Here, at least one width of the plurality of second deep trenches arranged in an island-like spaced-apart arrangement from the first main surface toward the substrate in the first region is smaller than the width of the plurality of first deep trenches.

[0013] The semiconductor device according to the embodiment can improve the reliability of the semiconductor device having an insulated gate field-effect transistor.

[0014] A method for manufacturing a semiconductor device according to another embodiment can improve the reliability of a semiconductor device having an insulated gate field-effect transistor. Attached Figure Description

[0015] Figure 1 This is a plan view showing a planar pattern of the semiconductor device according to the tip state in the first embodiment.

[0016] Figure 2 This is an equivalent schematic diagram of the insulated gate field-effect transistor and the buffer circuit according to the first embodiment.

[0017] Figure 3 This illustrates the first embodiment. Figure 1 A plan view of the plane in frame A1 shown.

[0018] Figure 4 This illustrates the first embodiment. Figure 1 An inclined cross-sectional view of the structure in frame A1 shown.

[0019] Figure 5 According to the first embodiment, along Figure 3 The cross-sectional view of the transverse section VV shown.

[0020] Figure 6 This is an oblique cross-sectional view showing the structure of a comparative example of a semiconductor device.

[0021] Figure 7 This is a cross-sectional view showing the manufacturing steps of a semiconductor device according to a first embodiment.

[0022] Figure 8 This illustrates the first embodiment. Figure 7 A cross-sectional view of the step to be performed after the step shown.

[0023] Figure 9 This illustrates the first embodiment. Figure 8 A cross-sectional view of the step to be performed after the step shown.

[0024] Figure 10 This illustrates the first embodiment. Figure 9 A cross-sectional view of the steps performed after the steps shown.

[0025] Figure 11 This illustrates the first embodiment. Figure 10 A cross-sectional view of the steps performed after the steps shown.

[0026] Figure 12 This illustrates the first embodiment. Figure 11 A cross-sectional view of the steps performed after the steps shown.

[0027] Figure 13 This illustrates the first embodiment. Figure 12 A cross-sectional view of the steps performed after the steps shown.

[0028] Figure 14 This illustrates the first embodiment. Figure 13 A cross-sectional view of the steps performed after the steps shown.

[0029] Figure 15 It is shown that, according to the first embodiment, the following is required: Figure 14 A cross-sectional view of the steps performed after the steps shown.

[0030] Figure 16 This is a first equivalent circuit diagram used to illustrate the function of the buffer unit according to the first embodiment.

[0031] Figure 17This is a second equivalent circuit diagram used to illustrate the function of the buffer unit according to the first embodiment.

[0032] Figure 18 It is shown that according to the second embodiment Figure 1 An inclined cross-sectional view of the corresponding part of the structure in frame A1 shown.

[0033] Figure 19 It is shown that according to the third embodiment Figure 1 An inclined cross-sectional view of the corresponding part of the structure in frame A1 shown. Detailed Implementation

[0034] The semiconductor device according to the embodiments will be described in detail below with reference to the accompanying drawings. In the specification and drawings, elements of the same or corresponding forms are indicated by the same reference numerals, and repeated descriptions thereof are omitted. In the drawings, configurations may be omitted or simplified for ease of description. Furthermore, at least some embodiments and each modification can be arbitrarily combined with each other.

[0035] (First Embodiment)

[0036] The semiconductor device of the first embodiment is described below with reference to the accompanying drawings.

[0037] Figure 1 A plan view of a semiconductor device according to this embodiment is shown. Figure 1 In a semiconductor device PSD (semiconductor chip), it has a first main surface and a corresponding second main surface. Figure 1 This is a plan view taken from the first main surface side. On the first main surface side of the semiconductor substrate SUB, for example along the edge side of the semiconductor device PSD (semiconductor chip), a gate pad region GPR and a diode pad region DPR are defined. A buffer region SNR is formed in the gate pad region GPR. Further, for example, in the semiconductor device PSD (semiconductor chip) outside the gate pad region GPR and the diode pad region DPR, a cell region EFR is defined to form an insulated gate field-effect transistor (MFET) of the semiconductor device PSD (semiconductor chip).

[0038] Within the gate pad region (GPR), a gate pad (GEP) is formed. The gate pad (GEP) is electrically connected to the gate electrode (MFET) of the insulated gate field-effect transistor (IGFET). The gate pad (GEP) is used for electrical connection to external components.

[0039] In the diode pad region DPR, a diode pad DOP is formed. For example, a temperature sensing diode (not shown) is formed in the diode pad region DPR as an element for detecting the temperature of a semiconductor device. Diode pad DOP1 is electrically connected to the anode of the temperature sensing diode. Similarly, diode pad DOP2 is electrically connected to the cathode of the temperature sensing diode. The diode pad DOP, which includes diode pad DOP1 and diode pad DOP2, is used for external electrical connections.

[0040] The source electrode SEL is formed as a cover cell region EFR. The source electrode SEL is electrically connected to the source of an insulated gate field-effect transistor (MFET). A passivation film (not shown) is formed to cover the source electrode SEL, etc. The passivation film has, for example, an opening that exposes the source electrode SEL. The exposed source electrode SEL is used as a source pad SEP for electrical connection to the outside.

[0041] Next, the equivalent circuits of the buffer circuit and the insulated-gate field-effect transistor will be described. For example... Figure 2 As shown, the buffer circuit SNC is electrically connected in parallel between the source S and drain D of the insulated-gate field-effect transistor MFET. The insulated-gate field-effect transistor MFET has capacitors CDS, CGD, and CGS as parasitic capacitors, as well as a diode PD1 as a parasitic diode.

[0042] Capacitor CDS is the parasitic capacitor between the drain (D) and source (S). Capacitor CGD is the parasitic capacitor between the gate (G) and drain (D). Capacitor CGS is the parasitic capacitor between the gate (G) and source (S). Diode PD1 is the parasitic diode between the source (S) and drain (D). Resistor RG is the resistance of the gate (G).

[0043] The buffer circuit SNC includes resistor RSNB, capacitor CDS2, capacitor CGD2, and capacitor CGS2. The buffer circuit SNC is formed by a second embedded insulator ZOF2 and a trench gate electrode TGEL disposed below the gate pad GEP. CDS2 is a parasitic capacitor between the drain D and the source S. Capacitor CGD2 is a parasitic capacitor between the gate G and the drain D. Capacitor CGS2 is a parasitic capacitor between the gate G and the drain D. Diode PD2 is a parasitic diode between the source S and the drain D.

[0044] Next, refer to Figures 3 to 5 Describe the structure surrounding the buffer circuit SNC and the buffer circuit SNC itself. (For...) Figure 1 The structure within the dashed square box A1 shown, Figure 3 An example of a planar pattern is shown. Figure 4 An example is shown in a cross-sectional perspective view. Figure 5An example is shown in a cross-sectional view.

[0045] like Figures 3 to 5 As shown, a buffer region SNR and a cell region EFR are defined on one side of a main surface (first main surface) of the semiconductor substrate SUB. The buffer region SNR is defined in the gate pad region GPR. Figure 4 As shown, in the buffer region SNR, the p-type diffused layer PDL is configured as a resistive element. Additionally, the p-type diffused layer PDL and the n-type pillar layer NCL are configured as capacitive elements. Furthermore, in Figure 4 and Figure 5 In this configuration, an n-type substrate NPSB (n-type epitaxial layer NEL) is disposed on one side of another main surface (second main surface) of the semiconductor substrate SUB. The n-type substrate NPSB is electrically connected to the drain electrode (not shown).

[0046] In the cell region EFR, a substrate diffusion layer BDL is formed at a predetermined depth from a main surface of the semiconductor substrate SUB. An insulated gate field-effect transistor (IGFET) channel is formed in the substrate diffusion layer BDL. From the bottom of the substrate diffusion layer BDL to a predetermined depth, an n-type pillar layer NCL is formed, contacting the n-type NPSB.

[0047] A trench gate electrode (TGEL) is formed, extending from a main surface of the semiconductor substrate (SUB) through the substrate diffusion layer (BDL) to the n-type pillar layer (NCL). The trench gate electrode (TGEL) is formed in the gate trench (TRC) by inserting a gate insulating film (GIF). The trench gate electrode (TGEL) is arranged in a mesh shape.

[0048] In the substrate diffusion layer BDL, an n-type source diffusion layer SDL is formed above a region extending from a main surface of the semiconductor substrate SUB to a depth shallower than the bottom of the substrate diffusion layer BDL. The source diffusion layer SDL is formed by inserting a gate insulating film GIF on one side of the trench gate electrode TGEL. Multiple buried insulators ZOF are formed from a main surface of the semiconductor substrate SUB toward the n-type substrate NPSB. The cell region EFR is a first region, forming a first embedded insulator ZOF1, and the buffer region SNR is a second region, forming a second insulator ZOF2. The first buried insulator ZOF1 is formed in a first deep trench DTC1, and the second insulator ZOF2 is formed in a second deep trench DTC2.

[0049] The first deep trench DTC1 and the second deep trench DTC2 are arranged, for example, in an island-like configuration, spaced a certain distance apart from each other. The first deep trench DTC1 is formed in the region surrounded by the trench gate electrode TGEL, which is arranged in a mesh shape in a plan view. Additionally, as... Figure 4 As shown, the first deep trench DTC1 is formed to contact the p-type columnar layer PCL and the p+ diffusion layer DCC.

[0050] A second deep trench, DTC2, is formed along the trench gate electrode TGEL, which extends in the Y-axis direction in a plan view in the form of spaced-apart strips. A second embedded insulator, ZOF2, is formed to contact the p-type pillar layer PCL. Note that in the plan view, the Y-axis direction is along the longitudinal direction of the trench gate electrode TGEL formed in the buffer region SNR. In the plan view, the X-axis direction is along the shorter direction of the trench gate electrode TGEL formed in the buffer region SNR. In the plan view, the X-axis and Y-axis are orthogonal to each other.

[0051] Furthermore, in a plan view, at least one width of the plurality of second deep trenches DTC2 is smaller than at least one width of the plurality of first deep trenches DTC1. Additionally, at least one depth of the first deep trenches DTC1 in the substrate direction is shallower than at least one depth of the second deep trenches DTC2.

[0052] For example, in a plan view, the opening size of the second deep trench DTC2 is smaller than the opening size of the first deep trench DTC1. For example, in a plan view, the width (opening width) of the first deep trench DTC1 is 0.7 micrometers or greater than 0.7 micrometers, and the width of the second deep trench DTC2 is 0.5 micrometers or greater than 0.5 micrometers and less than 0.7 micrometers. Additionally, for example, the depth of the first deep trench DTC1 in the substrate direction is 8 micrometers or greater than 8 micrometers, and the depth of the second deep trench DTC2 in the substrate direction is 6 micrometers or greater than 6 micrometers and less than 8 micrometers. Here, in a plan view, among the multiple sides constituting the opening, the opening width is the maximum value of the distance between the two opposite sides. The depth is the maximum distance in the thickness direction between the bottom surface of the deep trench DTC and the upper surface of the embedded insulator ZOF embedded in the deep trench DTC.

[0053] The p-type column layer (PCL) is also in contact with the n-type column layer (NCL). The p-type column layer (PCL) and the n-type column layer (NCL) are arranged alternately as a hyperconnection structure.

[0054] The p+ diffusion layer DCC is formed to contact the buried insulator ZOF, but the substrate diffusion layer BDL is formed to contact the n-type pillar layer NCL. The p+ diffusion layer DCC is formed in the cell region EFR to increase the inductive load tolerance of the cell region EFR.

[0055] The parasitic capacitor CDS is formed by the source diffusion layer SDL and the n-type pillar layer NCL. The parasitic capacitor CGD is formed by the trench gate electrode TGEL and the n-type pillar layer NCL. The parasitic diode PD1 is formed by the trench gate electrode TGEL and the source diffusion layer SDL.

[0056] In the buffer region SNR, a p-type diffusion layer PDL is formed at a predetermined depth from one of the main surfaces of the semiconductor substrate SUB. An n-type pillar layer NCL is formed, extending from the bottom of the p-type diffusion layer PDL to the n-type epitaxial layer NEL at a predetermined depth.

[0057] A trench gate electrode (TGEL) is formed, extending from a main surface of the semiconductor substrate (SUB), through the p-type diffusion layer (PDL), to the n-type pillar layer (NCL). The trench gate electrode (TGEL) is formed by inserting a gate insulating film (GIF) into the gate trench (TRC). In the buffer region (SNR), the trench gate electrode (TGEL) is formed in a stripe pattern spaced apart along the Y-axis. Conversely, in the cell region (EFR), the trench gate electrode (TGEL) extends along the Y-axis and is formed in a mesh shape spaced apart from each other along the X-axis, which intersects the Y-axis.

[0058] A resistor RSNB forms a buffer region SNC through a p-type diffused layer PDL located between two trench gate electrodes TGEL and TGEL. For example, the resistor RSNB extends in the Y-axis direction. At the end of the resistor RSNB on the EFR side of the cell region, a contact CTS electrically connected to the source electrode SEL (source S) is provided. For example, the resistance of the resistor RSNB can be adjusted by the length of the p-type diffused layer PDL from the contact CTS to the contact CTS.

[0059] The n-type pillar layer NCL is placed below the p-type diffused layer PDL for bonding. The parasitic capacitor CDS is formed by the p-type diffused layer PDL and the n-type pillar layer NCL. The capacitance of the parasitic capacitor CDS2 depends on the reverse bias (voltage) applied to the drain. Additionally, for example, by changing the dimensions (lengths in the X and Y directions) of the p-type diffused layer PDL (p-type pillar layer PCL), the junction region between the p-type diffused layer PDL (p-type pillar layer PCL) and the n-type pillar layer NCL can be altered to adjust the capacitance of the parasitic capacitor CDS2. As described later, the resistance value of the parasitic resistor RSNB and the capacitance of the capacitor CDS2 become key parameters for reducing surge voltage.

[0060] In the region between the trench gate electrode TGEL and another trench gate electrode TGEL, multiple buried insulators (ZOFs) are arranged in an island-like configuration with a distance between them in the Y-axis direction. Multiple buried insulators (ZOFs) are formed in the deep trench DTC, extending from a main surface of the semiconductor substrate SUB through the p-type diffusion layer PDL and the n-type pillar layer NCL to the n-type epitaxial layer NEL. The p-type pillar layer PCL is formed to contact the buried insulators (ZOFs), the n-type pillar layer NCL, and the p+ type diffusion layer DCC, respectively.

[0061] Parasitic capacitor CGD2 is formed by a trench gate electrode TGEL and an n-type pillar layer NCL. Parasitic capacitor CGS2 is formed by a trench gate electrode TGEL and a p-type diffusion layer PDL. The p-type diffusion layer PDL of the buffer region SNR and the base diffusion layer BDL of the cell region FER are, for example, separated by a trench gate electrode TGEL extending in the X-axis direction.

[0062] A protective insulating film (TPF) is formed on the main surface of the semiconductor substrate (SUB) to cover the cell region FER and the buffer region SNR, and an interlayer insulating film (ILF) is formed in contact with the upper part of the protective insulating film TPF. The source electrode (SEL) and the gate pad (GEP) are formed to cover the interlayer insulating film (ILF). The source electrode (SEL) is electrically connected to the source diffusion layer (SDL) and the substrate diffusion layer (BDL).

[0063] Additionally, the source electrode SEL is electrically connected to the p-type diffusion layer PDL via the contact CTS. A passivation film PVF is formed to cover the source electrode SEL and the gate pad GEP. The main components of the semiconductor device are constructed as described above.

[0064] Next, an example of the manufacturing method of the above-mentioned semiconductor device will be described. First, an n++ type substrate NPSB and a semiconductor substrate SUB having an n-type epitaxial layer NEL and a p-type epitaxial layer PEL are prepared (see...). Figure 7 ).

[0065] Next, a gate trench with a predetermined depth from the surface of the p-type epitaxial layer PEL (not shown) is formed on one main surface side of the semiconductor substrate SUB. Then, by performing a thermal oxidation process, a silicon oxide film (not shown) is formed on the surface of a portion of the p-type epitaxial layer PEL, including the p-type epitaxial layer PEL exposed in the gate trench. A polysilicon film (not shown) is then formed to fill the gate trench TRC.

[0066] Then, portions of the silicon oxide film and the polysilicon film on the upper surface of the p-type epitaxial layer PEL are removed. Therefore, as... Figure 7 As shown, a portion of the silicon oxide film remaining in the gate trench TRC is formed as the gate insulating film GIF. Furthermore, a portion of the polysilicon film remaining in the gate trench TRC is formed as the trench gate electrode TGEL. At this time, in the buffer region SNR, the trench gate electrode TGEL is, for example, formed to extend in the Y-axis direction (see...). Figure 3 and Figure 4 ).

[0067] Next, a protective insulating film IPF is formed on the surface of the p-type epitaxial layer PEL by performing a thermal oxidation process (see [link to documentation]). Figure 8Next, by performing photolithography and etching processes, a first deep trench DTC1 is formed in the cell region EFR and a second deep trench DTC2 is formed in the buffer region SNR (see reference). Figure 8 The first deep trench DTC1 and the second deep trench DTC2 are formed in an island-like configuration, spaced apart from each other. In a plan view, at least one width of the second deep trench DTC2 is smaller than at least one width of the first deep trench DTC1. Furthermore, at least one depth of the second deep trench DTC1 in the substrate direction is shallower than at least one depth of the deep trench DTC1.

[0068] Next, as Figure 8 As shown, n-type impurities are injected obliquely through the protective insulating film IPF and the deep trench DTC. Then, by performing heat treatment, an n-type pillar layer NCL is formed in each of the cell region EFR and the buffer region SNR. Next, as... Figure 9 As shown, p-type impurities are injected via a protective insulating film (IPF) and a deep trench (DTC). Then, by performing a heat treatment, a p-type pillar layer (PCL) is formed along the sidewall surface of the deep trench (DTC) in each of the cell region (EFR) and the buffer region (SNR). The p-type pillar layer (PCL) will contact the n-type pillar layer (NCL).

[0069] Then, a silicon oxide film (not shown) is formed, for example, as an embedded deep trench DTC. Next, a portion of the silicon oxide film on the upper surface of the semiconductor substrate SUB is removed by, for example, chemical mechanical polishing, leaving a portion of the silicon oxide film located in the deep trench DTC. Therefore, as... Figure 10 As shown, a first embedded insulator ZOF1 is formed in the cell region EFR, and a second embedded insulator ZOF2 is formed in the buffer region SNR. The second embedded insulator ZOF2 is formed in an island-like form spaced apart from each other in the Y-axis direction (see [reference]). Figure 3 and Figure 4 In a plan view, at least one width of the second buried insulator ZOF2 is smaller than at least one width of the first buried insulator ZOF1. Additionally, at least one depth of the second buried insulator ZOF2 in the substrate direction is shallower than at least one depth of the first buried insulator ZOF1.

[0070] Next, for example, through thermal oxidation, a protective insulating film TPF is formed by oxidizing the surface of the semiconductor substrate SUB (see...). Figure 11 Next, a photoresist pattern (not shown) is formed by performing a photolithography process to expose the regions in which the substrate diffusion layer and the p-type diffusion layer are formed. Using the photoresist pattern as an implantation mask, p-type impurities are implanted through a protective insulating film (TPF). Subsequently, the photoresist pattern is removed.

[0071] Therefore, as Figure 11 As shown, a p-type substrate diffusion layer BDL is formed in the cell region EFR. A p-type diffusion layer PDL is formed in the buffer region SNR. The substrate diffusion layer BDL and the p-type diffusion layer PDL are formed at a location shallower than the location where the trench gate electrode TGEL is formed, extending from the surface of the semiconductor substrate SUB. Therefore, in the buffer region SNR, the n-type pillar layer NCL and the p-type diffusion layer PDL (which are the resistor and capacitor of the buffer circuit SNC) are formed simultaneously with the n-type pillar layer NCL and the substrate diffusion layer BDL formed in the cell region EFR.

[0072] Next, as Figure 12 As shown, a photoresist pattern PR1 is formed by performing a photolithography process via a cover buffer region SNR (cell region EFR) to expose the region where the source diffusion layer is formed. Then, using the photoresist pattern PR1 as an implantation mask, n-type impurities are implanted through a protective insulating film TPF.

[0073] Therefore, a source diffusion layer SDL is formed in the cell region EFR. The source diffusion layer SDL is formed at a location shallower than the bottom of the substrate diffusion layer BDL, extending from the surface of the substrate diffusion layer BDL. Subsequently, the photoresist pattern PR1 is removed.

[0074] Next, as Figure 13 As shown, an interlayer insulating film (ILF) is formed to cover the semiconductor substrate (SUB) (protective insulating film (TPF)). Then, photolithography and etching processes are performed on the ILF, as shown... Figure 13 As shown, an opening CH1 is formed in the cell region EFR to expose the source diffusion layer SDL and the substrate diffusion layer BDL. Then, ion implantation is performed in the opening CH1 by using the interlayer insulating film ILF as a mask to form a p+ diffusion layer DCC near the boundary between the substrate diffusion layer BDL and the n-type pillar layer NCL. Incidentally, when the opening CH1 is formed, an opening CH2 is formed in the buffer region SNR to expose the p-type diffusion layer PDL.

[0075] Next, for example, an aluminum film (not shown) is formed to cover the interlayer insulating film (ILF) by sputtering or similar methods. After this, a predetermined photolithography and etching process is performed on the aluminum film. Therefore, as... Figure 14 As shown, the source electrode SEL is formed in the cell region EFR. The gate pad GEP is formed in the buffer region SNR (gate pad region GPR).

[0076] Next, as Figure 15As shown, a passivation film PVF is formed to cover the source electrode SEL and the gate pad GEP. Subsequently, multiple semiconductor devices are removed as chips by slicing the scribe lines (not shown). This completes the main part of the semiconductor device PSD.

[0077] In the aforementioned semiconductor device PSD, a buffer region SNR is defined and a buffer circuit SNC is provided in the region where an insulated gate field-effect transistor (MFET) is not located. The two functions of the buffer circuit SNC will now be described.

[0078] The primary function is to reduce the generated surge voltage through the SNC buffer circuit. For example... Figure 2 As shown, the insulated-gate field-effect transistor (MFET) initially has a parasitic capacitor CDS between the source (S) and drain (D). In the aforementioned semiconductor device PSD, in addition to the buffer circuit SNC (capacitor CDS2 and resistor RSNB), it is also electrically connected to its insulated-gate field-effect transistor MFET.

[0079] Therefore, as Figure 16 As shown, when the parasitic diode PD1 performs a recovery operation, a surge voltage (reverse bias) is generated. Since this surge voltage is absorbed as energy in the buffer section SNR, the surge voltage can be reduced (see the thick line in the equivalent circuit diagram). Therefore, damage to the insulated-gate field-effect transistor MFET or peripheral semiconductor devices (not shown) can be prevented.

[0080] Next, the second function is to reduce the surge voltage by self-conducting the insulated-gate field-effect transistor (MFET) using the generated surge voltage. Self-conduction is the phenomenon that a voltage (potential difference) is generated between the gate and source, and the gate is turned on by the parasitic capacitance ratio between the drain and source.

[0081] Next, as Figure 17 As shown, the voltage applied to the drain (point P1) is taken as voltage Vds. The voltage generated between the source S and capacitor CGS (point P2) is taken as voltage Vgs1. The voltage generated between the source S and resistor RSNB (point P3) is taken as voltage Vs2. The voltage generated between the source S, resistor RSNB, and capacitor CGS (point P4) is taken as voltage Vgs. Furthermore, the capacitance of capacitor CGS is taken as capacitance Cgs. The capacitance of capacitor CGD is taken as capacitance Cgd. The capacitance of capacitor CGD2 is taken as capacitance Cgd2. The capacitance of capacitor CGS2 is taken as capacitance CGS2.

[0082] The voltage Vgs1 is represented by the following equation 1.

[0083] Vgsl=Vds×(Cgd+Cgd2) / (Cgs+Cgs2+Cgd+Cgd2)-----(Equation 1)

[0084] The voltage Vgs2 is represented by the following equation 2.

[0085] Vgs2=Vs2×Cgs2 / (Cgs+Cgs2)-----(Equation 2)

[0086] The voltage Vgs is represented by the following equation 3.

[0087] Vgs=Vgs1+Vgs2-----(Equation 3)

[0088] Therefore, if the voltage Vgs is higher than the threshold voltage Vth of the insulated gate field-effect transistor (MFET) (Vgs≥Vth), then the insulated gate field-effect transistor (MFET) can be turned on by itself.

[0089] As described above, when the parasitic diode PD1 performs a recovery operation, a parasitic inductance (surge voltage) may appear between the source and drain. Here, when the insulated-gate boundary effect transistor (MFET) is turned off, for example, assuming a voltage of approximately 50 volts is applied to the drain D, in the case of a semiconductor device without a buffer region SNR (comparative example), the voltage can instantaneously rise to approximately 100 volts due to the parasitic inductance. Therefore, this surge voltage could potentially damage the insulated-gate boundary effect transistor.

[0090] For the comparative example, in the aforementioned semiconductor device PSD, by providing a buffer circuit SNC, a voltage Vgs2 (refer to Equation 2) can be further generated between the gate and source when a voltage is applied to the drain. Therefore, in the case of the comparative example of the semiconductor device, the voltage Vgs (refer to Equation 3) between the gate and source (point P5) is higher than the corresponding voltage between the gate and source, thereby easily enabling the self-conduction of the insulated gate boundary effect transistor (MFET).

[0091] By using a self-conducting insulated-gate boundary effect transistor (MFET), the voltage difference between the drain (D) and source (S) is eliminated, thus suppressing attempts to increase the voltage Vds.

[0092] The duration for which the voltage Vgs is applied can be controlled using the capacitance ratios shown in Equations 1 to 3. Therefore, the current flowing from the drain to the source can be limited by controlling the conduction, preventing excessive current flow. In other words, by controlling the current flowing from the drain to the source with the voltage Vgs, the increase in drain voltage can be suppressed.

[0093] In the aforementioned semiconductor device PSD, the buffer region SNR that forms the buffer circuit SNC is formed in the area where the insulated gate boundary effect transistor (MFET) is not formed, and this region is defined within the gate pad region GPR. The area of ​​the gate pad region GPR is approximately a few percent of the area of ​​the cell region EFR that forms the insulated gate boundary effect transistor (MFET).

[0094] Additionally, for example, by adjusting the length of the buffer region SNR extending in the Y-axis direction (see...). Figure 4 By employing methods such as [missing information], a snubber circuit SNC with optimal capacitor CDS2 and resistor RSNB can be formed to reduce surge voltage. Furthermore, this snubber circuit SNC can be formed simultaneously during the step of forming an insulated gate boundary effect transistor (MFET) in the cell region EFR without adding any additional steps, only by changing the mask pattern.

[0095] In the aforementioned semiconductor device PSD, the buffer region SNR defined in the gate pad region GPR is described as an example; as a region where an insulated gate type boundary effect transistor (MFET) is not formed, for example, in the buffer region SNR, it can be defined in the diode pad region DPR (see Figure 1 In the ), a diode is set as a temperature sensing element.

[0096] (Comparison Example)

[0097] Here, in order to illustrate the features of the first embodiment of the semiconductor device PSD, a semiconductor device cPSD according to a comparative example will be described. Figure 6 This is an example cross-sectional perspective view showing the configuration of a semiconductor device cPSD. In the plan view, the second deep trench DTC2 formed in the buffer region SNR of the semiconductor device cPSD has the same width as the first deep trench DTC1 formed in the cell region EFR, and the same depth in the substrate direction.

[0098] like Figure 6 As shown, the semiconductor device cPSD has the same two effects as the semiconductor device PSD according to the first embodiment. These two effects will then be described.

[0099] First, the first effect: such as Figure 16 As shown, when the parasitic diode PD1 performs a recovery operation, a surge voltage (reverse bias) is generated. This surge voltage is absorbed as energy in the buffer section SNR, which can reduce the surge voltage.

[0100] Next, the second effect is that the generated surge voltage can be reduced by enabling the self-conducting insulated-gate boundary effect transistor (MFET). However, the structure of the example semiconductor device cPSD introduces two new side effects associated with the surge voltage reduction structure. These two problems will be described below.

[0101] The first problem is the withstand voltage waveform oscillation (hereinafter referred to as "withstand voltage oscillation") when a voltage is applied between the drain and source and breakdown occurs. By forming a deep trench DTC1 below the gate pad region GPR, the withstand voltages of the device region EFR and the buffer region SNR become equal. Therefore, the breakdown current generated in the buffer region SNR through the resistor RSNB flowing through the drain-source current path causes the P-channel potential directly below the gate pad region GPR to rise compared to the source potential. Subsequently, the junction potential difference directly below the gate pad region GPR drops below the breakdown voltage and recovers from the breakdown state. After recovering from the breakdown state, since the current no longer flows, the potential difference between the P-channel potential and the source disappears, and breakdown occurs again directly below the gate pad region GPR. Therefore, the breakdown state and the blocking state repeat, resulting in an unstable measured potential.

[0102] The second problem is parasitic bipolar faults during avalanche breakdown, which reduce the load tolerance (L) through latch-up. Drain-source breakdown occurs, and the breakdown current generated in the buffer region SNR flows to the source. At this time, there is a parasitic bipolar transistor located directly below the contact CTS in the current path (the n-type source diffusion layer SDL is an n-parasitic bipolar transistor, the substrate diffusion layer BDL is a p-parasitic bipolar transistor, and the n-type pillar layer NCL is an n-parasitic bipolar transistor). The breakdown current flows in the base portion of the parasitic bipolar transistor, causing the parasitic bipolar transistor to fail due to the voltage drop, resulting in a reduction in the load tolerance (L) due to latch-up.

[0103] Conversely, in the first embodiment according to the semiconductor device PSD, in a plan view, at least one width of the deep trench DTC (second deep trench DTC2) formed in the buffer region SNR is formed to be smaller than at least one width of the deep trench DTC (first deep trench DTC1) formed in the cell region NER. For example, the width of the deep trench DTC (first deep trench DTC1) formed in the cell region NER is formed to be at least 0.5 micrometers. The second deep trench DTC2 formed in the buffer region SNR may have a width of 0.5 micrometers or greater than 0.5 micrometers, and a width of 0.7 micrometers or less than 0.7 micrometers. That is, the second deep trench DTC2 has a narrower opening width than the first deep trench DTC1.

[0104] Furthermore, the second deep trench DTC2 formed in the buffer region SNR has at least one depth in the substrate depth direction that is shallower than at least one depth of the first deep trench DTC1 formed in the cell region NER. For example, the first deep trench DTC1 has a depth of 8 micrometers or greater in the substrate direction, and the second deep trench DTC2 has a depth of 6 micrometers or greater but less than 8 micrometers in the substrate direction.

[0105] In the second deep trench DTC2 with a narrow opening width, the effective dose of implanted n-type and p-type impurities is reduced, widening the depletion layer region and improving breakdown voltage. By increasing the withstand voltage directly below the gate pad region GPR, which defines the buffer region SNR, breakdown is prevented directly below the gate pad region GPR. Since breakdown occurs in the cell region EFR, withstand voltage oscillations directly below the gate pad region GPR are suppressed.

[0106] Furthermore, by improving the breakdown voltage of the gate pad region GPR, which defines the buffer region SNR, breakdown directly below the gate pad region GPR is suppressed. Therefore, the reduction in L-load tolerance is suppressed to prevent parasitic bipolar transistor failure.

[0107] (Second Embodiment)

[0108] The semiconductor device of the second embodiment is described below with reference to the accompanying drawings.

[0109] like Figure 18 As shown, for example, the plurality of second deep trenches DTC2 formed in the buffer region SNR are configured to extend spaced apart from each other in the X-axis direction and have a wider spacing in the Y-axis direction than the spacing of the plurality of first deep trenches DTC1 formed in the cell region NER. For example, the spacing of the plurality of second buried insulators ZOF2 is formed to be 2.5 micrometers or greater, and 3.0 micrometers or less. The spacing of the plurality of first deep trenches DTC1 is, for example, formed to be less than 2.5 micrometers.

[0110] In addition, in the plan view, at least one of the multiple second deep trenches DTC2 formed in the buffer region SNR and at least one of the multiple first deep trenches DTC1 formed in the cell region NER are formed to have the same width.

[0111] In addition, at least one of the second deep trenches DTC2 formed in the buffer region SNR at a depth of the substrate is formed to substantially the same depth as at least one of the first deep trenches DTC1 formed in the cell region NER.

[0112] Incidentally, regarding other configurations, due to... Figure 3 , Figure 4 and Figure 5 The semiconductor devices shown are configured identically, and therefore are intended to avoid repetition of descriptions except where the same reference numerals are assigned to the same components.

[0113] Next, a method for manufacturing the aforementioned semiconductor device will be described. In the series of manufacturing steps of the semiconductor device described in the first embodiment, the semiconductor device is formed without changing the width and depth of each of the plurality of second deep trenches DTC2 formed in the buffer region SNR, and without changing the width and depth of each of the plurality of first deep trenches DTC1 formed in the cell region EFR. Alternatively, the semiconductor device can be formed by simply modifying the same manufacturing process as in the first embodiment to widen the spacing of the second deep trenches DTC2 formed in the buffer region SNR in the Y-axis direction.

[0114] Therefore, in the above-described semiconductor device, as described in the first embodiment, by increasing the withstand voltage directly below the gate pad region GPR, breakdown below the gate pad region GPR that defines the buffer region SNR is suppressed, and by suppressing breakdown in the cell region EFR, withstand voltage vibration directly below the gate pad region GPR is suppressed. That is, as described above, by widening the spacing of the second deep trench DTC2 directly below the gate pad region GPR, the withstand voltage directly below the gate pad region GPR is improved, and withstand voltage vibration is suppressed.

[0115] Furthermore, by improving the breakdown voltage of the gate pad region GPR, which defines the buffer region SNR, breakdown directly below the gate pad region GPR is suppressed. Therefore, parasitic bipolar transistor failure is prevented, and the reduction in L load tolerance is suppressed. Specifically, as described above, by widening the spacing of the second deep trench DTC2 directly below the gate pad region GPR, the withstand voltage directly below the gate pad region GPR is improved, and the reduction in L load tolerance is suppressed.

[0116] Furthermore, in the aforementioned semiconductor device, as described in the first embodiment, when the parasitic diode PD1 performs a recovery operation, the generated surge voltage can be absorbed as energy in the buffer circuit SNC. Additionally, by using the generated surge voltage to self-turn on the insulated-gate field-effect transistor MFET, the surge voltage can be reduced.

[0117] (Third Embodiment)

[0118] The semiconductor device of the third embodiment is described below with reference to the accompanying drawings.

[0119] like Figure 19 As shown, in the buffer region SNR, for example, when the trench gate electrode TGEL is formed in the form of strips spaced apart from each other in the Y-axis direction, it is formed by widening its width in the X-axis direction compared to the trench gate electrode TGEL formed in the cell region EFR. For example, the width of the trench gate electrode TGEL formed in the buffer region SNR in the X-axis direction is between 0.28 micrometers and 0.9 micrometers.

[0120] Incidentally, for other configurations, due to Figure 3 ,and Figure 4 and Figure 5 The semiconductor devices shown are configured identically, and therefore are intended to avoid repetition of descriptions except where the same reference numerals are assigned to the same components.

[0121] Next, a method for manufacturing the aforementioned semiconductor device will be described. The aforementioned semiconductor device can be formed by simply changing the pattern of the trench gate electrode (TGEL) using the same manufacturing process as described in the series of semiconductor device manufacturing processes in the first embodiment. That is, in the step of forming the trench gate electrode (see... Figure 6 The width of at least one trench gate electrode TGEL formed in the buffer region SNR is greater than the width of at least one trench gate electrode TGEL formed in the cell region EFR.

[0122] Furthermore, in the aforementioned semiconductor device, as described in the first embodiment, the surge voltage generated when the parasitic diode PD1 performs a recovery operation can be reduced. Additionally, by using the generated surge voltage to self-turn on the insulated-gate field-effect transistor (MFET), the surge voltage can be further reduced.

[0123] In addition to the effects described in the first embodiment, the above-described semiconductor device also has the following effects. Specifically, in the buffer region SNR, the trench gate electrode TGEL is formed by widening its width in the X-axis direction. Therefore, the path of current flowing through the p-type diffusion layer PDL is narrowed, and the resistance of the resistor RSNB is higher. By increasing the resistance value in the buffer circuit SNC, it is possible to further reduce the surge voltage. Furthermore, because the insulated-gate field-effect transistor MFET is proportional to its width in the X-axis direction, and thus deeper relative to the substrate direction, the gate-drain capacitor CGD2 is increased. This makes it easier for the insulated-gate field-effect transistor MFET to self-turn on, thereby enabling further reduction of the surge voltage.

[0124] Incidentally, the buffer circuits and other components of the semiconductor devices described in the embodiments can be combined in various forms as needed.

[0125] Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and needless to say, various modifications can be made without departing from the spirit of the present invention.

Claims

1. A semiconductor device, comprising: A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; An insulated gate field-effect transistor is disposed in a first region of the semiconductor substrate; as well as A buffer circuit is disposed in a second region different from the first region; The buffer circuit includes a resistor and a capacitor formed by a diffusion layer in the second region; In the first region, a plurality of first deep grooves spaced apart from each other in a plan view are formed; In the second region, a plurality of second deep trenches spaced apart from each other in the plan view are formed; Each of the plurality of first deep trenches has a first width; Each of the plurality of second deep trenches has a second width; and the second width of at least one of the second deep trenches in the second region is smaller than the first width of at least one of the plurality of first deep trenches in the first region. The plurality of first deep trenches having the first width and the plurality of second deep trenches having the second width are trenches deeper than the gate trenches formed in the semiconductor substrate.

2. The semiconductor device according to claim 1, The second deep trench has a width of 0.5 micrometers or greater than 0.5 micrometers and less than 0.7 micrometers in a plan view.

3. A method for manufacturing a semiconductor device, comprising the following steps: A first main surface and a second main surface opposite to the first main surface are provided to form an insulated gate field-effect transistor in a first region of a semiconductor substrate. A buffer circuit with resistors and capacitors is formed in a second region, different from the first region. In the first and second regions, the step includes forming a plurality of first deep trenches and a plurality of second deep trenches toward the semiconductor substrate. In the plurality of second deep trenches formed in the second region, the second width of at least one second deep trench in the second region is less than the first width of at least one first deep trench in the first region, and The plurality of first deep trenches having the first width and the plurality of second deep trenches having the second width are trenches deeper than the gate trenches formed in the semiconductor substrate.

4. The method for manufacturing a semiconductor device according to claim 3, further comprising: A first diffusion layer of a first conductivity type is formed, and the first diffusion layer is electrically connected to the semiconductor substrate. A second diffusion layer of the second conductivity type is formed. In the first region, above the first main surface and at a position shallower than the first diffusion layer, the second diffusion layer of the second conductivity type becomes the channel of an insulated gate field-effect transistor, and in the second region, it becomes the resistor and capacitor of the buffer circuit by bonding to the first diffusion layer.

5. The method for manufacturing a semiconductor device according to claim 3, The plurality of second deep trenches are formed in a plan view to have a width of 0.5 micrometers or greater than 0.5 micrometers and less than 0.7 micrometers.

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