Method for determining whether a display panel is a counterfeit, electronic device, and display panel

Abstract

A method for determining whether a display panel is a counterfeit, an electronic device, and a display panel are provided. The method includes generating a code by a code generator in an electronic module, the electronic module including a plurality of electronic components; sending the code to each of a first sequence generator in the electronic module and a second sequence generator in the display panel by the code generator, the display panel configured to be mounted to the electronic module; generating a first response value by the first sequence generator and sending the first response value to a verification component in the electronic module; generating a second response value by the second sequence generator and sending the second response value to the verification component; and comparing the received first response value with the received second response value by the verification component.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0073083, filed with the Korean Intellectual Property Office on June 19, 2019, which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of this disclosure generally relate to methods, electronic devices, and display panels for determining whether a display panel is a replica. Background Technology

[0004] Display devices can be manufactured by mounting the display panel within an electronic module. To prevent problems arising from unauthorized (e.g., counterfeit) display panels being connected to the application processor in the electronic module, such as when an unauthorized third party replaces the display panel, the electronic module can read a product identification code stored in non-volatile memory. The electronic module only operates to operate the display panel if the product identification code matches (or corresponds to) the identification code of a genuine (e.g., authorized) display panel.

[0005] However, when a display device uses a method of reading an identification code recorded (or stored) in the display panel, the identification code can be detected (e.g., determined) by observing the interface signal between the electronic module and the display panel. For example, in the case of a portable mobile device, the identification code can be detected by observing the Mobile Industry Processor Interface (MIPI) signal using a high-speed signal analysis system. Summary of the Invention

[0006] Embodiments of this disclosure provide a method for determining a copy of a display panel (e.g., determining whether the display panel is authorized), making it difficult (or nearly impossible) for an external user to deduce the code (e.g., identification code).

[0007] Embodiments of this disclosure further provide an electronic device including a display panel copy protection module, the electronic device employing a method that makes it difficult (e.g., practically impossible) to deduce the code.

[0008] According to an embodiment of the disclosure, a method for determining whether a display panel is a replica is provided. The method includes generating a code through a code generator in an electronic module including a plurality of electronic components, transmitting the code to each of a first sequence generator in the electronic module and a second sequence generator in the display panel configured to be mounted to the electronic module through the code generator, generating a first response value through the first sequence generator and transmitting the first response value to a verification component in the electronic module, generating a second response value through the second sequence generator and transmitting the second response value to the verification component, and comparing the received first response value with the received second response value by the verification component.

[0009] The first sequence generator and the second sequence generator can generate the first response value and the second response value by using a linear feedback shift register (LFSR).

[0010] Each term of the sequence generated using the LFSR can be a binary number having at least 16 bits.

[0011] The code can include a seed and a numerical value.

[0012] The first term of the sequence generated using the LFSR can be generated by moving an output value to the first bit of the seed and deleting the last bit of the seed, wherein the output value is obtained by inputting two bits selected from the seed to an XOR gate.

[0013] The first response value and the second response value can correspond to terms selected from the terms of the sequence generated using the LFSR according to the numerical value.

[0014] The first sequence generator and the second sequence generator can each include a data selector.

[0015] The data selector can output a j-bit binary term by selecting at least two bits from an i-bit binary term, where i is a natural number greater than or equal to 2, and j is less than i.

[0016] The code generator and the first sequence generator can be located in a processor of the electronic module, and the second sequence generator can be located in a driver IC of the display panel.

[0017] The processor can be configured to control the driver IC electrically connected to the processor.

[0018] In the process of comparing the received first response value with the received second response value by the verification component, the processor can control the display panel to operate when the first response value and the second response value are equal to each other, and the processor can control the display panel not to be operated when the first response value and the second response value are not equal to each other.

[0019] The method can further include, between transmitting the code and transmitting the first response value, generating a password by a second sequence generator and transmitting the password to the first sequence generator.

[0020] The code generator can be configured to generate the code based on a GPS coordinate, a current time, current data, or a One-Time Pad (OTP).

[0021] According to another embodiment of the disclosure, an electronic device includes a processor for transmitting and receiving an electrical signal to and from a display panel. The processor includes a code generator configured to generate a code and transmit the code to the display panel, a first sequence generator configured to output a first response value according to the code by using a Linear Feedback Shift Register (LFSR), and a verification component configured to receive a second response value from the display panel and compare the first response value and the second response value.

[0022] The display panel can include an interface provided in the electronic device and configured to transmit and receive the electrical signal, and a second sequence generator configured to output the second response value according to the code by using the LFSR.

[0023] The display panel can be mounted in the electronic device.

[0024] The electronic device can further include a power supply, a camera, a sensor, and a speaker, which can be configured to be controlled by the processor.

[0025] According to another embodiment of the disclosure, a display panel includes a power controller, a touch signal controller, a driver IC configured to control the power controller and the touch signal controller, and a second sequence generator located in one of the power controller, the touch signal controller, and the driver IC. The second sequence generator is configured to generate a pseudo-random number and transmit the pseudo-random number to an external electronic device.

[0026] The pseudo-random number can be generated based on a code received from the external electronic device.

[0027] The display panel can further include an interface through which the driver IC is electrically connected to a processor of the external electronic device, and the interface can be located in the external electronic device. BRIEF DESCRIPTION OF DRAWINGS

[0028] Exemplary embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings; however, the present disclosure can be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0029] In the drawings, to make the illustration clear, some dimensions can be exaggerated, and like reference numerals denote like elements throughout the accompanying drawings.

[0030] Figure 1 is a perspective view schematically showing an electronic device to which an embodiment of the present disclosure relates.

[0031] Figure 2 is a perspective view schematically showing an electronic device to which an embodiment of the present disclosure relates. Figure 1 is a plan view of the electronic device shown in FIG. 1, in which a display panel is in an unfolded state and connected to an electronic module.

[0032] Figure 3 is a block diagram schematically showing an electronic device to which an embodiment of the present disclosure relates.

[0033] Figure 4 is a flowchart illustrating a method for determining a replica of a display panel of an electronic device, to which an embodiment of the present disclosure relates.

[0034] Figures 5-9 is a block diagram illustrating Figure 4 steps of the method shown in FIG. 4.

[0035] Figure 10 is a flowchart illustrating a method for determining a replica of a display panel of an electronic device, to which another embodiment of the present disclosure relates.

[0036] Figures 11-14 is a block diagram illustrating Figure 10 some steps of the method shown in FIG. 6.

[0037] Figure 15 is a flowchart illustrating a method for determining a replica of a display panel of an electronic device, to which another embodiment of the present disclosure relates.

[0038] Figure 16 and Figure 17 are block diagrams respectively illustrating electronic devices, to which other embodiments of the present disclosure relate. DETAILED DESCRIPTION

[0039] Exemplary embodiments of the present disclosure will now be described in greater detail below with reference to the accompanying drawings; however, the present disclosure can be embodied in different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0040] It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or one or more intervening elements or layers can also be present. In contrast, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers present. By way of example, when a first element is described as "coupled" or "connected" to a second element, it can be directly coupled or connected to the second element or it can be indirectly coupled or connected to the second element through one or more intervening elements.

[0041] Throughout the description of the present disclosure, in the various drawings, the same drawing reference numerals are used for the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, use of "may" when describing embodiments of the present disclosure relates to "one or more embodiments of the present disclosure". Expressions such as "at least one of," when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Also, the term "exemplary" is intended to mean an example or an illustration. As used herein, the terms "use", "using", and "used" can be taken in their broadest possible context as synonymous with the terms "utilizing", "utilizing", and "utilized". As used herein, the terms "substantially", "approximately", and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the variations that would be recognized by those skilled in the art in measuring or calculating values.

[0042] Although the terms "first", "second", etc. are used to describe various components, the components are not limited by these terms. These terms are only used to distinguish one component from another. Thus, according to the technical concept of the present disclosure, a first component can be a second component, and vice versa.

[0043] The terms used herein are intended to describe particular example embodiments of the present disclosure and are not intended to limit the described example embodiments of the present disclosure. As used herein, the singular forms "a" and "an" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "includes," "including," "comprises," and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0044] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0045] Figure 1 is an exploded perspective view showing an electronic device to which an embodiment of the present disclosure relates, Figure 2 is a plan view showing Figure 1 is a plan view showing a display panel of the electronic device shown in FIG. 1A in a folded state. Figure 2 is a plan view showing a rear surface of the display panel and a rear surface of the electronic module.

[0046] Referring to Figure 1 and Figure 2 , the electronic device 1 includes a display panel 20 and an electronic module 10 housing the display panel 20.

[0047] Hereinafter, a display device including the display panel 20, such as a smart phone, is described as an example of the electronic device 1. However, the present disclosure can be applicable to any suitable display device, as long as the display device is an electronic device connecting a display panel, such as a tablet, a mobile phone, a video phone, an e-book reader, a desktop computer, a notebook computer, a netbook computer, a workstation, a server, a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), an MP3 player, a medical device, a camera, a television, or a wearable device. In one embodiment, the display panel 20 can be integrally installed in the electronic module 10, and can be configured to perform a function of the display device.

[0048] Examples of the display panel 20 include an Organic Light Emitting Diode (OLED) display panel, a Liquid Crystal Display (LCD) panel, a Plasma Display Panel (PDP), an electrophoretic display panel, a Micro Electro Mechanical System (MEMS) display panel, an electrowetting display panel, and the like.

[0049] The electronic device 1 can display an image on a display surface IS of the display panel 20. In the illustrated embodiment, the display surface IS is a front surface of the display panel 20 and has a planar shape defined by a first direction DR1 and a second direction DR2 intersecting (e.g., perpendicular to) the first direction DR1. However, this is merely illustrative. In another embodiment, the display surface IS can have a curved surface shape (e.g., a bent or folded shape).

[0050] A normal direction of the display surface IS (e.g., a thickness direction of the display panel 20) is indicated by a third direction DR3. A front surface (or top surface) and a rear surface (or bottom surface) of each element of the electronic device 1 are distinguished by the third direction DR3. However, the directions indicated by the first to third directions DR1, DR2, and DR3 are relative concepts and can be appropriately modified or varied. The display surface IS includes a display region DA in which an image is displayed and non-display regions NDA1 to NDA4 adjacent to the display region DA. The non-display regions NDA1 to NDA4 are regions in which an image is not displayed.

[0051] In one embodiment, the display region DA can have a quadrangular shape with rounded corners. The first non-display region NDA1 is arranged so as to surround the display region DA (e.g., can extend around an edge of the display region DA). In addition, the second non-display region NDA2 can be at least partially arranged in the display region DA. In addition, other surfaces of the display panel 20 (e.g., side surfaces and a rear surface of the display panel 20) other than the display surface IS can be (or can include or can only include) the third non-display region NDA3 and the fourth non-display region NDA4. However, the present disclosure is not limited thereto, and the shape of the display region DA and the shape of the non-display regions NDA1 to NDA4 can be relatively designed (e.g., appropriately modified or varied). In some embodiments, the non-display regions NDA1 to NDA4 can be absent on the display surface IS of the display panel 20, and the display region DA can be present on (e.g., can extend to or can be present on) the side surfaces of the display panel 20.

[0052] Referring to Figure 2 ,Figure 2 The rear surface of the display panel 20 is shown. The driver integrated circuit 260 can be mounted on the display panel 20 in a chip-on-glass (COG) configuration. For example, the driver integrated circuit 260 can be mounted on the glass substrate of the display panel 20 by inserting an anisotropic conductive film (ACF) between the driver integrated circuit 260 and the glass substrate of the display panel 20, and then compressing the ACF at a high temperature.

[0053] In one embodiment, the driver integrated circuit 260 may include a driver IC 200. In some embodiments, the driver integrated circuit 260 may be connected to the driver IC 200 and may include a source driver integrated circuit configured to apply a data voltage to the display area DA of the display panel 20, and a scan driver integrated circuit configured to apply a gate voltage to the display area DA of the display panel 20. In one embodiment, the driver integrated circuit 260 may include a combined driver integrated circuit that integrates the source driver integrated circuit configured to apply a data voltage to the display area DA of the display panel 20 and the scan driver integrated circuit configured to apply a gate voltage to the display area DA of the display panel 20.

[0054] Furthermore, in one embodiment, the driving integrated circuit 260 may include a power controller 220 and a touch signal controller 230. The power controller 220 may be configured to control the data voltage and the gate voltage. The touch signal controller 230 is an input device of the electronic device 1 and can calculate touch coordinates by sending a drive signal to the touch sensing unit and receiving a sensing signal.

[0055] Despite Figure 2 In the illustrated embodiment, a driver integrated circuit 260 is mounted on the display panel 20, but this disclosure is not limited thereto. In some embodiments, multiple driver integrated circuits 260 may be mounted on (or in) the display panel 20. Furthermore, this disclosure is not limited to the arrangement shown in the drawings, and various modifications may be made as appropriate.

[0056] Furthermore, in one embodiment, an interface 240 configured to send / receive electrical signals between the driver integrated circuit 260 and the processor 100 of the electronic module 10 can be mounted on the rear surface of the display panel 20. The driver IC 200 in the display panel 20 can send / receive electrical signals to / from the processor 100 in the electronic module 10 via the interface 240.

[0057] In one embodiment, the interface 240 can be a Film-On-Glass (FOG) flexible printed circuit. For example, the interface 240 can be mounted on a glass substrate of the display panel 20 by inserting an Anisotropic Conductive Film (ACF) between the interface 240 and the glass substrate of the display panel 20, and then compressing the ACF at a high temperature. The interface 240 can be connected to the electronic module 10, which transmits a data signal including image data and control data to control the operation of the display panel 20 when driving the display panel 20.

[0058] In one embodiment, the insulating pad 250 is disposed (e.g., can be mounted) on most of the area on the rear surface of the display panel 20 except for an area in which the driving integrated circuit 260 is disposed. The insulating pad 250 can prevent (or substantially prevent) an electric or magnetic interference signal generated in the electronic module 10 from being transmitted to the display panel 20.

[0059] The display panel 20 can be mounted in (or on) the electronic module 10. The first connector CNa can be located at one end of the interface 240, and the second connector CNb can be located on the printed circuit board 170 (e.g., formed in a partial area of the printed circuit board 170) of the electronic module 10. The first connector CNa and the second connector CNb can be connected to each other.

[0060] The electronic module 10 can include various suitable electronic components. The electronic components can include, for example, the printed circuit board 170, the power supply 130, the camera 140, the sensor 150, and the speaker 160. The sensor 150 can correspond to an illuminance sensor, a proximity sensor, a heart rate sensor, an ultraviolet sensor, etc. Furthermore, the arrangement of the electronic components in the electronic module 10 is not limited to the arrangement shown in the drawings. In other embodiments, some of the above-described electronic components can be omitted, and one or more components performing other (e.g., the same or different) functions can be added. That is, the electronic module 10 can be implemented in various suitable forms without departing from the scope of the present disclosure.

[0061] In an exemplary embodiment, the processor 100 and the memory 120 can be mounted on the printed circuit board 170 in the electronic module 10.

[0062] The processor 100 can be configured to perform a specific computation or task. For example, the processor 100 can be a mobile System-on-a-Chip (SoC), an application processor, a media processor, a microprocessor, a Central Processing Unit (CPU), or a similar device.

[0063] The processor 100 can be connected to the memory 120 through a bus such as an address bus, a control bus, and / or a data bus.

[0064] The memory 120 can be a Dynamic Random Access Memory (DRAM), a Mobile DRAM, a Static Random Access Memory (SRAM), a Parameter Random Access Memory (PRAM), a Ferroelectric Random Access Memory (FRAM), a Resistive Random Access Memory (RRAM), a Magnetic Random Access Memory (MRAM), or a flash memory.

[0065] The processor 100 can control various electronic components in the electronic device 1, for example, the power supply 130, the camera 140, the sensor 150, and the speaker 160.

[0066] The processor 100 can be further connected to an extension bus such as a Peripheral Component Interconnect (PCI) bus. Accordingly, the processor 100 can control input / output devices including one or more input devices (for example, a touch sensing unit in the display panel 20) and one or more output devices (for example, the display panel 20). For example, the processor 100 can control the driver IC 200, which controls the input / output device of the display panel 20 as a peripheral component, through the extension bus such as the interface 240.

[0067] The processor 100 can determine whether the display panel 20 connected to the electronic module 10 is an unauthorized (for example, an unauthorized replacement or a counterfeit) display panel. For example, when the display panel 20 is damaged due to external impact or a defect, a user of the electronic device 1 can replace the display panel 20 in the electronic module 10 without replacing any other components. The processor 100 in the electronic module 10 can determine whether the installed display panel 20 is an unauthorized after-sales service screen.

[0068] The electronic device 1 can include a replica determination module (for example, a replica judgment module) 110 and 210 included in the electronic module 10 and the display panel 20, respectively. Hereinafter, reference will be made to the replica determination module 110 and 210 as the replica judgment module 110 and 210. Figures 3 to 9The determination of whether the display panel 20 is an unauthorized display panel (hereinafter, the "unauthorized display panel" can be referred to as a "replica") will be described with reference to the electronic device 1 and the replica determination modules 110 and 210. The same components shown in the drawings are denoted by the same reference numerals, and repetitive explanation thereof can be omitted.

[0069] Figure 3 is a block diagram schematically illustrating an electronic device 1 to which an embodiment of the present disclosure relates.

[0070] Referring to Figure 3 , the electronic device 1 can include a first replica determination module 110 and a second replica determination module 210, which are included in the electronic module 10 and the display panel 20, respectively.

[0071] The first replica determination module 110 can perform a function by using hardware and / or software in the processor 100 of the electronic module 10. Similarly, the second replica determination module 210 can perform a function by using hardware and / or software in the driver IC 200 of the display panel 20. Hereinafter, an embodiment in which the replica determination modules 110 and 210 perform a function by hardware will be described.

[0072] The first replica determination module 110 can determine whether the display panel 20 is a replica by using one or more cryptographic algorithms between (e.g., in relation to) the first replica determination module 110 and the second replica determination module 210. The cryptographic algorithms can include a pseudo-random number, an asymmetric cryptographic algorithm, a cryptographic hash function, a key exchange algorithm, a key derivation function, a secret sharing algorithm, symmetric encryption, any other suitable cryptographic algorithm, and / or any combination of suitable cryptographic algorithms. An embodiment in which the display panel 20 is determined to be a replica by using a pseudo-random number as a cryptographic algorithm will be described below.

[0073] The first replica determination module 110 can include a code generator 111, a first sequence generator 112, and a verification component 113. The second replica determination module 210 can include a second sequence generator 212.

[0074] In one embodiment, each of the first sequence generator 112 and the second sequence generator 212 can generate a pseudo-random number.

[0075] The code generator 111 provides a seed for a pseudo-random number generation encryption algorithm to each of the first sequence generator 112 and the second sequence generator 212. Also, the code generator 111 can transmit a number value N to each of the first sequence generator 112 and the second sequence generator 212, by which at least one of the generated pseudo-random numbers is selected and outputted (in Figure 3 The seed and the number value N are displayed together as Seed N in the middle.

[0076] Each of the first sequence generator 112 and the second sequence generator 212 can generate a sequence of terms, where each term is an i-bit binary number (where i is a natural number greater than or equal to 2). In one exemplary embodiment, the i-bit binary number has 2 i -1 possible values not including zero (0). For example, a 4-bit binary number has 15 terms (e.g., 15 possible values or nibbles) - 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111 when the zero (0000) value is omitted. The number of possible sequential arrangements of the 15 4-bit binary terms generated by each of the first sequence generator 112 and the second sequence generator 212 is represented by 15! = 1,307,674,368,000. Thus, it can be seen that each of the first sequence generator 112 and the second sequence generator 212 generates a pseudo-random number when each of the first sequence generator 112 and the second sequence generator 212 arranges the terms generated by using a 4-bit or higher binary number in an arbitrary sequence.

[0077] In one embodiment, the seed generated by the code generator 111 can determine a first term of the i-bit binary terms generated by each of the first sequence generator 112 and the second sequence generator 212. Each of the first sequence generator 112 and the second sequence generator 212 can arrange the i-bit binary terms using an encryption algorithm. Also, the first sequence generator 112 and the second sequence generator 212 can select at least one of the arranged i-bit binary terms as a first response value SQ1 and a second response value SQ2, respectively, according to the number value N received from the code generator 111, and can output the first response value SQ1 and the second response value SQ2, respectively.

[0078] For example, when the code generator 111 generates the exemplary seed 1010 and transmits it to each of the first sequence generator 112 and the second sequence generator 212, each of the first sequence generator 112 and the second sequence generator 212 can generate the sequence 1010, 1011, 0001, 0010, 0011, 1000, 1001, 0100, 0101, 0110, 0111, 1100, 1101, 1110, and 1111 from the seed according to the exemplary algorithm. In this example, 1010 corresponds to the seed, 1011 corresponds to the first item, 0001 corresponds to the second item, 1111 corresponds to the fifteenth item, and so on. Also, when the code generator 111 specifies the numerical value N as 4, the first sequence generator 112 and the second sequence generator 212 can select 0011, i.e., the fourth item in the sequence, as the first response value SQ1 and the second response value SQ2, respectively, and can output the first response value SQ1 and the second response value SQ2, respectively.

[0079] The first response value SQ1 and the second response value SQ2 output by the first sequence generator 112 and the second sequence generator 212, respectively, can be transmitted to the verification part 113. When the first sequence generator 112 outputs the first response value SQ1 and then transmits the first response value SQ1 to the verification part 113, and the second sequence generator 212 outputs the second response value SQ2 and then transmits the second response value SQ2 to the verification part 113, the verification part 113 can determine whether the received first response value SQ1 and the received second response value SQ2 are the same (e.g., equal to each other). For example, when the first response value SQ1 and the second response value SQ2 received from the first sequence generator 112 and the second sequence generator 212, respectively, are the same, the verification part 113 can determine that the display panel 20 is not a replica (e.g., is an original display panel or an authorized replacement). On the other hand, when the first response value SQ1 and the second response value SQ2 received from the first sequence generator 112 and the second sequence generator 212, respectively, are different from each other, the verification part 113 can determine that the display panel 20 is a replica (e.g., is an unauthorized replacement).

[0080] In one embodiment, the processor 100 can determine whether to operate the display panel 20 according to whether the display panel 20 is determined to be a replica. For example, when the display panel 20 is determined to be not a replica, the processor 100 can control the display panel 20 to be operated (e.g., to be started). Also, when the display panel 20 is determined to be a replica, the processor 100 can control the display panel 20 not to be operated (e.g., not to be started).

[0081] Next, a method for determining whether the display panel 20 of the electronic device 1 is a replica, which the embodiment of the disclosure is related to, will be described in detail.

[0082] Figure 4 is a flowchart illustrating a method for determining whether a display panel of an electronic device is a counterfeit according to an embodiment of the disclosure. Figures 5 to 9 is a block diagram illustrating Figure 4 the steps of the method illustrated in FIG. 1.

[0083] Referring to Figure 4 , the method according to an embodiment of the disclosure can include a step S100 of generating a code, a step S200 of transmitting the code, a step S300 of generating and transmitting a first response value SQ1, a step S400 of generating and transmitting a second response value SQ2, and a step S500 of comparing the first response value SQ1 and the second response value SQ2.

[0084] Although embodiments in which the steps are performed sequentially according to the flowcharts are described below, it is apparent that some consecutive steps can be performed simultaneously (or substantially simultaneously), the order of the steps can be changed, one or more steps can be omitted, or one or more other steps can be further included between the described steps, without departing from the scope of the disclosure.

[0085] Referring to Figure 5 and in conjunction with Figure 4 , the step S100 of the code generator 111 generating a code and the step S200 of the code generator 111 transmitting the code can be performed.

[0086] For example, the step S100 of the code generator 111 generating a code can correspond to the step of the code generator 111 generating a code including an i-bit (where i is a natural number greater than or equal to 2) seed and a numerical value N described above. In addition, the step S200 of the code generator 111 transmitting the code can correspond to the step of the code generator 111 transmitting the code to the first sequence generator 112 and the second sequence generator 212 described above.

[0087] In one embodiment, the first sequence generator 112 and the second sequence generator 212 can arrange i-bit binary terms based on a linear feedback shift register (LFSR) structure as an algorithm. The arranged i-bit binary terms can be used as pseudo-random numbers.

[0088] An LFSR is a type of shift register and has a structure in which a value input to a register is calculated as a linear function of a previous state value. Exclusive-OR logic (XOR) can be a main function used in embodiments of the disclosure. An initial value of the LFSR is called a seed.

[0089] Because the operation of an LFSR is deterministic, the sequence of terms generated by an LFSR is determined by its previous value. Also, because the number of terms belonging to a register is finite, the sequence is iterated over a certain period of time. However, when the linear function is well chosen, it is possible to generate a sequence that is long in period and that appears to be random (e.g., has pseudo-random numbers). LFSRs are used in fields including pseudo-random numbers, pseudo-random noise, faster digital counters, wiping sequences, and the like.

[0090] A factor referred to as a number N (e.g., is necessary or essential) is used to determine an output value in a sequence determined by a seed (e.g., an initial value) of an LFSR. For example, after determining (e.g., setting or generating) the seed and the number N, the first sequence generator 112 can generate a first response value SQ1 according to the seed and the number N, and the second sequence generator 212 can generate a second response value SQ2 according to the seed and the number N. Accordingly, the code generator 111 can generate a code including the seed and the number N, and can transmit the generated code to each of the first sequence generator 112 and the second sequence generator 212. Also, each of the first sequence generator 112 and the second sequence generator 212 can receive the code including the seed and the number N from the code generator 111.

[0091] Next, referring to Figures 6 to 8 and in conjunction with Figures 3 to 4 the step S300 of generating and transmitting the first response value SQ1 and the step S400 of generating and transmitting the second response value SQ2 can be performed. In some embodiments, the two steps can be performed simultaneously (e.g., can be performed substantially simultaneously), but the present disclosure is not limited thereto. Figure 7 The process in which the first sequence generator 112 generates the first response value SQ1 is illustrated, and the second sequence generator 212 can employ the same or substantially similar process to generate the second response value SQ2.

[0092] For example, the step S300 of transmitting the first response value SQ1 corresponds to the step in which the first sequence generator 112 above generates the first response value SQ1 by using the received code and transmits the first response value SQ1 to the verification component 113. Also, the step S400 of transmitting the second response value SQ2 corresponds to the step in which the second sequence generator 212 above generates the second response value SQ2 by using the received code and transmits the second response value SQ2 to the verification component 113.

[0093] For example, when each of the first sequence generator 112 and the second sequence generator 212 arranges 4-bit binary terms (or nibbles) by the LFSR and receives a code including a term 1111 as a seed and 4 as a numerical value N from the code generator 111, each of the first sequence generator 112 and the second sequence generator 212 can generate a sequence of 15 4-bit binary terms as follows.

[0094] First, a value of 0111 as a first term is generated by moving 0 to the first bit of the seed and deleting the last bit, where 0 is an output value obtained by inputting two bits (e.g., the last two bits) of the seed (e.g., an initial value) 1111 to an exclusive OR (XOR) gate. Then, a value of 0011 as a second term is generated by moving 0 to the first bit of the first term and deleting the last bit of the first term, where 0 is an output value obtained by inputting the last two bits of the first term to the XOR gate. Then, a value of 0001 as a third term is generated by moving 0 to the first bit of the second term and deleting the last bit of the second term, where 0 is an output value obtained by inputting the last two bits of the second term to the XOR gate. Then, a value of 1000 as a fourth term is generated by moving 1 to the first bit of the third term and deleting the last bit of the third term, where 1 is an output value obtained by inputting the last two bits of the third term to the XOR gate. In the same manner, the sequence having a total of 15 terms is generated (e.g., the remaining 11 terms are generated) by moving an output value obtained by inputting the last two bits of the seed or the previous term to the XOR gate to the first bit of the seed or the previous term and deleting the last bit of the seed or the previous term.

[0095] When 4 is used as the numerical value N, the first sequence generator 112 and the second sequence generator 212 can output the fourth term (1000) as the first response value SQ1 and the second response value SQ2, respectively, and can output the fourth term (1000) to the verification component 113, respectively.

[0096] In the above example, another suitable value can be used as the seed, and the number of bits of the LFSR can be changed as appropriate. The total number of changes in the arrangement of terms can be determined by multiplying the number of cases of the seed by the number of cases of the numerical value N that can be calculated.

[0097] In some embodiments, a 16-bit or more LFSR can be used so that it is almost impossible to deduce (e.g., guess) the arrangement of terms by iterative measures. When a 16-bit LFSR is used, (2 16 -1) = 65,536 sequences can be represented. When a 32-bit LFSR is used, (2 16 -1) = 4,294,836,255 sequences can be represented. When a 32-bit LFSR is used, (2 32 -1) = 4,294,836,255 sequences can be represented. When a 32-bit LFSR is used, (2 32-1) = 18,446,744,065,119,600,000 sequences arrangements. For example, when a 16-bit LFSR is used, it is almost impossible to deduce the arrangement of the terms by iterative measures.

[0098] Next, with reference to Figure 9 and in conjunction with Figure 4 The step S500 of comparing the first response value SQ1 and the second response value SQ2 can be performed.

[0099] For example, the step S500 of comparing the first response value SQ1 and the second response value SQ2 corresponds to the step of comparing the first response value SQ1 and the second response value SQ2 by the verification component 113 described above.

[0100] The verification component 113 can compare the first sequence received from the first sequence generator 112 with the second sequence received from the second sequence generator 212. For example, when the first response value SQ1 and the second response value SQ2 are the same value, for example 1000, as a result of the exemplary steps described above, the verification component 113 can transmit the value to the processor 100 and the processor 100, in case of recognizing the matching (or equal) value, can send a command so that the display panel 20 installed to the electronic module 10 works.

[0101] Next, the method for determining whether the display panel 20 of the electronic device 1 is a counterfeit product, which the embodiment of the present disclosure relates to, will be described in detail. Hereinafter, the components identical or substantially similar to those described with reference to Figures 1 to 9 the same reference numerals are used to designate the same components, and repeated explanation thereof is omitted.

[0102] Figure 10 is a flowchart illustrating a method for determining whether a display panel of an electronic device is a counterfeit product, which another embodiment of the present disclosure relates to. Figures 11-14 is a block diagram illustrating some steps of the method shown in Figure 10 .

[0103] With reference to Figure 10 , the method which the embodiment relates to is different from the method which the embodiment described above with reference to Figure 4 in that, Figure 10 The method shown in

[0104] The method involved in this embodiment may include: a step of generating code S100; a step of sending code S200; a step of generating and sending password S210; a step of generating and sending first verification value SQ1 S300_1; a step of generating and sending second verification value SQ2 S400_1; and a step of comparing the first verification value SQ1 and the second verification value SQ2 S500. In this embodiment, the first sequence generator 112 and the second sequence generator 212_1 generate the first verification value SQ1 and the second verification value SQ2, respectively. The first verification value SQ1 and the second verification value SQ2 correspond to the terms corresponding to the first response value SQ1 and the second response value SQ2 in the above embodiment, and therefore, the same reference numerals are used.

[0105] refer to Figure 11 and combined Figure 10 The step S210 of generating and sending the cipher is described below. For example, step S210 of generating and sending the cipher corresponds to the step of the second sequence generator 212_1 generating the cipher PW and sending the cipher PW to the first sequence generator 112.

[0106] In one implementation, the second sequence generator 212_1 can generate a cipher PW. For example, the cipher PW can be used in the data selector MX of each of the first sequence generator 112 and the second sequence generator 212_1 (see example). Figure 13 This allows for the generation of an encryption seed of a j-bit binary number (where j is a natural number less than i and greater than or equal to 2) by selecting specific bits from an i-bit binary seed. Previously, the password PW could be shared between the electronic module 10 and the display panel 20 (e.g., it could be pre-stored in the electronic module 10 and the display panel 20).

[0107] The second sequence generator 212_1 can send the generated password PW to the first sequence generator 112. The second sequence generator 212_1 can send the password PW directly to the first sequence generator 112, or it can send the password PW through other components in the electronic module 10. Furthermore, the second sequence generator 212_1 can automatically memorize the generated password PW (e.g., it can store it in memory).

[0108] Next, refer to Figures 12 to 14 and combined Figure 10 The steps S300_1 for generating and sending the first verification value SQ1 and S400_1 for generating and sending the second verification value SQ2 will be described. Although Figure 13 The process of the second sequence generator 212_1 generating the second verification value SQ2 is shown, but Figure 13The illustrated process can also apply to the process by which the first sequence generator 112 generates the first verification value SQ1.

[0109] For example, the step S300_1 of generating and transmitting the first verification value SQ1 corresponds to a step by which the first sequence generator 112 generates the first verification value SQ1 by employing the received code and the received password PW and transmits the first verification value SQ1 to the verification component. In addition, the step S400_1 of generating and transmitting the second verification value SQ2 corresponds to a step by which the second sequence generator 212_1 generates the second verification value SQ2 by utilizing the received code and the memorized (e.g., stored and / or received) password PW and transmits the second verification value SQ2 to the verification component 113. Hereinafter, an exemplary embodiment employing a 32-bit binary number as a seed will be described.

[0110] In one embodiment, each of the first sequence generator 112 and the second sequence generator 212_1 can include at least one data selector MX. For example, the data selector MX can generate a 4-bit binary encryption seed by selecting four bits from a 32-bit binary seed. However, it is obvious that the number of bits of the seed and the number of bits of the encryption seed are not limited to the above-described example.

[0111] For example, first, the data selector MX of each of the first sequence generator 112 and the second sequence generator 212_1 can generate a 4-bit binary encryption seed from a 32-bit binary seed received from the code generator 111 by employing the password PW generated by the second sequence generator 212_1. Next, each of the first sequence generator 112 and the second sequence generator 212_1 can arrange the 4-bit binary term by using the LFSR. For example, when each of the first sequence generator 112 and the second sequence generator 212_1 generates the term 1111 as the encryption seed and receives the code 4 as the numerical value N from the code generator 111, the first sequence generator 112 and the second sequence generator 212_1 can generate the same first verification value SQ1 and second verification value SQ2, respectively (e.g., Figure 13 The illustrated 1000).

[0112] The first verification value SQ1 and the second verification value SQ2 generated by the first sequence generator 112 and the second sequence generator 212_1, respectively, can be transmitted to the verification component 113.

[0113] The step S500 of comparing the first verification value SQ1 and the second verification value SQ2 corresponds to a step by which the verification component 113 compares the first verification value SQ1 and the second verification value SQ2. The processor 100 can control whether the display panel 20 is operated according to whether the first verification value SQ1 and the second verification value SQ2 are equal (match) to each other.

[0114] As above, when each of the first sequence generator 112 and the second sequence generator 212_1 generates the first authentication value SQ1 and the second authentication value SQ2 by using the data selector MX that extracts a j-bit binary number using the previously shared password PW, it is virtually impossible for an external user to deduce the first authentication value SQ1 and the second authentication value SQ2 of the replica determination module.

[0115] Figure 15 is a flowchart illustrating a method for determining whether the display panel 20 of the electronic device 1 is a replica, which is related to another embodiment of the disclosure.

[0116] Referring to Figure 15 , the method related to the embodiment differs from the method illustrated in Figure 4 in that the code is generated differently in step S100_1.

[0117] The step S100_1 of generating the code related to the present embodiment corresponds to a step in which the code generator 111 generates the code based on the GPS coordinates, the current time, the current data, or a one-time pad (OTP).

[0118] In some embodiments, the code generator can generate the code based on the GPS coordinates, the current time, the current data, or a one-time pad (OTP). For example, the generated code can include the seed and the above-mentioned number N.

[0119] For example, the seed and the number N can be generated by using a pre-arranged algorithm that uses numbers of respective bits, which are represented by the GPS coordinates, the current time, the current data, or the OTP.

[0120] The item selected and output from the i-bit binary item by using the seed and the number N can be a random number (e.g., a random number close to a true random number).

[0121] Figure 16 and Figure 17 are block diagrams illustrating electronic devices, which are related to other embodiments of the disclosure, respectively.

[0122] Referring to Figure 16 and Figure 17 , the electronic devices 2 and 3 related to the embodiments differ from the electronic device described with reference to Figure 3 in that the second replica determination module 210 in the display panel 20 is located at a different position.

[0123] According to these embodiments, the second replica determination module 210 can be located in the power controller 220 or the touch signal controller 230. Each of the power controller 220 and the touch signal controller 230 can be electrically connected to the driver IC 200 and the processor 100 in the electronic module 10, and can transmit / receive an electrical signal accordingly. For example, the power controller 220 and the touch signal controller 230 can be controlled by the driver IC 200 in the display panel 20 and / or the processor 100 in the electronic module 10.

[0124] Accordingly, the second replica determination module 210 is located in the power controller 220 or the touch signal controller 230, and is configured to perform the process of determining whether the display panel 20 is a replica described above with reference to Figures 4 to 9

[0125] However, the location of the second replica determination module 210 is not limited to the location shown in the drawings. In another embodiment, the second replica determination module 210 can be inserted in (e.g., formed by) a plurality of components of the display panel 20 that are substantially controlled by the processor 100 to perform the process of determining whether the display panel 20 is a replica.

[0126] According to embodiments of the present disclosure, it is almost impossible to deduce a response value output by the method for determining whether the display panel is a replica.

[0127] Exemplary embodiments have been disclosed herein and, although a particular terminology is employed, such terminology is used in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics, and / or elements related to a particular embodiment can be used individually or in combination with features, characteristics, and / or elements related to other embodiments, as would be apparent to one of ordinary skill in the art of the present application, unless otherwise specified. Accordingly, one of ordinary skill in the art would understand that various changes in form and details can be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims and their equivalents.​

Claims

1. A method for determining whether a display panel mounted on a printed circuit board is a replica, the method comprising: Code is generated in the processor of the printed circuit board, the code including a numerical value and a seed of an i-bit binary number; The code is sent to the driver integrated circuit of the display panel; The driver integrated circuit generates a password and sends the password to the processor. In the processor, the password is used to select a j-bit binary seed from the i-bit binary seed, where i is a natural number greater than or equal to 2 and j is less than i; In the processor, a first response value is generated based on the encryption seed and the numerical value using a linear feedback shift register. In the driver integrated circuit, the password is used to select a j-bit binary seed from the i-bit binary seed, and a second response value is generated based on the encryption seed and the value using a linear feedback shift register, and the second response value is sent to the processor. as well as The processor compares the first response value with the received second response value.

2. The method according to claim 1, wherein, Each item in the sequence generated using the linear feedback shift register is a binary number with at least 16 bits.

3. The method according to claim 1, wherein, The first item of the sequence generated using the linear feedback shift register is generated by shifting the output value to the first bit of the seed and deleting the last bit of the seed, wherein the output value is obtained by inputting two bits selected from the seed into an XOR gate.

4. The method according to claim 3, wherein, The first response value and the second response value correspond to the items selected from the items in the sequence generated using the linear feedback shift register based on the numerical values.

5. The method according to claim 1, wherein, All of the driver integrated circuits include a data selector.

6. The method according to claim 5, wherein, The data selector can output a j-bit binary item by selecting at least two bits from an i-bit binary item. Where i is a natural number greater than or equal to 2, and Where j is less than i.

7. The method according to claim 1, wherein, The processor is configured to control the driver integrated circuit electrically connected to the processor.

8. The method according to claim 7, wherein, During the comparison of the first response value and the received second response value by the processor, when the first response value and the second response value are equal to each other, the processor controls the display panel to operate, and when the first response value and the second response value are different from each other, the processor controls the display panel to not be operated.

9. The method according to claim 1, wherein, The processor is configured to generate the code based on GPS coordinates, current time, current data, or a one-time key.

10. An electronic device, comprising: A processor for sending electrical signals to and receiving electrical signals from a display panel. The processor is configured as follows: Generate code, which includes a numerical value and an i-bit binary seed. Send the code to the display panel. Receive the password generated by the display panel. Using the aforementioned password, a j-bit encryption seed is selected from the i-bit binary seed, where i is a natural number greater than or equal to 2, and j is less than i. A first response value is generated using a linear feedback shift register based on the encryption seed and the numerical value. A second response value is received from the display panel, wherein the second response value is generated by the display panel using a linear feedback shift register based on an encryption seed and the value, the encryption seed being a j-bit binary number selected by the display panel from the i-bit binary number seed using the password, and... The first response value and the second response value are compared.

11. The electronic device according to claim 10, wherein, The display panel includes: A driver integrated circuit, configured to control a power controller and a touch signal controller, and The driver integrated circuit is configured to: generate the password, select a j-bit encryption seed from the i-bit binary seed using the password, generate the second response value based on the encryption seed and the value using a linear feedback shift register, and send the second response value to the processor.

12. The electronic device according to claim 11, wherein, The display panel also includes an interface through which the driver integrated circuit is electrically connected to the processor; and The interface is configured to send the electrical signal and receive the electrical signal.

13. The electronic device according to claim 10, wherein, The display panel is installed in the electronic device.

14. The electronic device of claim 10, further comprising a power supply, a camera, a sensor, and a speaker. in, The power supply, the camera, the sensor, and the speaker are configured to be controlled by the processor.

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