Semiconductor Memory Device and Memory System

Abstract

Provided is a semiconductor memory device and a memory system. The semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register, and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on a first sub-page in a first memory cell row during a scrub operation and based on performing a second ECC decoding on a second sub-page in a second memory cell row during a normal read operation on the second memory cell row. The control logic circuit records the error information in the error information register and controls the ECC engine circuit to skip ECC encoding and ECC decoding of selected memory cell rows of the first memory cell row and the second memory cell row based on the error information.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0072725, filed with the Korean Intellectual Property Office on Jun. 19, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to memories, and more particularly, to semiconductor memory devices and memory systems. Background art

[0004] Semiconductor memory devices can be classified into non - volatile memory devices (such as flash memory devices) and volatile memory devices (such as DRAMs). The high - speed operation and cost - efficiency of DRAMs make DRAMs likely to be used for system memories. Due to the continuous reduction of the manufacturing design rules of DRAMs, bit errors in memory cells in DRAMs may increase rapidly, and the yield of DRAMs may decrease. Summary of the invention

[0005] According to some example embodiments, a semiconductor memory device may include a memory cell array, an error correction code (ECC) engine circuit, an error information register, and a control logic circuit configured to control the ECC engine circuit. The memory cell array may include a plurality of memory cell rows. Each of the plurality of memory cell rows may include a plurality of dynamic memory cells. The control logic circuit may be configured to control the ECC engine circuit such that the ECC engine circuit generates an error generation signal based on performing a first ECC decoding on a first sub - page in at least one first memory cell row during a scrubbing operation on the at least one first memory cell row and based on performing a second ECC decoding on a second sub - page in at least one second memory cell row during a normal read operation on the at least one second memory cell row. The control logic circuit may also be configured to record error information in the error information register and control the ECC engine circuit based on reference error information such that the ECC engine circuit skips ECC encoding operations and ECC decoding operations on at least one selected memory cell row among the at least one first memory cell row and the at least one second memory cell row. The error information may at least indicate the amount of error occurrence in the first memory cell row and the second memory cell row.

[0006] According to some example embodiments, a semiconductor memory device may include a memory cell array including a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of dynamic memory cells. The semiconductor memory device may further include an error correction code (ECC) engine circuit, a refresh control circuit configured to generate a refresh row address of one or more memory cell rows to be refreshed among the plurality of memory cell rows, a scrub control circuit configured to count the refresh row address and generate a scrub address specifying at least one first memory cell row among the plurality of memory cell rows, an error information register, and a control logic circuit configured to control the ECC engine circuit and the refresh control circuit. The control logic circuit may be configured to control the ECC engine circuit such that the ECC engine circuit generates an error generation signal based on performing a first ECC decoding on a first sub-page in the at least one first memory cell row during a scrub operation on the at least one first memory cell row among the plurality of memory cell rows and based on performing a second ECC decoding on a second sub-page in the at least one second memory cell row during a normal read operation on the at least one second memory cell row among the plurality of memory cell rows. The control logic circuit may further be configured to record error information in the error information register and be configured to control the ECC engine circuit based on the reference error information such that the ECC engine circuit skips an ECC encoding operation and an ECC decoding operation on at least one selected memory cell row among the at least one first memory cell row and the at least one second memory cell row. The error information may at least indicate an amount of error occurrences in the first memory cell row and the second memory cell row.

[0007] According to some example embodiments, a memory system may include a semiconductor memory device and a memory controller configured to control the semiconductor memory device. The semiconductor memory device may include a memory cell array (the memory cell array including a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of dynamic memory cells), an error correction code (ECC) engine circuit, an error information register, and control logic circuitry configured to control the ECC engine circuit. The control logic circuitry may be configured to control the ECC engine circuit to cause the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on a first sub-page in at least one first memory cell row of the plurality of memory cell rows during a scrub operation on the at least one first memory cell row and based on performing a second ECC decoding on a second sub-page in at least one second memory cell row of the plurality of memory cell rows during a normal read operation on the at least one second memory cell row. The control logic circuitry may also be configured to record error information in the error information register and to control the ECC engine circuit based on reference error information to cause the ECC engine circuit to skip an ECC encoding operation and an ECC decoding operation on at least one selected memory cell row of the at least one first memory cell row and the at least one second memory cell row. The error information may at least indicate an amount of error occurrences in the first memory cell row and the second memory cell row. The control logic circuitry may be configured to transmit error information associated with the at least one selected memory cell row to the memory controller as an error information signal.

[0008] Accordingly, a semiconductor memory device according to some example embodiments may include an ECC engine circuit, may obtain error information associated with a permanent fault of some memory cell rows and some sub-pages based on information obtained during a scrub operation and a normal read operation on the memory cell rows, and transmit the error information associated with the permanent fault to the memory controller. Accordingly, the memory controller may reduce or prevent uncorrectable errors, thereby improving the functionality of a computing device (e.g., a computer) including the memory system including the memory controller and the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be described in more detail below with reference to the drawings.

[0010] Figure 1 is a block diagram illustrating a memory system according to some example embodiments.

[0011] Figure 2 is a block diagram illustrating a semiconductor memory device according to some example embodiments, Figure 1 in.

[0012] Figure 3 Shows an example of a first bank array in a semiconductor memory device of Figure 2 .

[0013] Figure 4 Is a block diagram showing a refresh control circuit in a semiconductor memory device of Figure 2 according to some example embodiments.

[0014] Figure 5 Is a circuit diagram showing an example of a refresh clock generator of Figure 4 shown according to some example embodiments.

[0015] Figure 6 Is a circuit diagram showing another example of a refresh clock generator in Figure 4 according to some example embodiments.

[0016] Figure 7 Is a circuit diagram showing interference between memory cells of a semiconductor memory device.

[0017] Figure 8 Is a block diagram showing an example of a sacrificial address detector in a semiconductor memory device of Figure 2 according to some example embodiments.

[0018] Figure 9 Shows Figure 8 a block diagram of an interference detector in a sacrificial address detector of

[0019] Figure 10 Is a block diagram showing an example of a scrub control circuit in a semiconductor memory device of Figure 2 according to some example embodiments.

[0020] Figure 11 Is a block diagram showing a scrub address generator in a scrub control circuit of Figure 10 according to some example embodiments.

[0021] Figure 12 Shows a weak word address generator in a scrub control circuit of Figure 10 according to some example embodiments.

[0022] Figure 13 Shows a part of a semiconductor memory device in a write operation of Figure 2 .

[0023] Figure 14 Shows a semiconductor memory device in a read operation or a refresh operation of Figure 2 .

[0024] Figure 15shows an error information register in a semiconductor memory device according to some example embodiments. Figure 2

[0025] Figure 16 is a block diagram showing an example of an ECC engine in a semiconductor memory device according to some example embodiments. Figure 2

[0026] Figure 17 shows an example of an ECC decoder in an ECC engine according to some example embodiments. Figure 16

[0027] Figure 18 and Figure 19 respectively show Figure 14 the error distribution of the first bank array in

[0028] Figure 20 is a flowchart showing a method of operating a semiconductor memory device according to some example embodiments.

[0029] Figure 21 is a block diagram showing a semiconductor memory device according to some example embodiments.

[0030] Figure 22 is a cross-sectional view of a 3D chip structure of a semiconductor memory device according to some example embodiments, employing Figure 21

[0031] Figure 23 is a diagram showing a semiconductor package including a stacked memory device according to some example embodiments. DETAILED DESCRIPTION

[0032] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown.

[0033] Figure 1 is a block diagram showing a memory system according to some example embodiments.

[0034] Referring to Figure 1 , the memory system 20 may include a memory controller 100 and a semiconductor memory device 200.

[0035] The memory controller 100 may control the overall operation of the memory system 20. The memory controller 100 may control the semiconductor memory device 200. The memory controller 100 may control the overall data exchange between an external host and the semiconductor memory device 200. For example, in response to a request from the host, the memory controller 100 may write data into the semiconductor memory device 200 or read data from the semiconductor memory device 200.

[0036] The memory controller 100 may be included in one or more instances of a processing circuit such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof (which may also be interchangeably referred to herein as an integrated circuit). The memory controller 100 may include one or more instances of the processing circuit, and / or the memory controller 100 may be implemented by one or more instances of the processing circuit. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory) (e.g., a solid state drive (SSD)) storing an instruction program, and a processor configured to execute the instruction program to implement the functions of the memory controller 100.

[0037] In addition, the memory controller 100 may issue (e.g., transmit) operation commands to the semiconductor memory device 200 to control the semiconductor memory device 200.

[0038] In some example embodiments, the semiconductor memory device 200 is a memory device including dynamic memory cells such as dynamic random access memory (DRAM), double data rate 4 (DDR4) synchronous DRAM (SDRAM), low power DDR4 (LPDDR4) DRAM, or LPDDR5 SDRAM.

[0039] The memory controller 100 may transmit a clock signal CLK, a command CMD, and an address (signal) ADDR to the semiconductor memory device 200, and exchange main data MD with the semiconductor memory device 200.

[0040] The semiconductor memory device 200 may transmit an error information signal EIS to the memory controller 100.

[0041] The memory controller 100 may determine an error management policy for defective cells in the semiconductor memory device 200 based on the error information signal EIS.

[0042] The semiconductor memory device 200 includes a memory cell array (MCA) 300 that stores main data MD and parity bits, an error correction code (ECC) engine 400, a control logic circuit 210, a scrub control circuit 500, and an error information register (EIR) 580. The ECC engine 400 may be interchangeably referred to herein as the ECC engine circuit and may be implemented by an example of a processing circuit further described below. The control logic circuit 210 may be configured to at least control the ECC engine 400. The memory cell array 300 may include a plurality of memory cell rows, and each of the plurality of memory cell rows in the memory cell array 300 may include a plurality of dynamic memory cells MC.

[0043] In some example embodiments, at least some of the semiconductor memory device 200 (including one or more or all of the control logic circuit 210, the ECC engine 400, the scrub control circuit 500, or the error information register 580) may be included in one or more instances of a processing circuit such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof. At least some of the semiconductor memory device 200 may include one or more instances of the processing circuit, and / or at least some of the semiconductor memory device 200 may be implemented by one or more instances of the processing circuit. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory) (e.g., a solid state drive (SDD)) storing an instruction program, and a processor configured to execute the instruction program to implement at least some of the functions of the semiconductor memory device 200, where the semiconductor memory device 200 includes one or more or all of the control logic circuit 210, the ECC engine 400, the scrub control circuit 500, or the error information register 580. In some example embodiments, the control logic circuit 210, the ECC engine 400, the scrub control circuit 500, or the error information register 580 may be implemented by separate processing circuits. In some example embodiments, two or more or all of the control logic circuit 210, the ECC engine 400, the scrub control circuit 500, or the error information register 580 may be implemented by the same processing circuit.

[0044] As described herein, it should be understood that any part of the semiconductor memory device 200 may be at least partially implemented by one or more instances of a processing circuit, and said any part of the semiconductor memory device 200 may be so implemented based on the semiconductor memory device 200 including one or more die (e.g., Figure 21 and Figure 22 any one of die 610 and / or 620 of the semiconductor memory device 600), where the die will be understood to include portions and / or blocks of semiconductor material fabricated to include one or more instances of an integrated circuit, where said one or more instances of the integrated circuit are configured to implement some or all of one or more parts of the semiconductor memory device 200 according to any example embodiment described herein. For example, based on discrete die (e.g., one or more die 610 and / or one or more die 620) including discrete instances of an integrated circuit, reference Figure 1 and / orFigure 2 The separated portion of the described semiconductor memory device 200 may be implemented by the separated die, where the integrated circuit configures the separated die to implement the separated portion of the semiconductor memory device 200 (e.g., ECC engine 400, scrub control circuit 500, error information register 580, control logic circuit 210, memory cell array 300, any combination thereof, etc.).

[0045] The ECC engine 400 (also referred to herein as the ECC engine circuit) may perform ECC encoding on write data to be stored in a target memory cell row (target page) of the memory cell array 300 under the control of the control logic circuit 210, and may perform ECC decoding or decoding on a codeword read from the target page.

[0046] The scrub control circuit 500 may generate a scrub address that specifies at least one sub-page in at least one first memory cell row in the memory cell row on which a scrub operation is to be performed, such that a scrub operation is performed on at least one first memory cell row at least partially specified by the scrub address in a plurality of memory cell rows of the memory cell array 300. The control logic circuit 210 may control the scrub control circuit 500.

[0047] During a scrub operation, the control logic circuit 210 may control the ECC engine 400 such that the ECC engine 400 reads data corresponding to a first codeword from at least one sub-page specified by the scrub address in the selected memory cell row, corrects at least one error bit in the first codeword, and writes the corrected first codeword back to the memory location storing the first data. Thus, the control logic circuit 210 may control the ECC engine 400 to cause the ECC engine 400 to perform a first ECC decoding operation based on reading data corresponding to the first codeword from each of the first sub-pages in the first sub-page and based on correcting at least one error bit in the first codeword, and to perform a scrub operation based on writing the corrected first codeword back to the memory location storing each of the first sub-pages in the memory cell array 300.

[0048] During a normal read operation, the control logic circuit 210 may control the ECC engine 400 to perform ECC decoding (e.g., second ECC decoding) on sub-pages in at least one second memory cell row in the memory cell array 300. The ECC engine 400 may generate an error generation signal based on performing the ECC decoding.

[0049] Accordingly, it will be appreciated that the control logic circuit 210 may control the ECC engine circuit to cause the ECC engine circuit to generate an error generation signal based on performing ECC decoding (e.g., first ECC decoding) on a first sub-page in the at least one first memory cell row during a scrub operation on the at least one first memory cell row in a memory cell row, and based on performing second ECC decoding on a second sub-page in the at least one second memory cell row during a normal read operation on the at least one second memory cell row in the memory cell row.

[0050] The control logic circuit 210 may record error information including at least (e.g., indicating) the number of error occurrences (e.g., error occurrence amount) in the first memory cell row and the second memory cell row. Accordingly, it will be appreciated that the control logic circuit 210 may record the error information in the error information register 580.

[0051] Figure 2 is a block diagram of Figure 1 the semiconductor memory device 200 in accordance with some example embodiments.

[0052] Referring to Figure 2 , the semiconductor memory device 200 includes a control logic circuit 210, an address register 220, a bank control logic 230, a refresh control circuit 245, a row address multiplexer 240, a column address latch 250, a row decoder 260, a column decoder 270, a memory cell array 300, a sense amplifier unit 285, an I / O gating circuit 290, an ECC engine 400, a scrub control circuit 500, a sacrificial address detector 560, an error information register 580, and a data I / O buffer 295.

[0053] In some example embodiments, at least some elements of the semiconductor memory device 200 may be included in one or more instances of a processing circuit such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof. At least some elements of the semiconductor memory device 200 may include one or more instances of the processing circuit, and / or at least some elements of the semiconductor memory device 200 may be implemented by one or more instances of the processing circuit. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuit may include: a non-transitory computer-readable storage device (e.g., a memory) (e.g., a solid state drive (SSD)) storing an instruction program, and a processor configured to execute the instruction program to implement the functions of at least some elements of the semiconductor memory device 200. In some example embodiments, two or more elements of the semiconductor memory device 200 may be implemented by separate processing circuits or the same processing circuit.

[0054] The memory cell array 300 includes first through eighth bank arrays 310 to 380. The row decoder 260 includes first through eighth bank row decoders 260a to 260h respectively coupled to the first through eighth bank arrays 310 to 380, the column decoder 270 includes first through eighth bank column decoders 270a to 270h respectively coupled to the first through eighth bank arrays 310 to 380, and the sense amplifier unit 285 includes first through eighth bank sense amplifiers 285a to 285h respectively coupled to the first through eighth bank arrays 310 to 380.

[0055] The first through eighth bank arrays 310 to 380, the first through eighth bank row decoders 260a to 260h, the first through eighth bank column decoders 270a to 270h, and the first through eighth bank sense amplifiers 285a to 285h may form first through eighth banks. Each of the first through eighth bank arrays 310 to 380 includes a plurality of memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BTL. The memory cells MC may be dynamic memory cells.

[0056] The address register 220 receives an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100. The address register 220 provides the received bank address BANK_ADDR to the bank control logic 230, provides the received row address ROW_ADDR to the row address multiplexer 240, and provides the received column address COL_ADDR to the column address latch 250.

[0057] The bank control logic 230 generates bank control signals in response to the bank address BANK_ADDR. In response to the bank control signals, one of the first through eighth bank row decoders 260a - 260h corresponding to the bank address BANK_ADDR is activated, and in response to the bank control signals, one of the first through eighth bank column decoders 270a - 270h corresponding to the bank address BANK_ADDR is activated.

[0058] The row address multiplexer 240 receives the row address ROW_ADDR from the address register 220 and receives the refresh row address REF_ADDR from the refresh control circuit 245. The row address multiplexer 240 selectively outputs the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 is applied to the first through eighth bank row decoders 260a - 260h.

[0059] The refresh control circuit 245 can sequentially output the refresh row address REF_ADDR in response to a first refresh control signal IREF1 or a second refresh control signal IREF2 from the control logic circuit 210.

[0060] When the command CMD from the memory controller 100 corresponds to an auto - refresh command, each time the control logic circuit 210 receives the auto - refresh command, the control logic circuit 210 can apply the first refresh control signal IREF1 to the refresh control circuit 245.

[0061] When the command CMD from the memory controller 100 corresponds to a self-refresh entry (SRE) command, the control logic circuit 210 may apply a second refresh control signal IREF2 to the refresh control circuit 245, and the second refresh control signal IREF2 is activated from the time point when the control logic circuit 210 receives the self-refresh entry command to the time point when the control logic circuit 210 receives the self-refresh exit (SRX) command. The refresh control circuit 245 may sequentially increase or decrease the refresh row address REF_ADDR in response to receiving the first refresh control signal IREF1 or during the activation of the second refresh control signal IREF2. Thus, the refresh control circuit 245 may generate a refresh row address REF_ADDR in response to a command received from the memory controller 100 (e.g., an auto-refresh command received from the memory controller 100 at the control logic circuit 210) so that one or more or all of the memory cell rows in the memory cell array 300 are refreshed.

[0062] One of the first to eighth bank row decoders 260a to 260h activated by the bank control logic 230 decodes the row address RA or the target scrub row address TSRA output from the row address multiplexer 240 and activates the word line corresponding to the row address RA or the target scrub row address TSRA. For example, the activated bank row decoder applies a word line drive voltage to the word line corresponding to the row address RA or the target scrub row address TSRA.

[0063] The column address latch 250 receives the column address COL_ADDR from the address register 220 and temporarily stores the received column address COL_ADDR. In some embodiments, in burst mode, the column address latch 250 generates a column address COL_ADDR' incremented from the received column address COL_ADDR. The column address latch 250 applies the temporarily stored or generated column address COL_ADDR' to the first to eighth bank column decoders 270a to 270h.

[0064] One of the first to eighth bank column decoders 270a to 270h that is activated activates a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR' or the target scrub column address TSCA through the I / O gating circuit 290.

[0065] The I / O gating circuit 290 includes circuitry for gating input / output data, and also includes input data masking logic, read data latches for storing data output from the first through eighth bank arrays 310 - 380, and write drivers for writing data to the first through eighth bank arrays 310 - 380. As an example, the I / O gating circuit 290 may have first through eighth bank I / O gating circuits 290a - 290h respectively coupled to the first through eighth bank arrays 310 - 380.

[0066] A codeword CW read from one of the first through eighth bank arrays 310 - 380 is read out by a sense amplifier coupled to the one bank array from which data is to be read, and is stored in the read data latch. After the ECC engine 400 performs ECC decoding on the codeword CW, the codeword CW stored in the read data latch may be provided to the memory controller 100 via the data I / O buffer 295.

[0067] Main data MD to be written to one of the first through eighth bank arrays 310 - 380 may be provided from the memory controller 100 to the data I / O buffer 295, the main data MD may be provided from the data I / O buffer 295 to the ECC engine 400, the ECC engine 400 may perform ECC encoding on the main data MD to generate parity bits, the ECC engine 400 may provide the main data MD and the parity bits to the I / O gating circuit 290, and the I / O gating circuit 290 may write the main data MD and the parity bits to a sub - page of a target page in one of the bank arrays via the write driver.

[0068] The data I / O buffer 295 may provide the main data MD from the memory controller 100 to the ECC engine 400 based on a clock signal CLK during a write operation of the semiconductor memory device 200, and may provide the main data MD from the ECC engine 400 to the memory controller 100 during a read operation of the semiconductor memory device 200.

[0069] During a scrub operation or a normal read operation of the semiconductor memory device 200, the ECC engine 400 performs ECC decoding on a codeword read from a sub - page of a target page, and when at least one error bit is detected in the main data MD in the codeword, may provide an error generation signal EGS to the control logic circuit 210 and correct the at least one error bit. The control logic circuit 210 may control the ECC engine (e.g., via a control signal CTL2) to cause the ECC engine 400 to generate the error generation signal EGS. The control logic circuit 210 may record the row address and column address of the codeword including the at least one error bit in the error information register 580 as error information EINF.

[0070] The scrub control circuit 500 can count the sequentially changing refresh row addresses REF_ADDR, and can output (e.g., generate) a normal scrub address SCADDR whenever (e.g., in response to) the scrub control circuit 500 has counted K refresh row addresses. Here, K is a natural number greater than 1. The normal scrub address SCADDR can include a scrub row address SRA and a scrub column address SCA. In the first scrub mode, the scrub control circuit 500 can provide the scrub row address SRA and the scrub column address SCA to the row decoder 260 and the column decoder 270, respectively. In some example embodiments, the scrub control circuit 500 can sequentially generate the normal scrub address SCADDR that specifies L codewords included in the first memory cell row among multiple memory cell rows, where L is a natural number equal to or greater than 1 and less than K.

[0071] The sacrifice address detector 560 can count the number (e.g., amount) of accesses to the first memory region in the memory cell array 300 to generate at least one sacrifice address VCT_ADDR that specifies at least one adjacent memory region adjacent to the first memory region when (e.g., in response to determining) the counted number of accesses reaches a threshold (e.g., a reference number (e.g., reference amount) during a reference interval). The at least one sacrifice address VCT_ADDR can be stored in an address storage table of the scrub control circuit 500.

[0072] In the second scrub mode, the scrub control circuit 500 can output the address of the codeword associated with the at least one sacrifice address VCT_ADDR stored in the address storage table as at least one weak codeword address WCADDR. The weak codeword address WCADDR can include a weak codeword row address WCRA and a weak codeword column address WCCA. In the second scrub mode, the scrub control circuit 500 can provide the weak codeword row address WCRA and the weak codeword column address WCCA to the row decoder 260 and the column decoder 270, respectively.

[0073] Therefore, it should be understood that the sacrifice address detector 560 can provide at least one sacrifice address VCT_ADDR to the scrub control circuit 500, and the scrub control circuit 500 can store the at least one sacrifice address VCT_ADDR in the address storage table in the scrub control circuit 500 as at least one weak codeword address WCADDR.

[0074] The control logic circuit 210 can control the operation of the semiconductor memory device 200. For example, the control logic circuit 210 can generate control signals for the semiconductor memory device 200 to perform a write operation or a read operation. The control logic circuit 210 includes a command decoder 211 that decodes a command CMD received from the memory controller 100 and a mode register 212 that sets the operation mode of the semiconductor memory device 200.

[0075] For example, the command decoder 211 can generate control signals corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc.

[0076] The control logic circuit 210 can generate a first control signal CTL1 that controls the I / O gating circuit 290, a second control signal CTL2 that controls the ECC engine 400 (e.g., causes the ECC engine to generate an error generation signal EGS), a third control signal CTL3 that controls the scrub control circuit 500, a fourth control signal CTL4 that controls the sacrificial address detector 560, and a fifth control signal CTL5 that controls the error information register 580. In addition, the control logic circuit 210 can provide a mode signal associated with a refresh cycle to the refresh control circuit 245.

[0077] The control logic circuit 210 can generate a mode signal MS based on a temperature signal representing the operating temperature of the semiconductor memory device 200.

[0078] The error information register 580 can provide (transmit) information associated with a permanent error of the error information EINF to the memory controller 100 as an error information signal EIS. In response to the fifth control signal CTL5, the error information register 580 can transmit the error information signal EIS to the memory controller 100 via one of a dedicated pin or a data I / O pin.

[0079] Figure 3 An example of Figure 2 a first bank array in a semiconductor memory device is shown.

[0080] Referring to Figure 3 , the first bank array 310 includes a plurality of word lines WL1 to WLm (m is a natural number equal to or greater than 2), a plurality of bit lines BTL1 to BTLn (n is a natural number equal to or greater than 2), and a plurality of memory cells MC arranged at intersections between the word lines WL1 to WLm and the bit lines BTL1 to BTLn. Each of the memory cells MC includes a cell transistor coupled to each of the word lines WL1 to WLm and each of the bit lines BTL1 to BTLn and a cell capacitor coupled to the cell transistor.

[0081] Figure 4 is a block diagram showing a refresh control circuit in a semiconductor memory device according to some example embodiments. Figure 2

[0082] Referring to Figure 4 , the refresh control circuit 245 may include a refresh clock generator 390 and a refresh counter 397.

[0083] In some example embodiments, some or all elements of the refresh control circuit 245 may be included in one or more instances of a processing circuit such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof, some or all elements of the refresh control circuit 245 may include one or more instances of the processing circuit, and / or some or all elements of the refresh control circuit 245 may be implemented by one or more instances of the processing circuit. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory) (e.g., a solid state drive (SSD)) storing an instruction program, and a processor configured to execute the instruction program to implement the functions of some or all elements of the refresh control circuit 245. In some example embodiments, two or more elements, or all elements, of the refresh control circuit 245 may be implemented by separate processing circuits or the same processing circuit.

[0084] The refresh clock generator 390 may generate a refresh clock signal RCK in response to a first refresh control signal IREF1, a second refresh control signal IREF2, and a mode signal MS. The mode signal MS may determine the refresh period of the refresh operation. As described above, whenever the refresh clock generator 390 receives the first refresh control signal IREF1 or during the activation of the second refresh control signal IREF2, the refresh clock generator 390 may generate the refresh clock signal RCK.

[0085] The refresh counter 397 may generate a refresh row address REF_ADDR sequentially specifying a memory cell row by performing a counting operation at the period of the refresh clock signal RCK.

[0086] Figure 5 is a circuit diagram showing an example of the refresh clock generator 390 according to some example embodiments. Figure 4

[0087] Reference Figure 5 , the refresh clock generator 390a may include: a plurality of oscillators 391, 392, and 393 (i.e., oscillators A, B, and C), a multiplexer 394, and a decoder 395a. The decoder 395a may decode the first refresh control signal IREF1, the second refresh control signal IREF2, and the mode signal MS to output a clock control signal RCS1. The oscillators 391, 392, and 393 generate refresh clock signals RCK1, RCK2, and RCK3 having different periods. The multiplexer 394 selects one of the refresh clock signals RCK1, RCK2, and RCK3 in response to the clock control signal RCS1 to provide a refresh clock signal RCK.

[0088] In some example embodiments, some or all of the elements of the refresh clock generator 390a may be included in one or more instances of a processing circuit such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof, some or all of the elements of the refresh clock generator 390a may include one or more instances of the processing circuit, and / or some or all of the elements of the refresh clock generator 390a may be implemented by one or more instances of the processing circuit. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory) (e.g., a solid state drive (SSD)) storing an instruction program, and a processor configured to execute the instruction program to implement the functions of some or all of the elements of the refresh clock generator 390a. In some example embodiments, two or more elements, or all elements, of the refresh clock generator 390a may be implemented by separate processing circuits or the same processing circuit.

[0089] Figure 6 is a circuit diagram showing another example of the refresh clock generator 390 in Figure 4 according to some example embodiments.

[0090] Reference Figure 6, the refresh clock generator 390b may include a decoder 395b, a bias unit 396a, and an oscillator 396b. The decoder 395b may decode the first refresh control signal IREF1, the second refresh control signal IREF2, and the mode signal MS to output a clock control signal RCS2. The bias unit 396a generates a control voltage VCON in response to the clock control signal RCS2. The oscillator 396b generates a refresh pulse signal RCK having a variable period according to the control voltage VCON. In Figure 6 ,"Vcc" represents, for example, a power supply voltage.

[0091] In some example embodiments, some or all of the elements of the refresh clock generator 390b may be included in one or more instances of a processing circuit such as hardware including a logic circuit, a hardware / software combination such as a processor executing software, or a combination thereof, some or all of the elements of the refresh clock generator 390b may include one or more instances of the processing circuit, and / or some or all of the elements of the refresh clock generator 390b may be implemented by one or more instances of the processing circuit. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SSoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory) (e.g., a solid state drive (SSD)) storing an instruction program, and a processor configured to execute the instruction program to implement the functions of some or all of the elements of the refresh clock generator 390b. In some example embodiments, two or more elements, or all elements, of the refresh clock generator 390b may be implemented by separate processing circuits or the same processing circuit.

[0092] Figure 7 is a circuit diagram showing interference between memory cells of a semiconductor memory device.

[0093] Referring to Figure 7 , a portion of the semiconductor memory device 200 includes memory cells 51, 52, and 53 (i.e., MC1, MC2, and MC3) and a bit-line sense amplifier (BLSA) 60.

[0094] Assume that each of the memory cells 51, 52, and 53 is connected to the same bit line BTL. In addition, the memory cell 51 is connected to the word line WL <g-1>, the memory cell 52 is connected to the word line WL <g>, and the memory cell 53 is connected to the word line WL<g+1>. As Figure 7 shown, the word line WL <g-1>and WL<g+1> and the word line WL <g>Adjacent. The memory cell 51 includes an access transistor CT1 and a cell capacitor CC1. The gate terminal of the access transistor CT1 is connected to the word line WL <g-1>, and one of its terminals is connected to the bit line BTL. The memory cell 52 includes an access transistor CT2 and a cell capacitor CC2. The gate terminal of the access transistor CT2 is connected to the word line WL <g>, and one of its terminals is connected to the bit line BTL. In addition, the memory cell 53 includes an access transistor CT3 and a cell capacitor CC3. The gate terminal of the access transistor CT3 is connected to the word line WL<g+1>, and one of its terminals is connected to the bit line BTL.

[0095] The bit line sense amplifier 60 may include an N-type sense amplifier that discharges the low-level bit line among the bit lines BTL and BTLB and a P-type sense amplifier that charges the high-level bit line among the bit lines BTL and BTLB.

[0096] During the refresh operation, the bit line sense amplifier 60 rewrites the stored data into the selected memory cell through the N-type sense amplifier or the P-type sense amplifier. During the read operation or the write operation, a selection voltage (e.g., Vpp) is supplied to the word line WL <g>. Then, even when no select voltage is applied to an adjacent word line WL <g-1>When at WL<g + 1>, due to the capacitive coupling effect, adjacent word lines WL <g-1>The voltages of WL<g + 1> also increase. This capacitive coupling is indicated by parasitic capacitances Ccl1 and Ccl2.

[0097] During a non - refresh operation, when the word line WL <g>When being accessed repeatedly, stored in the connection to the word line WL <g-1>The charges in the cell capacitors CC1 and CC3 of the memory cells 51 and 53 of WL<g+1> may gradually leak. In this case, the reliability of the logic "0" stored in the cell capacitor CC1 and the logic "1" stored in the cell capacitor CC3 may not be guaranteed. Therefore, it is necessary to perform a scrub operation on the memory cells at an appropriate time.

[0098] Figure 8 is a block diagram showing an example of a sacrificial address detector 560 in a semiconductor memory device according to some example embodiments. Figure 2

[0099] Referring to Figure 8 , the sacrificial address detector 560 may include an interference detector 570 and a sacrificial address generator 577.

[0100] In some example embodiments, some or all of the elements of the sacrificial address detector 560 may be included in one or more instances of a processing circuit such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof. Some or all of the elements of the sacrificial address detector 560 may include one or more instances of the processing circuit, and / or some or all of the elements of the sacrificial address detector 560 may be implemented by one or more instances of the processing circuit. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory) (e.g., a solid state drive (SSD)) storing an instruction program, and a processor configured to execute the instruction program to implement the functions of some or all of the elements of the sacrificial address detector 560. In some example embodiments, two or more elements, or all of the elements, of the sacrificial address detector 560 may be implemented by separate processing circuits or the same processing circuit.

[0101] The interference detector 570 may count the number of accesses to a first memory region (i.e., at least one memory cell row) based on the row address ROW_ADDR, and may generate a first detection signal DET1 when the counted number of accesses reaches a reference number during a reference (or predetermined) interval.

[0102] The sacrifice address generator 577 can generate at least one of a first sacrifice address VCT_ADDR1 and a second sacrifice address VCT_ADDR2 in response to a first detection signal DET1. At least one of the first sacrifice address VCT_ADDR1 and the second sacrifice address VCT_ADDR2 can be a row address specifying a second memory region or a third memory region adjacent to the first memory region. The sacrifice address generator 577 can provide at least one of the first sacrifice address VCT_ADDR1 and the second sacrifice address VCT_ADDR2 to an address storage table in the scrub control circuit 500.

[0103] Figure 9 is a block diagram of the interference detector 570 in the sacrifice address detector shown Figure 8 of.

[0104] Reference Figure 9 , the interference detector 570 can include an access counter 571, a threshold register 573, and a comparator 575.

[0105] In some example embodiments, some or all of the elements of the interference detector 570 can be included in one or more instances of a processing circuit such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof, some or all of the elements of the interference detector 570 can include one or more instances of the processing circuit, and / or some or all of the elements of the interference detector 570 can be implemented by one or more instances of the processing circuit. For example, more specifically, the processing circuit can include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuit can include a non-transitory computer-readable storage device (e.g., a memory) (e.g., a solid state drive (SSD)) storing an instruction program, and a processor configured to execute the instruction program to implement the functions of some or all of the elements of the interference detector 570. In some example embodiments, two or more elements, or all of the elements, of the interference detector 570 can be implemented by separate processing circuits or the same processing circuit.

[0106] The access counter 571 can count the number of accesses to the specified address (or the specified memory area) based on the row address ROW_ADDR in a predetermined time period. For example, the access counter 571 can count the number of accesses to the specified word line in a predetermined time period. The number of accesses can be counted on a specific word line or a group of word lines including at least two word lines. In addition, the counting of the number of accesses can be performed by a memory cell (e.g., a specific block cell, a bank cell, or a chip cell).

[0107] The threshold register 573 can store the maximum interference occurrence count that guarantees the data reliability in a specific word line or a memory cell. For example, the threshold (or the reference count) regarding a word line can be stored in the threshold register 573. Alternatively, the threshold regarding a group of word lines, a block, a bank cell, or a chip cell can be stored in the threshold register 573.

[0108] The comparator 575 can compare the reference count stored in the threshold register 573 with the number of accesses to the specific memory area counted by the access counter 571. If there is a memory area where the counted number of accesses reaches the reference count, the comparator 575 generates a first detection signal DET1. The comparator 575 provides the first detection signal DET1 to the sacrifice address generator 577.

[0109] The sacrifice address generator 577 receives the row address ROW_ADDR and generates at least one of a first sacrifice address VCT_ADDR1 and a second sacrifice address VCT_ADDR2 in response to the first detection signal DET1.

[0110] Figure 10 is a block diagram showing an example of a scrub control circuit 500 in a Figure 2 semiconductor memory device according to some example embodiments.

[0111] Refer to Figure 10 , the scrub control circuit 500 can include a counter 505, a scrub address generator 510, and a weak codeword address generator 520.

[0112] In some example embodiments, some or all of the elements of the scrub control circuit 500 may be included in one or more instances of a processing circuit such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof, some or all of the elements of the scrub control circuit 500 may include one or more instances of the processing circuit, and / or some or all of the elements of the scrub control circuit 500 may be implemented by one or more instances of the processing circuit. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory) (e.g., a solid state drive (SSD)) storing an instruction program, and a processor configured to execute the instruction program to implement the functions of some or all of the elements of the scrub control circuit 500. In some example embodiments, two or more elements, or all elements, of the scrub control circuit 500 may be implemented by separate processing circuits or the same processing circuit.

[0113] The counter 505 counts the refresh row address REF_ADDR to generate an internal scrub signal ISRB when the counter 505 counts the refresh row address REF_ADDR up to a quantity specified by a count control signal (not shown), wherein the internal scrub signal ISRB is activated during a first interval. The first interval may correspond to a time interval for refreshing one row of memory cells. In some example embodiments, the counter 505 is configured to activate the internal scrub signal ISRB in response to the counter 505 counting K of the refresh row addresses REF_ADDR in the refresh row address REF_ADDR.

[0114] In response to the internal scrub signal ISRB and the scrub mode signal SMS, the scrub address generator 510 generates a normal scrub address SCADDR associated with a normal scrub operation of a codeword in each row of memory cells (e.g., at least one selected row of memory cells, where the ECC engine 400 skips the ECC encoding operation and the ECC decoding operation for the at least one selected row of memory cells) in a first scrub mode, wherein the normal scrub address SCADDR changes gradually. For example, in response to the internal scrub signal ISRB and the scrub mode signal SMS, the scrub address generator 510 may generate a normal scrub address associated with a normal scrub operation of the at least one selected row of memory cells (the ECC engine 400 has skipped the ECC encoding operation and the ECC decoding operation for the at least one selected row of memory cells) in the first scrub mode.

[0115] The normal scrub address SCADDR includes a scrub row address SRA and a scrub column address SCA. The scrub row address SRA specifies a page in a bank array, and the scrub column address SCA specifies a codeword among the codewords in the said page. The scrub address generator 510 provides the scrub row address SRA to the corresponding row decoder and provides the scrub column address SCA to the corresponding column decoder.

[0116] Since the scrub operation performed based on the normal scrub address SCADDR is performed on all the codewords included in the memory cell array 300, the scrub operation performed based on the normal scrub address SCADDR can be referred to as a normal scrub operation.

[0117] In response to the internal scrub signal ISRB and the scrub mode signal SMS, the weak codeword address generator 520 generates a weak codeword address WCADDR associated with a weak scrub operation in a second scrub mode, where the weak scrub operation is associated with weak codewords in the bank array. For example, in response to the internal scrub signal ISRB and the scrub mode signal SMS, the weak codeword address generator 520 can generate a weak codeword address WCADDR associated with a weak scrub operation in the second scrub mode, where the weak scrub operation is associated with weak codewords in at least one selected memory cell row (the ECC engine 400 skips the ECC encoding operation and the ECC decoding operation for the at least one selected memory cell row). The weak codeword address WCADDR includes a weak codeword row address WCRA and a weak codeword column address WCCA. When the scrub mode signal SMS has a first logic level, the scrub mode signal SMS indicates a first scrub mode, and when the scrub mode signal SMS has a second logic level different from the first logic level, the scrub mode signal SMS indicates a second scrub mode. The scrub mode signal SMS can be included in the third control signal CTL3. The weak codeword address generator 520 provides the weak codeword row address WCRA to the corresponding row decoder and provides the weak codeword column address WCCA to the corresponding column decoder.

[0118] The weak codeword address generator 520 can include an address storage table therein, and the address storage table can store address information (e.g., corresponding addresses) of codewords associated with the sacrifice address VCT_ADDR.

[0119] Since the scrub operation performed based on the weak codeword address WCADDR is performed on the weak codewords included in the memory cell array 300, the scrub operation performed based on the weak codeword address WCADDR can be referred to as a weak scrub operation.

[0120] Figure 11 illustrates according to some example embodiments Figure 10 Block diagram of a scrub address generator in a scrub control circuit.

[0121] Reference Figure 11 , the scrub address generator 510 may include a page segment counter 511 and a row counter 513.

[0122] In some example embodiments, some or all of the elements of the scrub address generator 510 may be included in one or more instances of a processing circuit such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof, some or all of the elements of the scrub address generator 510 may include one or more instances of the processing circuit, and / or some or all of the elements of the scrub address generator 510 may be implemented by one or more instances of the processing circuit. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory) (e.g., a solid state drive (SSD)) storing an instruction program, and a processor configured to execute the instruction program to implement the functions of some or all of the elements of the scrub address generator 510. In some example embodiments, two or more elements, or all elements, of the scrub address generator 510 may be implemented by separate processing circuits or the same processing circuit.

[0123] In response to an internal scrub signal ISRB and a scrub mode signal SMS, the page segment counter 511 increments a scrub column address SCA by 1 when the internal scrub signal ISRB is activated in a first scrub mode, and whenever the scrub column address SCA reaches its maximum value, the page segment counter 511 activates a maximum address detection signal MADT and resets. The page segment counter 511 provides the maximum address detection signal MADT to the row counter 513.

[0124] In response to an internal scrub signal ISRB and a scrub mode signal SMS, the row counter 513 starts a counting operation by initially receiving the internal scrub signal ISRB, and increments a scrub row address SRA by 1 whenever the maximum address detection signal MADT is activated. Since the internal scrub signal ISRB is activated during a first interval while no refresh operation is performed on a row of memory cells, the page segment counter 511 may generate a scrub column address SCA associated with codewords in a page during the first interval.

[0125] Figure 12 Illustrated according to some example embodiments, Figure 10 The weak word address generator 520 in the scrub control circuit.

[0126] Reference Figure 12 , the weak word address generator 520 may include a table pointer 521, an address storage table 530, and a readout unit 540.

[0127] In some example embodiments, some or all of the elements of the weak word address generator 520 may be included in one or more instances of a processing circuit such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof. Some or all of the elements of the weak word address generator 520 may include one or more instances of the processing circuit, and / or some or all of the elements of the weak word address generator 520 may be implemented by one or more instances of the processing circuit. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory) (e.g., a solid state drive (SSD)) storing an instruction program, and a processor configured to execute the instruction program to implement the functions of some or all of the elements of the weak word address generator 520. In some example embodiments, two or more elements, or all elements, of the weak word address generator 520 may be implemented by separate processing circuits or the same processing circuit.

[0128] The address storage table 530 stores address information WCRA1 to WCRAs (s is a natural number greater than 1) and WCCA1 to WCCAt (t is a natural number greater than 1) of the weak words included in the memory cell array 300. The address information WCRA1 to WCRAs is designated as the weak word row address, and the address information WCCA1 to WCCAt is designated as the weak word column address. The weak words may be all or some of the weak pages among the pages in the first bank array 310 that include a number of error bits greater than a reference value. In addition, the weak words may be the codewords of the adjacent pages adjacent to the memory area that is intensively accessed. Therefore, it should be understood that the address storage table 530 may store address information associated with the weak words, such as address information indicating the corresponding addresses (e.g., WCRA1 to WCRAs, and / or WCCA1 to WCCAt) of the weak words.

[0129] The table pointer 521 can generate a pointer signal TPS that provides position information associated with the address storage table 530 during a first interval in a second scrub mode in response to an internal scrub signal ISRB and a scrub mode signal SMS, and provide the pointer signal TPS to the address storage table 530. The address storage table 530 can include a non-volatile memory. At least one of a first sacrificial address VCT_ADDR1 and a second sacrificial address VCT_ADDR2 provided from the sacrificial address generator 577 in Figure 8 can be stored in the address storage table 530. Figure 8 At least one of a first sacrificial address VCT_ADDR1 and a second sacrificial address VCT_ADDR2 provided from the sacrificial address generator 577 in Figure 8 can be stored in the address storage table 530.

[0130] The pointer signal TPS gradually increases for a predetermined period during the first interval, and whenever the pointer signal TPS is applied, the address storage table 530 can output, in response to the pointer signal TPS, a weak codeword address stored in the position (indicated by the pointer signal TPS) through the readout unit 540 as a weak codeword row address WCRA and a weak codeword column address WCCA. The readout unit 540 provides the weak codeword row address WCRA to the corresponding row decoder and provides the weak codeword column address WCCA to the corresponding column decoder.

[0131] For example, when the ECC engine 400 performs a scrub operation on a specific memory cell row multiple times and detects at least one error bit during a read operation on the specific memory cell row, the control logic circuit 210 determines that the specific memory cell row has a permanent fault. If the specific memory cell row with the permanent fault is not replaced, the error bits accumulate in the specific memory cell row, and an uncorrectable error may occur in the specific memory cell row. Therefore, the control logic circuit 210 or the memory controller 100 can replace the specific memory cell row with the permanent fault with a redundant memory cell row through a repair operation. Thus, the semiconductor memory device 200 can be configured to be able to reduce or prevent uncorrectable errors, thereby improving the function of a computing device (e.g., a computer) including the memory system 20, where the memory system 20 at least includes the semiconductor memory device 200 and may also include the memory controller 100.

[0132] Figure 13 Shows a semiconductor memory device in a write operation Figure 2 of a part.

[0133] In Figure 13 it shows the control logic circuit 210, the first bank array 310, the I / O gating circuit 290, and the ECC engine 400.

[0134] Reference Figure 13 , the first bank array 310 includes a normal cell array NCA and a redundant cell array RCA.

[0135] The normal cell array NCA includes a plurality of first memory blocks MB0 to MB15 (i.e., 311 to 313), and the redundant cell array RCA includes at least a second memory block 314. The first memory blocks 311 to 313 are the memory blocks that determine the memory capacity of the semiconductor memory device 200. The second memory block 314 is used for ECC and / or redundant repair. Since the second memory block 314 for ECC and / or redundant repair is used for ECC, data line repair, and block repair to repair the "failed" cells generated in the first memory blocks 311 to 313, the second memory block 314 is also referred to as an EDB block. In each of the first memory blocks 311 to 313, a plurality of first memory cells are arranged in rows and columns. In the second memory block 314, a plurality of second memory cells are arranged in rows and columns. The first memory cell connected to the intersection of the word line WL and the bit line BTL can be a dynamic memory cell. The second memory cell connected to the intersection of the word line WL and the bit line RBTL can be a dynamic memory cell.

[0136] The I / O gating circuit 290 includes a plurality of switch circuits 291a to 291d respectively connected to the first memory blocks 311 to 313 and the second memory block 314. In the semiconductor memory device 200, bit lines corresponding to data of the burst length (BL) can be accessed simultaneously to support the BL indicating the maximum number of accessible column positions. For example, the BL can be set to 8.

[0137] Although Figure 13 An example of an unexposed sense amplifier is shown, but the first bank sense amplifier 285a can be coupled between the first bank array 310 and the I / O gating circuit 290.

[0138] The ECC engine 400 can be connected to the switch circuits 291a to 291d through the first data line GIO[0:127] and the second data line EDBIO[0:15]. The control logic circuit 210 can receive the command CMD and the address ADDR and can decode the command CMD to generate a first control signal CTL1 for controlling the switch circuits 291a to 291d and a second control signal CTL2 for controlling the ECC engine 400.

[0139] When the command CMD is a write command, the control logic circuit 210 provides a second control signal CTL2 to the ECC engine 400, and the ECC engine 400 performs ECC encoding on the main data MD to generate parity bits associated with the main data MD and provides a codeword CW including the main data MD and the parity bits to the I / O gating circuit 290. The control logic circuit 210 provides a first control signal CTL1 to the I / O gating circuit 290 such that the codeword CW will be stored in a sub-page of a target page in the first bank array 310.

[0140] Figure 14 illustrates a semiconductor memory device in a read operation or a refresh operation Figure 2 of.

[0141] In Figure 14 it, the control logic circuit 210, the first bank array 310, the I / O gating circuit 290, the ECC engine 400, the scrub control circuit 500, and the error information register 580 are illustrated.

[0142] In some example embodiments, at least some elements of the semiconductor memory device 200a may be included in one or more instances of a processing circuit such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof, at least some elements of the semiconductor memory device 200a may include one or more instances of the processing circuit, and / or at least some elements of the semiconductor memory device 200a may be implemented by one or more instances of the processing circuit. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory) (e.g., a solid state drive (SSD)) storing an instruction program, and a processor configured to execute the instruction program to implement the functions of some or all elements of the semiconductor memory device 200a. In some example embodiments, two or more elements, or all elements, of the semiconductor memory device 200a may be implemented by separate processing circuits or the same processing circuit.

[0143] Referring to Figure 14 , when the command CMD is a refresh command specifying a refresh operation or a read command specifying a read operation, the control logic circuit 210 provides a first control signal CTL1 to the I / O gating circuit 290 such that a first (read) codeword RCW stored in a sub-page of a target page in the first bank array 310 is provided to the ECC engine 400. Although Figure 14 An example of an unexposed sense amplifier is shown, but the first bank sense amplifier 285a can be coupled between the first bank array 310 and the I / O gating circuit 290.

[0144] During a refresh operation, the ECC engine 400 performs a scrubbing operation by performing a first ECC decoding on the codeword RCW, correcting at least one error bit in the codeword RCW to generate a corrected codeword RCW, and writing the corrected codeword RCW back to the memory location of the memory subpage. When at least one error bit is detected during the scrubbing operation, the ECC engine 400 provides an error generation signal EGS to the control logic circuit 210 whenever an error bit is detected. A counter 214 in the control logic circuit 210 counts the error generation signal EGS, and the control logic circuit 210 records the error information EINF in the error information register 580. Based on counting the error generation signal EGS, the error information EINF can include at least the number of error occurrences of the selected memory cell row. During a normal read operation, the ECC engine 400 performs a second ECC decoding on the codeword RCW of each second subpage in the second memory cell row, and when the ECC engine 400 detects an error bit in the codeword RCW, provides an error generation signal EGS to the control logic circuit 210.

[0145] Accordingly, it will be appreciated that the control logic circuit 210 can control the ECC engine 400 to cause the ECC engine 400 to: perform a first ECC decoding operation based on reading data corresponding to the first codeword from each first subpage in the first subpage and based on correcting at least one error bit in the first codeword RCW to generate a corrected first codeword RCW; perform a scrubbing operation based on writing the corrected first codeword RCW back to the memory location of each first subpage in the memory first subpage of the memory cell array; and perform a second ECC decoding operation based on reading data corresponding to the second codeword RCW from each second subpage in the second subpage, based on correcting at least one error bit in the second codeword RCW to generate a corrected second codeword RCW, and based on outputting the corrected second codeword RCW.

[0146] The error information EINF can include address information ADDINF, error occurrence number ECNT, rank information RNK, the number of subpages FCWCNT including error bits, flag information FG indicating whether the error information EINF is first written to the error information register 580, and permanent failure information PF. The control logic circuit 210 controls the error information register 580 through a fifth control signal CTL5 to transmit the error information EINF of the memory cell row or subpage with a permanent failure to the memory controller 100 as an error information signal EIS.

[0147] Thus, after the ECC engine 400 performs the first ECC decoding on the first memory cell row, the control logic circuit 210 can transmit the address of the first memory cell row to the external memory controller 100 (which is outside the semiconductor memory device 200) as an error information signal EIS in response to determining that the error occurrence amount of the first sub-page of the first memory cell row is equal to or greater than M (where M is a natural number greater than 1), and after the ECC engine 400 performs the second ECC decoding on the second memory cell row, the control logic circuit 210 can transmit the address of the second memory cell row to the external memory controller 100 as an error information signal EIS in response to determining that the error occurrence amount of the second sub-page of the second memory cell row is equal to or greater than M. The control logic circuit 210 can transmit the error information signal EIS to the external memory controller 100 via one of a dedicated pin or a data input / output (I / O) pin. Thus, it will be understood that the control logic circuit 210 can be configured to transmit error information associated with at least one selected memory cell row, where the control logic circuit controls the ECC engine 400 to skip the ECC encoding operation and the ECC decoding operation for the at least one selected memory cell row.

[0148] Simultaneously with the ECC engine circuit 400 performing a scrubbing operation on the first memory cell row multiple times (e.g., performing multiple iterations of the scrubbing operation), in response to determining that the error occurrence quantity (e.g., error occurrence amount) of one first sub-page in the first sub-pages of the first memory cell row is equal to or greater than N (where N is a natural number greater than 1), the control logic circuit 210 can record the address of the one first sub-page in the first sub-pages in the error information register 580, and can record the address of the one first sub-page in the first sub-pages as having a permanent fault.

[0149] Simultaneously with the ECC engine circuit 400 performing a scrubbing operation on the first memory cell row once (e.g., precisely performing one iteration of the scrubbing operation), in response to determining that the error occurrence quantity (e.g., error occurrence amount) of the first sub-page of the first memory cell row is equal to or greater than M (where M is a natural number greater than 1), the control logic circuit 210 can record the address of the first memory cell row in the error information register 580, and can record the address of the first memory cell row as having a permanent fault.

[0150] While the ECC engine circuit 400 performs a normal read operation on the second memory cell row, in response to determining that the number of error occurrences (e.g., error occurrence amount) of the second sub-page of the second memory cell row is equal to or greater than M, the control logic circuit 210 may record the address of the second memory cell row in the error information register 580 and may record the address of the second memory cell row as having a permanent fault.

[0151] The control logic circuit 210 may control the ECC engine 400 such that the ECC engine 400 skips the ECC decoding operation and the ECC encoding operation on the memory cell row or sub-page having a permanent fault just after (e.g., immediately after, without any intervening operation by the control logic circuit 210) the control logic circuit 210 records the first memory cell row and / or the second memory cell row, and / or the first sub-page and / or the second sub-page in the error information register 580 as having a permanent fault. Thus, it will be understood that the control logic circuit 210 may record the error information in the error information register 580 and may control the ECC engine 400 to skip the ECC encoding operation and the ECC decoding operation on at least one selected memory cell row among the first memory cell row and the second memory cell row based on the error information recorded in the error information register 580.

[0152] Figure 15 illustrates an error information register in a semiconductor memory device according to some example embodiments Figure 2 thereof.

[0153] Reference Figure 15 , each of the indexes (e.g., entries) Idx1, Idx2, …, Idxu (u is a natural number greater than 2) may include page error information about each of some pages of the memory cell array 300. Each entry may correspond to one of the pages. The error information register 580 includes a plurality of columns 581, 582, 583, 584, 585, and 586.

[0154] The first column 581 stores sorting information RNK for sorting the number of error occurrences based on the number of error occurrences for each of the some pages. An entry having the ranking information RNK with the lowest value (e.g., 1) may be considered the highest rank, and an entry having the ranking information RNK with the highest value may be considered the lowest rank. For example, the first page associated with idx1 having 2 error occurrences during a given time period may correspond to an RNK with a value of 2, while the second page associated with idx2 having 4 error occurrences during the given time period may correspond to a higher RNK with a value of 1.

[0155] The second column 582 stores the address information ADDINF of each of the some pages. In some example embodiments, the address information ADDINF includes at least one of a bank group address BGA, a bank address BA, and a row address RA. Although Figure 3 a single bank array group (e.g., 310 - 380) is shown, additional bank array groups may exist. The bank group address can identify one of these groups. For example, if there is a first bank array group including bank arrays 310 - 380 and a second bank array group, and an error occurs in the first bank array group, then the BGA will identify the first bank array group. The bank address can identify one of the banks in the identified bank array group. The row address can identify the page of the one bank.

[0156] The third column 583 stores the error occurrence count ECNT of each of the some pages. For example, Figure 15 the error information register 580 of shows that the error occurrence count ECNT of the page with address information A is 2, while the error occurrence count ECNT of the page with address information B is 4.

[0157] The fourth column 584 stores the number FCWCNT of sub - pages including bit errors of each of the some pages. For example, if the second page has 4 bit errors (ECNT = 4), the second page has 64 sub - pages, but only 3 sub - pages out of the 64 sub - pages have bit errors (e.g., sub - page 1 and 12 each have 1 bit error, and sub - page 43 has 2 bit errors), then the entry for the second page will have an FCWCNT value of 3.

[0158] The fifth column 585 stores flag information FG, and the sixth column 586 stores the permanent fault information PF of each of the some pages. The flag information FG indicates whether the error information of the corresponding page is being written to the error information register 580 for the first time. When the error information of the corresponding page is being written to the error information register 580 for the first time, the flag information FG has a first logic level (e.g., 0). In some example embodiments, if the flag information FG of a page has a second logic level (e.g., 1), then the page previously had error information. The permanent fault information PF can indicate whether each of the some pages has a permanent fault. If a page or a sub - page has a permanent fault, the permanent fault information PF has a second logic level (e.g., 1). If a page or a sub - page has a transient fault, the permanent fault information PF has a first logic level (e.g., 0).

[0159] The memory controller 100 may determine an error handling strategy for a row or sub-page of memory cells with a permanent fault based on the error information EINF in the error information register 580.

[0160] Figure 16 is a block diagram showing an example of an ECC engine in a semiconductor memory device according to some example embodiments. Figure 2

[0161] Referring to Figure 16 , the ECC engine 400 includes selection circuits 405 and 407, an ECC encoder 410, and an ECC decoder 430.

[0162] In some example embodiments, some or all of the elements of the ECC engine 400 may be included in one or more instances of a processing circuit such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof, some or all of the elements of the ECC engine 400 may include one or more instances of the processing circuit, and / or some or all of the elements of the ECC engine 400 may be implemented by one or more instances of the processing circuit. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory) (e.g., a solid state drive (SSD)) storing an instruction program, and a processor configured to execute the instruction program to implement the functions of some or all of the elements of the ECC engine 400. In some example embodiments, two or more elements, or all elements, of the ECC engine 400 may be implemented by separate processing circuits or the same processing circuit.

[0163] The selection circuit 405 provides the main data MD to one of the normal cell area NCA and the ECC encoder 410 in response to a first selection signal SS1. The ECC encoder 410 may generate parity bits PRT associated with the write data WMD to be stored in the normal cell array NCA of the first bank array 310. The parity bits PRT may be stored in the redundant cell array RCA of the first bank array 310.

[0164] The selection circuit 407 provides the read data RMD read from the first bank array 310 to one of the data I / O buffer 295 and the ECC decoder 430.

[0165] The ECC decoder 430 may perform ECC decoding on the read data RMD based on the read data RMD and the parity bit PRT. When, as a result of the ECC decoding, the read data RMD includes at least one error bit, the ECC decoder 430 provides an error generation signal EGS to the control logic circuit 210 and corrects the error bit in the read data RMD to output the corrected main data C_MD.

[0166] The ECC encoder 410 may perform ECC encoding using a single error correction (SEC) code, and the ECC decoder 430 may perform ECC decoding using the SEC code. The first selection signal SS1 and the second selection signal SS2 may be included in the second control signal CTL2.

[0167] Figure 17 illustrates an example of the ECC decoder 430 in an ECC engine according to some example embodiments, Figure 16 of.

[0168] Referring to Figure 17 , the ECC decoder 430 may include a syndrome generation circuit 440, an error locator 460, and a data corrector 470. The syndrome generation circuit 440 may include a parity bit generator 441 and a syndrome generator 443.

[0169] In some example embodiments, some or all of the elements of the ECC decoder 430 may be included in one or more instances of a processing circuit such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof, some or all of the elements of the ECC decoder 430 may include one or more instances of the processing circuit, and / or some or all of the elements of the ECC decoder 430 may be implemented by one or more instances of the processing circuit. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory) (e.g., a solid state drive (SSD)) storing an instruction program, and a processor configured to execute the instruction program to implement the functions of some or all of the elements of the ECC decoder 430. In some example embodiments, two or more elements, or all elements, of the ECC decoder 430 may be implemented by separate processing circuits or the same processing circuit.

[0170] The parity bit generator 441 generates a parity bit CHB based on the read data RMD by performing an XOR (exclusive OR) array operation, and the syndrome generator 443 generates a syndrome SDR by comparing corresponding bits of the parity bit PRT and the parity bit CHB.

[0171] The error locator 460 generates an error position signal EPS (the error position signal EPS indicates the position of the error bit in the read data RMD) to provide the error position signal EPS to the data corrector 470 when not all bits of the syndrome SDR are "0". In addition, when the read data RMD includes an error bit, the error locator 460 provides an error generation signal EGS to the control logic circuit 210.

[0172] The data corrector 470 receives the read data RMD, corrects the error bit in the read data RMD based on the error position signal EPS when the read data RMD includes an error bit, and outputs the corrected main data C_MD.

[0173] Figure 18 and Figure 19 respectively show Figure 14 the error distribution in the first bank array in

[0174] Referring to Figure 18 , each of the regions 311a and 313a of the first bank array 310a includes a transient error bit EB, and the region 312a of the first bank array 310a includes a permanent error bit PEB. Therefore, the control logic circuit 210 controls the ECC engine 400 such that the ECC engine 400 performs an ECC operation on the regions 311a and 313a (ECC on), and the ECC engine 400 skips ECC encoding and ECC decoding of the sub - pages in the region 312a (ECC off).

[0175] Referring to Figure 19 , each of the regions 311b and 313b of the first bank array 310b includes a transient error bit EB, and the region 312b of the first bank array 310b includes transient error bits EB whose number is equal to or greater than M. Therefore, the control logic circuit 210 controls the ECC engine 400 such that the ECC engine 400 performs an ECC operation on the regions 311b and 313b (ECC on), and the ECC engine 400 skips ECC encoding and ECC decoding of the sub - pages in the region 312b (ECC off). If the ECC engine 400 does not skip ECC encoding and ECC decoding of the sub - page or memory cell row (page) with a permanent fault, the permanent fault cannot be notified to the memory controller 100, and a permanent single - bit error may propagate as an uncorrectable error.

[0176] Figure 20 is a flowchart showing a method of operating a semiconductor memory device according to some example embodiments.

[0177] Referring Figures 2 to 20 , a method of operating a semiconductor memory device 200 is provided, the semiconductor memory device 200 including a memory cell array 300 having a plurality of memory cell rows. In this method, the ECC engine 400 sequentially performs ECC decoding on one or more sub - pages of a target page in a read operation or a scrub operation (S110). When an error bit is detected as a result of the ECC decoding, the ECC engine 400 provides an error generation signal EGS to the control logic circuit 210, and the control logic circuit 210 records error information EINF in the error information register 580 (S120).

[0178] The control logic circuit 210 controls the ECC engine 400 to skip ECC encoding and ECC decoding of sub - pages or memory cell rows (selected memory regions) having a permanent fault by referring to the error information EINF in the error information register 580 (S130).

[0179] The control logic circuit 210 controls the error information register 580 such that the error information associated with the selected memory region is transmitted to the memory controller (S140). The memory controller 100 may determine an error management strategy for sub - pages or memory cell rows having a permanent fault based on the transmitted error information associated with the selected memory region (e.g., the selected at least one memory cell row).

[0180] Figure 21 is a block diagram showing a semiconductor memory device according to some example embodiments.

[0181] Referring Figure 21 , the semiconductor memory device 600 may include a first group of dies 610 and a second group of dies 620, which are configured to provide soft error analysis and correction functions in a stacked chip structure. Each die as described herein may refer to a portion (e.g., a block) of semiconductor material on which a given portion (e.g., a functional circuit) of the semiconductor memory device 600 is fabricated. In some example embodiments, the semiconductor memory device 600 may include and / or be configured to implement some or all of any example embodiments of the semiconductor memory device 200 as described herein. As described herein, it will be understood that any portion of the semiconductor memory device 200 may be implemented in part or in whole by one or more dies (e.g., any one of dies 610 and / or 620 of the semiconductor memory device 600), where the one or more dies will be understood to include portions and / or blocks of semiconductor material fabricated to include one or more instances of an integrated circuit, where the integrated circuit is configured to implement some or all of one or more portions or all portions of the semiconductor memory device 200 according to any example embodiment described herein. For example, based on discrete dies including discrete instances of integrated circuits, the discrete portions of the semiconductor memory device 200 described with reference to Figure 1 and / or Figure 2 may be implemented by the discrete dies (e.g., one or more dies 610 and / or one or more dies 620), where the discrete instances of the integrated circuit configure the discrete dies to implement the discrete portions of the semiconductor memory device 200 (e.g., the ECC engine 400, the scrub control circuit 500, the error information register 580, the control logic circuit 210, the memory cell array 300, any combination thereof, etc.).

[0182] The first group of dies 610 may include at least one logic die or buffer die 611. The second group of dies 620 may include a plurality of memory dies 620-1 to 620-p, which are stacked on the buffer die 611 and are configured to transfer data through a plurality of through-substrate via lines (e.g., through silicon via (TSV) lines (e.g., TSV line group 632 and / or parity TSV line group 634)).

[0183] At least one of the memory dies 620-1 to 620-p may include a cell core 622, which includes a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines.

[0184] The buffer die 611 may include an ECC engine 612 and an error information register 613 that stores error information (e.g., the buffer die 611 may include an integrated circuit that configures the buffer die 611 to implement the ECC engine 612 and the error information register 613 that stores error information), wherein when a transmission error is detected in the transmission data received through the TSV lines, the ECC engine 612 uses the transmission parity bits to correct the transmission error and generate error-corrected data. The buffer die 611 may also include an integrated circuit that configures the buffer die 611 to implement one or more other parts of the semiconductor memory device 200, and one or more other parts of the semiconductor memory device 200 at least include control logic circuits 210.

[0185] The ECC engine 612 may employ (e.g., implement) Figure 16 the ECC engine 400, and the error information register 613 may employ Figure 15 the error information register 580. Although not shown, the buffer die 611 may also include the above-mentioned refresh control circuit 245 and scrub control circuit 500.

[0186] The semiconductor memory device 600 may be a stacked chip type memory device or a stacked memory device that transfers data and control signals through TSV lines. The TSV lines may also be referred to as "penetrating electrodes".

[0187] The transmission error that occurs at the transmission data may be due to the noise that occurs at the TSV lines. Since the data failure due to the noise that occurs at the TSV lines can be distinguished from the data failure due to the incorrect operation of the memory die, it may be considered a soft data failure (or soft error). The soft data failure may be generated due to the transmission failure on the transmission path and can be detected and remedied by the ECC operation.

[0188] For example, when the transmission data is 128-bit data, the transmission parity bits may be set to 8 bits. However, the scope and spirit of the inventive concept are not limited thereto. The number of transmission parity bits may be increased or decreased.

[0189] From the above description, the data TSV line group 632 formed at one memory die 620-p may include 128 TSV lines L1 to Lp, and the parity check TSV line group 634 may include 8 TSV lines L10 to Lq.

[0190] The TSV lines L1 to Lp of the data TSV line group 632 and the parity check TSV lines L10 to Lq of the parity check TSV line group 634 may be connected to the microbumps MCB formed correspondingly between the memory dies 620-1 to 620-p.

[0191] At least one of the memory dies 620-1 to 620-p may include DRAM cells each including at least one access transistor and one storage capacitor.

[0192] The semiconductor memory device 600 may have a three-dimensional (3D) chip structure or a 2.5D (two and a half dimensional) chip structure to communicate with a host through a data bus B10. The buffer die 611 may be connected to the memory controller 100 through the data bus B10.

[0193] Figure 22 is a cross-sectional view of a 3D chip structure of a semiconductor memory device 600 according to some example embodiments, employing Figure 21 of.

[0194] Figure 22 FIG. shows a 3D chip structure 700 in which a host and a high bandwidth memory (HBM) are directly connected without an intervening layer.

[0195] Referring to Figure 22 , a host die 710 such as a system on chip (SoC), a central processing unit (CPU), or a graphic processing unit (GPU) may be disposed on a printed circuit board (PCB) 720 using flip chip bumps FB. Memory dies D11 to D14 may be stacked on the host die 710 to implement an HBM structure 620 as the Figure 21 memory dies in.

[0196] In Figure 22 , the buffer die 611 or the logic die of Figure 21 is omitted. However, the buffer die 611 or the logic die may be disposed between the memory die D11 and the host die 710. To implement an HBM (620) structure, through-silicon via (TSV) lines may be formed at the memory dies D11 and D14. The TSV lines may be electrically connected to micro bumps MCB placed between the memory dies.

[0197] Figure 23 is a diagram showing a semiconductor package including a stacked memory device according to some example embodiments.

[0198] Referring to Figure 23 , the semiconductor package 900 may include one or more stacked memory devices 910 and a memory controller 920.

[0199] The stacked memory device 910 and the memory controller 920 can be mounted on the insert 930, and the insert on which the stacked memory device 910 and the memory controller 920 are mounted can be mounted on the package substrate 940. The memory controller 920 can adopt (e.g., implement) Figure 1 the memory controller 100 in

[0200] In some example embodiments, one or more stacked memory devices 910 can include and / or be configured to implement some or all of any example embodiments of the semiconductor memory device 200 described herein. Each of the stacked memory devices 910 can be implemented in various forms and can be a memory device in the form of a high bandwidth memory (HBM) in which multiple layers are stacked. Thus, each of the stacked memory devices 910 can include a buffer die and multiple memory dies. The buffer die can include an ECC engine and an error information register, and each of the memory dies can include a memory cell array. Thus, each of the stacked memory devices 910 can control the ECC engine to skip ECC encoding and ECC decoding of the selected memory cell rows or some sub-pages based on the number of error occurrences, and can provide information associated with permanent faults (errors) to the memory controller 920.

[0201] Multiple stacked memory devices 910 can be mounted on the insert 930, and the memory controller 920 can communicate with the multiple stacked memory devices 910.

[0202] For example, each of the stacked memory devices 910 and the memory controller 920 can include a physical area, and communication can be performed between the stacked memory device 910 and the memory controller 920 through the physical area. Meanwhile, when each of the stacked memory devices 910 includes a direct access area, a test signal can be provided to each of the stacked memory devices 910 through conductive means (e.g., solder balls 950) mounted under the package substrate 940 and the direct access area.

[0203] Aspects of the inventive concept can be applied to a system using a semiconductor memory device that employs dynamic memory cells and an ECC engine.

[0204] The foregoing is an illustration of example embodiments and is not to be construed as a limitation thereof. Although several example embodiments have been described, those skilled in the art will readily appreciate that many modifications in the example embodiments are possible without materially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined by the claims. < / g> < / g> < / g> < / g> < / g>

Claims

1. A semiconductor memory device, comprising: a memory cell array including a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of dynamic memory cells; an error correction code (ECC) engine circuit; an error information register; and control logic circuitry configured to control the ECC engine circuit, wherein the control logic circuitry is configured to control the ECC engine circuit such that the ECC engine circuit generates an error generation signal based on performing a first ECC decoding on a first sub-page in at least one first memory cell row during a scrub operation on the at least one first memory cell row and based on performing a second ECC decoding on a second sub-page in at least one second memory cell row during a normal read operation on the at least one second memory cell row, wherein the control logic circuitry is further configured to record error information in the error information register and is configured to control the ECC engine circuit based on referring to the error information such that the ECC engine circuit skips an ECC encoding operation and an ECC decoding operation on at least one selected memory cell row among the at least one first memory cell row and the at least one second memory cell row, and wherein the error information at least indicates an error occurrence amount in the first memory cell row and the second memory cell row.

2. The semiconductor memory device according to claim 1, wherein the control logic circuitry is configured to control the ECC engine circuit such that the ECC engine circuit: performs a first ECC decoding operation based on reading data corresponding to a first codeword from each first sub-page in the first sub-page and based on correcting at least one error bit in the first codeword to generate a corrected first codeword, performs the scrub operation based on writing the corrected first codeword back to a memory location of the memory cell array storing each first sub-page in the first sub-page, and performs a second ECC decoding operation based on reading data corresponding to a second codeword from each second sub-page in the second sub-page, based on correcting at least one error bit in the second codeword to generate a corrected second codeword, and based on outputting the corrected second codeword.

3. The semiconductor memory device according to claim 1, wherein the control logic circuitry is configured to, while performing the scrub operation on the plurality of memory cell rows multiple times with the ECC engine circuit, in response to determining that an error occurrence amount of a first sub-page in the first memory cell row is equal to or greater than N, record an address of the first sub-page in the error information register and record the address of the first sub-page as having a permanent fault, where N is a natural number greater than 1.

4. The semiconductor memory device according to claim 3, wherein The control logic circuit is configured to control the ECC engine circuit to skip the ECC decoding operation and the ECC encoding operation on the one first sub-page in the first sub-page immediately after the control logic circuit records the one first sub-page in the first sub-page as having the permanent fault in the error information register.

5. The semiconductor memory device according to claim 1, wherein, the control logic circuit is configured to, simultaneously with the ECC engine circuit performing the scrubbing operation on the first memory cell row once, in response to determining that the error occurrence amount of the first sub-page of the first memory cell row is equal to or greater than M, record the address of the first memory cell row in the error information register and record the address of the first memory cell row as having a permanent fault, where M is a natural number greater than 1.

6. The semiconductor memory device according to claim 5, wherein, the control logic circuit is configured to control the ECC engine circuit to skip the ECC decoding operation and the ECC encoding operation on the first sub-page of the first memory cell row immediately after the control logic circuit records the first memory cell row as having the permanent fault in the error information register.

7. The semiconductor memory device according to claim 1, wherein, the control logic circuit is configured to, simultaneously with the ECC engine circuit performing the normal read operation on the second memory cell row, in response to determining that the error occurrence amount of the second sub-page of the second memory cell row is equal to or greater than M, record the address of the second memory cell row in the error information register and record the address of the second memory cell row as having a permanent fault, where M is a natural number greater than 1.

8. The semiconductor memory device according to claim 7, wherein, the control logic circuit is configured to control the ECC engine circuit to skip the ECC decoding operation and the ECC encoding operation on the second sub-page of the second memory cell row immediately after the control logic circuit records the second memory cell row as having the permanent fault in the error information register.

9. The semiconductor memory device according to claim 1, wherein: the control logic circuit is configured to: after the ECC engine circuit performs the first ECC decoding on the first memory cell row, in response to determining that the error occurrence amount of the first sub-page of the first memory cell row is equal to or greater than M, transmit the address of the first memory cell row to an external memory controller as an error information signal, where M is a natural number greater than 1; and The control logic circuit is configured to: after the ECC engine circuit performs the second ECC decoding on the second memory cell row, in response to determining that the error occurrence amount of the second sub-page of the second memory cell row is equal to or greater than M, transmit the address of the second memory cell row to the external memory controller as the error information signal.

10. The semiconductor memory device according to claim 9, wherein, the control logic circuit is configured to transmit the error information signal to the external memory controller via one of a dedicated pin or a data input / output pin.

11. The semiconductor memory device according to claim 1, further comprising: a scrub control circuit configured to generate a scrub address for at least one first memory cell row for which the scrub operation is to be performed, such that the scrub operation is performed on the at least one first memory cell row based on the scrub address specifying the at least one first memory cell row; and a refresh control circuit configured to generate a refresh row address in response to a command received from an external memory controller, so that one or more memory cell rows among the plurality of memory cell rows are refreshed, wherein the scrub control circuit is configured to count the refresh row address and generate the scrub address in response to the scrub control circuit counting K refresh row addresses in the refresh row address, and K is a natural number greater than 1.

12. The semiconductor memory device according to claim 11, wherein, the scrub control circuit is configured to sequentially generate the scrub address, and the scrub address specifies L codewords included in the first memory cell row, and L is a natural number equal to or greater than 1 and less than K.

13. The semiconductor memory device according to claim 11, wherein, the scrub control circuit includes: a counter configured to count the refresh row address to generate an internal scrub signal, wherein the counter is configured to activate the internal scrub signal in response to the counter counting the K refresh row addresses in the refresh row address; a scrub address generator configured to generate a normal scrub address associated with a normal scrub operation of the at least one selected memory cell row in a first scrub mode in response to the internal scrub signal and a scrub mode signal; and a weak codeword address generator configured to generate a weak codeword address associated with a weak scrub operation in a second scrub mode in response to the internal scrub signal and the scrub mode signal, wherein the weak scrub operation is associated with weak codewords in the at least one selected memory cell row.

14. The semiconductor memory device according to claim 13, wherein, the weak codeword address generator includes: an address storage table configured to store address information indicating corresponding addresses of the weak codewords; and a table pointer configured to generate a pointer signal providing position information associated with the address storage table in response to the internal scrub signal.

15. The semiconductor memory device according to claim 1, further comprising: A sacrifice address detector, configured to count the amount of accesses to a first memory region in the memory cell array, and to generate at least one sacrifice address specifying at least one adjacent memory region adjacent to the first memory region in response to determining that the counted amount of accesses reaches a threshold during a reference interval.

16. The semiconductor memory device according to claim 15, wherein: the sacrifice address detector is configured to provide the at least one sacrifice address to a scrub control circuit; and the scrub control circuit is configured to store the at least one sacrifice address as at least one weak codeword address in an address storage table in the scrub control circuit.

17. The semiconductor memory device according to claim 1, further comprising: a first set of dies, including at least one buffer die; and a second set of dies, including a plurality of memory dies, the plurality of memory dies being stacked on the at least one buffer die and configured to transfer data through a plurality of through-silicon via (TSV) lines, wherein at least one of the plurality of memory dies includes the memory cell array and the ECC engine circuit.

18. A semiconductor memory device, comprising: a memory cell array, including a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of dynamic memory cells; an error correction code (ECC) engine circuit; a refresh control circuit, configured to generate a refresh row address indicating one or more memory cell rows to be refreshed among the plurality of memory cell rows, a scrub control circuit, configured to count the refresh row address and generate a scrub address specifying at least one first memory cell row among the plurality of memory cell rows, an error information register, and a control logic circuit, configured to control the ECC engine circuit and the scrub control circuit, wherein the control logic circuit is configured to control the ECC engine circuit such that the ECC engine circuit generates an error generation signal based on performing a first ECC decoding on a first sub-page in the at least one first memory cell row during a scrub operation on the at least one first memory cell row among the plurality of memory cell rows, and based on performing a second ECC decoding on a second sub-page in the at least one second memory cell row during a normal read operation on the at least one second memory cell row among the plurality of memory cell rows, wherein the control logic circuit is further configured to record error information in the error information register, and is configured to control the ECC engine circuit based on referring to the error information such that the ECC engine circuit skips an ECC encoding operation and an ECC decoding operation on at least one selected memory cell row among the at least one first memory cell row and the at least one second memory cell row, and wherein the error information at least indicates an error occurrence amount in the first memory cell row and the second memory cell row.

19. A memory system, comprising: a semiconductor memory device; and A memory controller configured to control the semiconductor memory device, wherein the semiconductor memory device includes: A memory cell array including a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of dynamic memory cells; An error correction code (ECC) engine circuit; An error information register; and A control logic circuit configured to control the ECC engine circuit, wherein the control logic circuit is configured to control the ECC engine circuit to cause the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on a first sub-page in at least one first memory cell row during a scrubbing operation on the at least one first memory cell row among the plurality of memory cell rows and based on performing a second ECC decoding on a second sub-page in at least one second memory cell row during a normal read operation on the at least one second memory cell row among the plurality of memory cell rows, wherein the control logic circuit is further configured to record error information in the error information register and is configured to control the ECC engine circuit based on referring to the error information to cause the ECC engine circuit to skip an ECC encoding operation and an ECC decoding operation on at least one selected memory cell row among the at least one first memory cell row and the at least one second memory cell row, wherein the error information at least indicates an error occurrence amount in the first memory cell row and the second memory cell row, and wherein the control logic circuit is configured to transmit error information associated with the at least one selected memory cell row to the memory controller as an error information signal.

20. The memory system according to claim 19, wherein, The memory controller is configured to determine an error management strategy associated with the at least one selected memory cell row based on the transmitted error information associated with the at least one selected memory cell row.

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