Convolution interleaver, convolution interleaving method

Abstract

A convolution interleaver for performing convolution interleaving included in a time interleaver comprises: a first switch for switching a connection destination of an input of the convolution interleaver to one end of one of a plurality of branches; a FIFO memory provided in a part of the plurality of branches except one branch, the number of FIFO memories being different from each other in the part; a second switch for switching a connection destination of an output of the convolution interleaver to the other end of one of the plurality of branches; the first and second switches switch the above-mentioned connection destination when a plurality of data units equal to the number of code words per frame have passed, and the switching of the connection destination is performed by branching the connection destination by repeating a plurality of branches in sequence.

Description

[0001] The present application is a divisional application of Chinese patent application No. 201580013616.5 filed on September 10, 2015, with the invention name of “Time interleaver and time deinterleaver, as well as time interleaving method and time deinterleaving method”. Technical Field

[0002] The present invention relates to the field of digital communications, and more particularly to a time interleaver for time-interleaving a plurality of data units and a corresponding time deinterleaver. Background Art

[0003] In the past, it is known that in a transmitter equipped with a bit-interleaved coding and modulation (BICM) encoder using a quasi-cyclic low-density parity-check code (QCLDPC code) and quadrature amplitude modulation (QAM), there is a time interleaver that time-interleaves multiple data units generated by the BICM encoder, and a time deinterleaver corresponding to the time interleaver in a receiver.

[0004] As such a time interleaver and a corresponding time deinterleaver, for example, there are a hybrid interleaver that performs hybrid interleaving combining block interleaving and convolutional interleaving, and a corresponding hybrid deinterleaver described in the DVB-NGH standard book (non-patent document 1).

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: WO2010 / 061184

[0008] Non-patent literature

[0009] Non - Patent Document 1: DVB - NGH specification DVB BlueBook A160 (Draft ETSI EN303 105) "Digital Video Broadcasting (DVB); Next Generation broadcasting system to Handheld physical layer specification (DVB - NGH)", November 2012

[0010] Non - Patent Document 2: DVB - T2 implementation guidelines ETSI TS 102 831 "DigitalVideo Broadcasting (DVB); Implementation guidelines for a second generationdigital terrestrial television broadcasting system (DVB - T2)", v1.2.1, August2012

[0011] Non - Patent Document 3: DVB - C2 specification ETSI EN 302 769 "Digital VideoBroadcasting (DVB); Frame structure channel coding and modulation for a secondgeneration digital transmission system for cable systems (DVB - C2)", v1.2.1, April 2011 Summary of the Invention

[0012] A time interleaver related to one embodiment of the present invention is a time interleaver that performs time interleaving including convolution interleaving on multiple data units, and the convolution interleaver that performs the above-mentioned convolution interleaving comprises: a first switch that switches the connection destination of the input of the convolution interleaver to one end of a branch among a plurality of branches equal to the number of interleaving units configured with the interleaved data units; a FIFO (first in, first out) memory that is provided in a part of the above-mentioned multiple branches except one branch, and the number of branches in the part is different from each other; a second switch that switches the connection destination of the output of the convolution interleaver to the other end of a branch among the above-mentioned multiple branches; the above-mentioned first switch switches the above-mentioned connection destination when a plurality of data units equal to the number of code words per frame have passed through, and the switching of the connection destination is performed by sequentially repeating the above-mentioned multiple branches; the above-mentioned second switch switches the above-mentioned connection destination when a plurality of data units equal to the number of code words per frame have passed through, and the switching of the connection destination is performed by sequentially repeating the above-mentioned multiple branches. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a block diagram showing a configuration example of a communication circuit on the transmitter side including bit interleaved coding modulation.

[0014] Figure 2 This is a diagram showing an example of a schematic logical representation of data input to a time interleaver.

[0015] Figure 3A This is a diagram schematically showing an example of the logical operation of a time interleaver in compliance with the DVB-NGH standard.

[0016] Figure 3B This is a diagram schematically showing an example of the logical operation of a time interleaver in compliance with the DVB-NGH standard.

[0017] Figure 3C This is a diagram schematically showing an example of the logical operation of a time interleaver in compliance with the DVB-NGH standard.

[0018] Figure 4A This is a diagram schematically showing an example of logical operation of a time deinterleaver compliant with the DVB-NGH standard.

[0019] Figure 4B This is a diagram schematically showing an example of logical operation of a time deinterleaver compliant with the DVB-NGH standard.

[0020] Figure 4CThis is a diagram schematically showing an example of logical operation of a time deinterleaver compliant with the DVB-NGH standard.

[0021] Figure 5 This is a block diagram showing the structure of an implementation example of a time interleaver related to an embodiment of the present invention.

[0022] Fig. 6A Yes means Figure 5 A schematic diagram of an example operation of a column-row block interleaver.

[0023] Figure 6B Yes means Figure 5 A schematic diagram of an operation example of a block interleaver.

[0024] Figure 6C Yes means Figure 5 A schematic diagram of another operation example of a block interleaver.

[0025] Fig.6D Yes means Figure 5 A schematic diagram of another operation example of a block interleaver.

[0026] Fig. 6E Yes means Figure 5 A schematic diagram of an operation example of a switch on the input side of a convolutional interleaver.

[0027] Fig. 6F Yes means Figure 5 A schematic diagram of an operation example of a switch on the input side of a convolutional interleaver.

[0028] Figure 6G Yes means Figure 5 A schematic diagram of an example of the operation of a convolutional interleaver.

[0029] Figure 7 It means Figure 5 A block diagram of the structure of an installation example of a time deinterleaver corresponding to a time interleaver.

[0030] Figure 8 This is a diagram schematically showing an implementation example of a block interleaver according to an embodiment of the present invention.

[0031] Fig. 9 It is a diagram schematically showing the simulation results.

[0032] Fig.10 This is a block diagram showing the structure of another implementation example of a time interleaver related to an embodiment of the present invention.

[0033] Fig.11 It means Fig.10 A block diagram of the structure of an installation example of a time deinterleaver corresponding to a time interleaver. DETAILED DESCRIPTION

[0034] <<Research items of inventors>>

[0035] The DVB-NGH standard (Non-Patent Document 1) only describes the transmission order (sequence) of a plurality of time-interleaved data units (cells), but does not describe an actual method for generating the transmission order.

[0036] The present invention discloses a specific installation method and device of a time interleaver and a corresponding time deinterleaver.

[0037] It is needless to say that the application of the present invention is not limited to broadcasting based on DVB-NGH, the encoding method is not limited to the encoding method using QC LDPC code, and the modulation method is not limited to QAM.

[0038] Figure 1 This is a block diagram showing a configuration example of a communication circuit on the transmitter side including bit-interleaved coding and modulation (BICM).

[0039] The transmitter 100 includes an input processing unit 110 , a BICM encoder 120 , a time interleaver 130 , a modulator 140 , an RF (radio frequency) front end 150 , and an antenna 160 .

[0040] The input processing unit 110 changes the format of the input bits into blocks of a predetermined length called baseband frames. The BICM encoder 120 converts the baseband frames into a plurality of complex-valued data units and outputs them. The plurality of complex-valued data units are also processed by a circuit including at least a time interleaver 130, a modulator 140, and an RF front end 150. The time interleaver 130 performs time interleaving on the output of the BICM encoder 120 and outputs it. The modulator 140 processes the output of the time interleaver 130 using, for example, orthogonal frequency-division multiplexing (OFDM) modulation, and performs time interleaving and frequency interleaving that are usually used to improve diversity. The RF front end 150 converts the digital signal output from the modulator 140 into an analog RF (radio frequency) signal and amplifies the power of the analog RF signal. Furthermore, the RF front end 150 outputs the power-amplified analog RF signal to the antenna 160, and outputs the power-amplified analog RF signal from the antenna 160 as an electric wave.

[0041] exist Figure 1In the embodiment, a time interleaver 130 is configured between the BICM encoder 120 and the modulator 140.

[0042] The purpose of the time interleaver 130 is to mitigate burst errors. In fact, in the presence of burst errors, when multiple data units are interleaved with respect to time, a large number of data units that were originally in close proximity in the original data stream are no longer affected by the burst errors. Thus, time interleaving, for example, makes it easier to recover lost data when using a forward error correction code method.

[0043] Some time interleaving techniques are known in the art of communication systems such as DVB-C2, DVB-T2, DVB-NGH, etc. Most systems use multi-segment interleaving. The theoretical explanation behind all time interleaving methods is to reconfigure multiple data units across some code words.

[0044] For example, the time interleaving used in DVB-T2 is row-column block interleaving. Conceptually, row-column block interleaving is a method of writing multiple data units in the column direction of a matrix and reading the written multiple data units from the matrix in the row direction.

[0045] Another type of time interleaving is convolutional interleaving. Convolutional interleaving is a method of writing multiple data units into a larger FIFO (first in, first out) shift register. Convolutional interleaving uses half the memory size of block interleaving and can achieve the same time interleaving depth.

[0046] In the DVB-NGH standard (non-patent document 1), a hybrid interleaving scheme combining block interleaving and convolution interleaving is adopted in time interleaving. Conceptually, the DVB-NGH time interleaver convolves and interleaves multiple blocks each consisting of multiple data units. Among them, one block is called an interleaving unit (IU).

[0047] The combination of block interleaving and convolutional interleaving is chosen primarily to enable time-frequency-slicing (TFS), which is a promising technique for increasing multiplexing capacity.

[0048] The time interleaver 130 and its corresponding time deinterleaver are further described below.

[0049] Figure 2FIG. 1 is a schematic example of the logical representation of the data input to the time interleaver 130. Figure 2 A frame 204 is shown in FIG.

[0050] The frame 204 includes a plurality of code words 202, and each code word 202 includes a plurality of data units 201. Here, the number of code words per frame is expressed as N. FEC_TI , the number of data units per code word is expressed as N cells .exist Figure 2 In the example, N FEC_Ti =2, N cells = 12, each frame 204 includes N FEC_TI ×N cells =2×12=24 data units.

[0051] Furthermore, each frame 204 is logically divided into a plurality of interleaving units 203. Here, the number of interleaving units per frame is expressed as N. IU .exist Figure 2 In the example, N IU =3.

[0052] Figure 2 The data structure illustrated in the example is used to make it clear how the time interleaver 130 operates, and the present invention is not limited to Figure 2 The data structure shown in the example can obviously be based on N FEC_TI 、N cells 、N IU other values ​​to achieve this.

[0053] In addition, Figure 2 The smallest square in the figure corresponds to the data unit, but for the sake of simplicity in the diagram, only a part of it is assigned the label 201. In addition, the first character of the two characters in each data unit is a value temporarily assigned to identify the code word, and the second character is a value temporarily assigned to identify the data unit in each code word. In addition, the same is true in other figures.

[0054] In the DVB-NGH standard, Figure 3A - Figure 3C and Figure 4A - Figure 4C As shown, the input and output of the time interleaver 130 and the corresponding input and output of the time deinterleaver are clearly described.

[0055] Below, use Figure 3A - Figure 3C The time interleaver 130 is described below.

[0056] Figure 3AThe following is an overview of an example of the initial operation of the time interleaver 130 in compliance with the DVB-NGH standard. The initial operation of the time interleaver 130 includes a process of performing block interleaving on a code word that generates an interleaving unit.

[0057] exist Figure 3A In the example of , three consecutive input frames IN(m-2), IN(m-1), and IN(m) are shown as inputs to the delay unit 310 in the time interleaver 130. In addition, the input frames are input to the delay unit 310 in the order of IN(m-2), IN(m-1), and IN(m).

[0058] The plurality of interleaving units IU0, IU1, and IU2 of the input frames IN(m-2), IN(m-1), and IN(m) are subjected to different time delays by the delay unit 310. The time delay also includes a time delay of "0".

[0059] exist Figure 3A In the example of , each interleaving unit is subject to the following time delay.

[0060] The interleaved unit IU0 of each input frame is outputted without being delayed in the delay unit 310, as indicated by the absence of a delay line in the corresponding row.

[0061] The interleaved unit IU1 of each input frame is delayed by one interleaved unit in the delay unit 310 as indicated by the presence of one delay circuit (delay line) 310 - 11 in the corresponding row and is output.

[0062] The interleaved unit IU2 of each input frame is delayed by two interleaved units in the delay unit 310 as indicated by the presence of two delay lines 310 - 21 and 310 - 22 in the corresponding row and is output.

[0063] exist Figure 3A In the example of , the output of the delay unit 310 in the initial operation of the time interleaver 130 is represented by the intermediate frames INT(n-2), INT(n-1), IN(n), INT(n+1), INT(n+2). In addition, the intermediate frames are output from the delay unit 310 in the order of INT(n-2), INT(n-1), INT(n), INT(n+1), INT(n+2).

[0064] exist Figure 3AIn the example, only the intermediate frame INT(n) is complete, while the intermediate frames before and after it are, and the input frames not shown are input to the delay unit 310, processed by the delay unit 310, and output from the delay unit 310, thereby becoming complete.

[0065] Furthermore, the delay circuits (delay lines) 310 - 11 , 310 - 21 , and 310 - 22 in the delay unit 310 operate on a group of data units, that is, an interleaving unit, and do not operate on a single data unit like a typical convolution interleaver.

[0066] Figure 3B and Figure 3C The second operation of the time interleaver 130 according to the DVB-NGH standard is schematically shown. The second operation of the time interleaver 130 includes stacking a plurality of interleaving units 203 horizontally from left to right for each intermediate frame and then reading out the data units in the row direction.

[0067] In more detail, regarding the intermediate frame INT(n), if Figure 3B As shown, the interleaving units IU0, IU1, and IU2 are stacked horizontally from left to right by the stacking unit 320 in the time interleaver 130. Then, as shown in FIG. Figure 3C As shown, the data units of the accumulated interleaving units IU0, IU1, and IU2 are read out row by row by the reading unit 330 in the time interleaver 130 and output. Figure 3C The output string OUT(n) in indicates that the data units are output in the order of 40, 50, 24, ..., 19, 42, ..., 37, 0B, 1B.

[0068] It can be seen how in the output string OUT(n) multiple data units are advantageously spread out more widely in the codeword within the time interleaving depth. This is achieved by the stacking action performed by the stacking unit 320.

[0069] When a data unit stream corresponding to the output string OUT(n) is received in a receiver, the time deinterleaver of the receiver performs the opposite actions to those described for the time interleaver 130. In summary, a plurality of data units are divided into a plurality of interleaved units, which are stacked vertically from top to bottom in order to reconstruct a frame, and are further delayed in time.

[0070] Below, use Figure 4A - Figure 4C Document the time deinterleaver.

[0071] Figure 4A and Figure 4BThe following is an overview of an example of the initial operation of the time deinterleaver compliant with the DVB-NGH standard. The initial operation of the time deinterleaver includes receiving processing of the input stream IN(n) corresponding to the output stream OUT(n) output from the time interleaver 130 on the transmitter side.

[0072] like Figure 4A As shown, multiple data units of the input stream IN(n) are input to the separation unit 410 in the order of 40, 50, 24, ..., 19, 42, ..., 37, 0B, 1B, and are reconstructed into interleaved units by the separation unit 410.

[0073] like Figure 4B As shown, a plurality of interleaved units are input to the de-piling unit 420 and reconstructed into frames by the de-piling unit 420.

[0074] Figure 4C An outline of an example of the second operation of the time deinterleaver compliant with the DVB-NGH standard is shown.

[0075] exist Figure 4C In the example of , five consecutive intermediate frames, such as INT(n-2), INT(n-1), INT(n), INT(n+1), and INT(n+2), are shown as inputs to the delay unit 430 in the time deinterleaver. In addition, the intermediate frames are input to the delay unit 430 in the order of INT(n-2), INT(n-1), INT(n), INT(n+1), and INT(n+2). In addition, for the convenience of explanation, some intermediate frames are incomplete in the figure.

[0076] The delay unit 430 applies a time delay opposite to the time delay of the delay unit 310 to the plurality of interleaving units. Figure 4C In the example, the delay unit 430 applies a delay of two interleaving units to the interleaving unit IU0 of each intermediate frame, as indicated by the presence of two delay circuits (delay lines) 430-01 and 430-02 in the corresponding row, and outputs the result. The delay unit 430 applies a delay of one interleaving unit to the interleaving unit IU1 of each intermediate frame, as indicated by the presence of one delay circuit (delay line) 430-11 in the corresponding row, and outputs the result. The delay unit 430 does not apply a delay to the interleaving unit IU2 of each intermediate frame, as indicated by the absence of a delay circuit (delay line) in the corresponding row, and outputs the result.

[0077] Through the above processing, the frames OUT(p), OUT(p+1), and OUT(p+2) corresponding to the originally transmitted frames IN(m-2), IN(m-1), and IN(m) are restored.

[0078] However, the above description of the time interleaver and the time deinterleaver is only a logical description of the operation of the devices and methods of the time interleaver 130 and the time deinterleaver. Their implementation and installation do not necessarily use the described units 310-330 and units 410-430, and can be obtained by some methods. In particular, the data configuration and data movement in the defined two-dimensional matrix are only selected to simplify the understanding of the time interleaving process and the time deinterleaving process, such as configuring the defined two-dimensional matrix to different interrelated spatial positions. In the preferred implementation and installation, the physical recording of data can also be systematized in a memory with a two-dimensional array structure, but the data does not necessarily have to be physically reconfigured as described above, and can also be simply logically reconfigured, for example, using an appropriate addressing scheme.

[0079] The present invention provides a method for realizing and installing the above-mentioned time interleaving and time deinterleaving, which is accompanied by a reduction in the use of resources, preferably accompanied by a reduction in the use of memory in a time deinterleaver. The reduction in the use of memory in the time deinterleaver is effective because the time interleaver is sometimes mounted in a small and potentially portable electronic device, and the reduction in memory also effectively leads to a reduction in size and cost.

[0080] The following describes the time interleaving and time deinterleaving related to this.

[0081] <<Implementation Method>>

[0082] Figure 5 The structure of an implementation example of a time interleaver related to an embodiment of the present invention is shown. Figure 5 The time interleaving performed by the time interleaver is a hybrid interleaving that combines block interleaving and convolutional interleaving.

[0083] The time interleaver 500 includes a row-column block interleaver (BI0) 510, a block interleaver (BI1) 520, and a convolution interleaver 530. The convolution interleaver 530 logically includes a switch 540, a memory unit (M 1，0 、M 2，0 、M 2，1 )545-11, 545-21, 545-22 and switch 550. The output of the row-column block interleaver 510 is connected to the input of the block interleaver 520, and the output of the block interleaver 520 is connected to the input of the convolutional interleaver 530.

[0084] but, Figure 5It is only a logical display. Although the time interleaver 500 is not physically implemented, that is, it does not have a physical switch, it is obvious to a technician in this technical field that it can be implemented using, for example, a memory and a processor.

[0085] The following, Figure 5 The row-column block interleaver 510 is described.

[0086] The row-column block interleaver 510 includes cells / N IU Equal number of rows and N IU A matrix with equal number of columns. IU is the number of interleaving units per frame, N cells is the number of data units per code word. Figure 2 In the case of a frame structure, N cells =12, N IU =3.

[0087] exist Fig. 6A N cells =12, N IU =3 when the row-column block interleaver 510 is installed. Fig. 6A In the example of , 12 data units of the first code word are input to the row-column block interleaver 510 in the order of 00, 01, 02, ..., 09, 0A, 0B.

[0088] according to Fig. 6A It can be seen that the data units 00-0B are written in the column direction of the matrix in the order of their input by the row-column block interleaver 510, and after being written, they are read out from the row direction of the matrix. As a result, the 12 data units of the first code word are output from the row-column block interleaver 510 in the order of 00, 04, 08, 01, 05, 09, 02, 06, 0A, 03, 07, 0B.

[0089] It will be apparent to a person skilled in the art that the row-column block interleaver 510 can be advantageously implemented and installed using linear memory blocks operating with an addressing scheme such as that used in the installation instructions for DVB-T2 (non-patent document 2) or described in patent document 1. In addition, non-patent document 2 and patent document 1 are fully incorporated into the present application.

[0090] In particular, the row-column block interleaver keeps track of the memory locations from which the next data unit is read and reuses these memory locations for writing incoming data units. In detail, the address a of the i-th element of the j-th time interleaved block is (i，j)The calculation is based on the following equations 1 and 2. In addition, the j-th time interleaved block and the i-th element are respectively equivalent to the N-th element described above. cells (in Figure 2 In the case of a frame structure, it is each code word of 12) data units and the i-th data unit of each code word.

[0091] [Formula 1]

[0092] a (i，j) =(a (i-1，j) +k (j) )mod M+(a (i-1，j) +k (j) )div M

[0093] Here, k (0) =1, a (0，j) =0, M = Nr × Nc.

[0094] Where Nr is the number of rows and Nc is the number of columns. In addition, if j = 0, ..., then each time a code word is input, it increases by 1, i = 0, ..., N cells-1 -1(in Figure 2 In the case of the frame structure, Nr and Nc are respectively equivalent to N described above. cells / N IU (exist Figure 2 In the case of a frame structure, it is 12 / 3=4), N IU (exist Figure 2 In the case of frame structure, it is 3).

[0095] In the row-column block interleaver 510 at the transmitter side, k (j) Calculate using the following formula 2.

[0096] [Formula 2]

[0097] k (j) =(k (j-1) ×Nr)mod M+k (j-1) div Nc

[0098] The advantage of this method is that data units can be read and written through one cache, without using two caches to switch between the write action and the read action. This allows a block of linear RAM (random access memory) to be used for row-column block interleaving and row-column block deinterleaving based on similarity. In this regard, the memory size of the actual row-column block interleaver and the row-column block deinterleaver can be made the same in conceptual size. For example, in order to perform row-column block interleaving or row-column block deinterleaving of a frame consisting of 12 data units, a memory block with a memory space of 12 data units can be used.

[0099] The following, Figure 5 The block interleaver 520 is described.

[0100] The block interleaver 520 includes cells An equal number of rows and N FEC_TI A matrix with equal number of columns. cells is the number of data units per code word, N FEC_TI is the number of code words per frame. Figure 2 In the case of a frame structure, N cells =12, N FEC_Ti =2. In addition, the block interleavers 520A and 520B described later also include cells Equal number of rows and N FEC_TI A matrix of equal number of columns.

[0101] exist Figure 6B N cells =12, N FEC_Ti =2 is an example of an implementation of the block interleaver 520. Figure 6B In the example of , the 12 data units of the first codeword in one frame are input to the block interleaver 520 in the order in which they are output from the row-column block interleaver 510, here in the order of 00, 04, 08, ..., 03, 07, 0B. Then, the 12 data units of the next codeword in the one frame are input to the block interleaver 520 in the order in which they are output from the row-column block interleaver 510, here in the order of 10, 14, 18, ..., 13, 17, 1B.

[0102] like Figure 6BAs shown, the data units 00-0B of the initial codeword are written in the column direction of the matrix by the block interleaver 520 in the order of being output by the row-column block interleaver 510. The data units 10-1B of the subsequent codeword are written in the column direction of the matrix by the block interleaver 520 in the order of being output by the row-column block interleaver 510. The data units 00-0B and 10-1B written into the matrix are read out from the row direction of the matrix by the block interleaver 520. As a result, the 24 data units of the first frame are output from the block interleaver 520 in the order of being recorded 00, 10, 04, ..., 19, 02, ..., 17, 0B, 1B.

[0103] In this case, the block interleaver 520 operates as a row-column block interleaver like the row-column block interleaver 510. Therefore, the same considerations made for the row-column block interleaver 510 are also applicable to the implementation and implementation of the addressing scheme described in Formulas 1 and 2. In addition, when applied to the block interleaver 520, the j-th time interleaving block and the i-th element are respectively equivalent to the N-th time interleaving block described above. FEC_TI ×N cells (in Figure 2 In the case of a frame structure, each frame has 2×12=24 data units and the i-th data unit of each frame, such as j=0, ..., so that each time a frame is input, it increases by 1, i=0, ..., N FEC_TI ×N cells－1 (exist Figure 2 In the case of a frame structure of 2×12-1=23), Nr and Nc are respectively equivalent to N described above. cells (exist Figure 2 In the case of a frame structure, 12) and N FEC_TI (exist Figure 2 In the case of frame structure, it is 2).

[0104] Next, another implementation example of the block interleaver (BI1) in the time interleaver 130 is described.

[0105] exist Figure 6C Indicates Figure 6B The numerical example of the same case, that is, N cells =12, N FEC_Ti =2 is another implementation example of the block interleaver (BI1). However, in Figure 6C In FIG. 1 , the block interleaver (BI1) is represented as block interleaver 520A. In addition, Figure 6C The input data unit in Figure 6B The input data units are the same as in .

[0106] In the present invention, where reference is made to the block interleaver 520 , it is apparent that the block interleaver 520A can be implemented and installed in addition to the block interleaver 520 .

[0107] like Figure 6C As shown, the 12 data units 00-B of the initial code word are written into the matrix by the block interleaver 520A in the order in which they are output by the row-column block interleaver 510. The data unit 10-1B of the following code word is written into the matrix by the block interleaver 520A in the order in which they are output by the row-column block interleaver 510. However, the data units 00-0B and 10-1B are not written in the column direction as in the block interleaver 520, but are written diagonally. Furthermore, the data units 00-0B and 10-1B written into the matrix are read out from the row direction of the matrix by the block interleaver 520A in the same manner as the block interleaver 520. As a result, as shown in FIG. Figure 6C As shown, 24 data units of one frame are output from the block interleaver 520A in the order of 00, 1B, 10, ..., 09, 02, ..., 13, 17, 0B.

[0108] It will be apparent to those skilled in the art that the implementation and installation of the block interleaver 520A can be advantageously achieved using linear memory blocks operating with an addressing scheme such as that used in the DVB-C2 standard book (Non-Patent Document 3), which is also fully incorporated by reference in this application.

[0109] In particular, the block interleaver keeps track of the memory locations from which the next data unit is read and reuses these memory locations for writing incoming data units. In detail, the address a of the i-th element of the j-th time interleaved block is (i，j) The calculation is based on the following formula 3. In addition, the j-th time interleaved block and the i-th element are respectively equivalent to the N-th element described above. FEC_TI ×N cells (in Figure 2 In the case of a frame structure of , it is each frame of 2×12=24 data units and the i-th data unit of each frame.

[0110] [Formula 3]

[0111] a (i，j) =Nc×r (i，j) +c (i，j)

[0112] here,

[0113] i=0,....,Nr×Nc-1

[0114] c (i，j) =mod(i,Nc)

[0115] s(i，j) =mod(j×c (i，j) , Nr)

[0116] r (i，j) =mod(floor(i / Nc)-s (i，j) , Nr)

[0117] Where Nr is the number of rows, Nc is the number of columns, such as j = 0, ..., so that each time a frame is input, it increases by 1, i = 0, ..., N FEC_TI ×N cells -1(in Figure 2 In the case of a frame structure of 2×12-1=23), Nr and Nc are respectively equivalent to N described above. cells (exist Figure 2 In the case of a frame structure, 12) and N FEC_TI (exist Figure 2 In the case of frame structure, it is 2).

[0118] Next, another implementation example of the block interleaver (BI1) in the time interleaver 130 is described.

[0119] exist Fig.6D Indicates Figure 6B In the case of the same numerical example, N cells =12, N FEC_Ti =2 is another implementation example of the block interleaver (BI1). However, in Fig.6D In FIG. 5 , the block interleaver (BI1) is represented as block interleaver 520B. In addition, it is assumed that Fig.6D The input data unit in Figure 6B The input data units are the same as in .

[0120] In the present invention, where reference is made to the block interleaver 520 , it is apparent that the block interleaver 520B can be implemented and installed in addition to the block interleaver 520 .

[0121] like Fig.6D As shown, the 12 data units 00-0B of the initial codeword are written in the column direction of the matrix by the block interleaver 520B in the order of being output by the row-column block interleaver 510. The data unit 10-1B of the subsequent codeword is written in the column direction of the matrix by the block interleaver 520B in the order of being output by the row-column block interleaver 510. However, before the data unit is read out, the block interleaver 520B performs a row twisting process. After the row twisting, the data units 00-0B and 10-1B are read out from the row direction of the matrix by the block interleaver 520B.

[0122] In another description, the data unit 00-0B of the code word is written in the column direction of the matrix, and the data unit 10-1B of the next code word is written in the column direction of the matrix. Then, the data units 00-0B and 10-1B written in the matrix are read diagonally from the matrix.

[0123] Results, such as Fig.6D As shown, 24 data units of one frame are output from the block interleaver 520B in the order of 00, 14, 08, ..., 1B, 04, ..., 17, 0B, 10.

[0124] The implementation and implementation of the block interleaver 520B can be advantageously obtained using a linear memory block that operates by an addressing scheme that keeps track of the memory location where the next data unit is to be read out and reuses these memory locations for writing incoming data units. In detail, the address a of the i-th element between the j-th time blocks (i，j) The calculation is based on the following formula 4. In addition, the j-th time interleaved block and the i-th element are respectively equivalent to the N included in the above description. FEC_TI ×N cells (in Figure 2 In the case of a frame structure of , it is each frame of 2×12=24 data units and the i-th data unit of each frame.

[0125] [Formula 4]

[0126]

[0127] Where Nr is the number of rows, Nc is the number of columns, and Nr and Nc are equivalent to N described above. cells (exist Figure 2 In the case of a frame structure, 12) and N FEC_TI (exist Figure 2 In the case of frame structure, it is 2).

[0128] The block interleavers 520A and 520B have the advantage of complementing or replacing the data unit interleaver. If not, they have the advantage of being arranged before the row-column block interleaver 510, so they are better than the block interleaver 520. In particular, in DVB-NGH, the data unit interleaver is required to be before the row-column block interleaver 510 in order to perform quasi-random rearrangement of data units within a codeword. By using the block interleavers 520A and 520B, the data unit interleaver can be omitted.

[0129] The following, Figure 5 The convolution interleaver 530 is described.

[0130] Switches 540 and 550 are in N FEC_TIAfter the data units pass through, the connection destination position is moved by one. The number of connection switch positions is the number of branches in the convolution interleaver 530 and the number of interleaving units N. IU equal.

[0131] exist Fig. 6E means the above example Figure 2 In the case of a frame structure of N cells =12, N FEC_Ti =2, N IU =3, the first three steps of the switch 540 and the respective output data units, in Fig. 6F The following three steps and their respective output data units are shown in . However, Fig. 6E , Fig. 6F In the example, it is used as an input data unit. Figure 6B As shown, the output data units of the block interleaver 520, 24 data units of one frame, arrive at the switch 540 in the order of 00, 10, 04, ..., 19, 02, ..., 17, 0B, 1B.

[0132] according to Fig. 6E , Fig. 6F It can be seen that if N FEC_Ti =2 data units pass through, the switch 540 moves the connection destination from the uppermost or secondmost position to the lowermost position, or from the lowermost position to the uppermost position.

[0133] The data unit output from the switch 540 passes through the branch currently connected to the switch 540. The uppermost branch does not include a delay component, and the branches below the uppermost branch each add another delay component to the uppermost branch, and the delay components of 1, 2, 3, 4, etc. are included from the upper stage to the lower stage.

[0134] Each delay component M x，y Functions as a FIFO (first in, first out) shift register, including N cells / N IU ×N FEC_TI memory data unit. For example, Figure 2 In the case of frame construction, that is, in N cells =12, N FEC_Ti =2, N IU =3, each delay component M x，y Contains 12 / 3×2=8 memory data units. In addition, the delay component M x，y Equivalent to Figure 5 Memory units 545-11, 545-21, 545-22.

[0135] The data unit that has passed through each branch reaches the switch 550. And if N FEC_Ti =2 data units pass through, the switch 550 moves the connection destination from the uppermost or second-stage position to the lower-stage position, or from the lowermost stage position to the uppermost stage position.

[0136] Figure 6G The following is a schematic diagram of an operation example of the convolution interleaver 530 for the first three frames. The empty data units in the output are obtained by the storage contents in the memory units 545-11, 545-21, and 545-22 being advanced in stages. In particular, in this example, the three memory units 545-11, 545-21, and 545-22 hold 24 data units, which is three times the total of 8 data units, corresponding to the 24 empty data units in the output. From data unit 40 onwards, data units exist continuously.

[0137] It is obvious to a person skilled in the art that a circular buffer can be used to implement and install the delay line or the memory cells 545-11, 545-21, 545-22. In addition, the circular buffer has the advantage of avoiding physical copying of the memory cells. In this method, power consumption is effectively suppressed, which brings significant advantages for portable devices.

[0138] Figure 7 The structure of an implementation example of a time deinterleaver related to an embodiment of the present invention is shown. Figure 7 The time deinterleaving performed by the time deinterleaver is a hybrid deinterleaving that combines convolutional deinterleaving and block deinterleaving.

[0139] The time deinterleaver 700 includes a convolutional deinterleaver 730, a block deinterleaver (BDI1) 720, and a row-column block deinterleaver (BDI0) 710. The convolutional deinterleaver 730 logically includes a switch 740, a memory unit (M 1，0 ,M1,1,M 2，0 ) 745-01, 745-02, 745-11 and switch 750. The output of the convolutional deinterleaver 730 is connected to the input of the block deinterleaver 720, and the output of the block deinterleaver 720 is connected to the input of the row-column block deinterleaver 710. It can be seen that the time deinterleaver 700 is fully symmetrical with respect to the time interleaver 500.

[0140] The convolutional deinterleaver 730 is particularly sensitive to the number of data units held by the memory units 745-01, 745-02, and the movement speed of the switches 740 and 750, in accordance with the use of Figure 6E-6G The operation of the convolutional interleaver 530 described above operates in a substantially similar manner.

[0141] Memory cells 745-01, 745-02, 745-02 include N cells / N IU ×N FEC_TI If N FEC_TI If a data unit passes through, the connection destination is moved from the top or second position to the next position, or from the bottom position to the top position.

[0142] In addition, further detailed description is omitted here.

[0143] The following, Figure 7 The row-column block deinterleaver 710 is described.

[0144] The row-column block deinterleaver 710 includes N cells / N IU Row N IU Matrix of columns.

[0145] A memory implementation example for row-column block deinterleaver 710 is symmetrical to row-column block interleaver 510 and can be obtained by using a memory addressing scheme as follows. That is, the address a of the i-th element of the j-th time interleaved block is (i，j) The following equations 5 and 6 are used for calculation. In addition, the j-th time interleaved block and the i-th element are respectively equivalent to the N included in the above description. cells (in Figure 2 In the case of a frame structure, it is each code word of 12 data units and the i-th data unit of each code word.

[0146] [Formula 5]

[0147] a (i，j) =(a (i-1，j) +k (j) )mod M+(a (i-1，j) +k (j) )div M

[0148] Here, k (0) =1, a (0，j) =0, M = Nr × Nc.

[0149] Where Nr is the number of rows and Nc is the number of columns. If j = 0, ..., then each time a code word is input, it increases by 1, i = 0, ..., N cells-1 -1(in Figure 2 In the case of the frame structure, Nr and Nc are respectively equivalent to N described above. cells / N IU (exist Figure 2 In the case of the frame structure, it is 12 / 3=4), NIU (exist Figure 2 In the case of frame structure, it is 3).

[0150] In the row-column block deinterleaver 710 at the receiver side, k (j) The calculation is performed using the following formula 6.

[0151] [Formula 6]

[0152] k (j) =(k (j-1) ×Nc)mod M+k (j-1) div Nr

[0153] The following, Figure 7 The block deinterleaver 720 is described.

[0154] The block deinterleaver 720 includes N cells Row N IUFEC_TI Matrix of columns.

[0155] A memory implementation example of the block deinterleaver 720 is symmetrical with the block interleaver 520, and is obtained by using a memory using the addressing scheme described in Formula 5 and Formula 6 for deinterleaving addressing on the receiver side, as in the row-column block deinterleaver 710 described above. In addition, when applied to the block deinterleaver 720, the j-th time interleaving block and the i-th element are respectively equivalent to the N elements included in the above description. FEC_TI ×N cells (in Figure 2 In the case of a frame structure, there are 2×12=24 data units in each frame and the i-th data unit in each frame, such as j=0, ..., so that each time a code word is input, it increases by 1, i=0, ..., N FEC_TI ×N cells -1(in Figure 2 In the case of the frame structure, it is 2×12-1=23), and Nr and Nc are respectively equivalent to N described above. cells (exist Figure 2 In the case of a frame structure, 12) and N FEC_TI (exist Figure 2 In the case of frame structure, it is 2).

[0156] Alternatively, in the case of using the block interleaver 520A, the corresponding block deinterleaver is implemented and implemented by using the following addressing scheme. That is, the address a of the i-th element of the j-th time interleaved block is (i，j) The following formula 7 is used for calculation. In addition, the j-th time interleaved block and the i-th element are respectively equivalent to the N FEC_TI ×N cells (in Figure 2In the case of a frame structure, it is each frame of 2×12=24) data units and the i-th data unit of each frame.

[0157] [Formula 7]

[0158] a (i，j) =Nc×r (i，j) +c (i，j)

[0159] here,

[0160] i=0,…,Nr×Nc-1

[0161] c (i，j) =mod(i,Nc)

[0162] s (i，j) =mod(j×c (i，j) , Nr)

[0163] r (i，j) =mod(s (i，j) +floor(i / Nc),Nr)

[0164] Where Nr is the number of rows, Nc is the number of columns, such as j = 0, ..., so each time a code word is input, it increases by 1, i = 0, ..., N FEC_TI ×N cells -1(in Figure 2 In the case of the frame structure, it is 2×12-1=23), and Nr and Nc are respectively equivalent to N described above. cells (exist Figure 2 In the case of a frame structure, 12) and N FEC_TI (exist Figure 2 In the case of frame structure, it is 2).

[0165] Alternatively, in the case of using the block interleaver 520B, the corresponding block deinterleaver is implemented and installed by using the following addressing scheme. That is, the address a of the i-th element of the j-th time interleaving block is (i，j) The following formula 8 is used for calculation. In addition, the j-th time interleaved block and the i-th element are respectively equivalent to the N FEC_TI ×N cells (in Figure 2 In the case of a frame structure, it is each frame of 2×12=24) data units and the i-th data unit of each frame.

[0166] [Formula 8]

[0167]

[0168] Where Nr is the number of rows, Nc is the number of columns, and Nr and Nc are respectively equivalent to N described above.cells (exist Figure 2 In the case of a frame structure, 12) and N FEC_TI (exist Figure 2 In the case of frame structure, it is 2).

[0169] Next, a simplified time interleaver and a simplified time deinterleaver are described as other embodiments of the present invention. In addition, the time interleaver performs hybrid interleaving combining block interleaving and convolution interleaving, and the time deinterleaver performs hybrid deinterleaving combining block deinterleaving and convolution deinterleaving.

[0170] The row-column block interleaver 510 generates a number N of data units per code word. cells is the number of interleaving units N IU In the case where the number of cells is an integer multiple of , the conventional row-column block interleaver is used. However, in the case where this is not the case, a block interleaver that skips the following data unit and advances is required.

[0171] According to the DVB-NGH standard, L (IU，min) =floor(N cells / N IU ). Where floor(x) is the largest integer not exceeding x. large =mod(N cells , N IU ), N small =N IU -N large . Furthermore, the initial N large The interleaving unit includes L (IU，min) +1 data unit, followed by N small The interleaving unit includes L (IU，min) data units. As a result, N cells =(L (IU，min) +1)×N large +L (IU，min) ×N small .

[0172] exist Figure 8 An example of such a row-column block interleaver is shown in FIG. It can be seen that such a block interleaver cannot be directly implemented and implemented using the DVB-T2 addressing scheme described above, which inhibits the use of memory. This countermeasure requires skipping the reading of a predetermined data unit, which is large-scale and brings complex logic.

[0173] However, the inventors have realized that the row-column block interleaver 510 and the row-column block deinterleaver 710 form an outer component of the overall time interleaver circuit and the overall time deinterleaver circuit. Therefore, the row-column block interleaver 510 and the row-column block deinterleaver 710 can be simply removed from the time interleaver circuit and the time deinterleaver circuit without affecting the overall function or degrading the performance. Fig. 9 The simulation results supporting this finding are shown in .

[0174] exist Fig.10 A structural example of a corresponding time interleaver 1000 is shown in FIG.

[0175] Fig.10 The time interleaver 1000 includes a block interleaver (BI1) 1020 and a convolution interleaver 1030, and the convolution interleaver 1030 includes a switch 1040, a plurality of FIFO registers 1045, and a switch 1050. Fig.10 The square blocks in the convolution interleaver 1030 are FIFO registers 1045. In addition, the positions i (1 to N) set on the switch 1040 side are IU -1) and the position i (1 to N) on the switch 1050 side IU The FIFO register 1045 in the jth position from the switch 1040 to the switch 1050 in the branch between -1) is expressed as M i，j .

[0176] The distribution of the code words is determined by switch 1040 .

[0177] In one embodiment, switch 1040 is in N FEC－TI After data units have passed, the connection destination is moved to increase by 1 (0, 1, 2, ..., N IU -2, N IU The operation of the switch 1050 reproduces the operation of the switch 1040. That is, the switch 1050 moves the connection destination position to increase by 1 (0, 1, 2, ..., N) after NFEC-TI data units have passed. IU -2, N IU -1, 0, 1, …).

[0178] The present invention is not limited to switches 1040 and 1050 being in N FEC_TIAfter the data units pass through, the position of the connection destination is moved to increase by 1, or other increases can be performed. In the latter case, the size of each FIFO register 1045 is adjusted. For example, when the switch 1040 and the switch 1050 are switched every other jump (that is, when initially moving to all even positions 0, 2, 4, ... and then moving to all odd positions 1, 3, 5, ...), when connecting to the initial N large The initial N large Each FIFO register (Mi, j) 1045 connected at each position needs to be (L (IU，min) +1)×N FEC_TI Memory unit for data storage. In connection with the rest of the N small The switches 1040 associated with the interleaving units and the remaining N small Each FIFO register (M i，j )1045 is L (IU，min) ×N FEC_TI Memory for memory data units. The advantage is that the code word is extended to a larger time span.

[0179] For the block interleaver 1020, regardless of which block interleaver is described above, all possible implementations and implementations described specifically for the block interleavers 520, 520A, 520B can be used.

[0180] In the transmitter, each FIFO register (M i，j )1045 is the same size as the original N large interleaving units associated with i=1,...,N large -1, j = 1, ..., i is (L (IU，min) +1)×N FEC_TI Memory data unit, and the next N small Interleaving units are associated with each other, and at i=N large ,···,N IU -1, j = 1, ..., i is L (IU，min) ×N FEC_TI Memory data unit.

[0181] and Fig.10 The time deinterleaver 1100 corresponding to the time interleaver 1000 reflects the function of the time interleaver 1000. Fig.11 A structural example of the time deinterleaver 1100 is shown in FIG.

[0182] Fig.11The time deinterleaver 1100 includes a convolutional deinterleaver 1130 and a block deinterleaver (BDI1) 1120, and the convolutional deinterleaver 1130 includes a switch 1140, a plurality of FIFO registers 1145, and a switch 1150. In addition, Fig.10 The square blocks in the convolution deinterleaver 1130 are FIFO registers 1145. In addition, the positions i (0 to N) set on the switch 1140 side are IU -2) and the position i (0~N IU -2) in the branch from switch 1140 to switch 1150, the FIFO register 1045 at the kth position is expressed as M' i，i+k－1 =M' i，j .

[0183] Here, the switches 1140 and 1150 operate in correspondence with the switches 1040 and 1050. That is, the switches 1140 and 1150 operate in correspondence with the switches 1040 and 1050. FEC－TI After each data unit passes, the connection destination is switched, and the order of switching the positions is the same as that of switches 1040 and 1050. The above considerations on block deinterleaver 720 are also applicable to block deinterleaver 1120.

[0184] Depends on N cells Is it N IU Integer multiples of FIFO register (M' i，j )1145 size and the transmitter FIFO register (M i，j )1045The paired registers are different.

[0185] In particular, in N cells N IU In the case of an integer multiple of N, all FIFO registers 1145 are of the same size, that is, N cells / N IU ×N FEC_TI .

[0186] As a general conclusion, in N cells Not N IU In the case of an integer multiple of

[0187] FIFO register M' i，j The memory size for i = 0, ..., N large −1, j = i, …, N IU -2, yes (L (IU，min) +1)×N FEC_TI Memory data unit,

[0188] For i=N large ,…,N IU−2, j = i, …, N IU -2 is L (IU，min) ×N FEC_TI Memory data unit.

[0189] Block deinterleaver 1120 offsets the functionality of block interleaver 1020, as discussed in connection with block deinterleaver 720, and may be implemented by one of the block deinterleavers described above based on a block of RAM and its associated addressing scheme.

[0190] The overall communication scheme is known to only face the block interleaver and the block deinterleaver because the delay circuit is packed through the block interleaver and the block deinterleaver.

[0191] As proposed in this embodiment, the removal of the outer row-column block interleaver (BI0) 510 and the row-column block deinterleaver (BDI0) 710 will change Figure 3C The transmission order of the transmitter shown has the advantage of making implementation and installation easier.

[0192] Fig. 9 The following is an overview of simulation results comparing the performance of the DVB-NGH time interleaver with the performance of the time interleaver 1000 of the present embodiment. Fig. 9 The error curve is represented by the signal-to-noise power ratio (SNR). Fig. 9 It can be seen that the performance of the time interleaver 1000 will not be reduced by removing the outer row-column block interleaver (BI0) 510 and the row-column block deinterleaver (BDI0) 710, that is, the error curve of the time interleaver of DVB-NGH is fully consistent with the error curve of the time interleaver 1000 of this embodiment.

[0193] exist Fig. 9 The simulation results shown in include a Rayleigh burst fading channel with fixed fading bursts occurring during the center of the interleaved data unit. This is simulating the transmission of a wireless communication line with significant shielding. The fading rate (20%, 40%) is related to the time interleaving depth of the time interleaver. Furthermore, the simulation parameters are "Modulation mode: 256 non-uniform QAM", "LDPC code word length Nldpc=64800, coding rate 9 / 15", "Number of interleaving units: N IU =15", "Number of code words per interleaving unit: N FEC_Ti =8", "Number of interlaced frames: 30".

[0194] Although some embodiments have been described separately, it will be apparent to a person skilled in the art that they can be combined to obtain alternative embodiments.

[0195] <<Supplement>>

[0196] The communication method and the like related to the present invention are summarized.

[0197] (1) A first time interleaver is a time interleaver that performs time interleaving including convolution interleaving on a plurality of data units, the convolution interleaver performing the convolution interleaving comprising: a first switch that switches a connection destination of an input of the convolution interleaver to one end of a branch of a plurality of branches equal to the number of interleaving units configuring the interleaved data units; a FIFO (first in, first out) memory provided in a part of the plurality of branches other than one branch, the number of FIFOs being different from each other in the part; a second switch that switches a connection destination of an output of the convolution interleaver to the other end of a branch of the plurality of branches; the first switch switches the connection destination when a plurality of data units equal to the number of code words per frame have passed through, the connection destination being switched by sequentially repeating the plurality of branches; the second switch switches the connection destination when a plurality of data units equal to the number of code words per frame have passed through, the connection destination being switched by sequentially repeating the plurality of branches.

[0198] (2) A first time deinterleaver is a time deinterleaver that performs time deinterleaving including convolutional deinterleaving on a plurality of data units, the convolutional deinterleaver performing the convolutional deinterleaving comprising: a first switch that switches a connection destination of an input of the convolutional deinterleaver to one end of a branch of a plurality of branches equal to the number of interleaving units configuring the deinterleaved data units; a FIFO (first in, first out) memory provided in a part of the plurality of branches other than one branch, the number of FIFOs being different from each other in the part; and a second switch that switches a connection destination of an output of the convolutional deinterleaver to the other end of a branch of the plurality of branches; the first switch switches the connection destination when a plurality of data units equal to the number of code words per frame have passed through, the connection destination being switched by sequentially repeating the plurality of branches; and the second switch switches the connection destination when a plurality of data units equal to the number of code words per frame have passed through, the connection destination being switched by sequentially repeating the plurality of branches.

[0199] (3) A first time interleaving method is a time interleaving method for performing time interleaving including convolution interleaving on a plurality of data units, wherein a time interleaver for performing the time interleaving method comprises a convolution interleaver for performing the convolution interleaving; the convolution interleaver comprises: a first switch for switching a connection destination of an input of the convolution interleaver to one end of a branch of a plurality of branches equal to the number of interleaving units in which the interleaved data units are arranged; a FIFO (first in, first out) memory provided in a part of the plurality of branches other than one branch, the number of FIFOs being different from each other in the part; a second switch for switching a connection destination of an output of the convolution interleaver to the other end of a branch of the plurality of branches; the first switch switches the connection destination when a plurality of data units equal to the number of code words per frame have passed through, the connection destination being switched by sequentially repeating the plurality of branches; the second switch switches the connection destination when a plurality of data units equal to the number of code words per frame have passed through, the connection destination being switched by sequentially repeating the plurality of branches.

[0200] (4) A first time deinterleaving method is a time deinterleaving method for performing time deinterleaving including convolutional deinterleaving on a plurality of data units, wherein a time deinterleaver for performing the time deinterleaving method comprises a convolutional deinterleaver for performing the convolutional deinterleaving; the convolutional deinterleaver comprises: a first switch for switching a connection destination of an input of the convolutional deinterleaver to one end of a branch of a plurality of branches equal to the number of interleaving units configuring the deinterleaved data units; a FIFO (first in, first out) out) memory, which is provided in a part of the branches except one branch among the above-mentioned multiple branches, and the number of branches in the part is different from each other; the second switch switches the connection destination of the output of the convolution deinterleaver to the other end of a branch among the above-mentioned multiple branches; the above-mentioned first switch switches the above-mentioned connection destination when a number of data units equal to the number of code words per frame have passed, and the switching of the connection destination is performed by sequentially repeating the above-mentioned multiple branches; the above-mentioned second switch switches the above-mentioned connection destination when a number of data units equal to the number of code words per frame have passed, and the switching of the connection destination is performed by sequentially repeating the above-mentioned multiple branches.

[0201] Industrial Applicability

[0202] The present invention can be used in a time interleaver that time-interleaves multiple data units and a corresponding time deinterleaver.

[0203] Description of symbols

[0204] 100 Transmitter

[0205] 110 Input processing unit

[0206] 120 BICM encoder

[0207] 130 Time Interleaver

[0208] 140 Modulator

[0209] 150 RF front end

[0210] 160 Antenna

[0211] 310 Delay Unit

[0212] 320 stacking units

[0213] 330 Readout unit

[0214] 410 Separation Unit

[0215] 420 Destacking Unit

[0216] 430 Delay Unit

[0217] 500 Time Interleaver

[0218] 510 Row-column block interleaver

[0219] 520, 520A, 520B Block Interleaver

[0220] 530 Convolution Interleaver

[0221] 540 Switch

[0222] 545-11, 545-21, 545-22 memory unit

[0223] 550 Switch

[0224] 700 Time Deinterleaver

[0225] 710 Row-column block deinterleaver

[0226] 720 Block Deinterleaver

[0227] 730 Convolutional Deinterleaver

[0228] 740 Switch

[0229] 745-01, 745-02, 745-11 memory unit

[0230] 750 Switch

[0231] 1000 Time Interleaver

[0232] 1020 Block Interleaver

[0233] 1030 Convolution Interleaver

[0234] 1040 Switch

[0235] 1045 FIFO register

[0236] 1050 Switch

[0237] 1100 Time Deinterleaver

[0238] 1120 Block Deinterleaver

[0239] 1130 Convolutional Deinterleaver

[0240] 1140 Switch

[0241] 1145 FIFO register

[0242] 1150 Switch

Claims

1. A convolution interleaver is a convolution interleaver for interleaving a plurality of data units contained in a frame, wherein: have: an input end, the plurality of data units are input to the input end from a block interleaver, the block interleaver comprising a matrix, the matrix having N columns and used for block interleaving; An output end, outputting the multiple data units, so that the multiple data units are respectively classified into one of the M interleaving units; A circuit having M branches and a plurality of FIFO registers for delaying a plurality of data units, wherein the number of the plurality of FIFO registers arranged in the i-th branch is i, and i is 0 to N. IU -1, the FIFO register is a first-in-first-out register; a first switch disposed between the input terminal and the circuit; and a second switch, provided between the circuit and the output terminal, Where N is the number of code words per frame, IU is the number of interleaving units per frame, M and N IU equal, The first switch and the second switch are respectively connected to the same branch among the M branches, so that the input end and the output end are connected via the same branch. When N data units are input to the input end during the period when the first switch and the second switch are respectively connected to the Lth branch, the first switch and the second switch are respectively connected to the L+1th branch, where L is an integer from 1 to M-1, When N data units are input to the input end during a period in which the first switch and the second switch are respectively connected to the Mth branch, the first switch and the second switch are respectively connected to the first branch.

2. A convolution interleaving method is a convolution interleaving method for interleaving a plurality of data units contained in a frame, wherein: include: An input step of inputting the plurality of data units from a block interleaver including a matrix via a first switch to a circuit, wherein the matrix has N columns and is used for block interleaving; as well as outputting the plurality of data units from the circuit via a second switch so that the plurality of data units are respectively classified into one of the M interleaving units, The circuit has M branches and a plurality of FIFO registers for delaying a plurality of data units, the number of the plurality of FIFO registers arranged in the i-th branch is i, and i is 0 to N. IU -1, the FIFO register is a first-in-first-out register. Where N is the number of code words per frame, IU is the number of interleaving units per frame, M and N IU equal, The first switch and the second switch are respectively connected to the same branch among the M branches, When N data units are input to the circuit during the period when the first switch and the second switch are respectively connected to the Lth branch, the first switch and the second switch are respectively connected to the L+1th branch, where L is an integer from 1 to M-1. When N data units are input to the circuit during a period in which the first switch and the second switch are respectively connected to the Mth branch, the first switch and the second switch are respectively connected to the first branch.

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