Process Simulation Model Calibration Using Critical Dimension Scanning Electron Microscope

Abstract

A computer-implemented method for optimizing a process simulation model to process parameter values ​​that characterize semiconductor device manufacturing operations is disclosed, the process simulation model predicting the results of the semiconductor device manufacturing operations. The method involves generating cost values ​​using computational prediction results of the semiconductor device manufacturing operations and metrology results generated at least in part by performing the semiconductor device manufacturing operations in a reaction chamber, the reaction chamber being operated at a set of fixed process parameter values. Determination of parameters of the process simulation model may employ optimization of a pre-process profile, a resulting post-process profile of the parameters via relative profile metrology results. Cost values ​​such as optical scatterometry, scanning electron microscopy, and transmission electron microscopy may be used to guide the optimization.

Description

[0001] Incorporated by Reference

[0002] The PCT application form is filed concurrently with this specification as a part of this application. Each application to which this application claims the benefit or priority as identified in the concurrently filed PCT application form is incorporated herein by reference in its entirety and for all purposes. Background Art

[0003] The performance of semiconductor device manufacturing operations, such as plasma-assisted etching processes, is often essential to the success of semiconductor device processing workflows. However, the optimization or tuning of etching processes and / or tools associated therewith (e.g., etching reactors, photolithography masks, etc.) can be technically difficult and time-consuming, typically involving technicians manually adjusting etching process parameters or tool component designs to produce a desired target feature profile. Currently, there are no automated procedures with sufficient accuracy that can be relied upon to determine process parameter values ​​that result in a desired etching profile.

[0004] Certain models simulate the physical and / or chemical processes occurring on the surface of a semiconductor substrate during an etching process. Examples of such models include etch profile models (EPMs) implemented as behavioral models (e.g., SEMulator3D available from Coventor (a Lam Research Company) in Cary, North Carolina) or as surface reaction models; see, for example, the models of M. Kushner and colleagues and those of Cooperberg and colleagues. The former surface reaction model is described in Y. Zhang, "Low Temperature Plasma Etching Control through Ion Energy Angular Distribution and 3-Dimensional Profile Simulation," Chapter 3, dissertation, University of Michigan (2015), and the latter in Cooperberg, Vahedi, and Gottscho, "Semiempirical profile simulation of aluminum etching in a Cl2 / BCl3 plasma," J. Vac. Sci. Technol. A20 (5), 1536 (2002), both of which are incorporated herein by reference in their entirety. Additional descriptions of the etch profile model of M. Kushner and co-workers can be found in J. Vac. Sci. Technol. A 15(4), 1913 (1997), J. Vac. Sci. Technol. B 16(4), 2102 (1998), J. Vac. Sci. Technol. A 16(6), 3274 (1998), J. Vac. Sci. Technol. A 19(2), 524 (2001), J. Vac. Sci. Technol. A 22(4), 1242 (2004), J. Appl. Phys. 97, 023307 (2005), each of which is also incorporated herein by reference in its entirety. Further descriptions of Coventor's etch profile model can be found in U.S. Pat. No. 9,015,016 to Lorenz et al., filed on Nov. 25, 2008, and U.S. Pat. No. 9,659,126 to Greiner et al., filed on Jan. 26, 2015. The entire contents of each are also incorporated herein by reference in their entirety. Such models as disclosed may benefit from further development to approach the accuracy and reliability expected by the semiconductor processing industry.

[0005] The descriptions of background and context contained herein are provided only for the purpose of presenting the context of the disclosure as a whole. Many of the present inventions are the work of the inventors, and simply because such work is described in the background section or presented as context elsewhere in this article, it does not mean that it will be considered as prior art. Summary of the invention

[0006] One aspect of the present disclosure provides a computer-implemented method for optimizing a process simulation model, wherein the process simulation model predicts the results of a semiconductor device manufacturing operation from process parameter values ​​that characterize the semiconductor device manufacturing operation. The method may be characterized by including the following operations: (a) receiving current values ​​of one or more floating process model parameters to be optimized; (b) generating a configured process simulation model by providing the current values ​​of the one or more floating process model parameters to the process simulation model; (c) using the configured process simulation model to generate an operational prediction result of the semiconductor device manufacturing operation; (d) comparing the operational prediction result with a metrology result obtained from one or more substrate features, wherein the one or more substrate features are generated at least in part by performing the semiconductor device manufacturing operation, wherein the comparison base (e) generating one or more cost values ​​based on the difference between the computational prediction result and the metrology result of the semiconductor device manufacturing operation; (f) performing operation (b) again with the updated value of the current value of the one or more floating process model parameters; and (g) repeating (c)-(f) until the current value of the one or more floating process model parameters converges to generate a final value of the one or more floating process model parameters that minimizes the cost value.

[0007] In some embodiments, the process simulation model is additionally configured with a set of fixed process model parameter values ​​in (b), and the metrology results are generated by performing semiconductor device manufacturing operations in a reaction chamber operating under the set of fixed process parameter values. In some embodiments, the set of fixed process model parameter values ​​or the one or more floating process model parameters include (in in) one or more temperature values ​​in the reaction chamber, one or more RF conditions in the reaction chamber, one or more process gases in the reaction chamber, pressure in the reaction chamber, or any combination thereof.

[0008] In some embodiments, the semiconductor device manufacturing operation is a subtractive process or a material additive process. In some embodiments, the semiconductor device manufacturing operation is an etching process, a planarization process, or a deposition process.

[0009] In some embodiments, the one or more floating process model parameters include characteristics of a substrate undergoing the semiconductor device manufacturing operation, wherein the characteristics are reaction rate constants, reactant and / or product sticking coefficients, reactant diffusion constants, product diffusion constants, and / or light scattering properties. In some embodiments, the one or more floating process model parameters include vertical etch rate, lateral etch rate, nominal etch depth, etch selectivity, tilt angle of ion entry, twist angle of ion entry, visibility of entry features, angular distribution, sputtering maximum yield angle, and / or etching ratio per crystal direction. In some embodiments, the one or more floating process model parameters include a combination of any two or more characteristics of a substrate undergoing the semiconductor device manufacturing operation.

[0010] In some embodiments, generating the configured process simulation model in (b) also includes: providing a profile of the substrate to the process simulation model before the substrate undergoes the semiconductor device manufacturing operation, wherein the profile of the substrate has one or more features to be modified by the semiconductor device manufacturing operation.

[0011] In some embodiments, the method further comprises: providing, prior to (c), an initial profile of a substrate undergoing the semiconductor device manufacturing operation, whereby the computational prediction of the semiconductor device manufacturing operation generated in (c) uses the initial profile. In some embodiments, the initial profile is computationally generated using information about manufacturing steps occurring before the semiconductor device manufacturing operation. In some embodiments, the initial profile is determined by performing metrology on one or more initial substrate features, the one or more initial substrate features being generated by manufacturing steps occurring before the semiconductor device manufacturing operation.

[0012] In some embodiments, the result of a semiconductor device manufacturing operation is a signal generated by the interaction of incident electromagnetic radiation with an etched feature, a deposited feature, or a planarized feature. In some embodiments, generating the computational prediction result of the semiconductor device manufacturing operation includes the following operations: (i) using the configured process simulation model, generating a computational etch profile represented by a series of geometric profile coordinates; and (ii) generating a computed reflection or ellipsometry spectrum from the computational etch profile generated in (i) by simulating the reflection of electromagnetic radiation off the computational etch profile. In some cases, the method further includes: prior to (ii), performing profile trimming on the computational etch profile to flatten some random profile variations. In some embodiments, generating the computed reflection or ellipsometry spectrum includes performing a rigorous coupled wave analysis ("RCWA") simulation using the computational etch profile. In some embodiments, generating the computed reflection or ellipsometry spectrum involves performing a finite difference time domain ("FDTD") simulation using the computational etch profile. In some embodiments, the method further comprises: performing the semiconductor device manufacturing operation on a test substrate at the set of process parameter values ​​to produce an etched substrate; and exposing the etched substrate to incident electromagnetic radiation to produce an experimental reflectance spectrum comprising the metrology result. In some embodiments, the method further comprises generating one or more additional calculated reflectance or ellipsometry spectra. In some embodiments, the method further comprises generating the metrology result by performing reflectometry, dome scatterometry, angle-resolved scatterometry, small-angle X-ray scatterometry, and / or ellipsometry on a substrate comprising features produced by performing the semiconductor device manufacturing operation in the reaction chamber operating at the set of process parameter values.

[0013] In some embodiments, the result of the semiconductor device manufacturing operation is a profile of an etched feature, a profile of a deposited feature, and / or a profile of a planarized feature. In some embodiments, generating the computational prediction result of the semiconductor device manufacturing operation includes: using the configured process simulation model to generate a computational etching profile represented by etching profile coordinates. In some embodiments, the method may also include: performing the semiconductor device manufacturing operation on a test substrate under the set of process parameter values ​​to produce an etched substrate; and measuring the features of the etched substrate to produce experimental etching profile coordinates containing the metrology results. In some embodiments, measuring the features of the etched substrate includes performing microscopy or optical metrology on the etched substrate. In some cases, performing microscopy includes performing transmission electron microscopy (TEM) and / or scanning electron microscopy (SEM).

[0014] In some embodiments, the result of the semiconductor device manufacturing operation is a set of geometric profile parameters that characterize the geometry of etched features, deposited features, or planarized features. The geometric profile parameters may be optical critical dimension ("OCD") profile parameters. In some embodiments, generating the computational prediction result of the semiconductor device manufacturing operation includes: (i) using the configured process simulation model to generate a computational etch profile represented by a series of etch profile coordinates; and (ii) converting the computational etch profile generated in (i) into a first set of geometric profile parameters that characterize the geometry of the computational etch profile. In such an embodiment, the method may also include: performing the semiconductor device manufacturing operation on a test substrate under the set of process parameter values ​​to produce an etched substrate; measuring features of the etched substrate to produce experimental etch profile coordinates; and converting the experimental etch profile coordinates into a second set of geometric profile parameters that characterize the geometry of the etched features in the etched substrate. Additionally, in such embodiments, the one or more cost values ​​may be based on a difference between the operationally predicted results using the first set of geometric profile parameters and the metrological results using the second set of geometric profile parameters.

[0015] In some embodiments, the computational prediction results generated in (c) include a sequence of geometric profiles or profile parameters of substrate features computed from the configured process simulation model and corresponding to a time sequence representing different durations of a substrate subtractive process or a substrate additive process. In some embodiments, the metrology results of (d) include a sequence of geometric profiles or profile parameters of substrate features obtained from experimental measurements of a substrate at the different durations of the substrate subtractive process or the substrate additive process.

[0016] In some embodiments, the method further comprises: (i) configuring the process simulation model with the final values ​​of the one or more floating process model parameters from (g); and (ii) using the process simulation model configured with the final values ​​of the one or more floating process model parameters from (g) to: determine a pattern of a lithography mask; and generate the lithography mask. In some cases, generating the lithography mask comprises transferring the pattern to a resist layer. In some such cases, the method further comprises developing the resist layer and transferring the pattern to an underlying chrome layer.

[0017] In some embodiments, the method further includes: (i) configuring the process simulation model with the final values ​​of the one or more floating process model parameters from (g); (ii) utilizing the process simulation model configured with the final values ​​of the one or more floating process model parameters from (g) to: identify a design of a semiconductor processing device; and manufacture the semiconductor processing device by using the design of the semiconductor processing device.

[0018] In some embodiments, the method further includes: (i) configuring the process simulation model with the final values ​​of the one or more floating process model parameters from (g); and (ii) identifying operating conditions of a semiconductor processing device using the process simulation model configured with the final values ​​of the one or more floating process model parameters from (g) to enable manufacturing of semiconductor equipment by operating the semiconductor processing device under the operating conditions.

[0019] In some embodiments, repeating (c)-(f) includes: identifying a substantially local or global minimum in the one or more cost values ​​obtained. In some embodiments, the method further includes obtaining the metrology results by performing in-situ metrology within the reaction chamber, non-destructive independent metrology outside the reaction chamber, and / or independent destructive metrology outside the reaction chamber.

[0020] In some embodiments, generating the computational prediction results includes: using the configured process simulation model to calculate local reaction rates at a grid of a plurality of points representing a feature profile on a semiconductor substrate. In some embodiments, the step of calculating the local reaction rates using the configured process simulation model calculates the reaction rate as a function of time.

[0021] Another aspect of the present disclosure relates to a computer program product comprising a non-transitory computer-readable medium on which instructions are provided for causing a computing system to execute an optimized process simulation model, the optimized process simulation model calculating the results of the semiconductor device manufacturing operation from process parameter values ​​that characterize the semiconductor device manufacturing operation. The instructions include instructions for the following operations: (a) receiving process parameter values ​​as input to the optimized process simulation model; (b) executing the optimized process simulation model using the process parameter values; and (c) outputting the calculation results of the semiconductor device manufacturing operation. In some embodiments, the optimized process simulation model is optimized by one of the above methods. For example, a process simulation model is optimized by: (i) receiving current values ​​of one or more floating process model parameters to be optimized, (ii) generating a configured process simulation model by providing the current values ​​of the one or more floating process model parameters and a set of fixed process model parameter values ​​to the process simulation model, (iii) generating an operational prediction result of the semiconductor device manufacturing operation using the configured process simulation model, and (iv) comparing the operational prediction result of the semiconductor device manufacturing operation with metrology results obtained from one or more substrate features, the one or more substrate features being at least partially determined by the reaction chamber operating under the set of fixed process parameter values. (v) using the one or more cost values ​​and / or convergence check to generate updated values ​​of the current values ​​of the one or more floating process model parameters, (vi) performing operation (ii) with the updated values ​​of the current values ​​of the one or more floating process model parameters, and (vii) repeating (iii)-(vi) until the current values ​​of the one or more floating process model parameters converge to generate final values ​​of the one or more floating process model parameters that minimize the cost values.

[0022] The process simulation model associated with the computer program product can be optimized by any of the above operations in the method of optimizing the process simulation model aspect of the present disclosure. In some embodiments, the instructions also include instructions for the following operations: before (b), receiving an initial profile of a substrate undergoing the semiconductor device manufacturing operation.

[0023] In some embodiments, the one or more floating process model parameters include vertical etch rate, lateral etch rate, nominal etch depth, etch selectivity, tilt angle of ion entry, twist angle of ion entry, visibility of entry features, angular distribution, sputtering maximum yield angle, and / or etch ratio per crystal direction. In some embodiments, (ii) generating a configured process simulation model further comprises: providing a profile of the substrate to the process simulation model before the substrate undergoes the semiconductor device manufacturing operation, wherein the profile of the substrate has one or more features to be modified by the semiconductor device manufacturing operation.

[0024] In some embodiments, the result of a semiconductor device manufacturing operation is a signal generated by the interaction of incident electromagnetic radiation with an etched feature, a deposited feature, or a planarized feature. In some embodiments, generating the computational predicted result of the semiconductor device manufacturing operation includes: using the configured process simulation model, generating a computational etch profile represented by a series of geometric profile coordinates; and from the computational etch profile, generating a computational reflectance or ellipsometry spectrum by simulating reflection of electromagnetic radiation off the computational etch profile. In some embodiments, the optimized process simulation model is additionally optimized by: performing the semiconductor device manufacturing operation on a test substrate under the set of process parameter values ​​to produce an etched substrate; and exposing the etched substrate to incident electromagnetic radiation to produce an experimental reflectance spectrum containing the metrology result.

[0025] In some embodiments, the optimized process simulation model is additionally optimized by: generating the metrology results by performing reflectometry, dome scatterometry, angle-resolved scatterometry, small-angle X-ray scatterometry, and / or ellipsometry on a substrate, the substrate comprising features generated by performing the semiconductor device manufacturing operation in the reaction chamber operating under the set of process parameter values. In some embodiments, generating the operational prediction results of the semiconductor device manufacturing operation includes: using the configured process simulation model to generate an operational etch profile represented by etch profile coordinates. In some such embodiments, the optimized process simulation model is additionally optimized by: performing the semiconductor device manufacturing operation on a test substrate under the set of process parameter values ​​to produce an etched substrate; and measuring features of the etched substrate to produce experimental etch profile coordinates comprising the metrology results.

[0026] In some embodiments, the result of the semiconductor device manufacturing operation is a set of geometric profile parameters that characterize the geometry of etched features, deposited features, or planarized features. In some such embodiments, the geometric profile parameters are optical critical dimension ("OCD") profile parameters. In some embodiments, generating the computational prediction results of the semiconductor device manufacturing operation includes: using the configured process simulation model, generating a computational etch profile represented by a series of etch profile coordinates; and converting the computational etch profile into a first set of geometric profile parameters, the first set of geometric profile parameters characterizing the geometry of the computational etch profile. In some embodiments, the optimized process simulation model is additionally optimized by the following operations: performing the semiconductor device manufacturing operation on a test substrate under the set of process parameter values ​​to produce an etched substrate; measuring the features of the etched substrate to produce experimental etch profile coordinates; and converting the experimental etch profile coordinates into a second set of geometric profile parameters, the second set of geometric profile parameters characterizing the geometry of the etched features in the etched substrate.

[0027] In some embodiments, the instructions further include instructions for using the calculation results to determine the pattern of a photolithography mask. In some embodiments, the instructions further include instructions for using the calculation results to identify the design of a semiconductor processing device. In some embodiments, the instructions further include instructions for using the calculation results to identify operating conditions of a semiconductor processing device to enable the manufacture of semiconductor equipment by operating the semiconductor processing device under the operating conditions.

[0028] Another aspect of the present disclosure relates to a system comprising the above-mentioned computer program product and a lithography mask generation device, the lithography mask generation device being configured to determine a lithography mask pattern using the calculated results of semiconductor device manufacturing operations. A process simulation model associated with this system can be optimized by any of the above-mentioned operations in the method for optimizing the process simulation model aspect of the present disclosure.

[0029] Another aspect of the present disclosure relates to a system comprising the above-mentioned computer program product and a semiconductor processing device, the semiconductor processing device being configured to operate under process conditions provided in the calculated results of semiconductor device manufacturing operations. A process simulation model associated with the system can be optimized by any of the above-mentioned operations in the method of optimizing the process simulation model aspect of the present disclosure.

[0030] Another aspect of the present disclosure relates to methods of using a process simulation model to predict the results of a semiconductor device manufacturing operation (e.g., etching, planarizing, or depositing material), and using the results to improve the operation of the semiconductor device manufacturing operation. For example, such methods of use include generating an improved mask layout (which can be implemented in a mask), designing an improved reactor for performing the semiconductor device manufacturing operation, and / or defining a process window for the semiconductor device manufacturing operation. The process simulation model used in this aspect of the present disclosure can be optimized by any of the above operations in the method of optimizing the process simulation model aspect of the present disclosure.

[0031] These and other features will be described below with reference to the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Exemplary embodiments will now be described with reference to the accompanying drawings, in which:

[0033] Figure 1 An example of an etch profile computationally generated from an etch profile model of an etching process is shown.

[0034] Figure 2 represents an example of an etch profile similar to Figure 1 , but are calculated in this figure from experimental measurements made using one or more metrology tools.

[0035] Figure 3 An overview of a process for optimizing a process simulation model according to some embodiments is shown.

[0036] Figure 4 An embodiment of an optimization system is shown that employs a comparison of simulated and measured reflectance or ellipsometry values.

[0037] Figure 5 An embodiment of an optimization system is shown that employs a comparison of simulated and measured feature profile values.

[0038] Figure 6 An embodiment of an optimization system is shown that employs sets of "profile parameters" to potentially represent geometric features of a feature profile using fewer data points or groups of data points.

[0039] Figure 7 An exemplary computing system that may be used to optimize and / or use a process simulation model is shown.

[0040] Figure 8 An exemplary optimization system / flow using a top-down metrology tool such as a CD-SEM is shown. DETAILED DESCRIPTION

[0041] introduction

[0042] Disclosed herein are methods and / or programs for improving the utility of an etch profile model (EPM) process simulation model such as that noted above (and / or other similar models) such that the process simulation model can be used to generate a representation of a semiconductor feature profile resulting from semiconductor device manufacturing operations that has a degree of accuracy that is acceptable to the semiconductor processing industry. Overall, the disclosed methods improve the predictive capabilities of the process simulation model.

[0043] The process simulation model can simulate the "evolution" of the substrate surface profile by calculating the reaction rate or other process parameters associated with the etching process at each of many spatial locations, such as the continuous change of the etching profile of the feature when measured over time, or the time-dependent change of the feature shape at many spatial locations on the feature surface. The difference in reaction rate can arise from the etchant flux, the characteristics of the selected deposition material, the plasma conditions of the reaction chamber, or any of several other factors. Furthermore, the calculated reaction rate may fluctuate over the course of the simulated etching process. Not all process simulation models simulate the evolution during the operation of semiconductor device manufacturing, and some only predict the final profile when the reaction conditions (including the duration of the operation) and the initial feature profile are known.

[0044] In some embodiments, the output of the simulated etch profile may be a discrete set of data points (i.e., Figure 1 As shown, the contour coordinates of the spatially defined and / or otherwise mapped contour shape are represented. In addition, Figure 1 The simulation profile shown may correspond to Figure 2 The actual measured etch profile is shown, and the difference between the two profiles can be minimized. The evolution of the simulated etch profile over time depends on the modeled spatially resolved local etch rates, which in turn depend on the underlying chemistry and physics of the etching process.

[0045] Thus, profile simulations, such as those performed by EPM, may depend on a number of physical and / or chemical parameters associated with the chemical reaction mechanisms underlying the device fabrication process, as well as any physical and / or chemical parameters that may characterize the chamber environment, such as (but not limited to): temperature, pressure, plasma power, reactant flow rates, etc. Such parameters are typically under the control of the process engineer.

[0046] Process simulation models that rely on representations of surface reactions employ a set of core, or "basic" chemical and / or physical input parameters, examples of which include (but are not otherwise limited to): reaction probabilities, adhesion coefficients, ion and neutral particle fluxes, etc. The parameters may not be controllable independently of one another. Furthermore, in some process situations and / or configurations, the process engineer managing the manufacturing process may be unaware of one or more of these parameters, yet these parameters are required to run the process simulation model. Such parameters may be assumed by the literature to have some value, wherein their use results in some simplifications of the underlying physical and chemical mechanisms behind the process being modeled.

[0047] The disclosed method and / or program combines experimental techniques and data analysis methods to improve the practical industrial applicability of process simulation models for semiconductor manufacturing operations of modifying substrates.

[0048] In some embodiments, the technology disclosed herein optimizes chemical, physical, and / or behavioral input parameter values ​​(sometimes referred to as "floating" process model parameter values) used by these models and improves the prediction accuracy of the models by determining a more effective set of parameter values. Parameter optimization improves the accuracy of process simulation models in which these parameters are used, even in cases where the optimal values ​​determined for the underlying parameters may be different from the "true" or ideal physical / chemical values ​​that may be determined by the literature (or other experiments) for these parameters. The parameters to be optimized may not directly correspond to specific chemical or physical properties or mechanisms of the etching process. In some cases, they only represent parameters that allow the model to accurately predict the etching results for a given set of inputs (e.g., reactor conditions).

[0049] Process simulation models can take into account physical properties and / or measurable quantities within process equipment, as well as substrate and / or semiconductor wafer properties at the nanometer level. However, not all wafer properties can be conveniently measured directly, i.e., substrate samples often need to be cut out and / or left behind for observation and / or scanning via microscopes such as scanning electron microscopes (SEMs) and other metrology techniques.

[0050] definition

[0051] The following terms may be used intermittently throughout this specification.

[0052] In this application, the terms "semiconductor wafer", "wafer", "substrate", "wafer substrate" and "partially manufactured integrated circuit" are used interchangeably. Those skilled in the art understand that the term "partially manufactured integrated circuit" can refer to a semiconductor wafer during any of many stages of integrated circuit fabrication on a semiconductor wafer. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. This specific embodiment assumes that the implementation is implemented on a wafer. However, the disclosure is not so limited. The workpiece can have different shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can utilize the disclosed embodiments include many objects, such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical components, micromechanical devices, etc.

[0053] As used herein, "feature" is a non-planar structure on a substrate surface, which is typically a surface modified in a semiconductor device manufacturing operation. Examples of features include grooves, through holes, pads, columns, domes, etc. Features can be produced by photoresist development, mask definition, photolithography etching, photolithography deposition, epitaxial growth, mosaic deposition, etc. Features typically have an aspect ratio (depth or height to width). Examples of feature aspect ratios include at least about 1:1.05, at least about 1:1, at least about 2:1, at least about 5:1, at least about 10:1, or higher aspect ratios. In some embodiments, the feature has a width dimension (which may be a critical dimension) between about 10nm and 500nm, such as a width dimension between about 25nm and about 300nm. The feature profile may be gradually narrowed and / or include an overhang in the feature opening. A re-entrant profile is a profile that narrows from the bottom or interior of a feature to the feature.

[0054] As used herein, an "initial profile" is a profile of geometric features of a substrate surface to be processed by a semiconductor device manufacturing operation. The initial profile may have one or more features (or it may be a completely flat surface) and serves as a starting or input profile for a semiconductor device manufacturing operation, which then modifies the initial profile. The initial profile may be computationally generated using information about manufacturing steps preceding the semiconductor device manufacturing operation. Alternatively, the initial profile is generated by performing metrology on a substrate surface generated from manufacturing steps preceding the semiconductor device manufacturing operation. During the semiconductor device manufacturing operation, the substrate surface is modified from the initial profile to the final profile, either realistically or simulated.

[0055] As used herein, a "semiconductor device manufacturing operation" is a unit operation performed during the manufacture of a semiconductor device. Typically, an overall manufacturing process includes multiple semiconductor device manufacturing operations, each of which is performed in its own semiconductor manufacturing tool, such as a plasma reactor, a plating tank, a chemical mechanical planarization tool, a wet etching tool, etc. Categories of semiconductor device manufacturing operations include subtractive processes such as etching processes and planarization processes, and material additive processes such as deposition processes. In the context of each process, a substrate etching process includes a process for etching a mask layer, or more generally, a process for etching any material layer previously deposited and / or otherwise residing on the surface of a substrate. Such an etching process can etch a stack of layers in a substrate.

[0056] As used herein, a "result of a semiconductor device manufacturing operation" is a characteristic of a substrate that has undergone a semiconductor manufacturing operation. An example of such a result is a geometric profile of a substrate after a semiconductor manufacturing operation. The profile is a set of points in space that represent the location of a feature or group of features. For example, the profile may be a profile of an etched feature, a profile of a deposited feature, a profile of a planarized feature, etc. In another example, the result of a semiconductor manufacturing operation is a signal generated by the interaction of incident electromagnetic radiation with one or more substrate features (e.g., an etched feature, a deposited feature, or a planarized feature). In such an example, the result may be a reflection signal that may include, for example, a reflection amplitude as a function of wavelength and / or polarization state. The result may also be an elliptically polarized signal. In another example, the result of a semiconductor manufacturing operation is a set of profile parameters that characterize the geometry of features such as etched features, deposited features, or planarized features, such as optical critical dimension (OCD) profile parameters. Such profile parameters may characterize the overall characteristics of a feature (e.g., its average critical dimension, its sidewall angle, its depth, etc.).

[0057] The results of the semiconductor manufacturing operation can be obtained at a single point in time or at a range of multiple points in time during the semiconductor manufacturing operation. If the results are provided at only one point in time, that point in time can be the point in time when the semiconductor manufacturing operation is completed.

[0058] As used herein, "computational predictions of semiconductor device manufacturing operations" are predictions of semiconductor device manufacturing operations that are computationally generated, for example, by a computational model (e.g., a process simulation model of the device manufacturing operation under consideration). In some embodiments, the computational program calculates a predicted feature profile represented by geometric profile coordinates. In other cases, the computational program calculates a predicted optical response generated by electromagnetic radiation interacting with the predicted feature profile. In still other cases, the computational program calculates predicted geometric profile parameters of the feature profile generated by the semiconductor device manufacturing operation (e.g., a set of OCD profile parameters that characterize the geometry of the computed etching profile). In some embodiments, the feature profile, optical response, and / or profile parameters are computed as a function time (the semiconductor device manufacturing operation occurs through the function time). In some embodiments, in order to predict the results of the semiconductor device manufacturing operation, the computational program predicts the local reaction rate at a grid of multiple points representing the feature profile on the semiconductor substrate. This results in a substrate / feature profile that deviates from the initial profile used at the beginning of the operation.

[0059] In the case where a computational program calculates a predicted optical response, it can compute a reflectance spectrum or ellipsometric response by simulating the reflection of electromagnetic radiation off the computed etch profile. The reflectance spectrum or ellipsometric response can be generated using, for example, a rigorous coupled wave analysis ("RCWA") simulation or a finite difference time domain ("FDTD") simulation.

[0060] In some embodiments, the computational program generates a time series of geometric profiles or profile parameters of substrate features. In some embodiments, the computational program generates a time series of computed reflectance spectra or elliptical polarization responses generated by simulating reflections of electromagnetic radiation off the computed substrate feature profiles at different times. The time series can be generated at different durations of semiconductor device manufacturing operations. Computational prediction results of semiconductor device manufacturing operations can be provided for substrate subtractive processes and / or substrate additive processes.

[0061] The term "profile shaping" as used herein means smoothing a computed etch profile to even out some random profile variations. Profile shaping can be applied to computational predictions of semiconductor device manufacturing operations prior to another computational process, such as simulating reflections of electromagnetic radiation off the computed etch profile.

[0062] As used herein, "metrology results" means results generated at least in part by measuring features of a processed substrate. The measurement may be performed during or after a semiconductor device manufacturing operation in a reaction chamber operating under a set of fixed process parameter values. In some embodiments, the features of the processed substrate are measured to generate profile coordinates. In such an embodiment, measuring the features of the processed substrate may include performing microscopy (e.g., CD-SEM, SEM, TEM, STEM, REM, AFM), or optical metrology on the etched substrate. When optical metrology is used, the system can obtain the profile coordinates by calculating the profile coordinates from the measured optical metrology signal. In some embodiments, the metrology results are generated by converting the measured feature profile coordinates into a set of geometric profile parameters, which characterize the geometric structure (e.g., critical dimensions, sidewall angles, depth, etc.) of the features in the processed substrate. In some embodiments, the metrology results are obtained by performing reflectometry, dome scatterometry, angle-resolved scatterometry, small-angle X-ray scatterometry, and / or ellipsometry on the processed substrate. In some embodiments, the metrology results are endpoint detection for a specific process. In situ detectable endpoint detection can be measured by a number of optical techniques.

[0063] In some embodiments, metrology results are provided as a time series of measured geometric profiles, reflectance or ellipsometry data, or profile parameters of substrate features. These measured metrology results are generated at different durations of semiconductor device manufacturing operations.

[0064] As used herein, a "process simulation model" is a computational model that predicts the results of semiconductor device manufacturing operations. In other words, it outputs the results. As described, examples of results include feature profiles (e.g., detailed Cartesian coordinates of the features), profile parameters that characterize the features (e.g., critical dimensions, sidewall angles, depth, etc.), and / or reflectance / ellipsometry data generated if optical metrology is used to probe the features. These results are based on features generated or modified during the simulated semiconductor device manufacturing operations. These results can be predicted at one or more time points during the semiconductor device manufacturing operations.

[0065] The input to the process simulation model includes one or more process parameter values ​​that characterize the semiconductor device manufacturing operation. Typically, the process parameters used as input are reactor conditions such as temperature (pedestal, showerhead, etc.), plasma conditions (density, potential, power, etc.), process gas conditions (composition, partial pressure of components, flow rate, pressure, etc.), or the like. Typically, the process simulation model also receives an initial contour substrate that represents the contour of the substrate surface before being processed by the modeled semiconductor device manufacturing operation. In a simple case, the initial contour is just a flat surface. More typically, the initial contour has features such as mask or photoresist features.

[0066] Sometimes, the process simulation model simulates a subtractive process, such as a substrate etching process or a planarization process. In many embodiments, the process simulation model is an etch profile model as described herein. Sometimes, the process simulation model simulates an additive process, such as a substrate deposition process (e.g., chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.).

[0067] As used herein, a "configured process simulation model" describes a process simulation model that is configured with one or more floating process model parameters. When so configured, and after receiving input process parameters and an initial substrate profile, the process simulation model can be executed to predict the results of semiconductor device manufacturing operations.

[0068] As used herein, "process parameters" are parameters that characterize processes that occur in a reaction chamber during semiconductor device manufacturing operations, and are usually on the surface of a substrate modified by the operation. Typically, many such process parameters are required to uniquely characterize a process. Some process parameters characterize aspects of a process that are relatively easy to control and / or measure. Examples of such process parameters include temperature (of a pedestal, showerhead, etc.), plasma conditions (plasma density, plasma potential, applied power, etc.), process gas conditions (composition, partial pressure of components, flow rate, pressure, etc.), and adjustable chamber geometry parameters, such as the spacing between the pedestal and the showerhead. Other process parameters characterize processes that cannot be directly controlled and / or cannot be easily measured. Examples of such process parameters include local conditions (e.g., plasma density, direction, or energy at a certain location on the surface of a substrate), and mechanical properties (e.g., reaction rate constants, reactant and / or product adhesion coefficients, reactant diffusion constants, product diffusion constants, light scattering properties, and combinations thereof). The values ​​of process parameters are used as inputs to a process simulation model or configurations of a process simulation model. The value can be a scalar, vector, matrix, tensor, etc.

[0069] As used herein, a "fixed process model parameter" is a process parameter required by a process simulation model, but its value is fixed during an optimization procedure for improving the performance of the process simulation model. In other words, the value of the fixed process model parameter does not change during the optimization procedure. This is different from a floating process model parameter whose value changes during the optimization run. In some embodiments, the fixed process model parameter can be directly controlled and / or easily measured. Examples include the temperature in the reaction chamber, one or more applied radio frequency or plasma conditions in the reaction chamber, one or more process gas conditions in the reaction chamber, the pressure in the reaction chamber, or any combination thereof. However, the fixed process model parameter may alternatively be a local or mechanical parameter. Sometimes, for convenience in the model optimization procedure described herein, the value of a fixed process model parameter or a group of such values ​​is represented by the symbol μ.

[0070] As used herein, a "floating process model parameter" is a process parameter required by a process simulation model, but whose value is floated (changed, adjusted, etc.) during the optimization procedure. Iterative modification of the floating process model parameter from an initial or seed value to a final value is the goal of the model optimization procedure. If the optimization routine is successful, the process simulation model configured with the final value of the floating process model parameter provides better prediction capabilities than the process simulation model configured with the initial value of the floating process model parameter. Sometimes, for convenience in the model optimization procedure described herein, the value or group of values ​​of the floating process model parameter is represented by the symbol α.

[0071] In some embodiments, the floating process model parameters represent characteristics of a substrate undergoing a semiconductor device manufacturing operation. General examples include local conditions and / or mechanical properties in a reactor that are difficult to measure during a semiconductor device manufacturing operation. In some examples, the characteristics are reaction rate constants, reactant and / or product adhesion coefficients, reactant diffusion constants, product diffusion constants, local plasma properties (e.g., ion flux, ion direction, free radical flux, etc. at the substrate surface), light scattering properties, or any combination thereof. However, the floating process model parameters are not limited to such parameters. Parameters that may be more typically used as fixed process model parameters may also be used, or used as floating process model parameters, or used as part of floating process model parameters. Examples of such non-mechanical parameters include temperature in a reaction chamber, one or more RF conditions in a reaction chamber, one or more process gases in a reaction chamber, pressure in a reaction chamber, applied plasma conditions, or any combination thereof. In some embodiments, the floating process model parameters include parameters that are more globally focused on a given process, which is represented by a process simulation model. Examples of such floating process model parameters include vertical etch rate, lateral etch rate, nominal etch depth, etch selectivity, vertical deposition rate, plasma angle dependence of sputtering yield, and plasma energy dependence of sputtering yield, all for a given material undergoing a given semiconductor device manufacturing operation. Other examples of floating process model parameters include tilt angle of ion entry, twist angle of ion entry, visibility (of the entry feature) for etching and / or deposition, angular distribution (sometimes referred to as source σ), sticking coefficient (sometimes referred to as isotropic ratio), sputtering maximum yield angle, sputtering ratio, and etch ratio per crystal direction, again, all for a given material undergoing a given semiconductor device manufacturing operation.

[0072] In many embodiments, the floating process model parameter combination characterizes any two or more of the process model parameters of the substrate undergoing the semiconductor device manufacturing operation. The combination may be the product or sum of the individual values ​​of the parameters, any of which may be weighted based on the importance of the individual parameters to the predictive power of the model or based on other factors. Sometimes, some or all values ​​of the individual parameters are normalized before the combination. In some embodiments, the individual values ​​are provided as separate contributions in the form of vectors. In one example, the combination of parameters may be ion density and reaction rate with the material on the substrate. Without considering any other factors, the probability of removal will be proportional to the product of the ion density, reaction rate, substrate material density, and the surface area of ​​the original profile. Therefore, the ion density and reaction rate cannot be determined singly, but their product can be. In some cases, the floating process model parameters do not have a known connection relationship to a specific physical and / or chemical process of the device manufacturing operation. Such floating process model parameters are suitable when optimizing the behavioral process simulation model.

[0073] During the iterative optimization procedure, at any iteration, the value of the floating process model parameter is referred to as the "current value" of the floating process model parameter. The value of the parameter during the previous iteration may be referred to as the previous value of the floating process model parameter, and the value of the parameter during the subsequent iteration may be referred to as the subsequent value of the floating process model parameter. The modification of the value of the floating process model parameter from one iteration to the next iteration is sometimes referred to as an update of the current value of the floating process model parameter. At the end of the iterative optimization procedure, the value of the floating process model parameter is referred to as the final value of the floating process model parameter.

[0074] When used herein, "optimizing" a process simulation model is to improve the ability of the process simulation model to predict the results of the semiconductor device manufacturing operation that the model is designed to simulate. Generally, in the discussion here, the optimization routine optimizes the process simulation model by repeatedly adjusting the current values ​​of one or more floating process model parameters. In the case where both the predicted results and the experimental determination results are generated from the same semiconductor device manufacturing operation, during the optimization, the operational prediction results of the process simulation model using the current values ​​of the floating process model parameters can be compared with the experimental determination results (e.g., metrology results). The comparison provides a cost value (cost value) that reflects the size of the difference (or consistency) between the predicted / simulated results and the experimental determination results. The optimization routine uses the cost value to at least (i) determine whether the value of the floating process model parameter value has converged, and (ii) if the value has not converged, determine how to adjust the floating process model parameter for the next iteration. In some embodiments, the program uses not only the cost value of the current iteration, but also all or some of the cost values ​​of the historical iterations to search for the global optimal value.

[0075] When used herein, "comparing" the computational prediction results of the process simulation model with the experimental determination results (such as metrology results) means comparing one or more features or indicators of the two results. The comparison provides a cost value or multiple values ​​for the optimization process. Examples of differences (cost values) include L1 and L2 norms, Euclidean distances, and Mahalanobis distances in multidimensional result spaces. Taking the use of results with multiple features or indicators as an example, the comparison can be completed by extracting multiple indicators to describe the differences. For example, these indicators can be critical dimension (CD) differences at multiple heights of the feature, process endpoint differences (such as differences in the endpoint of an etching process), thickness differences of a given material, or spectral differences within the overall spectrum. These indicators constitute the cost function of the optimization; in the case of having weight factors for each of these indicators, the function can also be a combination of these indicators. The cost function is sometimes referred to herein as a "difference", which should be interpreted more broadly than the simple mathematical operation A minus B.

[0076] When used herein, the floating process model parameter values ​​"converge" when the process simulation model configured with the floating process model parameter values ​​is properly executed for the current application. Many convergence criteria are known in the art and can be applied. Some of them are described below. In general, the cost value is evaluated in each iteration of the optimization routine. The cost value generated during a single iteration can be evaluated separately or in combination with the cost values ​​from other iterations. Such evaluation allows the optimization routine to perform a convergence check. If the cost value or multiple cost values ​​indicate that the current value of the floating process model parameter provides a process simulation model that performs acceptably and / or no longer significantly improves, the optimization routine terminates the program and regards the current value of the floating process model parameter as the final value. The optimization routine has converged. Therefore, in some embodiments, the convergence method determines when the error of the parameter estimate can no longer be improved. This allows for a Bayesian view of the termination problem. The convergence check can search for a local or global minimum (or maximum, depending on the structure of the cost value) in the cost value. The termination of the optimization can use, for example, a stochastic gradient descent method, a batch gradient descent method, a Bayesian optimization method, etc.

[0077] Optimizer

[0078] Figure 3 An overview of an optimization procedure 300 for optimizing a process simulation model according to some embodiments is shown. The process simulation model is configured to predict outcomes of semiconductor device manufacturing operations using process parameter values ​​that characterize the semiconductor device manufacturing operations.

[0079] The method may involve receiving current values ​​of one or more floating process model parameters to be optimized at operation 302. In a first iteration, these current values ​​may be considered as initial values. Then, at operation 304, a configured process simulation model is generated by providing the current values ​​of one or more floating process model parameters, an input profile, and a set of fixed process model parameter values ​​to the process simulation model. At operation 306, an operational prediction result of a semiconductor device manufacturing operation is generated using the configured process simulation model. At operation 308, the operational prediction result of the semiconductor device manufacturing operation is compared at least in part with the generated metrology result by performing the semiconductor device manufacturing operation in a reaction chamber operating under the set of fixed process parameter values, wherein the comparison generates one or more cost values ​​based on the difference between the operational prediction result and the metrology result of the semiconductor device manufacturing operation. At operation 310, a convergence check is used to determine whether the optimization program has converged. If so, the program is indicated to be completed at 311. If not, the optimization program generates an update of the current value. See operation 312. The update may utilize the cost value, the current value of one or more floating process parameter values, and optionally one or more previous values ​​of the floating process model parameter values. At this point, process control returns to operation 304 along with the current value of the one or more floating process model parameters. Thereafter, operations 304, 306, 308, and 312 are repeated until the current value of the one or more floating process model parameters converges to produce a final value of the one or more floating process model parameters.

[0080] Figure 4 An embodiment system 400 of an optimization procedure for comparing simulated and measured reflectance or ellipsometry values ​​is shown. As indicated, the process simulation model is optimized to improve the ability of the process simulation model to predict the results (e.g., computationally generated feature profiles) of semiconductor device manufacturing operations that the model is designed to simulate. Iterative operation of the optimization system 400 involves iteratively adjusting the current value α of one or more floating process model parameters.

[0081] In some embodiments, an initial feature profile is input into a process simulation model, such as the previously discussed etch profile model (EPM), along with two types of process model parameters, represented in the figure as "α" and "μ". This input is shown as 402, and it starts the reflectance or ellipsometry comparison optimization system 400. As previously introduced, the terms "initial profile" and "initial feature profile" shown at 402 are used interchangeably and refer to spatial locations on the surface of a substrate to be processed by a semiconductor device manufacturing operation. For example, the initial profile may have one or more features (or it may be completely flat), and it serves as a starting or input profile for a semiconductor device manufacturing operation that will then modify the initial profile. The model parameters α represent one or more floating process model parameters that will be optimized over the course of the optimization process 300, and the fixed process model parameters are process model parameters that are required to execute the process simulation model but do not change over the course of the optimization process. The types of parameters used as floating and fixed process model parameters do not need to be set in stone, for example, local plasma properties such as ion flux may constitute floating model parameters in some optimization embodiments, and may constitute fixed model parameters in other optimization embodiments.

[0082] Next, after providing the initial profile and initial values ​​of parameters α and μ, the configured process simulation model is executed 404. During execution, the model adjusts the input initial profile to an output profile in a manner intended to predict the outcome of the semiconductor device manufacturing operations modeled by the process simulation model.

[0083] The execution of the process simulation model 404 and its attendant calculations and adjustments ultimately outputs an operationally generated feature profile shown by 406. This profile is the model's prediction of the outcome of the semiconductor device manufacturing operation under consideration. In the case of an etching process, the input feature profile may be a mask profile on a substrate, and the output operationally generated feature profile may be an etch profile in the substrate beneath the mask opening. However, in the case where the process simulation model models a planarization process or an additive process, the output operationally generated feature profile may be a profile of the substrate reflecting the planarization or additive process.

[0084] In some embodiments, a profile adjuster and / or profile adjustment operation (not shown) Figure 4 ) is performed on computational predictions of semiconductor device manufacturing operations prior to executing another computational procedure using the feature profile, such as prior to executing a computational procedure that simulates reflections of electromagnetic radiation off of the computed etch profile.

[0085] exist Figure 4In the depicted embodiment, the operation of a profile adjuster (if used) is performed on the computationally generated feature profile represented by 406. The profile adjuster, or profile adjustment operation, smoothes and / or otherwise reduces the effects of aberrations produced by the profile process simulation model in predicting the feature. These variations may be introduced by the stochastic behavior of the process simulation model.

[0086] In order to accurately predict the reflection pattern generated by providing incident electromagnetic radiation on the etched profile, which is the output 406 of the process simulation model, the optimization procedure employs computational tools or algorithms such as rigorous coupled wave analysis (RCWA), which assumes a certain periodicity of the etched features (e.g., features or feature regions), and further assumes the material properties of the etched substrate material and the material properties of the numerous gaps resulting from the etching. Furthermore, RCWA anticipates the predicted specific transition of a given material (i.e., a dielectric solid) to a different material (i.e., air) within an expected periodicity (i.e., a lengthwise distance defined in the art as a similar range from one feature region to the next feature region). An alternative to RCWA is the finite-difference time-domain (FDTD) technique.

[0087] The presence of non-periodic or random variations in the features may interfere with the proper operation of the RCWA method, such that the method may not accurately predict the reflectance or ellipsometry spectra produced when the variations are present.

[0088] The profile adjuster identifies and removes certain non-periodic structures from the feature. In some embodiments, the profile adjuster may determine whether to consider a deformation based on the height of the deformation.

[0089] For example, the profile adjuster may be configured to identify and consider only variants that exceed a pre-specified height. In some embodiments, "micro-bumps" (i.e., variants below a pre-specified height threshold) are discarded by the profile adjuster. Similarly, variants that exceed a pre-specified height threshold may be averaged or otherwise combined by the profile adjuster to produce an average profile prior to applying RCWA to compute the reflectance / ellipsometry spectrum.

[0090] Return to Implementation Plan Figure 4 , providing the operationally generated characteristic profile to the reflectance / ellipsometry spectrum generator 408 to output an operationally generated output reflectance / ellipsometry spectrum, represented in the figure as “R[λ] calc.For example, the reflectance / ellipsometry generator may be an algorithmic tool implementing RCWA or finite-difference time-domain (FDTD) as described herein. The reflectance / ellipsometry generator may be a standalone tool or may be implemented in a tool or a series of routines. In one example, the reflectance / ellipsometry generator is a YieldStar Spectrum Analyzer, available from ASML Netherlands BV, Veldhoven (The Netherlands). TM Scatterometer products. See, for example, Cramer et al., "High-NA optical CD metrology on small in-cell targets enabling improved higher order dose control and process control for logic", Proceedings of SPIE, 10145, Metrology, Inspection, and Process Control for Microlithography XXXI, 101451B (March 28, 2017), which is incorporated herein by reference in its entirety.

[0091] The accuracy of the computationally generated reflectance / ellipsometry spectrum depends on the predictive power of the process simulation model when configured with the current value of α. In the described procedure, the accuracy of the computationally generated reflectance / ellipsometry spectrum is calculated by comparing it to R[λ] exp The results of the real (non-computationally generated) results may be obtained as experimentally measured reflectance / ellipsometry spectra from optical metrology techniques (e.g., scatterometry and ellipsometry), as shown at 414 of the optimization system 400. The computationally and experimentally generated results are for the same detection technology (e.g., same polarization, wavelength range, incident and detection angles, etc. for optical metrology) and the same feature characteristics (e.g., CD at a specific depth, endpoint detection, deposited layer thickness, etc.).

[0092] Computational prediction result R[λ] calc And the measurement results R[λ] exp is compared (e.g., determines a difference, ratio, or other measure) by a "cost function calculator" 412 to output, for example, R[λ] exp -R[λ]calc This comparison provides a reflection of the predicted / simulated results (e.g. R[λ] calc ) and experimental determination results R[λ] exp The cost function is determined by comparing the size of the difference (or consistency) between the two. The optimization system 400 uses the cost value to at least (i) determine whether the value of the floating process model parameter has converged; and (ii) if the value has not converged, determine how to adjust the current value of the floating process model parameter for the next iteration and the adjustment amount. As previously introduced, an example of the comparison result (cost value) is a simple Euclidean distance in a multidimensional result space. In some embodiments, the cost function is determined in a result space associated with a scatter measurement tool, such as a YieldStar that provides scatter measurement results in the form of a specific image. TM Scatterometer products.

[0093] The estimator 418 employs a "convergence checker," which is an algorithm for evaluating the likely convergence of the floating process model parameter values ​​α. In some embodiments, execution of the convergence checker or estimator 418 involves identifying a substantial local or global minimum in one or more cost values ​​and / or an amount of change in α over a recent iteration. Upon determining convergence of α, the convergence checker indicates the convergence at 420, which results in output of a final or optimized value of the floating process model parameter α. As previously noted, iterative modification of the floating process model parameter values ​​from initial or seed values ​​(e.g., provided at 402) to final values ​​(e.g., output at 422) is the goal of the model optimization procedure performed by the optimization system 400. In some embodiments, iterative execution of the optimization procedure will result in a process simulation model configured with final values ​​of the floating process model parameters that provides better predictive capabilities than a process simulation model configured with, for example, initial values ​​of the floating process model parameters.

[0094] Typically, execution of the convergence checker 418 during one or more iterations of the optimization routine before the final convergence criteria are met will indicate that the cost value has not yet reached the required convergence condition. In such a case, the convergence checker adjusts the current value of α and outputs the adjusted value of α, as shown at 424. As will be appreciated by those skilled in the art, the adjustment of α may employ the current value of α and / or the cost value, and optionally one or more previous values ​​of α and / or the previous values ​​of the cost value. A gradient descent technique may be employed for this purpose. The adjusted α is then re-input as shown at 426, while the constant fixed process parameter μ is maintained in the process simulation model 404. In other words, the process simulation model is reconfigured with the adjusted α value. The process simulation model is then re-executed with the same initial profile and the same fixed process model parameters but the adjusted floating process model parameters. The optimization system 400 then repeats the operations of components 404 to 418, which may achieve the required convergence condition, or, if convergence is not achieved, repeats the operations of components 404 to 426. However, the metrology results obtained at 414 can be used again in this new loop. Through this loop, the optimization system 400 can further adjust α as needed. The optimization process continues for as many iterations as necessary to be able to output a final value of α, which corresponds to meeting the convergence condition of the cost value.

[0095] Now refer to Figure 5 , showing an example of an optimization system 500. Figure 4 In contrast to the optimized system 400 shown in FIG. 4 (which employs a comparison of reflection / elliptical polarization values), here Figure 5 , compares a computationally generated feature profile (for a given input α) shown as 506 with experimentally derived measurements of the feature profile (e.g., via an energy dispersive X-ray scanning electron microscope (“X-SEM”)) to adjust α toward convergence as shown at 520. In this case, the process simulation model directly outputs the feature profile, and the program does not include the reflectance / ellipsometry generator 408. Of course, if the process simulation model outputs information other than the feature profile, then the method would require an appropriate converter to change the output into a profile.

[0096] In other aspects, the remaining system components and operations 502, 504, 506, 512, 516, 518, 520, 522, 524 and 526 of the optimization system 500 are the same as or very similar to the components and operations 402, 404, 406, 412, 416, 418, 420, 422, 424 and 426 of the optimization system 400 described previously, and are therefore also similarly used to repeatedly optimize the process model parameter α representing one or more floating process model parameters while keeping μ representing one or more fixed process model parameters unchanged.

[0097] Also, similar to the optimization performed by system 400, the many types of parameters used as floating and fixed process model parameters need not be set in stone. For example, local plasma properties such as ion flux may constitute floating model parameters in some optimization implementations and may constitute fixed model parameters in other optimization implementations.

[0098] In detail, the optimization performed by the system 500 begins at 502, which involves inputting initial feature profiles α and μ into a process simulation model, such as an etch profile model (EPM). The process simulation model 504 executes to adjust the input initial profile to an output profile, such as substantially the same or similar to that performed by the model 404, in a manner intended to predict the outcome of the semiconductor device manufacturing operation modeled by the process simulation model (in this case, the feature profile). The execution of the process simulation model is accompanied by the computational generation of the feature profile shown as the final output 506 through the calculation and adjustment of the model 504. As previously discussed with respect to the optimization system 400, the profile is the prediction of the outcome of the process simulation model for the semiconductor device manufacturing operation under consideration.

[0099] However, unlike optimization system 400, optimization system 500 does not employ a reflectance / ellipsometry generator (e.g., shown as 408 in optimization system 400), and thus computationally generated feature profile 506 is provided directly to cost function calculator 512, which also receives experimentally derived measurements of the feature profile obtained via X-SEM, as shown at 514. The experimentally derived measurements are obtained by processing a real substrate using semiconductor device manufacturing operations (which are simulated by the process simulation model) and using the same initial substrate profile and fixed parameter values. As previously defined, whether computationally generated or experimentally derived, the geometry of a feature profile is a group of independent points in space representing the locations of a particular feature or group of features, or parameters representing such points (e.g., a series of CD values ​​at different heights). Note that there are many techniques that can be used to determine feature profiles. Some techniques output profiles directly (e.g., SEM and AFM techniques) and other techniques output profiles indirectly (e.g., optical metrology techniques). In the latter case, the direct result (e.g., reflectance spectrum) must be converted into a feature profile before comparing the direct result to the computationally generated result.

[0100] Similar to the implementation of cost function calculator 412 in optimization system 400, cost function calculator 512 compares the computationally generated feature profile with the experimentally derived measurements of the feature profile to output one or more cost values, such as indicated in the figure as "[Etch Profile] exp -[Etch Profile] calc(e.g., as indicated by 516). The comparison provides a reflection of the prediction / simulation results (e.g., [Etch Profile] calc And experimental judgment results [Etch Profile] exp . Also, the optimization system 500, being the same or similar to the optimization system 400, uses the cost value to at least (i) determine whether the floating process model parameter value has converged; and (ii) if the value has not converged, determine how to adjust the current value of the floating process model parameter for the next iteration and determine the adjustment amount. Of course, the adjustment of the floating process model parameter may use other information, such as the current and previous values ​​of the floating process model parameter, and / or the previous value of the cost value.

[0101] The cost value shown at 516 output by the cost function calculator 512 is provided to a convergence checker 518, which is an algorithm that evaluates the potential convergence of α indicated by the cost value. In some embodiments, and the same or similar to the execution of the convergence checker 418 of the optimization system 400, the execution of the convergence checker 518 involves identifying a substantial local or global minimum in one or more cost values. When convergence of α is indicated by the convergence checker, the convergence checker determines that convergence has occurred as shown at 520, which results in outputting the final or optimized floating process model parameter α.

[0102] As previously noted, iteratively modifying floating process model parameter values ​​from initial or seed values ​​(e.g., provided at 502) to final values ​​(e.g., output at 522) is a goal of the model optimization routine shown by the optimization system 400. In some embodiments, iterative execution of the optimization routine by the system 400 will result in a process simulation model configured with final values ​​of the floating process model parameters α that provide better predictive capabilities than a process simulation model configured with initial values ​​of, for example, the floating process model parameters.

[0103] Also, the execution of the convergence checker 518, which is the same as or similar to the execution of the convergence checker 418 of the optimization system 400, may indicate that the cost value has not yet reached the required convergence condition before the final convergence criteria are met. In such a case, the convergence checker adjusts the current value of α and outputs the adjusted value of α, as shown at 524. This adjusted α is then re-entered into the process simulation model 504 as shown at 526, and the fixed process parameters μ are maintained unchanged. In other words, the process simulation model is reconfigured with the adjusted value of α. The process simulation model is then re-executed with the same initial profile and the same fixed process model parameters but with the adjusted floating process model parameters. The optimization system 500 then repeats the operations performed as before via components 502 to 506, however, the experimental measurement profile obtained at 514 may be used again in this new cycle. Through this loop optimization, the system 500 may further adjust α as needed. The optimization continues for the required number of iterations to be able to output the final converged value at 522.

[0104] Now refer to Figure 6 , showing the optimization system 600. With the use of Figure 4 In contrast to the embodiment of the system 400 shown (which employs a comparison of reflection / elliptical polarization), Figure 6 The optimization system 600 shown does not include the reflectance / ellipsometry spectrum generator 408, but instead includes a profile parameter converter 608. The remaining operations of the components 602 to 624 of the optimization system 600 are somewhat similar to those corresponding to Figure 4 The corresponding operations of components 402 to 424 of the optimization system 400 are shown. Redundant descriptions of the same are omitted.

[0105] As previously described, the result of executing a process simulation model may be a substrate profile after (or during) the semiconductor device manufacturing operations simulated by the model. Such a profile may be represented as a group of independent points in space representing locations within or near a particular feature or group of features.

[0106] In the optimization process of system 600, and as opposed to using a substrate profile defined by a set of points in space, the process uses a set of "profile parameters" to represent the geometry of the feature profile, such as may be represented using fewer data points or groups of data points. That is, the process simulation model 604 (e.g., EPM) outputs a computationally generated feature profile, which may have many independent points in space as described above. Such points are then systematically reduced, or at least partially eliminated, by a "profile parameter converter" 608 to output a profile that may be referred to as a "reduced" profile, such as the profile parameter P shown at 610. iExamples of profile parameters include these characteristics of a feature or group of features: critical dimension, sidewall angle, depth, pitch, etc. Techniques for converting feature profiles into groups of profile parameters are known in the art and are commonly used in Optical Critical Dimension methods.

[0107] Similar to the optimization systems 400 and 500 described previously, the cost function calculator 612 of the optimization system 600 receives geometric profile parameters P derived from experimentally generated data (e.g., X-SEM, CD-SEM, or optical metrology). i These profile parameters can be derived from such experimentally generated data using the OCD method. The result is a geometric feature having parameters that characterize different aspects of the geometric model (e.g., a trapezoidal model or a rounded corner model). The cost function calculator 612 also receives the profile parameters from the profile parameter converter 608. Using these inputs, the cost function calculator 612 outputs one or more of its cost values, such as [P i ] exp -[P i ] calc 616. Such cost value is similarly received and used by convergence checker 618 as previously discussed with respect to convergence checker 418 and / or 518 to iteratively adjust α as needed to eventually reach convergence as shown at 620 and output a final α as shown at 622.

[0108] In some embodiments, the system simulated and experimentally evaluated via metrology has a deposited material of a multilayer stack, including an optional mask layer. A process simulation model calibrated using a multilayer stack including layers of different thicknesses and optionally different materials can have great practical value. Typically, the etching process is performed on a multilayer stack of heterogeneous materials. However, when calibrating a process simulation model using a substrate having a multilayer stack of materials to be etched, it is important that the simulation model uses the correct thickness value for each layer in the stack. In this regard, the method described herein can be performed by taking a physical substrate containing a multilayer stack to be used for calibration and performing a preliminary evaluation by metrology to determine the thickness of each layer in the stack. These thicknesses are then used for the computational representation of the substrate considered in the process simulation model. In this way, the simulation appropriately represents the physical structure that will be used to provide experimental information obtained by metrology for calibration of the process simulation model.

[0109] In some embodiments, after the process simulation model has been fully calibrated (e.g., the value of α has converged to a degree that the model can be used with certainty), the model is implemented and used to predict etching results and all applications associated therewith (e.g., defining photolithography masks, designing new etching equipment, specifying in etching process windows, etc.). During actual use of such a process simulation model, if it is found that the model has been unable to accurately predict the etching profile produced by the real etching process, such information can be used to further calibrate, or at least improve the calibration of the model. The simulation results of the conditions that led to the incorrect prediction are provided to the optimization routine together with the actual results of the etching process to further optimize the parameter values ​​(a) used for the process simulation model. In this way, the predictive ability of the process simulation model can be improved within the domain of physical conditions in which the model is used, and / or the domain of the model is extended to new physical applications represented by etching conditions that cause the model to incorrectly predict etching results. Of course, this recalibration can be used multiple times during the life of the process simulation model, that is, whenever a failed predictive ability is found.

[0110] Additional Implementation—CD-SEM Optimization Data

[0111] The etching model can generate a three-dimensional profile including x and y dimensions, which are on a plane parallel to (or on) the surface of the wafer or integrated circuit chip when viewed from above. The etching model can also provide z-dimensional information in a direction orthogonal to the surface of the wafer or integrated circuit. The z-direction value indicates the etching depth. On the contrary, the contour is a two-dimensional representation containing only x and y dimensions. Only the x and y dimensions are used to provide and implement the design layout of the photolithography photomask via the tapeout. In some embodiments, the etching model described herein generates an xy contour by specifying the z-direction height in the etching profile or by specifying the material in the etched stack. And, in some cases, the etching profile is provided only in two dimensions (z direction and x direction). In addition, the contour can be provided only in one dimension (x direction) or in a characteristic parameter such as a critical dimension or pitch.

[0112] CD-SEM or critical dimension scanning electron microscopy is an electron microscopy technique that provides a top view (showing the xy plane) of features and patterns on the surface of a substrate, such as an integrated circuit chip or a coupon. According to the advantage, these features can be viewed as top-down outlines on the substrate. CD-SEM can provide nanometer-scale resolution of the outlines. In addition to sharp outlines, CD-SEM can also provide intensity gradients at boundaries (outline edges). These gradients can at least partially reveal transition areas on the features where the feature sidewalls slope from one height to a different height. A single CD-SEM image can provide enough to resolve the slopes in the sidewalls of the outlines and a single layer at one or more layers (which may be etched independently). Multiple CD-SEM images taken at different stages of a multi-stage process can be overlapped to show the progression of the feature outline from one manufacturing process operation to the next.

[0113] Apparatus for performing CD-SEM may include specialized systems that examine patterns on a substrate by measuring the dimensions of the features of the pattern. Examples of CD-SEM systems include the Hitachi CG6300 and KLA-Tencor 8100XP and Applied Materials VeritySEM 5i. CD-SEMs are sometimes used for:

[0114] ADI (After Development Inspection): Inspection of the resist pattern after the pattern has been transferred by the exposure tool and subsequent development; and

[0115] AEI (Post-Etch Inspection): Inspecting a substrate after etching using a resist pattern as a mask and then measuring the dimensions of the etched pattern.

[0116] In developing manufacturing processes, CD-SEM is sometimes used to identify the effects of specific processing conditions on the transferred pattern, particularly the effects of the focus and dose of the exposure tool. The process window is generated using the relationship between the exposure conditions (focus and dose) and the exposure results.

[0117] As described, calibration or optimization of a process simulation model such as an etch model can be performed using a cross-sectional SEM or TEM, which is destructive and may present line boundaries that are sometimes difficult to interpret. Using these techniques is expensive and may result in insufficient sample collection. This negatively affects the turnaround time for etch model calibration and the accuracy of the results.

[0118] Calibration can also be performed using top-view information such as that obtained using a CD-SEM, which obtains a top-view image and extracts the CD (critical dimension) of the feature. Measuring CD is highly dependent on the structure profile. The challenge with CD-SEM is that there are sometimes inaccuracies in the location where the CD is determined, especially in the z-direction. The associated CD at the wrong location in the structure profile limits the robustness of the calibrated etch model. This can be handled by using a CD-SEM in conjunction with one or more techniques that provide z-resolved information such as the following techniques: CDSAXS (critical dimension small angle X-ray scattering), transmission electron microscopy (such as STEM), thin film, or OCD scattering measurement techniques. Feature representations that include a z-direction component are sometimes referred to herein as profile-based representations, and are metrology techniques based on the generated profile, such as X-ray scattering, TEM, and OCD metrology.

[0119] As described, in terms of the profile evolution at the wafer level, the etching results can be simulated via the etching model. The embodiments described herein use only CD-SEM or in combination with other metrology to calibrate the floating parameters of the etching model. In some embodiments, the calibration uses a CD-SEM assisted by one or more other metrology methods (e.g., STEM and / or optical scattering measurement) that provide more detailed profile information. The time evolution measured by CD-SEM in combination with profile metrology (e.g., optical scattering measurement or STEM) can provide boundary conditions (calibration information) for optimizing the floating parameters of the etching model. The top-view profile nano-resolution generated by CD-SEM is supplemented by the accuracy of the side-view profile information collected by CDSAXS, TEM, and / or OCD technology. The calibration procedure can use multiple test patterns / samples at the wafer level (e.g., gauges from a chip design library (clip design library)). Each test pattern is transferred to a test substrate where etching or processing is performed, and the resulting substrate features are measured using CD-SEM and optionally one or more other metrology techniques.

[0120] Optimization of CD-SEM output can be utilized Figure 4 , 5 6. A separate process flow specific to the process using CD-SEM is depicted in Figure 8 .

[0121] like Figure 8As shown, the process begins by supplying various parameters required to run the process simulation model. The overall process iteratively improves one of these parameters (floating parameters). Initially, the process simulation model (identified herein as "SEM3D or SKM") receives the following as input: (a) control parameters (α vector or floating parameters), (b) constant parameters (μ vector or fixed parameters), (c) incoming profile (xz representation of resist, mask, or other stack design layout), and (d) incoming pattern (top-down xy representation of pattern resist, mask, or other stack design layout). Executing the process simulation model with these inputs provides one or more of the feature profile (xz), outline (xy), and LER or LWR of one or more features being modeled as output.

[0122] In the inner optimization loop, cross-sectional metrology data (e.g., CDSAXS, STEM, X-SEM, etc.) and top-view metrology data (e.g., CD-SEM) are provided from one or more substrates processed using the incoming profile / pattern and undergoing device fabrication operations modeled by the process simulation model. The values ​​of the metrology data may be compared with the corresponding outputs of the process simulation model (is A=A'?; is B=B'?; and is C=C'?), and any differences may be used to generate one or more cost functions as described above.

[0123] In the outer optimization loop, the profile, contour and / or LER / LWR output by the process simulation model is provided to a spectrum generator such as RCWA or FDTD as described above. The generated output is compared to the experimentally generated spectrum (B=B'?) to again generate different cost functions as described above. The experimentally generated spectrum can be generated by any of a number of optical metrology techniques with or without OCD conversion. See Figure 4 and 6 In some embodiments, the comparison is performed on the data for a particular scattering measurement tool or technique (e.g., the YieldStar TM tools) space.

[0124] The inner and outer optimization loops may be used separately or together. When used together, a combined cost function based on the general parameter B together with one or more of A, C, and D is generated. This cost function is then used to adjust the value of the floating parameter α as described elsewhere herein.

[0125] The backscattered electron intensity of the CD-SEM allows the determination of the CD profile and LWR / LER (line width roughness and / or line edge roughness). This information can be provided as a CD-SEM output to facilitate model calibration. A process simulation model (for example, an etch profile model, such as a surface dynamics model or behavioral model described herein) is used to simulate modifications of an input structure such as a design layout or mask, or a portion thereof, such as provided in one or more gauges / microcircuits. As described elsewhere herein, the difference between the simulation results and the experimental results is evaluated by a cost function of one or more metrics. The cost function using the CD-SEM output can be combined with a metrology cost function of other data streams that do not use CD-SEM (such as X-ray scattering, TEM, or OCD techniques) to facilitate optimization via, for example, nonlinear regression of a floating parameter value α.

[0126] As noted, the CD-SEM output may include feature profiles as well as LWR and / or LER. Furthermore, through the intensity gradients present in the CD-SEM images, the CD-SEM output may capture the evolution of the etch profile within multiple locations of various materials of the stack (e.g., spin-on material, hard mask, underlying substrate, etc.) and / or within various steps of the etch. The intensity gradient may at least partially reflect transition regions of the profile where the sidewall has a slope (i.e., it is not purely vertical). Thus, while the CD-SEM may have an advantage in determining feature profiles (in the xy plane), it may also provide some z-direction information. This may supplement the 1D or 2D structural information.

[0127] By using CD-SEM metrology data in combination with other metrology data, a multi-feature process simulation model can be generated. For example, in addition to feature profiles (calibrated by X-ray scattering, TEM, SEM, AFM, OCD, etc.), a single etch model can be used to predict top-view feature or pattern profiles / gradients (calibrated by CD-SEM) and / or LER and / or LWR estimates (calibrated by CD-SEM). Any of these predicted results for manufacturing operations may exist in multiple time steps. For process simulation models that use multiple time steps, calibration information may require multiple time snapshots captured via metrology.

[0128] In some embodiments, in order to optimize the process simulation model, the method can combine the cost functions of two or more of the following types of metrology data into a weighted hybrid metrology: TEM / SEM / AFM (differences in xz data), OCD (differences in spectra), and CD-SEM (differences in contour / gradient values, which are typically viewed from the vantage point of the xy plane). In some embodiments, the optimization procedure uses the error bar of the metrology in the L2 norm cost function (such as in chi-square). Of course, as described, other cost functions can be used. Training, validation, and testing can be used, as used in conventional machine learning. Further description of the machine learning program flow is described elsewhere in this article. Global optimization methods can be used to search for the lowest MSE (mean square error) relative to experimental data.

[0129] Related optional points—CD-SEM

[0130] In some embodiments, multiple sample loading methods (e.g., provided by different gauges / chips) of CDF-SEM are used with one or more other metrology techniques such as OCD and / or TEM to produce optimized metrology results, depending on profile sensitivity and accuracy requirements.

[0131] In cases where metrology uncertainty is high, two or more of the following parameters are used together in the process simulation model parameter space: calibrated core parameters, etch physics parameters, etch behavior parameters, and / or structural parameters.

[0132] Iterative Optimization of Core Parameters and Other Profile Parameters The core parameters, which express the profile parameters as a function of the local feature density and the shape of the neighboring structures, can be calibrated for large sample sizes using 1D and 2D images of CD-SEM.

[0133] This optimization process flow using CD-SEM based hybrid metrology to calibrate the etch model may have several advantages, such as:

[0134] 1.CD-SEM can provide accurate 2D profile (xy information) input. STEM can provide detailed and accurate profile (including z direction information). OCD provides good precision profile measurement (including z direction information). Combining the strengths of these individual techniques provides good accuracy.

[0135] 2. Calibration allows direct mapping between etch model parameters and top view profile (xy view), and optional etch models between them. It provides a direct path to integrate OPC / CD-SEM (industry standard) with etch OPC plus profile metrology. OPC and CD-SEM are commonly used in industry without considering profile effects. In some embodiments herein, consideration of etch profile is integrated into the standard OPC flow. In addition, when the etch model provides a simulated profile compared to profile metrology, the method not only extends the OPC simulation to EtchOPC (with simulated profile), but also extends CD-SEM to CD-SEM + post-etch profile metrology. This "etch extension" can be integrated into the standard OPC flow.

[0136] 3. Profile evolution is linked to the etch step-wise changes in the CD-SEM profile, providing a method to compare the consistency of each step and assess the error of each step.

[0137] 4. Low cost: OCD (being a non-destructive technique) costs less than CD-SEM (bias applied due to interaction with the electron beam), which is therefore less expensive than STEM (destructive).

[0138] Etching Outline Model

[0139] As mentioned, the etching profile model (EPM) is a type of process simulation model. It calculates a theoretically determined etching profile from a set of input etching reaction parameters (independent variables), which characterize some features of the etching reaction (such as several potential physical and chemical etching processes and reaction mechanisms). These processes can be modeled as a function of time and position in a grid representing the etched features and their environment. Examples of input parameters include plasma parameters such as ion flux, and chemical reaction parameters such as the probability that a specific chemical reaction will occur. Other examples include the characteristics of the etched substrate (such as a layer-by-layer description of thickness and material), the initial mask layout of one or more features to be etched, process chamber conditions, etc. Such parameters can be obtained from a variety of sources including other models, which calculate these parameters from general reactor configurations and process conditions such as pressure, substrate temperature, plasma source parameters (such as power, frequency, duty cycle provided to the plasma source), reactants, and their flow rates. In some embodiments, such a model can be part of an EPM.

[0140] EPM treats such parameters as independent variables (which may be fixed and / or floating in the context of the optimization routine described herein), and functionally generates an etching profile as a response variable. In other words, the grouped independent variables are parameters used as inputs to the model, and the response variables are the etching profile features calculated by the model. EPM can use one or more relationships between reaction parameters and etching profiles. These relationships may include, for example, coefficients, weights, and / or other model parameters (as well as linear functions of reaction parameters and / or other model parameters, second or higher order polynomial functions, etc.) applied to the independent variables in a defined manner to generate a response variable about the etching profile. Such weights, coefficients, etc. may represent one or more of the above-mentioned reaction parameters. In some embodiments, these model parameters are floating process model parameter values ​​that are tuned or adjusted during the optimization techniques described herein. In some embodiments, some of the reaction parameters are model parameters to be optimized, while others are used as fixed process model parameters. For example, in some embodiments, chemical reaction parameters may be floating process model parameters that may be optimized, while plasma parameters may be fixed process model parameters.

[0141] As described, some EPMs employ fundamental reaction mechanism parameters and may be fundamental to the underlying chemical and physical properties, and therefore the experimental process engineer generally has no control over these quantities. In an etch profile model, these variables may be applied at each location of the grid and multiple times (separated by defined time steps). In some embodiments, the grid resolution may vary between about a few angstroms and about one micron. In some embodiments employing time-dependent modeling, the time step may vary between about le-15 and le-10 seconds. In some embodiments, the optimization employs two types of mechanism-independent variables: (1) local plasma parameters, and (2) local chemical reaction parameters. These parameters are "local" in that they may vary as a function of location (in some cases to the resolution of the grid). Examples of plasma parameters include local plasma properties, such as flux and energy of particles of, for example, ions, free radicals, photons, electrons, excited species, depositor species, and their energy and angular distributions. Examples of chemical and physicochemical reaction parameters include rate constants (e.g., the probability that a particular chemical reaction will occur at a particular time), adhesion coefficients, energy thresholds for etching, reference energies, energy exponents for defining sputtering yields, angular yield functions and their parameters, etc. Furthermore, parameterized chemical reactions may include reactions in which reactants include etched materials and etchants. It should be understood that, in addition to reactions that directly etch substrates, chemical reaction parameters may additionally include many types of reactions. Examples of such reactions include side reactions, which include parasitic reactions, deposition reactions, reactions of byproducts, etc. Any of these may affect the overall etching rate. It should also be understood that, in addition to the above-mentioned plasma and chemical reaction input parameters, the model may also require other input parameters. Examples of such other parameters include the temperature at the reaction location, the partial pressure of the reactants, etc. In some cases, these and / or other non-mechanism parameters may be input into a module that outputs some of the mechanism parameters. In some embodiments, the model does not use mechanism parameters, at least not directly.

[0142] Initial (unoptimized) values ​​for EPM model variables, as well as variables that are fixed during optimization (e.g., plasma parameters in some embodiments), can be obtained from a variety of sources, such as from literature, through calculations by other computational modules or models, etc. In some embodiments, independent input variables (e.g., plasma parameters) can be determined using a model such as from an etch chamber plasma model (in the case of plasma parameters). Such a model can calculate the available input EPM parameters from a variety of process parameters over which the process engineer has control (e.g., by turning knobs), for example, chamber environmental parameters such as pressure, flow rate, plasma power, wafer temperature, ICP coil current, bias voltage / power, pulse frequency, pulse duty cycle, etc.

[0143] EPM can take any of many different forms. Ultimately, it provides a relationship between independent variables and dependent variables. The relationship can be linear or nonlinear. In some embodiments, EPM is referred to in the art as a cell-based Monte Carlo surface reaction modeler. These models, which are presented in various forms, operate to simulate the morphological evolution of wafer features over time in the context of semiconductor wafer manufacturing. The model emits pseudoparticles having energy and angular distributions generated by a plasma model or experimental diagnosis for any radial position on the wafer. The pseudoparticles are statistically weighted to represent the flux of free radicals and ions toward the surface. The model handles a variety of surface reaction mechanisms that lead to etching, sputtering, mixing, and deposition on the surface to predict profile evolution. During the Monte Carlo integration, the trajectories of many ions and neutral pseudoparticles are tracked within the wafer features until they react or leave the computational domain. EPM has the ability to predict advanced etching, stripping, atomic layer etching, ionized metal physical vapor deposition, and plasma enhanced chemical vapor deposition on a variety of materials.

[0144] In some embodiments, the EPM utilizes a rectilinear grid in two or three dimensions with a resolution fine enough to appropriately handle / model the dimensions of the wafer features (although in principle, the grid (whether 2D or 3D) may utilize non-linear coordinates). The grid may be viewed as an array of grid points in two or three dimensions. It may also be viewed as an array of cells representing local areas in 2D, or local volumes in 3D, associated with (centered at) each grid point. Each cell within the grid may represent a different solid material or mixture of materials. Whether a 2D or 3D grid is selected as the basis for modeling may depend on the class / type of substrate features being modeled. For example, a 2D grid may be used to model long trench features (e.g., in polysilicon substrates), with the 2D grid depicting the cross-sectional shape of the trench under the assumption that the geometry of the trench ends is not overly dependent on reactive processes occurring along a large portion of the trench length and away from the trench ends (i.e., for the purposes of this cross-sectional 2D model, the trench is assumed to be infinite, which is also a reasonable assumption for trench features away from the ends of the trench features). On the other hand, modeling circular through-hole features (through silicon vias (TSVs)) using a 3D mesh may be appropriate (since the x, y horizontal dimensions of the features are identical to each other).

[0145] The grid spacing may range, for example, from sub-nanometers (e.g., from 1 angstrom) to several microns (e.g., 10 microns). In general, each grid cell is assigned a material identifier, such as resist, polysilicon, vapor-phase etchant, or plasma (e.g., in regions of space not occupied by features), which may change during profile evaluation. Solid-phase species may be represented by material identifiers in the operational cells; vapor-phase species may be represented by operational pseudo-particles. In this way, the grid provides a reasonably detailed representation (e.g., for operational purposes) of the substrate features and the surrounding gas environment (e.g., plasma) as the geometry / topography of the wafer features evolves over time during a reactive etch process.

[0146] Some of the above descriptions have focused on process simulation models, such as surface dynamic models, that employ a mechanistic representation of semiconductor device manufacturing operations. Such models are described in more detail in U.S. Published Patent Application No. 20170228482, filed on February 8, 2016, and U.S. Published Patent Application No. 20170363950, filed on June 21, 2016, both of which are hereby incorporated by reference in their entirety. However, some implementations use quite different models to represent semiconductor device manufacturing operations. In some cases, the model does not employ (at least not directly employ) mechanistic parameters that attempt to describe the underlying chemical and physical properties of semiconductor device manufacturing operations. For example, a behavioral model may employ an excerpt of a process to predict the structural details of features produced by one or more semiconductor device manufacturing operations. An example of a behavioral model is the SEMulator3D from Coventor (a Lam Research company). TM Examples of behavioral models are presented in US Pat. No. 9,015,016 and US Pat. No. 9,659,126, both of which were previously incorporated by reference.

[0147] In many embodiments, the process simulation model described herein models features in three dimensions. In some cases, the process simulation model described herein not only predicts the impact of semiconductor device manufacturing operations on a feature, but also predicts the impact on groups of features on areas of the design layout (e.g., large multi-component areas).

[0148] Although the above description has focused on etching models, the present disclosure also relates to other models, such as models for predicting the effects of a planarization process or a deposition process on a substrate.

[0149] Experiment and profile measurement

[0150] In order to optimize the process simulation model, a variety of experiments may be performed to determine, with experimentally acceptable accuracy, the actual profile resulting from an actual process performed under a variety of process conditions specified by a variety of sets of process parameters. Thus, for example, a first set of values ​​for a set of process parameters (e.g., etchant flow rate, plasma power, temperature, pressure, etc.) is specified, the chamber apparatus is set accordingly, the etchant flows into the chamber, the plasma is ignited, etc., and a first semiconductor substrate is processed to produce a first profile. Then a second set of values ​​for the same set of process parameters is specified, a second substrate is processed to produce a second profile, and so on.

[0151] A variety of combinations of process parameters can be used to present a wide or concentrated process space as needed to optimize the process simulation model. The same combination of process parameters is then used to calculate (independent) input parameters such as mechanism parameters through the process simulation model to provide a profile output (dependent variable) that can be compared with experimental results. Because experiments are expensive and time-consuming, techniques can be used to design experiments in a way that reduces the number of experiments required to provide a robust training set for optimizing the process simulation model. Techniques such as experimental design (DOE) can be used for this purpose. In general, such techniques determine which set of process parameters to use in a variety of experiments. It selects a combination of process parameters by considering statistical interactions, randomization, etc. between process parameters. For example, DOE can identify a small number of experiments covering a limited parameter range around the center point of a completed process.

[0152] In some approaches, the researcher will perform all experiments early in the model optimization process and use only those experiments in the optimization routine iterations until convergence. Alternatively, the experiment designer may perform some experiments for the early iterations of the optimization and then perform additional experiments as the optimization continues. The optimization program may inform the experiment designer of the specific parameters that should be evaluated for subsequent iterations and therefore the specific experiments that should be performed.

[0153] One or more in-situ or offline metrology tools may be used to measure the experimentally generated profiles resulting from these experimental process operations. The measurements may be made at the end of the process, during the process, or at one or more time points during the process. When the measurements are made at the end of the process, the measurement metrology may be destructive, and when the measurements are made at intervals during the etching process, the measurement metrology is generally non-destructive (thus not interrupting the etching). Examples of suitable metrology techniques include, but are not limited to, in-situ reflectometry, OCD, cross-sectional SEM, CD-SEM, and others mentioned above. Note that the metrology tool may directly measure the profile of the feature, such as in the case of SEM (where the experiment essentially forms an image of the etch profile of the feature), or it may indirectly determine the etch profile of the feature, such as in the case of OCD measurements (where some post-processing is performed to derive the etch profile of the feature from the actual measurement data). Metrology techniques can be classified according to where they are performed and what they do to the sample; the classifications include in-situ, offline non-destructive, and destructive metrology. In-situ metrology includes, for example, reflectometry, and ellipsometry; off-line non-destructive metrology includes, for example, single wavelength and broadband OCD metrology or scatterometry, dome scatterometry, CD-SAXS, and CD-SEM (top-down SEM); and destructive metrology includes, for example, X-SEM, STEM, and TEM.

[0154] Regardless, the result of the experiment and metrology procedures is a set of measured profiles, each of which generally comprises a series of values ​​for a series of coordinates or a set of grid values ​​representing the profile shape of the features described above. The profiles are then used as input to train, optimize, and improve the computerized etch profile model as described herein.

[0155] Reflectometry and Ellipsometry Spectroscopic Analysis and Modeling Tools

[0156] When using a process simulation model to generate feature profile values, the optical parameters generated from the geometry may be modeled or predicted using an optical modeling routine such as the RCWA method or similar techniques.

[0157] RCWA is the only method that can be used to describe the properties of reflected (diffracted, scattered) radiation from a periodic structure such as a grating or transmitted through such a grating. RCWA was developed substantially by Moharam and Gaylord and is described in the scientific literature. See, for example, MG Moharam and TK Gaylord "Rigorous coupled-wave analysis of planar-grating diffraction" J. Opt Soc of America, Vol. 71, Issue 7, pp. 811-818 (1981), which is incorporated herein by reference in its entirety. RCWA calculates the intensity and polarization properties of multiple diffraction orders (zeroth and higher). Other optical modeling methods that can provide results include, but are not limited to, the C-method, the modal method, the Rayleigh approximation, the electric field integral equation (EFIE), and the conjugate gradient fast Fourier transform (CG-FFT).

[0158] RCWA is a semi-analytical method in operational electromagnetics that is often used to solve scattering from periodic dielectric structures. It is a Fourier space method, so the device and the field are represented as a sum of spatial harmonics. The method is based on Floquet's theorem, and the solution of periodic differential equations can be expanded using Floquet functions (or sometimes called Bloch waves, especially in solid-state physics). The device is divided into layers that are each uniform in the z direction. For curved devices with properties such as dielectric permittivity that is graded along the z direction, a step approximation is required. The electromagnetic modes in each layer are calculated and propagated analytically through these layers. The overall problem is solved by matching the boundary conditions at each of the interfaces between the layers using techniques such as scattering matrices. In order to solve for the electromagnetic modes determined by the wave vector of the incident plane wave, Maxwell's equations (in partial differential form) and boundary conditions are expanded by Floquet functions in a periodic dielectric medium and transformed into large algebraic equations. By truncating higher order Floquet functions, infinite algebraic equations become finite and solvable by computers, depending on the required accuracy and convergence rate.

[0159] Another way to computationally generate optical parameters that are (or may be) generated by the interaction of light beams is by using the finite-difference time-domain (FDTD) method. This is a numerical analysis technique for electrodynamics. It is a grid-based finite-difference method for finding approximate solutions to Maxwell's equations in partial differential form for time dependence. The equations are discretized into time and space partial derivatives. The resulting finite-difference equations are solved in a jumpy fashion: the electric field vector component in a volume of space is solved at a given point in time, and then the magnetic field vector component is solved in the same volume at the next point in time, and the procedure is repeated until the desired instantaneous or steady-state electromagnetic field is calculated.

[0160] Convergence Check

[0161] The above-mentioned floating process model parameter optimization procedure may be an iterative nonlinear optimization procedure, for example, which optimizes an error metric or a cost value which is generally a nonlinear function of an input parameter, and thus, various techniques known in the art may be employed. See for example: Biggs, MC, "Constrained Minimization Using RecursiveQuadratic Programming," Towards Global Optimization (LCWDixon and G.P. Szergo, eds.), North-Holland, pp341-349, (1975); Conn, NR, NIMGould, and Ph.L. Toint, "Trust-Region Methods," MPS / SIAM Series on Optimization, SIAM andMPS(2000); Moré, JJand DCSorensen, "Computing a Trust Region Step," SIAMJournal on Scientific and Statistical Computing, Vol.3, pp 553-572, (1983); Byrd, RH, RBSchnabel, and GAShultz, "Approximate Solution of the Trust RegionProblem by Minimization over Two-Dimensional Subspaces," Mathematical Programming, Vol. 40, pp 247-263 (1988); Dennis, JE, Jr., "Nonlinear least-squares," State of the Art in Numerical Analysis ed. D. Jacobs, Academic Press, pp 269-312 (1977); Moré, JJ, "The Levenberg-Marquardt Algorithm:Implementation andTheory," Numerical Analysis,ed.GAWatson,Lecture Notes in Mathematics 630,Springer Verlag,pp 105-116(1977);Powell,MJD, "A Fast Algorithm for Nonlinearly Constrained Optimization Calculations," Numerical Analysis, G. A. Watson ed., Lecture Notes in Mathematics, Springer Verlag, Vol. 630 (1978); each of which is incorporated herein by reference. .

[0162] In general, the comparison for calculating the cost compares multiple aspects or indicators of the operational prediction and metrology results. The difference between the operational generation and the measured values ​​of these indicators constitutes a cost function for optimization. Examples of these indicators include critical dimension (CD) differences of multiple heights of materials, thickness differences of given materials, and spectral differences of overall spectra. The cost function can be a combination of them, optionally with weight factors for them. The difference can be expressed as L1 or L2 norm, Euclidean distance, Mahalanobis distance, etc. In some embodiments, these techniques optimize the objective function (herein, the cost function / value) subject to several restrictions that can be imposed on input parameters and / or error indicators. In several such embodiments, the restriction function itself can be nonlinear. For example, in an embodiment in which the operational etching profile is represented by a group of stacked parts trapezoids output by a process simulation model, the cost value can be defined as the difference between the area represented by the boundaries of these stacked parts trapezoids and the area where the experimental etching profile is measured. In this case, the error indicator is a nonlinear function of the dependent variable output by the process simulation model, and therefore a restricted optimization technique is selected from those just described, which allows the specification of nonlinear restrictions. Examples of widely used cost functions are provided by SciPy.org on the World Wide Web at: docs.scipy.org / doc / scipy / reference / generated / scipy.optimize.least_squares.html#scipy.optimize.least_squares.

[0163] Application of process optimization simulation model

[0164] The optimized computerized etch models disclosed herein can aid in semiconductor processing workflows in any situation where detailed evaluation and characterization of an etch process is required. For example, if a new etch process is being developed, the model can be used to determine etch profile characteristics for many combinations of process parameters without having to go into the lab and perform each experiment individually. In this way, the optimized etch profile model can enable faster process development cycles and, in some embodiments, can significantly reduce the effort required to fine-tune a target profile.

[0165] Lithographic operations and mask development can also benefit greatly from accurate etch profile modeling, since estimating edge placement errors is often quite important in lithographic work, and accurate calculation of profile shape provides this information.

[0166] U.S. Patent Application No. 15 / 367,060, filed December 1, 2016, which is hereby incorporated by reference in its entirety, describes edge placement error detection and lithography mask design. Note that there are at least two levels of design layout corrections that can be applied in this regard: lithography and etch. In other words, both optical and etch based considerations can be used to determine mask layout. Etch based considerations are used to make decisions using models prepared as described herein.

[0167] To make a photolithographic mask using the layout decisions described herein, the process begins with a so-called "blank," which includes a glass substrate coated with a chromium layer and a resist layer. Sometimes materials are used instead of or in addition to chromium. For example, an attenuated phase-shift mask uses an additional layer such as a molybdenum silicide layer. The resist can be a positive or negative resist. Upon electron beam exposure, the resulting pattern is formed on the resist, which can be transferred to the underlying chromium layer via an etching process. The chromium provides opaque areas on the photolithographic mask that cast shadows during exposure of the semiconductor wafer.

[0168] The manufacture of photolithographic masks is similar to the photolithography step during semiconductor device manufacturing. However, as opposed to light (e.g., deep UV), the exposure of the resist is accomplished by electron beam. The blank is exposed to electron beam radiation impinging on the resist in locations specified by the mask design layout (which is at least partially determined using an EPM of the type described herein). The mask is then developed to produce the pattern of the layout. The resist pattern now formed is then transferred to the underlying chrome layer by an appropriate etching process (e.g., plasma or wet etching). Thereafter, the resist is removed and the exposed chrome pattern is covered with a film to prevent contamination.

[0169] The optimization model disclosed herein can also help solve the inverse problem: where a specific target etch profile is desired, and a combination of one or more specific process parameters (or EPM input parameters) for achieving the specific target etch profile is desired. In addition, this can be done by experimental trial and error, but accurate modeling of the etch profile generated from a given set of process parameters (or EPM input parameters) and conditions can replace the need for experimentation, or at least in the initial stages of exploring the process / input parameter space, until good candidates can be identified for complete experimental studies. In some embodiments, the model can actually be numerically inverted in a fully automatic manner, that is, the parameters that produce a given etch profile are repeatedly located in groups. Once again, the reduction in the dimensionality of the etch profile coordinate space (via PCA) and the projection of the desired etch profile onto this space can make this numerical inversion more feasible.

[0170] Based on the disclosure provided herein, EPM can be used to facilitate process window and hardware optimization. In some embodiments, EPM is used to determine a parameter set (e.g., process window) for an existing unmodified reactor or reactor design. In some embodiments, EPM is used to determine a modified reactor design, such as, but not limited to, components of a reactor. For example, EPM may suggest nozzle design modifications (e.g., changing the hole pattern or internal flow lines from an existing design). In other examples, EPM may suggest plasma generator design modifications (e.g., changing the configuration and / or setting of a capacitively coupled plasma ("CCP") electrode or inductively coupled plasma ("ICP") coil from an existing design). In one example, EPM may suggest changes to the design or position of a wafer pedestal. In yet another example, EPM may suggest changes to the position or shape of a chamber wall. A general description of CCP and ICP reactors is provided in U.S. Published Patent Application No. 20170363950, filed on June 21, 2016, and is incorporated herein by reference in its entirety.

[0171] In some embodiments, the optimized EPM can be integrated with an etcher device, or integrated into a semiconductor manufacturing facility infrastructure that deploys one or more etcher devices. The optimized EPM can be used to determine the appropriate adjustment for process parameters to provide a desired etching profile, or to understand the effect of changes in process parameters on the etching profile. Thus, for example, a system for processing semiconductor substrates in a manufacturing facility may include an etcher device for etching semiconductor substrates, the operation of which is adjusted by a set of independent input parameters, which are controlled by a controller that implements the optimized EPM. A suitable controller for controlling the operation of the etcher device typically includes a processor and a memory, the memory stores the optimized EPM, and the processor uses the stored EPM to calculate the etching feature profile for a set of given values ​​of the set of input process parameters. After calculating the profile, in some embodiments, the controller can (in response to the shape of the calculated profile) adjust the operation of the etcher device by changing one or more values ​​in the set of independent input parameters.

[0172] In some embodiments, the model is used to monitor and process the in-situ optical signal in real time to generate geometric etching parameters (e.g., real-time endpoint or critical dimension monitoring) from the in-situ optical information. Such in-situ monitoring and processing capabilities can be provided in any of a number of reactor configurations (e.g., capacitively coupled plasma reactors and inductively coupled plasma reactors). In some embodiments, the feature characterization program (e.g., endpoint evaluation) completes processing in about 100 m or less (from the time when it receives the input variable value such as the optical measurement value). In some embodiments, the feature characterization algorithm completes processing in about 20 ms or less. Such fast processing can be used in applications with key step change requirements or in high etching rate processes (e.g., etching processes completed in less than about one minute). In processes with many variations caused by the processing system (e.g., in RF pulses or gas pulses), or when the wafer structure itself has a complex structure (e.g., in a stack of alternating materials), data arrays (e.g., thousands of them) may be required, sometimes for each of multiple time samples (e.g., more than one hundred, or more than one thousand). The running time of the model also depends on the type of algorithm used. In some embodiments, the model processes all or most of the time evolution of the spectral information from the beginning of the etching process to the present time. This may require, for example, the use of multi-way principal component analysis (PCA) and multi-way partial least squares (PLS) to generate a large number of models, wherein each model compares the optical measurement trajectory from the beginning of etching to the present time step relative to the historical trajectory of the corresponding time interval. During the real-time process monitoring during the model calibration period and the etching time is extended, such a model may have an increased computational demand. In such a case, the system may be configured with additional processing power, such as a processor with a large amount of buffer space, multi-threading, and / or multi-core.

[0173] In some embodiments, the model uses an optical output signal (or other aspects of the optical signal) that only occupies a limited range of wavelengths, which can be selected for determining the geometric parameters of interest. The signal in this range is used as an independent variable (or group of independent variables) of the model. In some such embodiments, most of the available optical signals are not used as input. The selected range may represent a small portion of the full range of values ​​that can be measured by the metrology tool (e.g., less than about 10% or even discrete values). Using the selected range as model input requires fewer operations, and therefore the calculation is faster to determine the geometry of the etched features. It can also allow the selected dependent variable to be calculated without interference from related geometric parameters, for example, the etch depth can be calculated without significant interference from the input signal that is strongly related to the critical dimension. For example, a first wavelength range may be strongly related to the etch depth, while a different wavelength range may be strongly related to the critical dimension but only weakly related to the etch depth. In order to avoid masking the signal, the program focused on the etch depth uses only the optical signal in the first wavelength range.

[0174] In general, the etcher device that can be used with the disclosed optimized EPM can be any type of semiconductor processing device suitable for etching a semiconductor substrate by removing material from the semiconductor substrate. In some embodiments, the etcher device can constitute an inductively coupled plasma (ICP) reactor: in some embodiments, it can constitute a capacitively coupled plasma (CCP) reactor. Therefore, the etcher device used with these disclosed optimized EPMs can have a processing chamber, a substrate holder for holding a substrate in the processing chamber, and a plasma generator for generating plasma in the processing chamber. The device may also include one or more valve-controlled process gas inlets for flowing one or more process gases into the processing chamber, one or more gas outlets connected to one or more vacuum pumps for exhausting gas from the processing chamber, etc. Further details about the etcher device (also generally referred to as an etching reactor, or a plasma etching reactor, etc.).

[0175] Background of the Disclosed Computational Implementations

[0176] Some embodiments disclosed herein relate to systems for generating and / or using process simulation models. Some embodiments disclosed herein relate to methods for generating and / or using process simulation models implemented on such systems. The system for generating the process simulation model may be configured to analyze data for calibration or optimization of representations or relationships for representing the effects of semiconductor device manufacturing operations on substrates. The system for generating the process simulation model may also be configured to receive data and instructions, such as program codes representing actual processes occurring during semiconductor device manufacturing operations. In this way, the process simulation model is generated or programmed on such a system. The programmed system using the process simulation model may be configured to (i) receive inputs, such as process parameters that personalize the initial design layout or mask of semiconductor device manufacturing operations and / or features generated in the substrate: and (ii) execute instructions for determining the effects of semiconductor device manufacturing operations on substrates. To this end, the system may calculate the time-dependent (or non-time-dependent) results of semiconductor device manufacturing operations.

[0177] Many types of computing systems having any of a variety of computer architectures may be used as the disclosed system for implementing process simulation models and algorithms for generating and / or optimizing such models. For example, the system may include software components executed on one or more general purpose processors, or specially designed processors such as programmable logic devices (e.g., field programmable gate arrays (FPGAs)). In addition, the system may be implemented on a single device or distributed across multiple devices. The functions of the computing elements may be combined with each other, or further divided into multiple submodules.

[0178] In some embodiments, the code executed on an appropriately programmed system during the generation or execution of a process simulation model may take the form of a software component, which may be stored on a non-volatile storage medium (e.g., a CD, a flash memory device, a removable hard drive, etc.), which contains a number of instructions that drive a computer device (e.g., a personal computer, a server, a network device, etc.).

[0179] To some extent, software components are implemented as groups of commands prepared by programmers / developers. However, modular software that can be executed by computer hardware is an executable code submitted to memory using "machine code" selected from a specific machine language instruction set, or "native instructions" designed into the hardware processor. The machine language instruction set or native instruction set is known to the hardware processor and is essentially built into the hardware processor. This is the "language" by which system and application software communicate with the hardware processor. Each native instruction is a discrete code that is recognized by the processing architecture and can specify a specific register for arithmetic, addressing, or control functions; a specific memory location or offset; and a specific addressing mode for interpreting operands. More complex operations are established by combining these simple native instructions, which are executed in sequence or otherwise directed by control flow instructions.

[0180] The relationship between executable software instructions and hardware processors is structural. In other words, the instructions themselves are a series of symbols or values. They do not convey any information per se. The processor is pre-configured by design to interpret the symbols / values, which gives meaning to the instructions.

[0181] The models used herein can be configured to be executed on a single machine at a single location, on multiple machines at a single location, or on multiple machines at multiple locations. When multiple machines are employed, individual machines can be customized for their specific tasks. For example, operations requiring large encoding blocks and / or significant processing power can be implemented on large and / or fixed machines.

[0182] In addition, some embodiments relate to tangible and / or non-transient computer-readable media or computer program products, which include program instructions and / or data (including data structures) for performing a number of computer-implemented operations. Examples of computer-readable media include, but are not limited to, semiconductor memory devices, phase change devices, magnetic media (e.g., disk drives, tapes), optical media (e.g., CDs), magneto-optical media, and hardware devices (e.g., read-only memory devices (ROM) and random access memory (RAM)) that are specifically configured to store and execute program instructions. The computer-readable medium may be directly controlled by the end user, or the medium may be indirectly controlled by the end user. An example of a directly controlled medium includes a medium located at a user facility, and / or a medium that is not shared with other entities. An example of an indirectly controlled medium includes a medium that can be indirectly connected to a user via an external network and / or via a service that provides shared resources (e.g., "the cloud"). Examples of program instructions include both machine code generated by an encoder and archives containing higher-order codes that can be executed by a computer using an interpreter.

[0183] In many embodiments, data or information used in the disclosed methods and apparatus are provided in electronic form. Such data or information may include design layouts, fixed parameter values, floating parameter values, feature profiles, metrology results, etc. When used herein, data or other information provided in electronic form can be used for storage on a machine and transmission between machines. Traditionally, data in electronic form is provided in digital form and can be stored as bits and / or bytes in a variety of data structures, lists, databases, etc. Data can be embodied electronically, optically, etc.

[0184] In some embodiments, the process simulation models can each be viewed as a form of application software that interfaces with a user and with system software. System software typically interfaces with computer hardware and associated memory. In some embodiments, system software includes operating system software and / or hardware, as well as any middleware and drivers installed in the system. System software provides the basic non-task-specific functions of the computer. Conversely, modules and other application software are used to perform specific tasks. Each native instruction for a module is stored in a memory device and represented by a numerical value.

[0185] An exemplary computer system 800 is depicted in Figure 7As shown, computer system 800 includes an input / output subsystem 802, which can be implemented for interfaces that interact with human users and / or other computer systems depending on the application. Embodiments of the present invention can be implemented in program code on system 800, and I / O subsystem 802 is used to receive input program descriptions and / or data from human users (e.g., via GUI or keyboard) and display the program descriptions and / or data back to the user. I / O subsystem 802 can include, for example, a keyboard, a mouse, a graphical user interface, a touch screen, or other input interfaces, and, for example, an LED or other flat panel display, or other output interfaces. Other components of embodiments of the present disclosure (e.g., an order engine) can be implemented together with a computer system that can be similar to computer system 800, but may not have I / O.

[0186] The program code may be stored in a non-transitory medium, such as a persistent storage device 810 or a memory 808, or both. One or more processors 804 read the program code from the one or more non-transitory media and execute the code to enable the computer system to perform the methods performed by the embodiments of the present invention, such as those involving the generation or use of process simulation models as described herein. It should be understood by those skilled in the art that the processor can receive source code, such as to perform training and / or modeling operations, and interpret or write the source code into machine code that is understandable at the hardware gate level of the processor. The bus couples the I / O subsystem 802, the processor 804, the peripheral device 806, the memory 808, and the persistent storage device 810.

[0187] in conclusion

[0188] In the description, many specific details are set forth to provide a thorough understanding of the embodiments presented. The disclosed embodiments may be implemented without some or all of these specific details. In other cases, well-known process operations are not described in detail so as not to unnecessarily obscure the disclosed embodiments. Although the disclosed embodiments are described in conjunction with specific embodiments, it should be understood that these specific embodiments are not intended to limit the disclosed embodiments.

Claims

1. A computer-implemented method for optimizing a process simulation model that predicts results of a semiconductor device manufacturing operation from process parameter values ​​that characterize the semiconductor device manufacturing operation, the method comprising: (a) receiving current values ​​of one or more floating process model parameters to be optimized; (b) generating a configured process simulation model by providing the current values ​​of the one or more floating process model parameters, an initial profile of a substrate undergoing the semiconductor device manufacturing operation, and a set of fixed process model parameter values ​​to the process simulation model; (c) generating, using the configured process simulation model, computational predictions of the semiconductor device manufacturing operations, wherein the computational predictions include predicted profiles of one or more substrate features; (d) comparing the computationally predicted results of the semiconductor device manufacturing operations with metrology results obtained from one or more substrate characteristics generated at least in part by performing the semiconductor device manufacturing operations in a reaction chamber operating at the set of fixed process parameter values, wherein the comparison generates one or more cost values ​​based on differences between the computationally predicted results of the semiconductor device manufacturing operations and the metrology results; (e) using the one or more cost values ​​and / or convergence checks to generate updated values ​​for the current values ​​of the one or more floating process model parameters; (f) performing operation (b) with the updated value of the current value of the one or more floating process model parameters; and (g) repeating (c)-(f) until the current values ​​of the one or more floating process model parameters converge to produce final values ​​of the one or more floating process model parameters that minimize the cost value; The one or more floating process model parameters are process model parameters that are to be optimized during the optimization process, and the fixed process model parameters are process model parameters that are required to execute the process simulation model but do not change during the optimization process.

2. The method of claim 1, wherein the semiconductor device manufacturing operation is a subtractive process or a material additive process. 3 . The method of claim 1 , wherein the semiconductor device manufacturing operation is an etching process, a planarization process, or a deposition process.

4. The method of claim 1 , wherein the set of fixed process model parameter values ​​or the one or more floating process model parameters include one or more temperature values ​​in the reaction chamber, one or more RF conditions in the reaction chamber, one or more process gases in the reaction chamber, a pressure in the reaction chamber, or any combination thereof.

5. The method of claim 1 , wherein the one or more floating process model parameters comprise characteristics of a substrate undergoing the semiconductor device fabrication operation, wherein the characteristics are reaction rate constants, reactant and / or product sticking coefficients, reactant diffusion constants, product diffusion constants, and / or light scattering properties.

6. The method of claim 1 , wherein the one or more floating process model parameters include vertical etch rate, lateral etch rate, nominal etch depth, etch selectivity, tilt angle of ion entry, twist angle of ion entry, visibility of entry features, angular distribution, sputtering maximum yield angle, and / or etch ratio per crystal direction.

7. The method of claim 1, wherein the one or more floating process model parameters comprise a combination of any two or more characteristics of a substrate undergoing the semiconductor device fabrication operation.

8. The method according to claim 1, wherein (b) generating a configured process simulation model further comprises: A profile of the substrate is provided to the process simulation model before the substrate undergoes the semiconductor device fabrication operation, wherein the profile of the substrate has one or more features to be modified by the semiconductor device fabrication operation.

9. The method of claim 1, whereby generating the operational prediction of the semiconductor device manufacturing operation in (c) uses the initial profile.

10. The method of claim 9, wherein the initial profile is computationally generated using information related to manufacturing steps occurring prior to the semiconductor device manufacturing operation.

11. The method of claim 10, wherein the initial profile is determined by performing metrology on one or more initial substrate features resulting from fabrication steps occurring prior to fabrication operations of the semiconductor device.

12. The method according to claim 1, wherein: The result of semiconductor device fabrication operations is a signal generated by the interaction of incident electromagnetic radiation with etched features, deposited features, or planarized features.

13. The method of any one of claims 1-12, wherein generating the operational prediction results of the semiconductor device manufacturing operation comprises: (i) generating a computational etching profile represented by a series of geometric profile coordinates using the configured process simulation model; and (ii) generating a calculated reflectance or ellipsometry spectrum from the calculated etch profile generated in (i) by simulating reflection of electromagnetic radiation off the calculated etch profile.

14. The method according to claim 13, further comprising: Prior to (ii), the operational etch profile is profile trimmed to even out some random profile variations.

15. The method of claim 13, wherein generating a calculated reflection or ellipsometry spectrum comprises performing a rigorous coupled wave analysis simulation using the calculated etch profile.

16. The method of claim 13, wherein generating the calculated reflectance or ellipsometry spectrum comprises performing a finite-difference time-domain simulation using the calculated etch profile.

17. The method according to claim 13, further comprising: performing the semiconductor device manufacturing operations on a test substrate under the set of fixed process model parameter values ​​to produce an etched substrate; as well as The etched substrate is exposed to incident electromagnetic radiation to produce an experimental reflectance spectrum including the metrology results.

18. The method of claim 13, further comprising generating one or more additional calculated reflectance or ellipsometry spectra.

19. The method of any one of claims 1-12, further comprising generating the metrology results by performing reflectometry, dome scatterometry, angle-resolved scatterometry, small-angle x-ray scatterometry, and / or ellipsometry on a substrate comprising features generated by performing the semiconductor device manufacturing operations in the reaction chamber operating under the set of fixed process model parameter values.

20. The method of any of claims 1-12, wherein a result of the semiconductor device fabrication operation is a profile of an etched feature, a profile of a deposited feature, or a profile of a planarized feature.

21. The method of any one of claims 1-12, wherein generating the operational prediction results of the semiconductor device manufacturing operation comprises: A computational etch profile represented by etch profile coordinates is generated using the configured process simulation model.

22. The method according to claim 21, further comprising: performing the semiconductor device manufacturing operation on a test substrate under the set of fixed process model parameter values ​​to produce an etched substrate; as well as Features of the etched substrate are measured to generate experimental etch profile coordinates including the metrology results.

23. The method of claim 22, wherein measuring features of the etched substrate comprises performing microscopy or optical metrology on the etched substrate.

24. The method of claim 23, wherein performing microscopy comprises performing transmission electron microscopy and / or scanning electron microscopy.

25. The method of any one of claims 1-12, wherein a result of the semiconductor device fabrication operation is a set of geometric profile parameters that characterize the geometry of etched features, deposited features, or planarized features.

26. The method of claim 25, wherein the geometric profile parameter is an optical critical dimension profile parameter.

27. The method of any one of claims 1-12, wherein generating the operational prediction results of the semiconductor device manufacturing operation comprises: (i) generating a computational etch profile represented by a series of etch profile coordinates using the configured process simulation model; as well as (ii) converting the computational etch profile generated in (i) into a first set of geometric profile parameters, wherein the first set of geometric profile parameters characterizes the geometry of the computational etch profile.

28. The method of claim 27, further comprising: performing the semiconductor device manufacturing operations on a test substrate under the set of fixed process model parameter values ​​to produce an etched substrate; measuring features of the etched substrate to generate experimental etch profile coordinates; as well as The experimental etch profile coordinates are converted into a second set of geometric profile parameters that characterize the geometry of etched features in the etched substrate.

29. The method of claim 28, wherein the one or more cost values ​​are based on a difference between the operationally predicted results using the first set of geometric profile parameters and the metrological results using the second set of geometric profile parameters.

30. The method according to any one of claims 1 to 12, wherein: The computational prediction results generated in (c) include a sequence of geometric profiles or profile parameters of substrate features computed from the configured process simulation model and corresponding to a time sequence representing different durations of a substrate-subtracting process or a substrate-adding process; and The metrology results of (d) comprise a sequence of geometric profiles or profile parameters of features of the substrate obtained from experimental measurements of the substrate at the different durations of the substrate-subtractive process or the substrate-additive process.

31. The method according to any one of claims 1 to 12, further comprising: (i) configuring the process simulation model using the final values ​​of the one or more floating process model parameters from (g); as well as (ii) using the process simulation model configured with the final values ​​of the one or more floating process model parameters from (g) to implement: Determining the pattern of the photolithography mask; and The photolithography mask is generated.

32. The method of claim 31 , wherein generating the photolithography mask comprises transferring the pattern to a resist layer.

33. The method of claim 32, further comprising developing the resist layer and transferring the pattern to an underlying chrome layer.

34. The method according to any one of claims 1 to 12, further comprising: (i) configuring the process simulation model with final values ​​of the one or more floating process model parameters from (g); (ii) utilizing the process simulation model configured with the final values ​​of the one or more floating process model parameters from (g) to achieve: identifying semiconductor processing equipment designs; and The semiconductor processing device is manufactured by using the design of the semiconductor processing device.

35. The method according to any one of claims 1 to 12, further comprising: (i) configuring the process simulation model with final values ​​of the one or more floating process model parameters from (g); (ii) identifying operating conditions of a semiconductor processing apparatus using the process simulation model configured with the final values ​​of the one or more floating process model parameters from (g) to enable manufacturing of semiconductor devices by operating the semiconductor processing apparatus under the operating conditions.

36. The method of any one of claims 1-12, wherein repeating (c)-(f) until the current values ​​of the one or more floating process model parameters converge comprises: A substantially local or global minimum is identified among the one or more obtained cost values.

37. The method of any one of claims 1-12, wherein generating the operational prediction result comprises: Local reaction rates at a grid of a plurality of points representing a feature profile on a semiconductor substrate are calculated using the configured process simulation model.

38. The method of claim 37, wherein the step of calculating local reaction rates using the configured process simulation model calculates reaction rates as a function of time.

39. The method according to any one of claims 1-12, further comprising obtaining the metering result by performing in-situ metering within the reaction chamber, non-destructive independent metering outside the reaction chamber, and / or independent destructive metering outside the reaction chamber.

40. A computer program product comprising a non-transitory computer readable medium on which instructions are provided for causing a computing system to execute an optimized process simulation model that calculates results of semiconductor device manufacturing operations from process parameter values ​​that characterize semiconductor device manufacturing operations, wherein the instructions include instructions for: (a) receiving process parameter values ​​as input to the process simulation model for said optimization; (b) executing the optimized process simulation model using the process parameter values, wherein the optimized process simulation model is optimized by: (i) receiving current values ​​of one or more floating process model parameters to be optimized, (ii) generating a configured process simulation model by providing the current values ​​of the one or more floating process model parameters, an initial profile of a substrate undergoing the semiconductor device manufacturing operation, and a set of fixed process model parameter values ​​to the process simulation model, (iii) generating, using the configured process simulation model, a computational prediction of the semiconductor device manufacturing operation, wherein the computational prediction includes a predicted profile of one or more substrate features, (iv) comparing the computationally predicted results of the semiconductor device manufacturing operations with metrology results obtained from one or more substrate characteristics generated at least in part by performing the semiconductor device manufacturing operations in a reaction chamber operating at the set of fixed process parameter values, wherein the comparison generates one or more cost values ​​based on differences between the computationally predicted results of the semiconductor device manufacturing operations and the metrology results, (v) using the one or more cost values ​​and / or convergence checks to generate updated values ​​for the current values ​​of the one or more floating process model parameters, (vi) performing operation (ii) with the updated value of the current value of the one or more floating process model parameters, and (vii) repeating (iii)-(vi) until the current values ​​of the one or more floating process model parameters converge to produce final values ​​of the one or more floating process model parameters that minimize the cost value; and (c) outputting the calculation results of the semiconductor device manufacturing operation; in, The one or more floating process model parameters are process model parameters that are to be optimized during the optimization process, and the fixed process model parameters are process model parameters that are required to execute the process simulation model but do not change during the optimization process.

41. The computer program product of claim 40, wherein the instructions further comprise instructions for: prior to (b), receiving an initial profile of a substrate undergoing the semiconductor device fabrication operation.

42. The computer program product of claim 40, wherein the one or more floating process model parameters include vertical etch rate, lateral etch rate, nominal etch depth, etch selectivity, tilt angle of ion entry, twist angle of ion entry, visibility of entry features, angular distribution, sputtering maximum yield angle, and / or etch ratio per crystal direction.

43. The computer program product of claim 40, wherein (ii) generating a configured process simulation model further comprises: A profile of the substrate is provided to the process simulation model before the substrate undergoes the semiconductor device fabrication operation, wherein the profile of the substrate has one or more features to be modified by the semiconductor device fabrication operation.

44. The computer program product of claim 40, wherein: The result of semiconductor device fabrication operations is a signal generated by the interaction of incident electromagnetic radiation with etched features, deposited features, or planarized features.

45. The computer program product of any one of claims 40-44, wherein generating the operational prediction results of the semiconductor device manufacturing operation comprises: generating a computational etch profile represented by a series of geometric profile coordinates using the configured process simulation model; as well as From the calculated etch profile, a calculated reflection or ellipsometry spectrum is generated by simulating reflection of electromagnetic radiation off the calculated etch profile.

46. ​​The computer program product of claim 45, wherein the optimized process simulation model is additionally optimized by: performing the semiconductor device manufacturing operations on a test substrate under the set of fixed process model parameter values ​​to produce an etched substrate; and The etched substrate is exposed to incident electromagnetic radiation to produce an experimental reflectance spectrum including the metrology results.

47. The computer program product of claim 40, wherein the optimized process simulation model is additionally optimized by generating the metrology results by performing reflectometry, dome scatterometry, angle-resolved scatterometry, small-angle x-ray scatterometry, and / or ellipsometry on a substrate comprising features generated by performing the semiconductor device manufacturing operations in the reaction chamber operating under the set of fixed process model parameter values.

48. The computer program product of claim 40, wherein generating the operational prediction results of the semiconductor device manufacturing operations comprises: A computational etch profile represented by etch profile coordinates is generated using the configured process simulation model.

49. The computer program product of claim 48, wherein the optimized process simulation model is additionally optimized by: performing the semiconductor device manufacturing operations on a test substrate under the set of fixed process model parameter values ​​to produce an etched substrate; and Features of the etched substrate are measured to generate experimental etch profile coordinates including the metrology results.

50. The computer program product of claim 40, wherein a result of the semiconductor device fabrication operation is a set of geometric profile parameters that characterize the geometry of etched features, deposited features, or planarized features.

51. The computer program product of claim 50, wherein the geometric profile parameters are optical critical dimension profile parameters.

52. The computer program product of claim 40, wherein generating the operational prediction results of the semiconductor device manufacturing operations comprises: generating a computational etch profile represented by a series of etch profile coordinates using the configured process simulation model; as well as The computational etch profile is converted into a first set of geometric profile parameters that characterize the geometry of the computational etch profile.

53. The computer program product of claim 52, wherein the optimized process simulation model is additionally optimized by: performing the semiconductor device manufacturing operations on a test substrate under the set of fixed process model parameter values ​​to produce an etched substrate; measuring features of the etched substrate to generate experimental etch profile coordinates; and The experimental etch profile coordinates are converted into a second set of geometric profile parameters that characterize the geometry of etched features in the etched substrate.

54. The computer program product of any one of claims 40-44, further comprising instructions for using the calculation results to determine a pattern of a lithography mask.

55. The computer program product of any one of claims 40-44, further comprising instructions for using the calculation results to identify a design of a semiconductor processing device.

56. The computer program product according to any one of claims 40-44, further comprising instructions for using the calculation result to identify an operating condition of a semiconductor processing apparatus to implement manufacturing of a semiconductor device by operating the semiconductor processing apparatus under the operating condition.

57. A system comprising the computer program product of any one of claims 40-44 and a lithography mask generation apparatus, the lithography mask generation apparatus being configured to determine a lithography mask pattern using the calculation results of the semiconductor device manufacturing operation.

58. A system comprising the computer program product of any one of claims 40-44 and a semiconductor processing apparatus configured to operate under process conditions provided in the calculated results of the semiconductor device manufacturing operation.

59. A computer-implemented method for optimizing a process simulation model that predicts outcomes of semiconductor device manufacturing operations from process parameter values ​​that characterize the semiconductor device manufacturing operations, the method comprising: (a) receiving current values ​​of one or more floating process model parameters to be optimized; (b) generating a configured process simulation model by providing the current values ​​of the one or more floating process model parameters, an initial profile of a substrate undergoing the semiconductor device manufacturing operation, and a set of fixed process model parameter values ​​to the process simulation model; (c) generating, using the configured process simulation model, computational predictions of the semiconductor device manufacturing operations, wherein the computational predictions include predicted profiles of one or more substrate features; (d) comparing the computational predictions of the semiconductor device manufacturing operations with top-down metrology results obtained from one or more substrate features generated at least in part by performing the semiconductor device manufacturing operations in a reaction chamber operating at the set of fixed process parameter values, wherein the comparison generates one or more cost values ​​based on differences between the computational predictions of the semiconductor device manufacturing operations and the top-down metrology results; (e) using the one or more cost values ​​and / or convergence checks to generate updated values ​​for the current values ​​of the one or more floating process model parameters; (f) performing operation (b) with the updated value of the current value of the one or more floating process model parameters; and (g) repeating (c)-(f) until the current values ​​of the one or more floating process model parameters converge to produce final values ​​of the one or more floating process model parameters that minimize the cost value; The one or more floating process model parameters are process model parameters that are to be optimized during the optimization process, and the fixed process model parameters are process model parameters that are required to execute the process simulation model but do not change during the optimization process.

60. The method of claim 59, wherein the top-view metrology results comprise one or more CD-SEM images of the one or more substrate features produced at least in part by performing the semiconductor device fabrication operations in a reaction chamber operating at the set of fixed process parameter values.

61. The method of claim 59 or 60, wherein (d) further comprises comparing the computationally predicted results of the semiconductor device manufacturing operation with profile-based metrology results obtained from the one or more substrate features, the one or more substrate features being generated at least in part by performing the semiconductor device manufacturing operation in a reaction chamber operating under the set of fixed process parameter values, and The one or more cost values ​​constitute at least one cost function based on a difference between the computational prediction results and the profile-based metrology results of the semiconductor device manufacturing operation.

62. The method of claim 61, wherein the profile-based metrology results are obtained by a CD-SAXS metrology procedure.

63. The method of claim 61, wherein the profile-based metrology results are obtained by a transmission electron microscopy metrology procedure.

64. The method of claim 61, wherein the profile-based metrology results are obtained by an optical critical dimension metrology procedure.

65. A computer program product comprising a non-transitory computer readable medium on which instructions are provided for causing a computing system to execute an optimized process simulation model that calculates results of semiconductor device manufacturing operations from process parameter values ​​that characterize semiconductor device manufacturing operations, wherein the instructions include instructions for: (a) receiving process parameter values ​​as input to the process simulation model for said optimization; (b) executing the optimized process simulation model using the process parameter values, wherein the optimized process simulation model is optimized by: (i) receiving current values ​​of one or more floating process model parameters to be optimized, (ii) generating a configured process simulation model by providing the current values ​​of the one or more floating process model parameters, an initial profile of a substrate undergoing the semiconductor device manufacturing operation, and a set of fixed process model parameter values ​​to the process simulation model, (iii) generating, using the configured process simulation model, a computational prediction of the semiconductor device manufacturing operation, wherein the computational prediction includes a predicted profile of one or more substrate features, (iv) comparing the computationally predicted results of the semiconductor device manufacturing operations with top-down metrology results obtained from one or more substrate features produced at least in part by performing the semiconductor device manufacturing operations in a reaction chamber operating at the set of fixed process parameter values, wherein the comparison generates one or more cost values ​​based on differences between the computationally predicted results of the semiconductor device manufacturing operations and the top-down metrology results, (v) using the one or more cost values ​​and / or convergence checks to generate updated values ​​for the current values ​​of the one or more floating process model parameters, (vi) performing operation (ii) with the updated value of the current value of the one or more floating process model parameters, and (vii) repeating (iii)-(vi) until the current values ​​of the one or more floating process model parameters converge to produce final values ​​of the one or more floating process model parameters that minimize the cost value; and (c) outputting the calculation results of the semiconductor device manufacturing operation; in, The one or more floating process model parameters are process model parameters that are to be optimized during the optimization process, and the fixed process model parameters are process model parameters that are required to execute the process simulation model but do not change during the optimization process.

66. The computer program product of claim 65, wherein the top-down metrology results comprise one or more CD-SEM images of the one or more substrate features produced at least in part by performing the semiconductor device fabrication operations in a reaction chamber operating at the set of fixed process parameter values.

67. A computer program product according to claim 65 or 66, wherein (iv) further comprises comparing the computationally predicted results of the semiconductor device manufacturing operation with profile-based metrology results obtained from the one or more substrate features, the one or more substrate features being generated at least in part by performing the semiconductor device manufacturing operation in a reaction chamber operating under the set of fixed process parameter values, and The one or more cost values ​​constitute at least one cost function based on a difference between the computational prediction results and the profile-based metrology results of the semiconductor device manufacturing operation.

68. The computer program product of claim 67, wherein the profile-based metrology results are obtained by a CDSAXS metrology procedure.

69. The computer program product of claim 67, wherein the profile-based metrology results are obtained by a transmission electron microscopy metrology procedure.

70. The computer program product of claim 67, wherein the profile-based metrology results are obtained by an optical critical dimension metrology procedure.

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