Package structure and method of forming a package structure

Abstract

Some embodiments of the present disclosure provide a package structure and a method of forming a package structure. The package structure includes a first via structure formed in a substrate and a semiconductor die formed below the first via structure. The package structure also includes a conductive structure formed in a cap layer above the substrate. The conductive structure includes a first via portion formed directly above the first via structure and a second via portion, and no conductive material is formed directly below the second via portion and directly contacts the second via portion.

Description

Technical Field

[0001] Some embodiments of this disclosure relate to a packaging structure. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then patterning these material layers using photolithography to form circuit components and elements thereon. Many integrated circuits are typically fabricated on a single semiconductor wafer, and individual dies on the wafer are separated by wire cuts along the lines defined between the integrated circuits. These individual dies are typically packaged separately, for example, in multi-wafer modules or other package types.

[0003] Novel packaging technologies, such as package-on-package (PoP), have begun to be developed, in which a top package with a device die is bonded to a bottom package with another device die. By employing novel packaging technologies, various packages with different or similar functions can be integrated together.

[0004] Although existing packaging structures and methods for manufacturing them are generally applicable to the desired purpose, they are not entirely satisfactory in all aspects. Summary of the Invention

[0005] The purpose of this disclosure is to provide a packaging structure to solve at least one of the above-mentioned problems.

[0006] Some embodiments of this disclosure provide a packaging structure. The packaging structure includes a first through-hole structure and a semiconductor die. The first through-hole structure is formed in a substrate. The semiconductor die is formed below the first through-hole structure. The packaging structure also includes a conductive structure. The conductive structure is formed in a sheath above the substrate. The conductive structure includes a first via portion and a second via portion. The first via portion is formed directly above the first through-hole structure, and no conductive material is formed directly below and in direct contact with the second via portion.

[0007] Some embodiments of this disclosure provide a packaging structure. The packaging structure includes a through-hole structure and a first semiconductor die. The through-hole structure is formed in a packaging layer. The first semiconductor die is formed adjacent to the through-hole structure. The packaging structure includes a first via portion and a second via portion. The first via portion is formed directly on the through-hole structure. The second via portion is adjacent to the first via portion. The second via portion has a first end and a second end in a vertical direction, and the first end directly contacts the packaging layer. The packaging structure also includes a first wire portion and a second wire portion. The first wire portion is formed on the first via portion. The second wire portion is formed on the second via portion. The first wire portion is connected to the second wire portion, and the second end of the second via portion directly contacts the second wire portion. The packaging structure further includes a connector. The connector is formed on the second via portion. The connector includes a protrusion, and the second via portion is formed directly below the protrusion of the connector.

[0008] Some embodiments of this disclosure provide a method for forming a package structure. The method includes forming a via structure in a substrate and forming a semiconductor die below the substrate. The method further includes forming a first sheath layer above the substrate, and forming a first opening and a second opening in the first sheath layer. The first opening exposes the via structure, and the second opening exposes the substrate. The first opening has a circular shape when viewed from above, and both openings have a circular shape when viewed from above. The method also includes forming a conductive material in the first and second openings, and the conductive material is also formed above the first sheath layer to form a conductive structure. The conductive structure includes a first via portion in the first opening and a second via portion in the second opening. The first via portion is formed directly above the via structure, and the bottom surface of the second via portion directly contacts the substrate.

[0009] The beneficial effects of this disclosure are that the package structure includes a first via structure formed in a substrate. A semiconductor die is formed below the first via structure, and a conductive structure is formed above the substrate. The conductive structure includes a first portion and a second portion. The first portion includes a first via portion and a first metal portion. The second portion includes a second via portion and a second metal portion. A conductive connector is formed on the conductive structure. The first via portion is formed directly on the first via structure, and the bottom surface of the second via portion directly contacts the substrate. The second via portion acts as a support to reduce stress. This reduces the formation of cracks and voids. Therefore, the quality, yield, and reliability of the package structure are improved. Attached Figure Description

[0010] The various aspects of this disclosure are best understood from the following detailed description when reading the accompanying drawings. It should be noted that the features are not necessarily drawn to scale. In fact, the dimensions of the features may be arbitrarily enlarged or reduced for clarity of illustration.

[0011] Figures 1A to 1I Cross-sectional views are shown of various stages in forming the packaging structure according to some embodiments of the present disclosure.

[0012] Figure 1I' A cross-sectional view of a packaging structure according to some embodiments of the present disclosure is shown.

[0013] Figure 2A The first opening and the second opening according to some embodiments of the present disclosure are shown along... Figure 1F A top view of line A-A'.

[0014] Figure 2B The first guide hole portion and the second guide hole portion according to some embodiments of the present disclosure are shown along... Figure 1G A top view of line B-B'.

[0015] Figure 2C A top view of a first guide hole portion and a second guide hole portion according to some embodiments of the present disclosure is shown.

[0016] Figure 2D The first guide hole portion and the second guide hole portion are shown along some embodiments of the present disclosure. Figure 1G A top view of the D-D' line.

[0017] Figure 3 Some embodiments according to this disclosure are shown. Figure 1G An enlarged view of region A in the image.

[0018] Figures 4A to 4B Cross-sectional views are shown of various stages of a first portion and a second portion of a conductive structure forming an encapsulation structure according to some embodiments of the present disclosure.

[0019] Figure 4C The first guide hole portion and the second guide hole portion according to some embodiments of the present disclosure are shown along... Figure 4B A top view of the C-C' line.

[0020] Figure 5A A top view of a conductive structure according to some embodiments of the present disclosure is shown.

[0021] Figure 5B A top view showing the positional relationship between the conductive structure and the conductive connector according to some embodiments of the present disclosure.

[0022] Figures 6A to 6E Cross-sectional views are shown of various stages in forming the packaging structure according to some embodiments of the present disclosure.

[0023] The attached figures are labeled as follows:

[0024] 100a, 100b, 100c, 100d: Package structure

[0025] 102,602,621:Substrate

[0026] 102a: Front surface

[0027] 102b: Back surface

[0028] 103: Barrier Layer

[0029] 104: Conductive Structure

[0030] 108, 608: Through-hole structure

[0031] 109: Insulation layer

[0032] 110, 122, 610: Internal Wiring Structure

[0033] 112: Dielectric layer

[0034] 114,124,614,664: Conductive layer

[0035] 116, 126, 624: Conductive pads

[0036] 120, 620, 680: Semiconductor dies

[0037] 121:Substrate

[0038] 128,156,676,682: Conductive connectors

[0039] 130: Bottom filling layer

[0040] 136,650: Encapsulation layer

[0041] 139,667: Substrate

[0042] 140: First protective layer

[0043] 141: First Opening

[0044] 145: Second opening

[0045] 145a: The first part of the second opening

[0046] 145b: The second part of the second opening

[0047] 148,648: Conductive structure

[0048] 1481, 6481: The first part of the conductive structure

[0049] 1482, 6482: The second part of the conductive structure

[0050] 148a, 648a: First guide hole section

[0051] 148b, 648b: First metal part

[0052] 148c, 648c: Second guide hole section

[0053] 148d, 648d: Second metal part

[0054] 150: Second protective layer

[0055] 151: Third opening

[0056] 155: Under-bump metal layer

[0057] 156a, 676a: Protrusions

[0058] 156b, 676b: Top

[0059] 604, 612, 622, 660: Protective coating

[0060] 619: Adhesive film

[0061] D1, Da: First diameter

[0062] D2, Db: Second diameter

[0063] Dc: Third diameter

[0064] Dd: Fourth diameter

[0065] S1: First distance Detailed Implementation

[0066] The following disclosure provides numerous different embodiments or examples to implement various features of this disclosure. Specific examples of the various components and their arrangements are described below to simplify this disclosure. Of course, these examples are for illustrative purposes only and are not intended to be limiting. For example, if the specification describes a first feature formed above a second feature, it indicates that it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features are not in direct contact. Furthermore, in various examples, this disclosure may use repeated reference numerals and / or letters. Such repetition is for simplification and clarity and does not imply any association between the various embodiments and / or configurations discussed.

[0067] Several variations of the embodiments are described. Similar reference numerals are used to denote similar elements in the accompanying drawings and exemplary embodiments of various aspects of this disclosure. It should be understood that additional operations may be provided before, during, and after the method, and that some described operations may be substituted or omitted in other embodiments of the method.

[0068] Other features and processes may also be included. For example, test structures may be included to aid in the verification testing of 3D packaged or 3D integrated circuit devices. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which allow for testing of the 3D packaged or 3D integrated circuit using probes and / or probe cards, etc. Verification tests can be performed on intermediate and final structures. Additionally, the structures and methods disclosed herein can be combined with test methods that incorporate intermediate verification of existing good dies to increase yield and reduce costs.

[0069] Some embodiments of this disclosure provide packaging structures and methods for forming the same. Figures 1A to 1I Cross-sectional views are shown of various stages in forming a package structure 100a according to some embodiments of the present disclosure. The package structure 100a may be a chip-on-a-wafer (CoWoS) on a substrate or other suitable package. The package structure 100a includes a via structure formed over a semiconductor die and a conductive structure formed over the via structure. The conductive structure includes a first via portion and a second via portion. Both ends of the first via portion are available for connection, but only one end of the second via portion is available for connection. The second via portion is formed to reduce stress and prevent the formation of cracks and voids.

[0070] like Figure 1A As shown, a substrate 102 is provided. The substrate 102 includes a front surface 102a and a rear surface 102b. The substrate 102 may be made of silicon or other semiconductor materials. Optionally or additionally, the substrate 102 may include other elemental semiconductor materials, such as germanium. In some embodiments, the substrate 102 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 102 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenide, or indium gallium phosphide. In some embodiments, the substrate 102 includes an epitaxial layer. For example, the substrate 102 has an epitaxial layer covering a bulk semiconductor.

[0071] A plurality of conductive structures 104 are formed in a substrate 102. The conductive structures 104 extend from the front surface 102a of the substrate 102 toward the rear surface 102b of the substrate 102. In some embodiments, the conductive structures 104 are formed by forming a plurality of trenches (not shown) extending from the front surface 102a of the substrate 102. Subsequently, a barrier layer 103 is filled into each trench, and the conductive structures 104 are formed on the barrier layer 103 and in each trench.

[0072] An interconnect structure 110 is formed above the conductive structure 104 and the substrate 102. The interconnect structure 110 can serve as a redistribution (RDL) structure for wiring. The interconnect structure 110 includes a plurality of conductive layers 114 and a plurality of conductive pads 116 formed in a plurality of dielectric layers 112. In some embodiments, the conductive pads 116 are exposed on the top surface of the topmost dielectric layer 112 as bonding pads, or the conductive pads 116 protrude from the top surface of the topmost dielectric layer 112.

[0073] The dielectric layer 112 may be made of or comprise one or more polymer materials. The one or more polymer materials may include polyphenylene oxide. The dielectric layer 112 may be made of or comprise a dielectric material other than a polymeric material, such as polybenzoxazole (PBO), polyimide (PI), one or more other suitable polymeric materials, or a combination thereof. In some embodiments, some or all of the dielectric layer 112 may be made of or comprise a dielectric material other than a polymeric material. The dielectric material may include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more other suitable materials, or a combination thereof.

[0074] The conductive layer 114 and the conductive pad 116 may be made of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta), or tantalum alloy. In some embodiments, the conductive layer 114 and the conductive pad 116 are formed by electroplating, electroless plating, printing, chemical vapor deposition (CVD), or physical vapor deposition (PVD).

[0075] After that, as Figure 1B As shown, according to some embodiments of the present disclosure, a semiconductor die 120 is formed above the conductive layer 116. The semiconductor die 120 includes a substrate 121 and an interconnect structure 122 above the substrate 121. The interconnect structure 122 of the semiconductor die 120 includes a plurality of conductive layers 124.

[0076] In some embodiments, a semiconductor die 120 is diced from a wafer, and the semiconductor die 120 may be a "known-good-die." The semiconductor die 120 may be a system-on-chip (SoC) chip or a memory die. In some other embodiments, the semiconductor die 120 is a system-on-integrated circuit (SoIC) device, which includes two or more chips with integrated functionality. In some embodiments, the memory die includes a static random access memory (SRAM) device, a dynamic random access memory (DRAM) device, a high bandwidth memory (HBM) device, or another memory die. The number of semiconductor dies 120 is not limited to two and can be adjusted according to the specific application.

[0077] In some embodiments, a plurality of conductive pads 126 are formed under the conductive layer 124 of the semiconductor die 120, and each conductive pad 126 is connected to each conductive pad 116 via a plurality of conductive connectors 128.

[0078] The conductive pad 126 is made of a metallic material, such as copper, copper alloy, aluminum, aluminum alloy, tungsten, tungsten alloy, titanium, titanium alloy, tantalum, or tantalum alloy. In some embodiments, the conductive pad 126 is formed by electroplating, electroless plating, printing, chemical vapor deposition, or physical vapor deposition.

[0079] The conductive connector 128 is made of solder material, such as tin (Sn), tin-silver (SnAg), tin-lead (SnPb), tin-copper (SnCu), tin-silver-copper (SnAgCu), tin-silver-zinc (SnAgZn), tin-zinc (SnZn), tin-bismuth-indium (SnBiIn), tin-indium (SnIn), tin-gold (SnAu), tin-zinc-indium (SnZnIn), tin-silver-antimony (SnAgSb), or other suitable materials. In some embodiments, the conductive connector 128 is formed by electroplating, electroless plating, printing, chemical vapor deposition, or physical vapor deposition processes.

[0080] Next, as Figure 1C As shown, according to some embodiments of this disclosure, a bottom fill layer 130 is formed between the semiconductor die 120 and the interconnect structure 110. The bottom fill layer 130 surrounds and protects the conductive connector 128. In some embodiments, the bottom fill layer 130 directly contacts the conductive connector 128.

[0081] In some embodiments, the underfill layer 130 is made of or comprises a polymeric material. The underfill layer 130 may comprise an epoxy resin. In some embodiments, the underfill layer 130 comprises fillers dispersed in the epoxy resin.

[0082] In some embodiments, forming the underfill layer 130 involves an injection process, a spin coating process, a dispensing process, a film lamination process, an application process, one or more other applicable processes, or a combination of the foregoing processes. In some embodiments, a thermosetting process is used during the formation of the underfill layer 130.

[0083] Subsequently, an encapsulation layer 136 is formed above the bottom fill layer 130. An interface exists between the bottom fill layer 130 and the encapsulation layer 136, and this interface is lower than the top surface of the semiconductor die. The encapsulation layer 136 surrounds and protects the semiconductor die 120. In some embodiments, the encapsulation layer 136 directly contacts a portion of the semiconductor die 120.

[0084] Encapsulation layer 136 is made of a formable compound material. The formable compound material may include a polymer material, such as an epoxy resin with dispersed fillers. In some embodiments, a liquid formable compound material is applied over semiconductor dies 120. The liquid formable compound material may flow into the space between semiconductor dies 120. A thermal process is then used to cure the liquid formable compound material and transfer it into the encapsulation layer 136.

[0085] After that, as Figure 1D As shown, according to some embodiments of this disclosure, a portion of the encapsulation layer 136 is removed. This exposes the top surface of the semiconductor die 120. The top surface of the semiconductor die 120 is substantially flush with the top surface of the encapsulation layer 136. Where appropriate, the term "substantially" may also correspond to 90% or higher, for example: 95% or higher, particularly 99% or higher, including 100%.

[0086] In some embodiments, a planarization process is used to thin the encapsulation layer 136. The planarization process may include chemical mechanical polishing (CMP), grinding, etching, other suitable processes, or a combination of the foregoing.

[0087] Next, as Figure 1EAs shown, according to some embodiments, substrate 102 is inverted and placed above a carrier substrate 139. In some embodiments, carrier substrate 139 serves as a temporary substrate. During subsequent process steps (e.g., processes described in more detail later), the temporary substrate provides mechanical and structural support. Carrier substrate 139 is made of semiconductor material, ceramic material, polymer material, metallic material, other suitable materials, or combinations thereof. In some embodiments, carrier substrate 139 is a glass substrate. In some other embodiments, carrier substrate 139 is a semiconductor substrate, such as a silicon wafer.

[0088] Subsequently, the substrate 102 is thinned using the carrier substrate 139 as a support. In some embodiments, the substrate 102 is thinned from the rear surface 102b until the conductive structure 104 is exposed. In some embodiments, the conductive structure 104 and the barrier layer 103 are exposed and pass through the thinned substrate 102. Thus, a via structure 108 is formed in the substrate 102. In some embodiments, the via structure 108 is a through substrate via (TSV) structure. In some other embodiments, the via structure 108 may be referred to as a through silicon via (TSV).

[0089] After that, as Figure 1F As shown, according to some embodiments of this disclosure, the carrier substrate 139 is removed, and a first passivation layer 140 is formed on the rear surface 102b of the substrate 102. A first opening 141 is formed in the first passivation layer 140 to expose the through-hole structure 108, and a second opening 145 is formed in the first passivation layer 140 to expose the substrate 102. The first opening 141 has an inclined sidewall surface, and the second opening 145 also has an inclined sidewall surface.

[0090] The first protective layer 140 is made of polystyrene. The first protective layer 140 may be made of an organic material, such as azole, benzocyclobutene (BCB), silicone, acrylate, siloxane, other suitable materials, or combinations thereof. In some other embodiments, the first protective layer 140 may be made of an organic material. Organic materials include silicon oxide, undoped silicon glass, silicon oxynitride, silicon nitride, silicon carbide, other suitable materials, or combinations thereof. In some embodiments, the first protective layer 140 is formed by a deposition process, such as physical vapor deposition, chemical vapor deposition, or other suitable processes.

[0091] The first opening 141 and the second opening 145 are formed by a patterning process. The patterning process includes photolithography and etching. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying (e.g., hard baking). The etching process may include dry etching or wet etching.

[0092] Figure 2A The first opening 141 and the second opening 145, according to some embodiments of the present disclosure, are shown along... Figure 1F A top view of line A-A'.

[0093] The first opening 141 and the second opening 145 are both circular when viewed from above. The diameter of the first opening 141 gradually decreases from top to bottom, and the diameter of the second opening 145 also gradually decreases from top to bottom. In some embodiments, the bottom surface of the first opening 141 has a first diameter D1, and the bottom surface of the second opening 145 has a second diameter D2. The second diameter D2 is larger than the first diameter D1. In some embodiments, the first diameter D1 of the bottom surface of the first opening 141 is in the range of about 15 micrometers to about 20 micrometers. In some embodiments, the second diameter D2 of the bottom surface of the second opening 145 is in the range of about 40 micrometers to about 50 micrometers.

[0094] Next, as Figure 1G As shown, according to some embodiments of this disclosure, a conductive material is formed in the first opening 141 and the second opening 145 to form a conductive structure 148. Therefore, the conductive structure 148 includes a first portion 1481 and a second portion 1482. The first portion 1481 includes a first guide hole portion 148a in the first opening 141 and a first metal portion 148b on the first guide hole portion 148a. The second portion 1482 includes a second guide hole portion 148c in the second opening 145 and a second metal portion 148d on the second guide hole portion 148c. The bottom surface of the first guide hole portion 148a is flush with the bottom surface of the second guide hole portion 148c. Figure 1G The dashed lines shown are for the purpose of providing a more convenient understanding of the structure. However, there is no actual boundary between the first guide hole portion 148a and the first metal portion 148b, nor is there an actual boundary between the second guide hole portion 148c and the second metal portion 148d.

[0095] It should be noted that the first via portion 148a has a first end and a second end in the vertical direction. The first end directly contacts the through-hole structure 108, while the second end directly contacts the first metal portion 148b. The second via portion 148c has a first end and a second end in the vertical direction. The first end directly contacts the substrate 102, and the second end directly contacts the second metal portion 148d. The first metal portion 148b is physically connected to and electrically connected to the second metal portion 148d. The second via portion 148c is electrically connected to the through-hole structure 108 through the second metal portion 148d, the first metal portion 148b, and the first via portion 148a.

[0096] It should be noted that both ends of the first via portion 148a can be electrically connected to other conductive materials, but only one end of the second via portion 148c can be electrically connected to other conductive materials. The entire bottom surface of the second via portion 148c directly contacts the substrate 102. Therefore, no conductive layer or conductive material is formed directly beneath the second via portion 148c, and no conductive layer or conductive material directly contacts the second via portion 148c. The bottom surface of the second via portion 148c does not directly contact conductive material or conductive layer. The first metal portion 148b has a recessed top surface, and the second metal portion 148d also has a recessed top surface. The second via portion 148c is located between two adjacent through-hole structures 108.

[0097] After forming conductive material in the first opening 141 and the second opening 145 and above the substrate 102, a portion of the conductive material is removed by an etching process such as dry etching or wet etching to form a conductive structure 148.

[0098] The conductive material may be made of copper, copper alloys, aluminum, aluminum alloys, tungsten, tungsten alloys, titanium, titanium alloys, tantalum, or tantalum alloys. In some embodiments, the conductive material is formed by electroplating, electroless plating, printing, chemical vapor deposition, or physical vapor deposition.

[0099] Figure 2B The first guide hole portion 148a and the second guide hole portion 148c according to some embodiments of the present disclosure are shown along... Figure 1G A top view of line B-B'.

[0100] like Figure 2B As shown, the second guide hole portion 148c is separated from the first guide hole portion 148a by the first protective layer 140 along the B-B' line in the horizontal direction. The width or diameter of the second guide hole portion 148c is greater than the width or diameter of the first guide hole portion 148a.

[0101] Figure 2CA top view of a first guide hole portion 148a and a second guide hole portion 148c according to some embodiments of the present disclosure is shown. Figure 1G Some embodiments according to this disclosure are shown along Figure 2C A cross-sectional view of the C-C' line. Figure 2B for Figure 2C Part of, and Figure 2C The positional relationship between the second via portion 148c and the semiconductor die 120 is shown.

[0102] like Figure 2C As shown, in some embodiments, the second via portion 148c is located in the peripheral region, outside the semiconductor die 120. The second via portion 148c is located at a corner of the semiconductor die 120. In some embodiments, the second via portion 148c is located in the middle portion between two adjacent semiconductor dies 120. In some other embodiments, the second via portion 148c is located directly on the semiconductor die 120.

[0103] Figure 2D The first guide hole portion 148a and the second guide hole portion 148c according to some embodiments of the present disclosure are shown along... Figure 1G A top view of the D-D' line.

[0104] like Figure 2D As shown, the first metal portion 148b and the second metal portion 148d form a polygonal shape, for example, an octagonal shape, when viewed from above. The first metal portion 148b overlaps the through-hole structure 108. The first metal portion 148b and the second metal portion 148d cover the first guide hole portion 148a and the second guide hole portion 148c. More specifically, the first guide hole portion 148a (shown in dashed lines) and the second guide hole portion 148c (shown in dashed lines) are formed directly below the first metal portion 148b and the second metal portion 148d.

[0105] Figure 3 Some embodiments according to this disclosure are shown. Figure 1GAn enlarged view of region A. The bottom surface of the first guide hole portion 148a has a first diameter Da, and the bottom surface of the first metal portion 148b has a second diameter Db. The bottom surface of the second guide hole portion 148c has a third diameter Dc, and the bottom surface of the second metal portion 148d has a fourth diameter Dd. The first diameter Da is smaller than the third diameter Dc, and the second diameter Db is smaller than the fourth diameter Dd. The second diameter Db is smaller than the third diameter Dc. In some embodiments, the first diameter Da is in the range of about 15 micrometers to about 20 micrometers, and the second diameter Db is in the range of about 18 micrometers to about 23 micrometers. In some embodiments, the third diameter Dc is in the range of about 40 micrometers to about 50 micrometers, and the fourth diameter Dd is in the range of about 45 micrometers to about 55 micrometers.

[0106] The distance between the edge of the first via portion 148a and the edge of the second via portion 148c is a first distance S1. In some embodiments, the first distance S1 is smaller than the diameter of the second via portion 148c of the conductive structure 148. In some embodiments, the first distance S1 is in the range of about 10 micrometers to about 15 micrometers. If the first distance S1 is less than 10 micrometers, the stress generated in the first via portion 148a and the second via portion 148c may not be balanced and may cause unwanted cracks. If the first distance S1 is greater than 15 micrometers, the size of the conductive structure 148 may be too large and occupy too much wiring area.

[0107] After that, as Figure 1H As shown, according to some embodiments of this disclosure, a second sheath 150 is formed over the first sheath 140 and on the conductive structure 148. Then, a portion of the second sheath 150 is removed to form a third opening 151. The third opening 151 is formed directly over the second metal portion 148d.

[0108] Next, as Figure 1I As shown, according to some embodiments of this disclosure, an under bump metallurgy (UBM) layer 155 is formed in the third opening 151, and a conductive connector 156 is formed above the UBM layer 155. The UBM layer 155 is formed directly above the second via portion 148c of the conductive structure 148. The conductive connector 156 is electrically connected to the conductive structure 148 through the UBM layer 155. The conductive connector 156 overlaps a portion of the via structure 108.

[0109] The under-bump metal layer 155 may be made of a conductive material, such as copper, copper alloy, aluminum, aluminum alloy, tungsten, tungsten alloy, titanium, titanium alloy, tantalum, or tantalum alloy. In addition, the under-bump metal layer 155 may contain an adhesive layer and / or a wetting layer. In some embodiments, the under-bump metal layer 155 further includes a copper seed layer. In some embodiments, the under-bump metal layer 155 includes an adhesive layer made of Ti / Cu and a wetting layer made of Cu. In some embodiments, the under-bump metal layer 155 is formed by an electroplating process, such as an electrochemical electroplating process or an electroless process.

[0110] In some embodiments, the conductive connector 156 is made of a metal layer, such as copper, copper alloy, nickel, nickel alloy, aluminum, aluminum alloy, tin, tin alloy, lead, lead alloy, silver, silver alloy, or a combination of the aforementioned metals or alloys. In some embodiments, the conductive connector 156 is formed by an electroplating process, such as an electrochemical electroplating process or an electroless process.

[0111] The conductive connector 156 includes a protrusion 156a and a top 156b. The protrusion 156a is formed in a third opening 151, and the top 156b is formed above the protrusion 156a. The protrusion 156a extends toward the inner interconnect structure 110 and the through-hole structure 108. The protrusion 156a is embedded in a first sheath 140. Figure 1I The dashed lines shown are for the purpose of providing a more convenient understanding of the structure; however, there is no actual boundary or division between the protrusion 156a and the top 156b.

[0112] Because the conductive structure 148 and the first sheath 140 are made of different materials, the coefficient of thermal expansion (CTE) of the conductive structure 148 is mismatched with that of the first sheath 140. As the package structure 100a miniaturizes, the difference in CTE between the materials of the structures (e.g., the sheath and the conductive material (redistribution layer)) causes stress to accumulate at the conductive structure / sheath interface. Furthermore, because the conductive connector 156 is offset relative to the via structure 108, the stress in the first region (directly above the via structure 108) and the stress in the second region (directly below the conductive connector 156) are different and not balanced. This unbalanced stress may cause cracks in the conductive structure or voids in the sheath during the packaging process.

[0113] It should be noted that, since the through-hole structure 108 is not aligned with the conductive connector 156, the second via portion 148c is formed directly below the conductive connector 156 to provide support and balance stress. More specifically, the second via portion 148c is formed directly below the protrusion 156a of the conductive connector 156 to reduce stress. Therefore, cracking is prevented and the reliability of the package structure 100a is improved.

[0114] Figure 1I' A cross-sectional view of a package structure 100b according to some embodiments of the present disclosure is shown. Except for an insulating layer 109 formed between the substrate 102 and the first sheath 140, the package structure 100b is similar to or equivalent to... Figure 1I The first packaging structure 100a is described in the document. The process and materials used to form the packaging structure 100b are similar to or equivalent to the process and materials used to form the packaging structure 100b, and will not be described in detail here.

[0115] like Figure 1I' As shown, the insulating layer 109 provides an insulating effect. It should be understood that no conductive material or conductive layer is formed directly beneath or in direct contact with the second via portion 148c of the conductive structure 148. The bottom surface of the second via portion 148c is in direct contact with the insulating layer 109. In some embodiments, the insulating layer 109 is made of silicon nitride or silicon oxide.

[0116] Figures 4A to 4B Cross-sectional views are shown of various stages in forming a first portion 1481 and a second portion 1482 of a conductive structure 148 of an encapsulation structure 100c according to some embodiments of the present disclosure. Except that the top view of the second via portion 148c has an annular shape, the encapsulation structure 100c is similar to or equivalent to... Figure 1I The first packaging structure 100a in the middle.

[0117] like Figure 4A As shown, a first opening 141 and a second opening 145 are formed in the first protective layer 140. The second opening 145 has a first portion 145a and a second portion 145b, and the first portion 145a is connected to the second portion 145b to form an annular shape when viewed from above.

[0118] After that, as Figure 4B As shown, according to some embodiments of the present disclosure, conductive material is formed in the first opening 141 and the second opening 145 to form a conductive structure 148.

[0119] The conductive structure 148 includes a first portion 1481 and a second portion 1482. The first portion 1481 includes a first via portion 148a in the first opening 141 and a first metal portion 148b on the first via portion 148a. The second portion 1482 includes a second via portion 148c in the second opening 145 and a second metal portion 148d on the second via portion 148c. Figure 1G The dashed lines shown are for the purpose of providing a more convenient understanding of the structure. However, there is no actual boundary between the first guide hole portion 148a and the first metal portion 148b, nor is there an actual boundary between the second guide hole portion 148c and the second metal portion 148d.

[0120] Figure 4C The first guide hole portion 148a and the second guide hole portion 148c according to some embodiments of the present disclosure are shown along... Figure 4B A top view of line C-C'. (See attached image.) Figure 4C As shown, the second guide hole portion 148c has an annular shape when viewed from above.

[0121] Figure 5A A top view of a conductive structure 148 according to some embodiments of the present disclosure is shown. Figure 1G The packaging structure 100a according to some embodiments of the present disclosure is shown along... Figure 5A A cross-sectional view of the E-E' line.

[0122] like Figure 5A As shown, in top view, the through-hole structure 108 (dashed line) has a circular shape, the first guide hole portion 148a (dashed line) has a circular shape, and the second guide hole portion 148c (dashed line) has a circular shape. The distance between the first guide hole portion 148a and the second guide hole portion 148c is a first distance S1. The bottom surface of the first guide hole portion 148a directly contacts the through-hole structure 108, while the bottom surface of the second guide hole portion 148c directly contacts the substrate 102.

[0123] Figure 5B A top view showing the positional relationship between conductive structure 148 and conductive connector 156 according to some embodiments of the present disclosure. Figure 1I The packaging structure 100a according to some embodiments of the present disclosure is shown along... Figure 5B A cross-sectional view of the F-F' line.

[0124] like Figure 5BAs shown, a conductive connector 156 is formed above a conductive structure 148. The conductive structure 148 has an octagonal shape, while the conductive connector 156 has an elliptical shape. A second guide hole portion 148c is located approximately at the center of the conductive connector 156. A first guide hole portion 148a is located at the edge of the conductive connector 156. The size of the second guide hole portion 148c is larger than the size of the first guide hole portion 148a. Forming the second guide hole portion 148c avoids stress accumulation in some areas and thus reduces stress.

[0125] In some embodiments, there are two first guide hole portions 148a below the conductive structure 148. A conductive connector 156 completely covers one of the first guide hole portions 148a and partially covers the other. In some embodiments, the conductive structure 148 covers both first guide hole portions 148a and one second guide hole portion 148c. The number of first guide hole portions 148a may be greater than two, and the number can be adjusted according to the actual application.

[0126] The ratio of the area of ​​the second via portion 148c to the area of ​​the conductive connector 156 is in the range of approximately 30% to approximately 70%. When the ratio falls within the above range, stress can be reduced to effectively prevent the formation of cracks and voids. In addition, since the larger conductive connector 156 will transfer more stress from the substrate 102, the ratio of the area of ​​the second via portion 148c to the area of ​​the conductive connector 156 should be designed to fall within the above range to reduce stress without affecting the wiring.

[0127] Figures 6A to 6E Cross-sectional views are shown of various stages in forming a package structure 100d according to some embodiments of the present disclosure.

[0128] like Figure 6A As shown, a protective layer 604 is formed over a substrate 602. In some embodiments, the substrate 602 serves as a temporary substrate. During subsequent process steps (e.g., processes described in more detail later), the temporary substrate provides mechanical and structural support. The substrate 602 is made of a semiconductor material, a ceramic material, a polymer material, a metallic material, other suitable materials, or a combination of the foregoing. In some embodiments, the substrate 602 is a glass substrate. In some other embodiments, the substrate 602 is a semiconductor substrate, such as a silicon wafer.

[0129] The sheath 604 is deposited or laminated onto the substrate 602 via an adhesive layer (not shown). The sheath 604 provides structural support for bonding integrated circuit dies and helps reduce die offset issues, which will be described in further detail below. In some embodiments, the sheath 604 is a polymer layer or a layer containing a polymer. The sheath 604 is a polystyrene... The layer may be azole layer, polyimide layer, solder resist (SR) layer, Ajinomoto buildup film (ABF) layer, die bonding layer, other suitable layer, or combination of the foregoing layers.

[0130] An interconnect structure 610 is formed above the first sheath 604. The interconnect structure 610 can serve as a redistribution structure for wiring. The interconnect structure 610 includes a plurality of conductive layers 614 formed in a plurality of sheaths 612. A conductive structure 648 is formed in the plurality of sheaths 612. The conductive structure 648 includes a first portion 6481 and a second portion 6482. The first portion 6481 includes a first via portion 648a and a first metal portion 648b. The second portion 6482 includes a second via portion 648c and a second metal portion 648d.

[0131] Subsequently, a through-hole structure 608 is physically connected to and electrically connected to the first via portion 648a of the conductive structure 648. In some embodiments, the through-hole structure 608 is referred to as a through interposer via (TIVS).

[0132] In some embodiments, the through-hole structure 608 is made of copper, aluminum, nickel, platinum, other suitable conductive materials, or combinations thereof. In some embodiments, the through-hole structure 608 is formed by electroplating, physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy (MBE), atomic layer deposition (ALD), or other suitable processes.

[0133] like Figure 6B As shown, according to some embodiments, a semiconductor die 620 is disposed on an interconnect structure 610 via an adhesive film 619. In some embodiments, the front side (active side) of the semiconductor die 620 is away from the interconnect structure 610. The rear side (non-active side) of the semiconductor die 620 faces the interconnect structure 610. An encapsulation layer 650 is then deposited over the interconnect structure 610. Therefore, the via structure 608 and the semiconductor die 620 are encapsulated by the encapsulation layer 650.

[0134] The semiconductor die 620 includes a substrate 621, a sheath 622, and a plurality of conductive pads 624. Various device elements may be formed in or on the substrate 621. The device elements include active devices and / or passive devices. In some other embodiments, the device elements include image sensor devices, logic devices, memory devices, other suitable types of devices, or combinations thereof.

[0135] The adhesive film 619 is used to bond or attach the semiconductor die 620 to the interconnect structure 610. The adhesive film 619 includes a die attach film (DAF), other suitable layers, or a combination of die attach films or other suitable layers. In some embodiments, the encapsulation layer 650 includes a polymer material. In some embodiments, the encapsulation layer 650 includes a molding compound.

[0136] After that, as Figure 6C As shown, according to some embodiments, a sheath 660 is formed above the encapsulation layer 650. A conductive layer 664 is formed and embedded in the sheath 660. The conductive layer 664 is electrically connected to the via structure 608 and the semiconductor die 620. The sheath 660 is made of one or more dielectric materials, and the sheath 660 provides stress relief during subsequent bonding processes to alleviate bonding stress.

[0137] Next, as Figure 6D As shown, according to some embodiments, Figure 6C The structure shown is flipped and attached to a carrier substrate 667. Then, substrate 102 is removed to expose the protective layer 604.

[0138] After that, as Figure 6E As shown, according to some embodiments, a bump under-metal layer 675 is formed in the sheath 604, and a conductive connector 676 is formed above the bump under-metal layer 675. In addition, a semiconductor die 680 is formed above the sheath 604 via a conductive connector 682. In some embodiments, the height of the conductive connector 676 is greater than the height of the conductive connector 682.

[0139] The conductive connector 676 includes a protrusion 676a and a top 676b formed above the protrusion 676a. The protrusion 676a extends toward the through-hole structure 608 and is embedded in the sheath 604. Figure 6E The dashed lines shown are for the purpose of providing a more convenient understanding of the structure; however, there is no actual boundary or division between the protrusion 676a and the top 676b.

[0140] The conductive connector 676 is electrically connected to the second via portion 648c via the conductive layer 614 and the second metal portion 648d. The second via portion 648c is electrically connected to the through-hole structure 608 via the second metal portion 648d, the first metal portion 648b, and the first via portion 648a. The second via portion 648c has one end connected to the second metal portion 648d, and the other end directly contacts the encapsulation layer 650. No conductive material or conductive layer is formed directly beneath or in direct contact with the second via portion 648c.

[0141] It should be understood that the second guide hole portion 648c is formed to prevent stress accumulation in certain areas and thus reduce stress. The second guide hole portion 648c provides reliable support. Therefore, the formation of cracks and voids is avoided, and the reliability of the packaging device 100d is improved.

[0142] Some embodiments of this disclosure provide a packaging structure and a method for forming the same. The packaging structure includes a first through-hole structure formed in a substrate. A semiconductor die is formed below the first through-hole structure, and a conductive structure is formed above the substrate. The conductive structure includes a first portion and a second portion. The first portion includes a first via portion and a first metal portion. The second portion includes a second via portion and a second metal portion. A conductive connector is formed on the conductive structure. The first via portion is formed directly on the first through-hole structure, and the bottom surface of the second via portion directly contacts the substrate. The second via portion serves as a support to reduce stress. This reduces the formation of cracks and voids. Therefore, the quality, yield, and reliability of the packaging structure are improved.

[0143] In some embodiments, a packaging structure is provided. The packaging structure includes a first through-hole structure and a semiconductor die. The first through-hole structure is formed in a substrate. The semiconductor die is formed below the first through-hole structure. The packaging structure also includes a conductive structure. The conductive structure is formed in a sheath above the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion being formed directly above the first through-hole structure, and no conductive material is formed directly below and in direct contact with the second via portion.

[0144] In some embodiments, the conductive structure further includes a first wire portion above the first via portion and a second wire portion above the second via portion, with the first wire portion directly contacting the second wire portion. In some embodiments, a bottom surface of the first via portion is flush with a bottom surface of the second via portion. In some embodiments, the entire bottom surface of the second via portion directly contacts the substrate. In some embodiments, on the same horizontal plane reference, the second via portion is separated from the first via portion by a sheath. In some embodiments, the package structure further includes an under-bump metal layer and a connector. The under-bump metal layer is formed directly above the second via portion. The connector is formed above the under-bump metal layer. The connector includes a protrusion in the sheath, and the second via portion is formed directly below the protrusion of the connector. In some embodiments, the connector overlaps with the through-hole structure.

[0145] In some embodiments, the package structure further includes an interconnect structure. The interconnect structure is formed below the first via structure. The interconnect structure is located between the first via structure and the semiconductor die. In some embodiments, the first via portion has a circular shape when viewed from above, the second via portion has a circular shape when viewed from above, the first via portion has a first diameter, the second via portion has a second diameter, and the second diameter is larger than the first diameter. In some embodiments, the package structure further includes a second via structure. The second via structure is formed in the substrate. The second via portion is located between the first via structure and the second via structure. In some embodiments, the second via portion has an annular shape when viewed from above.

[0146] In some embodiments, a packaging structure is provided. The packaging structure includes a through-hole structure and a first semiconductor die. The through-hole structure is formed in a packaging layer. The first semiconductor die is formed adjacent to the through-hole structure. The packaging structure includes a first via portion and a second via portion. The first via portion is formed directly on the through-hole structure. The second via portion is adjacent to the first via portion. The second via portion has a first end and a second end in a vertical direction, and the first end directly contacts the packaging layer. The packaging structure also includes a first wire portion and a second wire portion. The first wire portion is formed on the first via portion. The second wire portion is formed on the second via portion. The first wire portion is connected to the second wire portion, and the second end of the second via portion directly contacts the second wire portion. The packaging structure further includes a connector. The connector is formed on the second via portion. The connector includes a protrusion, and the second via portion is formed directly below the protrusion of the connector.

[0147] In some embodiments, the package structure further includes an interconnect structure. The interconnect structure is formed below the first semiconductor die. A first via portion is electrically connected to the interconnect structure via a through-hole structure. In some embodiments, a distance between the first via portion and a second via portion is less than a diameter of the second via portion. In some embodiments, the package structure further includes a second semiconductor die. The second semiconductor die is formed above the first semiconductor die. The second semiconductor die is adjacent to the connector. In some embodiments, the second via portion has a circular shape when viewed from above, and a diameter of the second via portion gradually decreases from a second end toward a first end.

[0148] In some embodiments, a method for forming a package structure is provided. The method includes forming a via structure in a substrate and forming a semiconductor die below the substrate. The method further includes forming a first sheath layer above the substrate, and forming a first opening and a second opening in the first sheath layer. The first opening exposes the via structure, and the second opening exposes the substrate. The first opening has a circular shape when viewed from above, and the second opening also has a circular shape when viewed from above. The method also includes forming a conductive material in the first and second openings, and the conductive material is also formed above the first sheath layer to form a conductive structure. The conductive structure includes a first via portion in the first opening and a second via portion in the second opening. The first via portion is formed directly above the via structure, and the bottom surface of the second via portion directly contacts the substrate.

[0149] In some embodiments, the method further includes forming a second sheath over the first sheath, forming a third opening in the second sheath to expose a portion of the conductive structure, and forming a connector in the third opening. A second via portion is formed directly below the connector. In some embodiments, the method further includes forming an underfill layer covering the semiconductor die and forming an encapsulation layer covering the underfill layer. In some embodiments, the second via portion has an annular shape when viewed from above.

[0150] The foregoing summary of features of several embodiments enables those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent configurations do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this disclosure without departing from its spirit and scope.

Claims

1. A packaging structure, comprising: A first through-hole structure is formed in a substrate; A semiconductor die is formed below the first via structure; A conductive structure is formed in a protective layer above the substrate; The conductive structure includes a first through-hole portion and a second through-hole portion. The first through-hole portion is formed directly above the first through-hole structure, and no conductive material is formed directly below the second through-hole portion and in direct contact with the second through-hole portion. as well as A connector is formed on the second guide hole portion and electrically connected to the conductive structure; The connector overlaps with the first through-hole structure.

2. The packaging structure as claimed in claim 1, wherein the conductive structure further includes a first line portion above the first via portion and a second line portion above the second via portion, and the first line portion directly contacts the second line portion.

3. The packaging structure as claimed in claim 1, wherein a bottom surface of the first guide hole portion is flush with a bottom surface of the second guide hole portion.

4. The packaging structure as claimed in claim 1, wherein the entire bottom surface of the second via portion is in direct contact with the substrate.

5. The packaging structure as claimed in claim 1, wherein, on the same horizontal plane reference, the second guide hole portion is separated from the first guide hole portion by the protective layer.

6. The packaging structure as described in claim 1, further comprising: A protrusion under the metal layer is directly above the second guide hole portion; The connector is formed above the metal layer under the bump, the connector includes a protrusion in the sheath, and the second guide hole portion is directly below the protrusion of the connector.

7. The packaging structure of claim 6, wherein the conductive structure further includes a first line portion above the first via portion, the first line portion overlapping the first through-hole structure.

8. The packaging structure as described in claim 1, further comprising: An interconnect structure is formed below the first via structure, wherein the interconnect structure is located between the first via structure and the semiconductor die.

9. The packaging structure as claimed in claim 1, wherein the first guide hole portion has a circular shape when viewed from above, the second guide hole portion has a circular shape when viewed from above, the first guide hole portion has a first diameter, the second guide hole portion has a second diameter, and the second diameter is larger than the first diameter.

10. The packaging structure as described in claim 1, further comprising: A second through-hole structure is formed in the substrate, wherein the second through-hole portion is located between the first through-hole structure and the second through-hole structure.

11. The packaging structure of claim 1, wherein the second guide hole portion has an annular shape when viewed from above.

12. A packaging structure, comprising: A through-hole structure is formed within an encapsulation layer; A first semiconductor die is formed adjacent to the via structure; The first guide hole portion is directly on the through hole structure; A second guide hole portion is adjacent to the first guide hole portion, wherein the second guide hole portion has a first end and a second end in a vertical direction, and the first end directly contacts the encapsulation layer; A first line portion is formed on the first guide hole portion; A second line portion is formed on the second guide hole portion, wherein the first line portion is connected to the second line portion, the second end of the second guide hole portion directly contacts the second line portion, and the second line portion has a recessed top surface; A metal layer under a bump is formed directly on the recessed top surface of the second line portion and directly contacts the recessed top surface of the second line portion. as well as A connector is formed on the second guide hole portion, wherein the connector includes a protrusion and the second guide hole portion is directly below the protrusion of the connector.

13. The packaging structure of claim 12, further comprising: An interconnect structure is formed beneath the first semiconductor die, wherein the first via portion is electrically connected to the interconnect structure through the via structure.

14. The packaging structure of claim 12, wherein a distance between the first guide hole portion and the second guide hole portion is less than a diameter of the second guide hole portion.

15. The packaging structure of claim 12, further comprising: A second semiconductor die is formed above the first semiconductor die, wherein the second semiconductor die is adjacent to the connector.

16. The packaging structure of claim 12, wherein the second guide hole portion has a circular shape when viewed from above, and a diameter of the second guide hole portion gradually decreases from the second end toward the first end.

17. A method for forming an encapsulation structure, comprising: A through-hole structure is formed in a substrate; A semiconductor die is formed beneath the substrate; A first protective layer is formed on the substrate; A first opening and a second opening are formed in the first protective layer, wherein the first opening exposes the through-hole structure and the second opening exposes the substrate. The first opening has a circular shape when viewed from above, and the second opening has a circular shape when viewed from above. A conductive material is formed in the first opening and the second opening, and the conductive material is also formed above the first protective layer to form a conductive structure, wherein the conductive structure includes: A first guide hole portion in the first opening; and A second guide hole portion in the second opening, wherein the first guide hole portion is directly above the through-hole structure, and a bottom surface of the second guide hole portion directly contacts the substrate; and A connector electrically connected to the conductive structure is formed on the second guide hole portion; The connector overlaps with the through-hole structure.

18. The method of forming an encapsulation structure as described in claim 17, further comprising: A second protective layer is formed on top of the first protective layer; A third opening is formed in the second sheath to expose a portion of the conductive structure; as well as The connector is formed in the third opening, wherein the second guide hole portion is directly below the connector.

19. The method of forming an encapsulation structure as described in claim 17, further comprising: A bottom fill layer is formed covering the semiconductor die; as well as An encapsulation layer is formed that covers the bottom filling layer.

20. The method of forming an encapsulation structure as claimed in claim 17, wherein the second via portion has an annular shape when viewed from above.

21. A packaging structure, comprising: A first semiconductor die is formed in a packaging layer; A first via portion is formed above the encapsulation layer; A second via portion is adjacent to the first via portion, wherein the second via portion directly contacts the encapsulation layer; A line portion is formed above the first guide hole portion and the second guide hole portion, wherein the first guide hole portion is electrically connected to the second guide hole portion through the line portion, and the line portion has a recessed top surface; as well as A metal layer under a bump is formed directly on the recessed top surface of the line portion and directly contacts the recessed top surface of the line portion.

22. The packaging structure of claim 21, further comprising: A through-hole structure is formed in the encapsulation layer, wherein the through-hole structure directly contacts the first guide hole portion.

23. The packaging structure of claim 21, further comprising: A second semiconductor die is formed on top of the first semiconductor die.

24. The packaging structure of claim 23, further comprising: A first connector is formed between the first semiconductor die and the second semiconductor die; as well as A second connector is formed above the second guide hole portion, wherein a top surface of the second connector is higher than a top surface of the first connector.

25. A packaging structure, comprising: A first semiconductor die is formed in a packaging layer; A first via portion is formed above the encapsulation layer; A second via portion is adjacent to the first via portion, wherein the second via portion directly contacts the encapsulation layer; A line portion is formed above the first guide hole portion and the second guide hole portion, wherein the first guide hole portion is electrically connected to the second guide hole portion through the line portion, and the line portion has a recessed top surface; as well as A bump under-metal layer is formed directly on the recessed top surface of the line portion and directly contacts the recessed top surface of the line portion, wherein the bump under-metal layer is directly above the second guide hole portion.

26. The packaging structure of claim 25, further comprising: A connector is formed above the metal layer under the bump, wherein the connector includes a protrusion and the second guide hole portion is directly below the protrusion of the connector.

27. The packaging structure of claim 25, further comprising: A protective layer is formed beneath the encapsulation layer; as well as A conductive layer is formed in the protective layer.

28. The packaging structure of claim 27, further comprising: A via structure is formed adjacent to the first semiconductor die, wherein the via structure is electrically connected to the conductive layer.

29. The packaging structure of claim 25, wherein the under-bump metal layer is formed in a protective layer.

30. The packaging structure of claim 29, further comprising: A second semiconductor die is formed above the protective layer, wherein a top surface of the second semiconductor die is higher than a top surface of the under-bump metal layer.

31. The packaging structure of claim 25, wherein a width of the line portion is greater than a width of the first via portion.

32. The packaging structure of claim 25, wherein the first semiconductor die includes a substrate and a conductive pad, and the conductive pad is further away from the first via portion than the substrate.

33. The packaging structure of claim 25, wherein the second guide hole portion has a circular shape when viewed from above.

34. The packaging structure of claim 25, wherein a bottom surface of the first guide hole portion is flush with a bottom surface of the second guide hole portion.

35. The packaging structure of claim 25, wherein, on the same horizontal plane reference, the second guide hole portion is separated from the first guide hole portion by a protective layer.

36. A packaging structure, comprising: A first through-hole structure is formed in a substrate; A semiconductor die is formed below the first via structure; A conductive structure is formed in a protective layer above a substrate, wherein the conductive structure includes a first via portion and a second via portion, the second via portion having a bottom surface that directly contacts the substrate, and a first diameter of the bottom surface of the first via portion being smaller than a second diameter of the bottom surface of the second via portion; and A connector is formed on the second guide hole portion and electrically connected to the conductive structure; The connector overlaps with the first through-hole structure.

37. The packaging structure of claim 36, wherein the conductive structure further includes a first line portion above the first via portion and a second line portion above the second via portion, and the first line portion directly contacts the second line portion.

38. The packaging structure of claim 37, wherein a bottom surface of the first line portion has a third diameter, a bottom surface of the second line portion has a fourth diameter, and the third diameter is smaller than the fourth diameter.

39. The packaging structure of claim 36, further comprising: A protrusion under the metal layer is directly above the second guide hole portion; The connector is formed above the metal layer under the bump, the connector includes a protrusion in the sheath, and the second guide hole portion is directly below the protrusion of the connector.

40. The packaging structure of claim 36, further comprising: An interconnect structure is formed below the first via structure, wherein the interconnect structure is located between the first via structure and the semiconductor die.

41. A packaging structure, comprising: A first through-hole structure is formed in a substrate; A second through-hole structure is formed adjacent to the first through-hole structure; A semiconductor die is formed beneath the first via structure and the second via structure; A conductive structure is formed above the first through-hole structure; The conductive structure includes a first through-hole portion and a second through-hole portion, wherein the second through-hole portion is located between the first through-hole structure and the second through-hole structure, and the second through-hole portion is located above the first through-hole structure and the second through-hole structure. as well as A connector is formed on the second guide hole portion and electrically connected to the conductive structure; The connector overlaps with the first through-hole structure.

42. The packaging structure of claim 41, wherein the second via portion is electrically connected to the first via portion via a first wire portion and a second wire portion.

43. The packaging structure of claim 42, wherein the first line portion is directly above the first guide hole portion, and the second line portion is directly above the second guide hole portion.

44. The packaging structure of claim 41, further comprising: A protrusion under the metal layer is directly above the second guide hole portion; The connector is formed above the metal layer under the bump, the connector includes a protrusion in a protective layer, and the second guide hole portion is directly below the protrusion of the connector.

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