Low power, high bandwidth, low latency data bus

Abstract

The data bus includes a device controller coupled to a first interface for digital communication using a first communication protocol, the device controller includes a master bus controller that uses a second communication protocol to control a multi-branch bus, and a slave device that is coupled to the multi-branch bus and is configured to use the second communication protocol to utilize the device controller to transmit and receive digital communication. Use a device attached to one end of the transmission line and terminate each transmission line end by another device attached to the other end. The second communication protocol supports multiple data rates using a fixed frame format. Secure synchronization can be established by systematically eliminating all error positions rather than searching for valid candidates. Noise in the audio frequency band can be reduced by scrambling data using a pseudo-random generator.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 62 / 678,993, filed May 31, 2018, and U.S. Provisional Patent Application No. 62 / 721,412, filed August 22, 2018; each of which is incorporated herein by reference in its entirety.

[0003] This application is a continuation-in-part of U.S. Patent Application No. 16 / 125,617 filed on September 7, 2018, which is incorporated herein by reference in its entirety. Technical Field

[0004] The present disclosure relates generally to data communications and, more particularly, for example, to systems and methods for transferring digital data between devices. Background Art

[0005] Various interfaces for transmitting and receiving digital data between electronic devices are known in the art. However, existing interfaces do not meet all the needs of many modern systems. It is generally desirable to achieve high-bandwidth communication for multiple connected devices while maintaining reliability and good signal quality, and meeting the needs of low-cost, low-power devices. For example, adaptive noise cancellation (ANC) headsets may require complex and expensive equipment, and high-bandwidth communication between an ANC headset and a host device may be desirable for certain applications, such as processing noise cancellation signals on the host device.

[0006] In some methods, high bandwidth communications are achieved through a digital communication link that is terminated at the receiver. These methods can provide satisfactory signal integrity for certain configurations, but if there is a requirement for low power consumption at the same time, the static power consumption in the receiver terminal may be undesirable. In addition, many of these methods are not optimized for low latency data transmission because data communication may take a complete sampling period to be transmitted on the digital communication link. Some systems typically have additional requirements, such as supporting connections to multiple devices and supporting physical links that meet certain length requirements (e.g., 1-2 meters). Additional requirements may include communication between connected devices, support and flexibility to comply with different device types, and support for various data transmission implementations, including bulk data transmission in systems where data is transmitted in a serialized format.

[0007] In view of the foregoing, there is a continuing need in the art for improved digital data communication systems and methods. Summary of the invention

[0008] The present disclosure provides a system and method for solving the demand for improved digital data communication between physically connected devices in the art. In various embodiments, a data bus system and method include a device controller coupled to a first interface for digital audio data communication according to a first communication protocol. The device controller includes a master bus controller for controlling a multi-drop bus according to a second communication protocol. The first slave device is coupled to the multi-drop bus and is configured to transmit and receive digital audio data communication using the device controller according to the second communication protocol. Each transmission line is terminated using a device attached to one end of the transmission line and by another device attached at the other end, and reflections caused by impedance mismatch caused by including an intermediate signaling node are controlled to allow multi-drop device support and high-speed signaling. The second communication protocol can support multiple audio data rates using a fixed frame format.

[0009] In some embodiments, a first slave device and a second slave device connected to the bus are timed so that the transmitted message is sent as a sequence of forward-traveling waves or backward-traveling waves, thereby enabling multi-drop high-speed bidirectional communication using terminated transmission lines. In one embodiment, differential signaling is used for communication, and one line is terminated at a logic high and one line is terminated at a logic low to reduce common-mode interference. In one embodiment, differential signaling is used to reduce EMI, and when data is not being transmitted, the termination of each transmission line is handled by setting the output driver to one of a high level and a low level according to the terminal level, and the bus is idle, thereby enabling lower power consumption through the transmission endpoints.

[0010] In some embodiments, intermediate nodes on the transmission line are connected to the transmission line with short interruptions to the traveling wave, and the stubs and / or interruptions of the transmission line are required to be significantly shorter than the shortest wavelength used for signaling (e.g., less than 1 / 50 of the shortest wavelength). Power consumption can be reduced by using a signaling rate greater than the minimum required signaling rate and leaving the bus idle for a portion of each clock cycle or each frame, thereby reducing power loss in the terminal, as long as the output terminal level is equal to the final output state level (idle level). The power required for signaling can be obtained by a capacitive or inductive drop regulator, thereby minimizing power loss in the regulator. Power consumption can be further limited by reducing the transmission voltage on the bus, and differential signaling can be used to achieve low voltage signaling, while the system is robust against external noise and EMI.

[0011] In some embodiments, the delay between components is measured by charging the bus to a known value, disabling the driver at the beginning and end of the transmission line to ensure that the bus is floating and unterminated during the measurement, thereby waiting for the device to change the level on the bus and measuring the transition delay. The driver at each end of the transmission line can be disabled by allowing multiple drivers to change the current bus state during the enumeration of the components attached to the bus. The current bus state can be set by the controller, and one or more devices can change the transmission line to the opposite value within a given time window that allows the device to count. The device controller may also include a phase-locked loop (PLL) or a delay-locked loop (DLL) that provides a first clock signal for synchronizing communication according to a first communication protocol, a second clock signal for synchronizing communication according to a second communication protocol, and a third clock signal for use in audio data processing.

[0012] In various embodiments, the second communication protocol supports different communication bandwidths using a fixed frame structure. In some embodiments, the data port or data after each synchronization signal is modulated by a high frequency carrier or a pseudo-random generator, thereby reducing current modulation in the audio frequency band for lower interference in the audio system. The device controller, the first slave device and the second slave device may include an audio headset or other audio listening device. In some embodiments, the terminal at the end of the transmission line is temporarily disabled during the activation of the transmitter to reduce power consumption.

[0013] In various embodiments, a method includes using a first slave device coupled to a multi-drop bus, receiving and transmitting digital audio data across a first interface according to a first communication protocol, controlling the multi-drop bus with a device controller according to a second communication protocol, receiving and transmitting digital audio data with the device controller according to the second communication protocol, and setting a transmitter in each end of a transmission line to a known state to enable termination of any signal. In some embodiments, the second communication protocol can use a fixed frame format to support multiple audio data rates.

[0014] The method may further include using a phase locked loop or a delay locked loop to generate a first clock signal for synchronous communication according to a first communication protocol, a second clock signal for synchronous communication according to a second communication protocol, and a third clock signal for use in audio data processing. In some embodiments, the second communication protocol supports different communication bandwidths using a fixed frame structure. Jitter can be added to a PLL or DLL to reduce the EMI of the transmission through spectrum expansion. The data transmitted on the bus can be scrambled during transmission and descrambled during reception to reduce the spectral content in the audio frequency band.

[0015] The scope of the present invention is defined by the claims, which are incorporated into this section by reference. By considering the following detailed description of one or more embodiments, those skilled in the art will be provided with a more complete understanding of embodiments of the present invention, as well as the realization of additional advantages thereof. Reference will be made to the attached sheets of the accompanying drawings, which will first be briefly described. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1A is an exemplary bus interface system in accordance with one or more embodiments.

[0017] Figure 1B and 1C An exemplary headset is illustrated in accordance with one or more embodiments.

[0018] Figure 2A is an example of a bus interface system in accordance with one or more embodiments.

[0019] Figure 2B An exemplary headset is illustrated in accordance with one or more embodiments.

[0020] Figure 3 Illustrated are exemplary timing sequences according to one or more embodiments.

[0021] Figure 4 An exemplary time-gated phase-locked loop (PLL) is illustrated in accordance with one or more embodiments.

[0022] Figure 5A and 5B An exemplary clocking solution is illustrated in accordance with one or more embodiments.

[0023] Fig. 6A and 6B An exemplary clocking solution is illustrated in accordance with one or more embodiments.

[0024] Figure 7 An exemplary clocking solution is illustrated in accordance with one or more embodiments.

[0025] Fig. 8A and 8B An exemplary clocking solution is illustrated in accordance with one or more embodiments.

[0026] Fig.9A -F illustrates an exemplary frame structure according to one or more embodiments.

[0027] Fig. 10A A method for latency measurement of an attached device in accordance with one or more embodiments is illustrated.

[0028] Fig. 10BA method for counting attached devices according to one or more embodiments is illustrated.

[0029] Fig.11A An exemplary duplex communication arrangement is illustrated in accordance with one or more embodiments.

[0030] Fig. 11B Examples of differential signaling, synchronization, and digital data communications are illustrated in accordance with one or more embodiments.

[0031] Fig. 11C An example of a differential signaling system in accordance with one or more embodiments is illustrated.

[0032] Fig.11D Another example of a differential signaling system in accordance with one or more embodiments is illustrated.

[0033] Fig.12 An exemplary PLL locking sequence is illustrated in accordance with one or more embodiments.

[0034] Fig.13 is an exemplary PLL synchronization enable circuit according to one or more embodiments.

[0035] Fig.14 Exemplary synchronization signaling in accordance with one or more embodiments is illustrated.

[0036] Fig.15 Exemplary operations of a digital data communication system according to one or more embodiments are illustrated.

[0037] Fig.16A , 16B 16C illustrate example frame structures that may be used in accordance with one or more embodiments.

[0038] Fig.17 An example frame is illustrated in accordance with one or more embodiments.

[0039] Fig.18A , 18B 18C illustrate example frame configurations for read and write operations (including bulk transfers) according to one or more embodiments.

[0040] Fig.19 An example frame synchronization algorithm is illustrated in accordance with one or more embodiments.

[0041] The included drawings are for illustrative purposes and are intended only to provide examples of possible systems and methods for providing the disclosed methods and systems for context-aware audio processing. These drawings are not in any way limiting any changes in form and detail that may be made to those disclosed by those skilled in the art without departing from the spirit and scope of the present disclosure. DETAILED DESCRIPTION

[0042] The present disclosure solves the need for improved digital data communication between electronic devices in the art. In various embodiments, a system and method for providing low power, high bandwidth, multi-branch and / or low latency communication between a master device and one or more slave devices connected by a physical data link is disclosed. The present disclosure provides many advantages over conventional systems and methods, including lower power consumption, a combination of high bandwidth and long link length, low and well-controlled latency, support for multi-branch topologies other than point-to-point connections, and simple synchronization between devices.

[0043] In various embodiments, low power is achieved even for terminated devices by a process that includes sending bits quickly and then leaving the bus idle for the remainder of the clock cycle or the remainder of the duration of the frame. Differential data buses terminated with opposite polarity promote low power operation and reduced electromagnetic interference (EMI). The present disclosure also promotes low power consumption in configurations with unterminated ends, where a high frequency clock or timing element is used to ensure that data can be received in one or more time units, thereby enabling a choice between a high signal-to-noise ratio (SNR) and a high data rate without changing the physical system, for example, multiple time slots can be used to define each symbol to enable a tradeoff between bandwidth and signal integrity.

[0044] The present disclosure also provides a multi-branch differential long length bus with multiple devices, which use end transmitters as actual terminals and use opposite terminal polarities to ensure that public signaling for low EMI is reduced. The algorithm for synchronization of connected devices includes finding time slots that do not change according to the expected pattern, and systematically eliminating all invalid positions for safe synchronization. In this way, even with arbitrary random data, certain implementations of the system can guarantee safe synchronization. When a single synchronization candidate is left, the search will be completed first, and therefore, any random data will not cause false synchronization. An algorithm for bulk data transmission is also provided to facilitate transmission between memory modules independent of bus business. In some embodiments, lower EMI is achieved by adding jitter to the system clock. Interference in the audio band can be reduced by scrambling the data symbols before transmission and descrambling the values ​​(to obtain the original values) after reception. These and other features and advantages of the present disclosure will be understood with reference to the following disclosure.

[0045] Various embodiments are disclosed herein. In one embodiment, a system includes: a master device coupled to a multi-drop bus for digital communication using a communication protocol including a plurality of time slots; and a first slave device coupled to the multi-drop bus and configured to transmit and receive digital communication using the master device according to the communication protocol. At least one of the time slots is used to define a communication configuration for the first slave device to dynamically optimize bandwidth and / or signal integrity. The multi-drop bus is a differential data bus terminated at different voltage levels on two lines, thereby promoting low power operation and low electromagnetic interference. In one aspect, the multi-drop bus is a multi-drop differential long length bus configured to receive multiple slave devices using an end transmitter. Power consumption is reduced by operating at a signaling rate greater than the required signaling rate and leaving the multi-drop bus idle for a portion of each cycle.

[0046] In one embodiment, the system is also configured to synchronize two or more connected devices, including identifying time slots that do not change according to a desired fixed pattern, and eliminating invalid positions for safe synchronization. The system is also configured to facilitate bulk data transmission independent of the multi-drop bus digital communication service. On the other hand, the first slave device and the second slave device connected to the bus are timed so that the transmitted message is sent as a sequence of forward traveling waves or backward traveling waves, thereby enabling multi-drop high-speed bidirectional communication using terminated transmission lines. The intermediate nodes on the multi-drop bus are connected to the multi-drop bus with short interruptions to the traveling waves, and the physical length of the interruption to the transmission line generated by the intermediate node is shorter than the shortest wavelength used for signaling.

[0047] In some embodiments, the delay between devices is measured by charging the bus to a known value, disabling the driver at the beginning and end of the bus so that the bus floats during the measurement and is not terminated, waiting for the device to change the level on the bus, and measuring the transition delay. Use PLL or DLL to obtain the lock between the master device and the first slave device. Obtain system timing from the fractional PLL set in the master device and / or the first slave device, and jitter the PLL by adding the output from the pseudo-random generator to the fractional adder, thereby reducing EMI. In one embodiment, the pseudo-random generator is configured to scramble the output of one or more data ports, thereby enabling lower EMI by whitening the output spectrum. The PLL and / or DLL may include a time gate enabled during the initial lock of the PLL, and only synchronization information is allowed to pass later to avoid the PLL locking to random bus traffic.

[0048] In various embodiments, a method includes: providing a master device coupled to a multi-drop bus for digital communication using a communication protocol including a plurality of time slots; coupling a first slave device to the multi-drop bus, and configuring the slave device to transmit and receive digital communications with the master device according to the communication protocol; and using at least one of the time slots to define a communication configuration for the first slave device to dynamically optimize bandwidth and / or signal integrity. The method may also include operating the multi-drop data bus as a differential data bus terminated with opposite polarity, thereby facilitating low power operation and low electromagnetic interference, and / or synchronizing two or more connected devices, including identifying time slots that do not change according to a desired fixed pattern, and eliminating invalid positions for safe synchronization. In some embodiments of the method, a first slave device and a second slave device connected to the bus are timed so that the transmitted message is sent as a sequence of forward-traveling waves or backward-traveling waves, thereby enabling multi-drop high-speed bidirectional communication using terminated transmission lines.

[0049] refer to Figure 1A , an exemplary audio system 100 will be described according to one or more embodiments of the present disclosure. The audio system 100 includes a host device 110 and at least one connected device 130. The host device 110 can be any electronic device configured to send or receive audio data to or from the connected device 130, including, for example, a smart phone, a tablet computer, a laptop computer, a car voice interface, a voice conferencing system, an audio playback system, or other electronic device. The connected device 130 may include one or more electronic devices configured to send, receive and / or process audio data, and may include, for example, one or more microphones, speakers, or audio processing systems. Although the present embodiment is discussed with reference to audio communication, it should be understood that according to the present disclosure, the systems and methods described herein can be implemented using other electronic devices and data types.

[0050] In the illustrated embodiment, the host device 110 includes an application processor 112, an audio CODEC 114, and an interface component 116. The application processor 112 controls the communication of digital audio data between the host device 110 and the connected device 130. The audio CODEC 114 provides audio input and / or output processing according to the requirements of the host device 110. The interface component 116 facilitates the physical connection between the host device 110 and the connected device 130 via the cable 120 and a compatible connector. In various embodiments, the interface component 116 may include a port for accommodating a connector and a corresponding interface controller for implementing a communication protocol. In the embodiments described herein, a universal serial bus (USB) connector and interface are described; however, it should be understood that other cables, connectors, and protocols may be used according to the embodiments described herein.

[0051] In one or more embodiments, the application processor 112 uses a multi-conductor bus protocol including clock and data lines such as defined by the SoundWire specification or the USB specification to facilitate communication between the host device 110 and the connected device 130. The application processor 112 can communicate with the audio CODEC 114 in a master-slave relationship using an audio interface (such as SoundWire or another digital interface). The audio CODEC 114 facilitates communication between the application processor 112 and the interface component 116, thereby converting audio data between the two interface protocols. The audio data is transmitted between the interface component 116 and the device controller 140, which is configured to handle data transmission across the cable 120. The device controller 140 is also adapted to operate as a master device for communicating with one or more slave devices (such as audio components 142 and audio components 144) across the interface bus of the connected device 130, and is adapted to facilitate other device functions, such as processing user input through the user interface component 146. In one embodiment, the bus lines include a power bus (VBUS), a differential pair D+ and D- for data transmission, grounding, and a device ID. Those skilled in the art will appreciate that other bus line configurations may be used in accordance with the teachings of the present disclosure.Communications between the various devices and components of the audio system 100 may be facilitated in accordance with the digital data communication systems and methods disclosed herein.

[0052] refer to Figure 1B , Figure 1A An exemplary connected device 130 may be implemented as a USB headset 150 that includes a USB connector 152 for connecting to the interface component 116 of the host device 110, a device controller housed in the connector 152, a user interface 157 (such as a button), and a wired data 158 bus that connects the device controller with the audio components 160 and 170. In one embodiment, the headset 150 is an adaptive noise cancellation (ANC) headset. Figure 1C , illustrates an exemplary embodiment of audio components 160 and 170 for use in an ANC headset. The audio components 160 / 170 are implemented as slave devices on the data bus 158 of the headset 150. Each of the audio components 160 / 170 includes an audio output circuit 182 for receiving audio data from the slave component and driving one or more speakers 186 to play the audio data for the user, and an audio input circuit 180 for receiving sensor data from one or more microphones 184, digitizing the received data, and providing the digitized audio data to the slave for transmission across the data bus 158 to the master.

[0053] exist Figure 2AAnother embodiment of a connected device is illustrated in FIG. Connected device 230 includes connector 216, cable 220, device controller 240, user interface 246, and audio components 242 and 244. Connector 216 is adapted to interface with an interface component of a host device (such as Figure 1A The connector 216 is coupled to the interface component 116 of the device 230. The cable 220 couples the connector 216 to the device controller 240, which provides an interface between the communication protocol used to communicate with the host device and the bus protocol of the connected device 230. The device controller 240 acts as a master of the communication bus coupling one or more slave devices, such as the audio component 242 and the audio component 244. The user interface 246 is coupled to the device controller 240 to provide user control, such as volume control or mute on a set of headphones.

[0054] refer to Figure 2B , Figure 2A An exemplary connected device 230 can be implemented as a USB headset 250 (e.g., a USB headset) that includes a USB connector 252 for connecting to the interface component 116 of the host device 110, a USB cable 254, a device controller 256, a user interface 257 (such as buttons), and a wired data bus 258 that connects audio components 260 and 270 to the device controller 256.

[0055] The system and method of the present disclosure support long wired links, low power implementations and high bandwidth communications. In various embodiments, low duty cycles are used for signals, which reduces the static power consumption associated with terminated links. In various aspects of the present disclosure, low duty cycles are implemented on a per-symbol basis (e.g., by using short symbols) and / or by quickly transmitting data packets and then letting the bus idle for a short period of time. One advantage of these methods is that low latency links are supported because data packets can be transmitted quickly, after which the bus enters idle and consumes little or no power. In one or more embodiments, higher data rates are supported by incorporating an internal phase-locked loop (PLL) or DLL (delay locked loop) in each receiving device to generate a higher speed internal clock based on regularly transmitted synchronization symbols. An advantage of using symbols with low duty cycles is that they allow low power consumption at medium transmission rates because the static power consumption of the link using the termination is reduced due to the low duty cycle. In other words, low power consumption for medium to low speed signaling can be achieved with a link capable of high baud rates using terminated transmission lines because the power consumption of the various embodiments disclosed herein scales linearly with the bandwidth used (since the power consumption of the PLL receiving the data will be constant, but can be made to be a small fraction of the total power budget). Thus, the data link implementations disclosed herein can have low power consumption when using medium to low bandwidths, and still be able to transmit large amounts of data with slightly higher power consumption. In both cases, the PLL clock frequency or DLL delay can be constant or vary as required by the system.

[0056] The present disclosure also supports multi-drop bus topologies by providing control at intermediate nodes, thereby allowing high quality signals to be obtained even when there is an impedance mismatch at the intermediate nodes that would result in poor signal integrity in conventional systems. In many conventional systems, this is addressed by avoiding terminations at the ends of the transmission lines rather than controlling the slew-rate of the signal, however, this results in a slower system due to the limitation of the maximum slew-rate that can avoid reflections. The various systems and methods disclosed herein do not suffer from this limitation.

[0057] Embodiments disclosed herein provide a robust and reliable data link with minimal degradation of signal integrity. In some embodiments, a transmitter may disable its own parallel termination resistor when transmitting to further reduce power consumption. In some embodiments, a transmitter at each end of a bus transmission line may provide termination by setting the output level to a static value when not transmitting. By setting the voltage level to the static idle value of the system and matching the series output impedance to the bus impedance (i.e., the output transmitter at each end acts as a terminal when it is not transmitting), low power consumption (e.g., no power consumption other than the operation of the internal clock, etc.) will be achieved when there is no transmitted data. In conventional systems, changes in impedance in the transmission line will result in reflections in the transmitted signal. This fact has led to conventional systems adhering to design constraints based on the concept that multiple components cannot be easily placed on intermediate nodes on the transmission line without severely distorting the transmitted signal.

[0058] However, in the present disclosure, it should be recognized that if the change in impedance occurs over a relatively short distance compared to the shortest wavelength involved, there will be little signal interference and a practical system can be implemented. As an example, an experimental system using a 50 ohm transmission line included multiple intermediate nodes, each of which involved a small stub (1-2 cm in length), and this resulted in a change in slew rate from 4.7ns to 4.8ns (or about 100ps increase) and a reduction in amplitude of about 6% for each node. Therefore, even if the slew rate is slightly increased and the amplitude is reduced a little, the change in the signal is minimal, a good eye diagram is obtained, and robust data transmission is achieved. Therefore, even if conventional theory has led to the system requiring any change in impedance along the transmission line to be prevented to avoid reflections, as long as the length of these interferences is much shorter than the wavelength of the fastest signal involved, these reflections can be controlled to have such small amplitudes that are not harmful to the actual functional system.

[0059] The experimental system has a stub length of 2 cm, which is equivalent to a transmission time of less than 0.1 ns in air, or much shorter than the rise time (5 ns). In this case, the factor between the rise time and the delay through the stub is greater than 50, and results in minimal delay and interference in the system. If the delay is already 5 ns (equivalent to a 150 cm cable without shielding), the system rise time and delay in the system will be comparable, and the cable will appear to be expandable (open-ended). Therefore, sized as disclosed herein, one or more systems of the present disclosure will allow the transmission of very fast signals properly terminated at the end of the transmission line, and simultaneously allow multiple components to reside on the same transmission line, thereby solving the problem of obtaining a multi-drop bus system that still allows high transmission speeds. In addition, by timing the sequencing of the transmission of the signal so that the forward or backward wave is controlled, it is possible to avoid problems with active transmitters residing on intermediate nodes on the transmission line that interfere with the traveling wave.

[0060] Now refer to Figure 3 An example of a timing sequence according to one or more embodiments is described, which shows information traveling between a master device and three slave devices. By optimizing the timing related to the direction of data transmission, higher bandwidth can be obtained. In various embodiments, all packets will disappear once they reach the terminal at the end of the line where they are absorbed. Assume that the master M1 is located at the end of a transmission line with multiple slave devices (S1, S2 and S3) located on the same transmission line, where the slave devices are labeled with numbers one, two, three, etc., because each slave device is farther away from the master device.

[0061] When sending a forward-traveling wave from the master, the master M1 sends a message first (time A), followed by slave S1 when the forward wave has just passed (time C), and then slave S2 sends its forward-traveling wave message when the end of the message from slave S1 has been completed (time E). When the message from slave S2 has been completed, slave S3 sends a forward-traveling wave message. When all forward-traveling wave messages have been completed and absorbed by the terminal at the other end of the transmission line, the last device residing on the transmission line (e.g., slave S3 at time F) begins to transmit a backward-traveling wave toward the master M1. Just after the message from the last device has passed, etc., the backward-traveling wave follows the transmission of the backward-traveling wave from the second device to the last device residing on the transmission line (e.g., slave S2 at time G). When all backward-traveling wave messages have been completed and absorbed by the terminal at the master device, the master M1 will once again begin to transmit messages using the forward-traveling wave as previously described.

[0062] In some embodiments, two devices can transmit messages simultaneously if the devices are located at opposite ends of the transmission line and the effect of their own transmitted waves is subtracted from the measured waves (the superposition of the forward and backward traveling waves). In some embodiments, this can also be performed even with devices located at midpoints of the transmission line, however, in some embodiments, devices located at midpoints should generally not transmit while receiving, as this may result in reflections of the forward or backward traveling waves.

[0063] In various embodiments, a communication bus for use with audio devices such as audio headsets includes a multi-drop bus capable of high bandwidth and low power consumption using differential impedance matched signaling. The bus has high control and audio bandwidth and supports links up to more than 10 meters. In one or more embodiments, the total bus link length is two meters or less. Reference Figure 1A , the link length is the length of the two terminal endpoints Z END 146, and includes the length of the cable 120 from the device controller 140 that can be integrated into the connector to the user interface component 146 (length A), the length of the wire from the user interface component 146 to the intermediate node (length B1 and length B2), and the length of the wire from the intermediate node to the terminal endpoint (length C1 and length C2). In one embodiment, the link has a total length of 0-200cm from the terminal endpoint, including the following ranges: length A, 0-80cm; length B, 0-60cm; and length C, 0-60cm. In one embodiment, stubs B2 and C2 should be kept as short as possible to minimize the impact on signal integrity.

[0064] refer to Figure 2A In one embodiment, the length of the USB cable is from 0-200 cm, and the link length between each terminal end point and the device controller 240 is from 0-100 cm. In the illustrated embodiment, the link between the terminal end of the headset and the farthest speaker or microphone is less than 200 cm, but other distances may be used.

[0065] In various embodiments, the link supports standard clock rates, such as 12.288 MHz and 19.200 MHz, thereby providing compatibility with standard telecommunications and audio systems. In one embodiment, a link distance of 10 meters is supported in the 12.288 MHz operating mode by increasing the turnaround delay when switching the signaling direction.

[0066] In various embodiments, it is desirable that the locking range of the PLL is narrow and that a constant number of bits is maintained between each synchronization symbol. Additionally, in various embodiments, it is desirable to maintain 48kHz compatibility with multiple clock systems. The present disclosure provides initial synchronization between slave and master devices that is simple and robust, and in various embodiments, uses a constant frame size. The use of a constant frame size is in contrast to SoundWire and similar protocols, which enable multiple frame sizes to ensure compatibility with multiple clock systems. In one or more embodiments, one or more beacon bits are represented within a frame to maintain synchronization between multiple sources, such as multiple audio ports utilizing different sampling frequencies.

[0067] Below, an exemplary operation mode according to one or more embodiments of the present disclosure is illustrated in the table:

[0068] Mode Name telecommunications USB Audio unit Master Audio Clock 9.600 12.000 12.288 MHz Bus length (minimum) 0 0 0 m Bus length (maximum) 2.0 2.1 2.1 m Master to slave bandwidth 51.200 48.000 49.152 Mbaud Bandwidth from slave to master 51.200 48.000 49.152 Mbaud Control bandwidth 6.400 6.000 6.144 Mbaud Control words 32 32 32 Bits Control updates 200 187.5 192 kHz Bit rate link 134.400 126.000 129.024 MHz PLL, typical 268.800 252.000 258.048 MHz PLL reference frequency 3200 3000 3072 kHz PLL power consumption, approx. 250 230 240 W The interval between synchronization symbols 42 42 42 Bits Waiting time of master or slave (one line) 313 333 326 ns

[0069] The systems and methods disclosed herein provide additional advantages including energy efficient design, solve some problems in terms of synchronization symbol interference frame size, including efficient bandwidth utilization scheme by merging synchronization columns with commands, have a simple clock scheme, use a single clock source, enable fine-tuning of delay for optimal signal integrity, support 12.288, 19.200 and 12.000MHz systems, do not require wideband PLL tracking (i.e., the PLL only needs to support a relatively narrow lock range), constant frame size can be used with varying data formats to support multiple clock systems, and use micro-stepping of sample intervals to accurately measure slave delays for optimizing eye diagrams when receiving data. In various embodiments, for example, while maintaining a constant frame length, a multi-drop bus can be used for multiple clock systems, such as telecommunications, USB, and audio operating modes. In some cases, lower synchronization frequencies such as 768kHz can be used for longer bus diameters.

[0070] The sync symbol can be combined with the signaling of the command by careful timing of the slave delay so that the time slot after the master has completed the sync symbol (typically a 0-1 transition) can be used to signal a command or allow multiple devices to respond in the same time slot by leaving the time slot undriven and allowing the devices to change the current level, but not drive the current level (similar to a wired-or configuration).

[0071] Clock support

[0072] As previously discussed, one problem encountered with conventional bus topologies involves supporting different clock frequencies, including the multipliers or dividers required to obtain the desired base frequency. As an example, 48kHz can be obtained by dividing 19.200MHz by 400 (4x5x5) or 12.288MHz by 256 (4x4x4x4). In various embodiments disclosed herein, commands transmitted on the bus do not interfere with the audio stream. In one embodiment, commands are issued at the same pace (or sub-multiples thereof) as the audio data. In some embodiments, there are constraints on PLL or DLL clock synchronization to embed the clock into the data line, thereby saving wires and power consumption. By using differential signaling, electromagnetic interference (EMI) can be constrained.

[0073] In one embodiment, a solution is provided that includes adding extra bits to give space for synchronization and commands within the communication frame. The system can support a variety of clock frequencies and can optimize the frame structure relative to the bandwidth utilization of a given long bus diameter constraint. The structure of this embodiment is deterministic and simple to decode, and does not require complex analog circuits to determine the exact clock frequency, such as the number of clock pulses between each synchronization symbol frame remains constant.

[0074] Existing systems (such as SoundWire) contain multiple defined frame formats - for example, 8 column sizes and 19 possible row values ​​for a total of 152 combinations. One challenge is to design a system that supports both 12.288 MHz and 19.200 MHz operation, since each has different multipliers (19200 / 48=400 and 12288 / 48=256) without requiring a special analog system. In various embodiments described herein, a single frame size can be used that allows support for both 12.288 MHz and 19.200 MHz, and even 12.000 MHz systems.

[0075] The PLL and clock solutions disclosed herein solve various problems associated with conventional systems. When there is an unterminated transmission line, there are reflections that may interfere with signal quality. One solution is to slow down data transmission. However, for many systems, high-speed transmission is desired, and therefore, it is preferred to terminate the line to eliminate unwanted reflections. By using a high clock speed and a low duty cycle for the data (either for each symbol or as an idle space at the end of each cycle / line), it is possible to reduce the static power consumption of each transmitted bit, and thereby obtain lower power consumption for medium-speed links.

[0076] When there are only two devices, synchronization between the devices is simplified because there is no cross traffic. In addition, such a system may not require terminations at each end because the two devices do not experience any half voltage when the devices are at the ends of the transmission line. In the case of multiple devices, there is a possibility that the slave device will lose the lock on the master device. One solution is to restart the bus, but this is undesirable for many implementations because the system will lose audio for a period of time. Various embodiments of the present disclosure solve the problem of slave devices that lose synchronization while other devices on the bus continue to operate by solving clock synchronization.

[0077] refer to Figure 4 , an exemplary phase locked loop (PLL) 300 will now be described, which may be included in Figure 1A The device controller 140 and Figure 2A The device controller 240, and Figure 1A The slave device audio component 142 and the audio component 144 and Figure 2A The PLL 300 allows the circuit to remain locked even in the presence of signals from multiple slave devices that are time division multiplexed with the master synchronization signal.

[0078] The PLL 300 (or DLL) generates an output clock signal having a phase and frequency relative to the phase and frequency of the input reference clock. During operation, the reference clock signal through the time gate 302 and the feedback signal from the divider 310 are input into the phase detector 304. The phase detector 304 compares the phase and frequency of the input reference clock signal and the feedback signal, and outputs a control signal to adjust the feedback signal accordingly to have a phase and frequency synchronized with the phase and frequency of the reference clock signal. The phase detector 304 aligns the phase of the rising (or falling) edge of the reference clock signal and the feedback signal. The output of the phase detector 304 is provided to the loop filter 306 to adjust the voltage and frequency of the voltage controlled oscillator (VCO) 308. The signal output from the VCO 308 passes through the divider 310 to generate the feedback signal. The output clock signal is provided to various system components as described herein. In the illustrated embodiment, the divider is configured to a multiple of a frame size of 144 bits, but other integer values ​​may be selected (e.g., M=16, M=42, M=48, or M=80). Using M=4 gives 4 time slots directly, or 8 time slots using two phases of the clock used for data capture of the bus signal. Using M=8 gives 8 time slots directly, or 16 time slots using two phases, which provides a simple solution with high resolution.

[0079] In various embodiments, the time gate 302 is enabled at all times during the initial startup, and thereafter only during the reception of a reference synchronization pulse from the master device. This enables the circuit to lock to the master even if multiple slave devices are also signaling on the bus and these slave devices are offset in time from the master. In addition, if the PLL / DLL loses lock with the master synchronization, the device will disable the output driver to avoid bus conflicts and re-enable the wide search for the synchronization pulse. In some embodiments, by using the time gate as a phase detector (for example, by using a sufficiently narrow time window), the phase detector can be completely eliminated. This can be used to reduce timing jitter (the time gate will still be controlled by the output from the VCO through the divider). In some embodiments, the phase detector will be of the phase-frequency type, so it is sensitive to both frequency and phase difference (III-IV type phase detector), thereby ensuring safe initial acquisition of the correct state.

[0080] An exemplary clock division solution for use with embodiments of the present disclosure will now be described. Figure 5A and 5B In one embodiment illustrated in FIG. 1 , the clock solution is an implementation of a frequency locked loop (FLL) 400 that generates three synchronous clock signals, an audio clock 402 for audio input and output processing, a USB clock 404 for USB communications between a host device and connected devices, and a data bus and DSP clock 406 for use in a low latency data bus of the present disclosure. The synchronization pulses present in the USB protocol can be used as a timing reference.

[0081] In the illustrated embodiment, a synchronization detector 410 is coupled to the input of the FLL 400. The synchronization detector 410 determines whether the clock signal is synchronized with the system clock (USB clock reference) to allow proper bus communication. If the synchronization symbol is not synchronized (arrive out of sync), the synchronization detector 410 will cause the FLL 400 to modify the clock period to bring it into synchronization with the master clock. The FLL 400 can be implemented as shown to include a digital filter and predictor 412, a digital-to-analog converter (DAC) 414, such as a delta-sigma DAC, a voltage controlled oscillator (VCO) 417, a divider 424, a frequency counter 418 and a subtractor block 414 to compare the result with a reference frequency 408. Another aspect of the illustrated embodiment is the use of a reference frequency integer 48384 (see reference 408), which can be used to cause the FLL 400 to generate a desired divided frequency using a divider 420, a divider 422 and a fractional divider 426. In Figure 5B, which can be used to divide a clock signal by a fractional value. The fractional divider 430 is implemented using a phase adder 432 and a divider 434, where a certain phase value is added to the phase sum of each clock cycle, and when the current phase sum exceeds a certain maximum phase value, another phase value is subtracted from the current sum and the output is activated. If a two-complement adder is used, the phase value can be taken as 2 N The step size is 0.001 and due to the automatic wrap-around that occurs in the two's complement operation without the need for subtraction. In some embodiments, the delta-sigma converter can perform integration instead of a phase adder, thereby eliminating the spur produced by the fractional division. This can be used to reduce the EMI of the output clock signal by spreading the output spectrum.

[0082] Below, an exemplary clocking solution for various embodiments of the present disclosure is illustrated in the table.As used herein, the term "EarLink" refers to the audio bus system and method of the present disclosure.

[0083]

[0084] An exemplary embodiment of a second clocking solution is Fig. 6A and 6B . The second clock solution is an implementation of a frequency locked loop (FLL) 500 that generates three synchronized clock signals, an audio clock 502 for audio input and output processing, a USB clock 504 for USB communications between the host device and connected devices, and a data bus and DSP clock 506 for use in the low latency data bus of the present disclosure. The FLL 500 includes a sync detector 510, a filter and predictor 512, a delta-sigma DAC 516, a VCO 517, a divider 524, a frequency counter 518, and a subtractor block 514, except as described herein, which can be used in conjunction with Figure 5A and 5B FLL 400 generates the desired divided frequency using divider 520, divider 522 and PLL 540, which outputs a frequency of 125 / 128 of the audio clock frequency. Figure 6B An embodiment of a PLL 540 is illustrated in , and includes a 1 / 128 reference input from the output of the divider 520 , a phase detector 544 , a loop filter 546 , a VCO 548 , and a 1 / 125 divider 550 .

[0085] exist Figure 7An exemplary embodiment of a third clock solution is illustrated in FIG. The third clock solution is an implementation of a frequency locked loop (FLL) 600 that generates three synchronized clock signals, an audio clock 602 for audio input and output processing, a USB clock 604 for USB communications between a host device and a connected device, and a data bus and DSP clock 606 for use in a low latency data bus of the present disclosure. The FLL 600 includes a sync detector 610, a filter and predictor 612, a delta-sigma DAC 616, a VCO 617, a divider 624, a frequency counter 618, and a subtractor block 614, which can be used in conjunction with the sync detector 610, a filter and predictor 612, a delta-sigma DAC 616, a VCO 617, a divider 624, a frequency counter 618, and a subtractor block 614, except as described herein. Figure 5A and 5B 6 are implemented in a similar manner. FLL 600 generates the desired divided frequency using divider 620, divider 622 and PLL 630, and PLL 630 outputs a frequency at 21 times the audio clock frequency.

[0086] An exemplary embodiment of a fourth clocking solution is Fig. 8A and 8B 5-7 . The fourth clock solution is an implementation of a frequency locked loop (FLL) 700 that generates three synchronized clock signals, an audio clock signal 702 at 12.288 MHz for audio input and output processing, a USB clock signal 704 at 12 MHz for USB communication between a host device and a connected device, and a data bus and DSP clock signal 706 at 258.048 MHz for use in a low latency data bus of the present disclosure. The FLL 700 includes a synchronous detector 710, a filter and predictor 712, a delta-sigma DAC 716, a VCO 717, a divider 724, a frequency counter 718, and a subtractor block 714, which can be implemented in a manner similar to the corresponding components of FIGS. 5-7 except as described herein. The FLL 700 generates the desired divided frequency using a fractional divider 720, a divider 722, and a fractional divider 730, which outputs the frequency at 21 times the audio clock signal 702. An embodiment of the fractional divider 720 is Figure 8B, which can be used to generate data bus and DSP clock signals 706. The fractional divider 720 is implemented using a phase adder 732 and a divider 734, where a specific phase value is added to the phase sum of each clock cycle, and when the current phase sum exceeds a certain maximum phase value, another phase value is subtracted from the phase sum and the output is activated. In some cases, a jitter generator 736 provides jitter to the phase adder to not only divide the clock by a fractional value, but also add the jitter value to the intermediate phase value. This will increase the jitter of the clock, but can be used to reduce the EMI of the system clock by controlling the amount of jitter added. Typically, the emitted EMI will be reduced by 15-20dB by this action. The jitter generator 736 can be implemented using a digital pseudo-random generator or other digital circuit that generates random numbers. If the pseudo-random generator adds an average value to a phase adder sequence that is different from zero, this should be taken into account when updating the phase adder.

[0087] Frame structure

[0088] According to various embodiments of the present disclosure, a single frame structure may be used across multiple supported frequencies.An exemplary frame structure for use with the disclosed embodiments will now be described.

[0089] refer to Fig.9A In an embodiment, the frame structure includes a frame of constant size of 42 bits, where the synchronization pattern is repeated at a frequency of once per frame. In one embodiment, the number of command bits per message is 32 bits and the message synchronization bits are repeated every 48kHz. Each frame may include one or more subframes, for example, four subframes and each subframe has the same structure and looks the same in terms of synchronization. An exemplary organization of command bits is illustrated below, where SCMD is the start of a command, S48 is a 48kHz beacon, RES is a reserved field, OP2-OP0 is a three-bit operation code, Dev3-0 is a 4-bit device number, DAT is data to be transmitted as part of the command, PAR is a parity bit for security, and ACK is an acknowledgement bit:

[0090] SCMD S48 RES OP2 OPI OP0 DEV3-0 DAT PAR ACK .

[0091] Bit S is equal to one bit at the start of the first subframe for every 48kHz time tick or every 64 frames or 256 subframes (for every 24kHz time tick or 512 subframes for 9.600MHz systems). The S bit can be used to find the start of the frame and synchronize multiple sound sources to 48kHz (e.g., the start of the first frame should be a sampling event).

[0092] Details of the data organization are in Fig.9A. A zero-to-one transition is used by the PLL in the slave device to synchronize the internal timing with the master, followed by the command bit CMD. Next, 16 bits of audio can be transmitted from the master device to the slave device, followed by one or more time slot delays (to allow for changes in signal direction) during the switch from the master device to the slave device (including read, R, command). Next, 16 bits of audio can be transmitted from the slave device to the master device, followed by one or more time slot delays.

[0093] Embodiments for 9.600 MHz, 12.000 MHz and 16.000 MHz systems are described in Fig. 9B and 9C . These formats will enable support for telecom clocks and can vary the bandwidth utilized between master and slave from about 1 / 3 to 2 / 3 of the bandwidth used by either the master or the slave. These formats have the advantage that the number of bits per row is 10 or slightly more for more efficient transmission at clock frequencies associated with 19.200 MHz. This frequency or 38.40 MHz = 2*19.20 MHz is commonly used for use in telecom applications such as mobile phones and handheld devices.

[0094] refer to Fig.9D and 9E , additional frame structures will be described. According to various embodiments, there are the same number of bits in each frame between each synchronization pulse. However, the number of bits can be varied, for example, by changing the amount of bandwidth used for commands. The frame structure can also vary in the number of rows and columns and still maintain the same number of bits. For example, Fig.9D and 9E Both include the same number of bits per frame. By dividing each frame by a larger number of bits (e.g., 80 or 144 bits), which can be broken down into various factors, the frame organization can be changed without changing the PLL multiplication factor, at the expense of higher jitter in the receive eyeopening due to the higher bandwidth.

[0095] An exemplary message field organization is illustrated below:

[0096]

[0097] It should be understood that while many commands may be conventional (do nothing, read and write registers), the DELAY command may be used to find the delay between devices attached to the transmission line for optimal timing. This can be accomplished by the master first charging the line to a certain value, then holding that value with a bus keeper or with a floating bus, after which the master driver is released, and after which any device attached to the bus can toggle that value. Positioning the device closest to the master will affect the switching of the bus line first, which can be reliably measured using a high-speed timed counter to detect timing events or using multiple delay circuits. During the measurement, the bus will not be terminated so as not to affect the timing. The measurement can be performed inside the master device (to optimize the slave transmit timing) or inside the slave device (to optimize the slave to slave communication timing).

[0098] Fig.9F Exemplary protocol symbols according to various embodiments are illustrated. Another exemplary command setting is further illustrated in the table below:

[0099]

[0100] An embodiment of a "register read operation" will now be described. To perform a register read operation, the following instruction sequence may be executed: (i) write the correct address value using an address write operation, and (ii) perform a register read operation (the data field will contain the read value). If a range of registers needs to be read, this can be done without updating the address register between each read operation. This is possible because the address counter may be incremented by one for each read operation.

[0101] An embodiment of a "register write operation" will now be described. To perform a register write operation, the following instruction sequence may be executed: (i) write the correct address value using an address write operation, and (ii) perform a register write operation (the data field will contain the read value). If a range of registers are to be written, this can be accomplished without updating the address register between each write operation. This is possible because the address counter may be incremented by one for each write operation.

[0102] An embodiment of an "address register write operation" will now be described. Register access is controlled by an address register. Before performing a register operation, the value of the address register is first defined. This occurs with an address register write operation. The address register points to the currently valid register in the addressed slave device. Subsequent accesses (read or write operations) can increment the address register. This enables faster access to multiple registers. In various embodiments, there is only a single register that controls both read and write operations, and any read or write operation can increment the value of the address register. The increment occurs after the value of the address register has been used once in a read or write operation. The current value of the address register cannot be read back using the commands shown in the table.

[0103] An embodiment of a "beacon" command will now be described. This command can be sent out by a master device with a repetition period of 48kHz. It can be used by slave devices to synchronize the audio timing to the start of a frame so that all audio sources are synchronized.

[0104] An embodiment of the "Device Loop Delay" command will now be described. This command measures the turnaround delay from a slave device to a master by measuring the transition initiated by the slave device and traveling to the master. In this embodiment, a mechanism for measuring the two-path delay is provided. Reference will now be made to Fig. 10A An embodiment of a method 800 for delay measurement is described. First, the master sends a command to the device to indicate that the delay measurement will begin (step 802). Next, the termination is disabled at both ends (step 804), and the transmission line is charged with a known symbol (step 806). In step 808, the known device responds by discharging the transmission line. In step 810, the delay is measured from the charging event to the discharging event. In step 812, if the system includes end terminations, the terminations are enabled at both ends of the transmission line.

[0105] In one implementation, the master sends out a device loop delay command, followed by the device number to be queried. Next, the master sends out the device ID value in the data field. If the device ID is equal to the data field, an internal flag ("device_update_ready") will be set, and if the device ID is not equal to the data field, the internal flag will be reset. Next, the bus is brought to a known state by the master (i.e., the bus is initialized to a known logic value, zero). The master will maintain this state using a weak bus keeper or using a floating bus, and after driving the bus to a known state, disable its transmitter and ensure that the terminals at both ends are disabled during the measurement. As an example, the master can use a 0-1 signal for synchronization and put the bus in a "1" state.

[0106] Then, the slave device can use the strong internal driver from the device to drive the state to different values.In one embodiment, the slave device outputs the following sequence, where Z is a disabled driver, and 0 is driving a low signal--ZZZZ-00-ZZZZ--and double zeros will ensure the correct reading of zeros under all delay conditions.When the master receiver receives the transition signal from one or more slaves, it will know the delay from timing.The timing of this event will be used to find the two-way delay to the nearest device, and the eye diagram of the receiver is optimized by controlling the transmission or reception timing delay.The delay value can be measured based on the internal oversampling clock inside the master device or using the delay line or delay sampling inside the master device.In some cases, in the case of a significant amount of noise or clock jitter on the bus, it may be necessary to repeat the program many times to obtain a good delay reading.This can also involve reading the return value from multiple time slots, and obtaining it with fine resolution (e.g., 2ns), and then averaging multiple read values ​​(e.g., 64). If the return value can occur anywhere from 0-36ns, we will need a total of 19 values, each based on multiple measurements returned from the slave device to accurately determine the delay in all cases, and in each case, we may have to perform multiple (e.g., 64) readings to return a good average. By starting the search from the middle delay position, it is possible to significantly reduce the search time. In addition, it is also possible to reduce the search time by changing the search direction depending on what the last return value is, because this gives an indication of whether the delay is too long or too short. In the case of restrictions, we will measure about 50% of the zeros and ones returned from the slave exactly at the transition. In addition, we will need to add 1 / 2 data time slot to get the best sampling point.

[0107] In another implementation, the master can write back the value it has read from the slave, and then cause the slave to self-adjust internal delays. This can be used to optimize the communication from the slave to the master, i.e., reduce the required bandwidth for adjustment. Similarly, a slave can write the value it has read from another slave, and cause the other device to self-adjust its internal transmit timing.

[0108] When the master sets the bus to a known value, the charge left on the bus will be absorbed by the master, thereby clearing the transmission line of any previous information. If there are multiple slaves, they can be eliminated one at a time using their device ID (16-bit constant). The slave closest to the master will correspond to the delay value obtained. In other words, during the measurement of device delay or the counting of devices attached to the bus, the first device attached to the transmission line (typically the master) and the last device attached to the bus (typically the slave) will both disable their drivers during this procedure to enable a floating bus, which is maintained by the inherent charge inside the transmission line.

[0109] In various embodiments, only devices with a digital DEV and a device id equal to or higher than the data field value will activate the output. A binary search can then be used to find the device with the highest address current connected to the bus, eliminating that device from the search by assigning it a different device ID (typically 3 bits to save bandwidth and continuing to find the address of the second highest device attached to the bus, etc.). In other words, an arbitration procedure must first be used so that the MSB of the device ID is read first and all slaves with lower device IDs will fall back. This procedure will continue until only a single device will respond (note that this procedure is similar to I 2 C multi-master and SoundWire address arbitration).

[0110] In one embodiment, all devices will shut down normal data traffic in the last line of the frame when the delay command is used to ensure that it will not interfere with the measurement. In some embodiments, slave devices can be programmed to use specific delays corresponding to a certain geometric configuration, thereby eliminating the need to find the physical delay before interacting with the component and eliminating the need to include non-volatile memory or other means to communicate delay values ​​to internal circuits.

[0111] refer to Fig. 10B , illustrates a method 850 for counting attached devices that contain internal device numbers rather than device numbers suitable for the bus. In step 852, the master sends a command to indicate that counting will begin. In step 854, the terminals at both ends are disabled, and in step 856, the master continues to charge the transmission line with a known symbol. If the bit from the device number is high, the unknown device on the bus responds by discharging the transmission line (step 858). After a known delay, all devices with low bits in the device number for this position will abort (step 860). If more than one device is left (step 862), then the next device bit is checked, and device arbitration continues in step 864. If only a single device is left, the device is assigned an address in step 866. If the master knows the long IDs (e.g., 16 bits) of all attached devices in advance, it can simply address these devices at a time and reassign a new short ID (3 bits) to each device immediately after booting without performing address arbitration.

[0112] An embodiment of the "Set Device Address" command will now be described. After a power-on reset, the slave device is assigned a device address value of zero. When this command is executed, the addressed device will get a new address (0-7). Notification address 7 (111) is included for broadcast. In one embodiment, only devices with device_update_ready set will be updated.

[0113] Duplex operation

[0114] Now refer to Fig.11A Describes an embodiment of duplex operation. In various embodiments, bus 900 can operate in simplex or duplex operation mode. In this arrangement, the I / O port can be configured to transmit and receive both signals simultaneously through the design of the output driver, which can be used to enable bus lengths exceeding 25 meters, such as can be used in home audio systems.

[0115] In this embodiment, the transient response at the forward and backward traveling waves is used to evaluate what is happening when there are two simultaneous drivers. The voltage at any point is determined by the sum of the forward and backward traveling waves. Therefore, we can measure the point at any node and subtract the effects from the two drivers, rather than simply by considering the impedance of the output driver and the impedance of the transmission line.

[0116] For simplicity, let's first evaluate the case with only two drivers 902 and 904 located at each end of the transmission line. Let's also assume that drivers 902 and 904 use series terminations with a value equal to the transmission line impedance Z0 to properly terminate the link. This means that both the forward and backward traveling waves will be half of the initial driver voltage. Since the voltage at any point can be found from the sum of the forward and backward traveling waves, we can find the correct received voltage by subtracting half of the driver voltage from the measured voltage. This can be done for the differential case by simply adding half of the reversed transmit voltage to the received signal (e.g., by using capacitor swaps and adding half of the differential transmit voltage). In this method, the two-way delay during the turnaround in the transmitter direction is not required for many configurations and much longer links (e.g., 25 meters) are possible in the case of continued operation, and there is no interruption in the data stream due to the absence of turnaround delays, and full-duplex operation at very high speeds is possible (0.1-5Gbps). Note that this configuration does not require any timing adjustments as long as operation is confined to one node at each line end and at least one node sends out synchronization pulses on a regular basis.

[0117] Multiple from

[0118] Now will describe multiple slaves various embodiments.Although duplex operation is relatively simple when having a single master and a single slave, for multiple slaves, the situation becomes more complicated.One problem is that the intermediate node will reflect the wave from either direction because it does not present a termination (so that multi-branch connection can be realized).Therefore, traditional duplex operation may be impractical for some implementations.However, it is possible to increase throughput by using the appropriate timing of the signal.In various embodiments, the signal will first be from the master to the slave.Other slaves may need to wait until the forward wave from the master has passed through these devices before it can start to transmit.Therefore, an exemplary timing diagram for handling this situation and not requiring any switching delay will be the following transmission sequence: {M, S1, S2, S3, S4, S5}, and then when changing direction, repeat the pattern with the reverse {S5, S4, S3, S2, S1, M}, where M represents the master, and S1 is the slave closest to the master, and S5 is the slave farthest from the master. In other words, the devices attached to the bus will transmit a sequence for either forward or backward waves, and the approach avoids problems with reflections from intermediate points on the transmission line. Before attempting this approach, the timing delays of the devices attached to the bus will be determined and corrected.

[0119] By ensuring that a differential signaling scheme is used for all communications, transmit and receive EMI will be significantly reduced. Fig. 11B An example of differential signaling 920 is shown starting with an idle period, followed by a sync signal, then data and then going idle again. The idle period should also be of differential nature to avoid common mode noise, meaning that the termination on one line should end up high and the other end should end up low to avoid static power consumption during the idle period and thereby enable very low power consumption for modest bandwidth requirements.

[0120] Fig. 11C An example of a differential signaling system 930 is shown with terminations to high and low signaling voltages to ensure the lowest possible EMI and lowest possible power consumption in idle mode. Fig.11DA similar example of a differential signaling system 940 is shown, wherein the transmitters 942, 944, 946 and 948 at each end are used as serial terminals of the bus, thereby reducing the power consumption at the end node, due to the absence of terminal loads and simplifying the implementation. When the bus driver at each end is not signaling data, it will enter an idle state, signaling the default terminal voltage, thereby reducing the power consumption in the idle state. In some embodiments, one of the two transmission lines can use a power line instead of grounding for shielding, thereby also being able to transmit power. Some embodiments can use 4 twisted wires instead of shielded coaxial cables, for example, including DATA+, DATA-, grounding and power supply in a four-wire twisted pair configuration for low EMI requirements. Grounding and power lines will further reduce EMI. In other embodiments, a single shield will be used, and power and differential data will be located in three wires inside the shield.

[0121] In some applications, it is important to minimize the audio noise caused by random signaling occurring on the bus. This can be done by changing the signaling levels of various sources on the bus, for example, by using a pseudo-random generator at the transmitter and receiver of the data port, thereby randomizing the bus traffic and thereby reducing the spectral content in the audio band. In some cases, randomization can be performed using spectral sharpening, so that by multiplying the data signal with high-frequency content (for example, by multiplying each line with a random or predefined value), the spectral content in the audio band is even lower. In some cases, randomization can be performed by simply multiplying the line with a carrier outside the audible bandwidth. In some embodiments, each port includes an error tester (for example, an 8-bit pseudo-random generator for verification and testing). The port tester can also be used to scramble and descramble audio data. Multiplication in the digital domain can be performed by XOR or XNOR gates. For example, almost the same pseudo-random generator can be used to recover the original data sequence, see, for example, the SoundWire specification for examples of pseudo-random generators and receivers / tester. Similar techniques have been used earlier, for example in radio modems, in order to reduce or remove the DC content from the transmitted data stream. Here scrambling is not used as much as to avoid the transmission of multiple symbols with the same value, which could lead to a loss of synchronization, but is used to reduce the low-frequency content of the output spectrum in order to avoid any interference in the audio band.

[0122] In some cases, randomization can be performed using a delta-sigma modulator with a known pattern to not only randomize the output from the various transmitters and thereby reduce any audio interference, but even to noise-shape the output spectrum of the noise by intentionally controlling the noise transfer function of the modulator.

[0123] Cable Specifications

[0124] Exemplary cable specifications according to various embodiments will now be described. For in-ear headsets, thin cables may be used to meet user requirements, such as a shielded configuration using thin AWG30 or AWG34 wires. For longer links or for large headsets and headphones, thicker cables may be used, which also reduces the attenuation of the bit, except that only 4, not 8, wires are required. An example would be a twisted pair cable pair similar to the CAT5 requirement (wire type AWG24). For example, a standard 100BASE-TX cable may be used. The attenuation of a 15 meter link would be 66db / 100mx15m=9.9dB or 3.1 times. Therefore, when designing a system, the difference between the transmit voltage and the maximum receiver hysteresis should take this into account.

[0125] Intermediate Node

[0126] An exemplary embodiment with an intermediate node will now be described. In various embodiments, the end node has a series output impedance of Z0 to match the transmission line, while the intermediate node will investigate 1 / 2Z0 impedance (because the intermediate node will essentially be looking into two transmission lines, each with impedance Z0). It is generally desirable to provide the same performance for all nodes. In various embodiments, (i) each node has an output voltage of U0; and (ii) each end node has an output impedance of Z0. If the traveling wave is valid when it reaches the node, the impedance of the intermediate node will result in a reflected wave. This situation can be avoided by proper timing of the signal (i.e., each node first transmits a signal after the signal wave with the previously transmitted information has passed). The traveling wave will eventually be absorbed at the end of the transmission line. Exemplary transmission line impedances and signaling voltages may include Z0=75Ω, U0=250mV, where differential signaling is used.

[0127] Additionally, an intermediate node on the transmission line will face two line inputs, and if its output impedance is the same as a node at the far end of the transmission line, the output signaling voltage will be lower. This can be corrected by using a lower output impedance for the intermediate node, by increasing the output drive voltage of the intermediate node, or by adjusting the receiver on the transmission line to a lower threshold voltage.

[0128] Boot Sequence

[0129] An exemplary startup sequence will now be described. In various embodiments, conventional signaling is differential, two-level signaling. However, in order to obtain a unique mode for startup conditions and for resynchronization after a possible slave fault or after a power-off condition, the master can be configured to send out a third or different higher voltage level. This level will not be used for data transmission, but only for resynchronization or startup conditions (waking up from low-power standby) from the device. This will not affect the EMI emitted, because the higher level is only used during initial synchronization (e.g., the first 1ms). In one embodiment, the startup sequence consists of 12 bit gaps with a voltage level twice that of the normal signaling level. In various embodiments, the synchronization edge used by the PLL will be followed immediately after the startup sequence. The startup sequence will not be transmitted during normal operation to reduce EMI and increase available bandwidth. In the illustrated embodiment, during startup or resynchronization, the master will have approximately 62.5% of the original bandwidth left (using a 12.288MHz clock frequency) and 40% of the normal bandwidth left in the 9.60MHz operating mode. In a simplified implementation, a DC offset is added to a certain number (e.g., 12) of time slots, and because the receiver is differential, the extra offset will not affect the data, but can be used to detect power-up conditions. In an even simpler implementation for initial and startup conditions only, a logic voltage such as 1.0V can be used for wake-up detection, thereby eliminating the need for a differential receiver in a low-power state.

[0130] Exemplary differential signaling voltages are illustrated in the table below.

[0131] parameter Minimum maximum unit Signaling voltage high 250 350 mV Signaling voltage low -75 75 mV Receive Low -300 100 mV Receive High 200 1200 mV

[0132] In various embodiments, to ensure a safe boot mechanism from a device, a higher voltage level is used on the bus line when the slave device needs to return to synchronization again. This higher voltage will be used to distinguish between normal data traffic and reset conditions. It can also be used for power-on circuits for low-power wake-up (e.g., wake-up words) when the bus is running. The higher bus voltage can occur for a longer time than normal data symbols to avoid random noise on the bus to trigger the wake-up circuit and reduce power consumption. In order to obtain reasonable tolerances, good noise immunity, and low power consumption, it is recommended that the wake-up event will consist of a 12-bit gap pointer (trail). This is equivalent to a minimum occurrence time of approximately 89ns at the highest bit clock of 134.400MHz.

[0133] refer to Fig.12, in step 1002, the system is powered on, and the lock flag and driver are disabled (step 1004), and the phase detector is disabled (step 1006). In step 1008, a wide search is enabled to detect the device. If a special sequence for the device is detected in step 1010, a synchronization pulse is detected in step 1012. If a special sequence for the device is not detected, the steps are repeated until the special sequence is detected. In step 1014, if the PLL is locked, the wide search is disabled (step 1016), and the driver is enabled (step 1018). When the time gate is opened (step 1020), the synchronization sequence (steps 1012-1018) is repeated. If the PLL is not locked (step 1014) and the narrowband is enabled (step 1022), the driver is disabled in step 1024, and control is transferred to step 1008 to repeat the wide search at high power.

[0134] Now refer to Fig.13 The operation of the special startup circuit 1100 is described. During normal operation, there will be no startup sequence and the output from this circuit will be zero. The output from this circuit is used until the PLL becomes locked. In operation, the circuit will filter the input from the bus and if the bus has been above a certain high threshold for a certain time, the PLL is enabled to look for the next high to low transition. When the bus level is low, the circuit will discharge any accumulated charge and begin the uninterrupted sequence of looking for high values ​​again.

[0135] parameter Minimum maximum unit VREF1 250 350 mV VREF2 500 600 mV Low to reset 0 8 ns High to enable PLL 50 100 ns

[0136] The length of this series of logic ones will depend on the clock frequency and the length of the high value sync pulse. This can be used by analog circuits to check for the start of sync under error conditions.

[0137] The output from the phase detector is enabled after 50ns (up to 120ns) or a logic one, followed by a logic zero. In the illustrated embodiment, this enables audio transmission even during a fault using up to 4 consecutive time slots. During a fault condition, the first 4 columns are reserved for audio transmission, while every 5th column is used to send a logic zero, followed by more audio, until the start of the sync pulse. After the 0-1 transition, the phase detector output is disabled again. In one embodiment, after the slave device has acquired lock, it looks inside the narrow window for synchronization transitions determined by the current lock position and ignores all other bus traffic.

[0138] Lock detector

[0139] parameter Minimum [ns] Maximum [ns] Enable 50 120 Reset time 0 8

[0140] An exemplary signaling solution will now be described. In the first signaling sequence solution:

[0141] Use three-level signaling: {-1, 0, +1}, as signaled by {low, zero, high}, for reduced EMI, similar to CAT5 signaling.

[0142] Logical zero: same level as before (four zeros may be followed by a value from a reverse sequence, i.e. going in the opposite direction after a number of zeros to ensure a safe start of detection).

[0143] Logical Ones: The next value in a sequence of ternary values ​​(e.g., multiple ones) will be signaled as the sequence {zero, high, zero, low, zero, high, low, etc.}. It is then more likely that the sync values ​​will use a different sequence (e.g., {high, low, high, low} or {zero, high, zero, high}) to distinguish between sync and data than legitimate data values. In other words, ternary encoding enables a receiver to reliably distinguish between sync and data while enabling a reduction in EMI by reducing the harmonics generated.

[0144] In the second signaling sequence solution, two-level signaling is used. In one embodiment, no device other than the master can have more than 4 time slots in a row, or zeros will be inserted between packets. If multiple devices send out data after each other, a gap is used between every 4 bits, and zeros are inserted. If the analog delay circuit can be made with a narrower tolerance than the above, more bits can be transmitted in sequence. This is an example of a special encoding in which bandwidth is compromised to enable synchronization symbols that are different from any legal data values. Other encoding schemes such as 8 / 10B encoding can be used to distinguish between synchronization and data.

[0145] In the third signaling sequence solution, DC offset is applied to all signaling from the master device, while the slave will not use DC offset. The differential signal is modulated by the master device with a common mode signal to indicate the start of the frame. Although this will increase EMI to some extent, this will only occur for a short period during the initial synchronization. Regardless of the current signaling mode on the bus and any previously encountered state inside any slave device, this change in DC offset can be reliably detected by the slave device, and synchronization can thus always be obtained. Fig.14 (3) illustrates an example of this solution.

[0146] High-speed transformation

[0147] refer to Fig.15, an embodiment of the operation of the present disclosure will be described. This solution allows the synchronization rate to be changed even while the audio is still running. In one embodiment, 250mV signaling can be used for both slow mode and fast mode, and the synchronization edge of the received signal inside the gated time window is used for audio sampling. In slow mode, if the time slot is not driven, there is no additional power consumption on the bus, and there is less additional power consumption from the internal PLL running at a higher rate. Therefore, a higher frequency of slow mode can be selected, which is used as a low power mode. In slow mode, it is relatively easy for the device to check synchronization (e.g., 2 time slots out of 12 time slots for synchronization). In one embodiment, all devices maintain synchronization at all times. In another embodiment, the device can enter a sleep mode and wait for a special VDD wake-up signal, which will induce a delay (e.g., 1ms) before it functions.

[0148] In one or more embodiments, the transition to high speed starts in slow mode with slow sync (e.g., 768kHz). Additional sync symbols are inserted to prepare for high speed mode, and the time slots are made shorter, but the original 768kHz transition is maintained. It is assumed that the symbols are read in the middle of the transmission interval. The slow mode device does not see the additional sync symbols. Each transmitter includes an internal clock that runs at least twice the original time slot clock to insert shorter symbols. In high speed mode, there are now more time slots. In various embodiments, the slow device can read in fast mode. This solution enables changes in bandwidth and synchronization repetition rate while keeping audio running while having both slow and fast devices attached to the bus at the same time. It basically inserts sub-intervals in the existing timing and uses these sub-intervals to add bandwidth to the existing transmission protocol. This method can be used for backward compatibility with existing interfaces (such as SoundWire) and also enables support for higher bandwidths, but the original interface cannot be provided.

[0149] Frame synchronization and bulk transfer

[0150] Those of ordinary skill in the art will recognize the many advantages of the systems and methods disclosed herein. In various embodiments, multiple upstreams facing the interface device (from the device) can be attached to the bus at various points and can communicate with each other at full speed due in part to accurate timing measurements. Due to the timing control and differentiation between the forward and backward waves propagated through the transmission line, signaling from different devices can be stacked close together. This enables high bandwidth even with a moderate slew rate that reduces EMI, which is beneficial for certification and compliance with EMI standards such as FCC Class A and B devices (Part 15).

[0151] The system described herein can be used to facilitate low-power data communication on two wires. The interface supports multi-branch operation with a master and one or more slave devices, and allows point-to-point communication between slave devices at full speed and across longer distances than conventional time-division multiplexing low-latency systems. Lower electromagnetic interference (EMI) is achieved through differential low-voltage operation and control of conversion rates. Each slave device includes a PLL / DLL, and the system supports terminated multi-branch, multi-device system arrangements.

[0152] The system and method include a simple frame structure and initial synchronization sequence that provide many advantages over conventional methods. In various embodiments, the initial synchronization between slave and master equipment is simple, robust and uses a constant frame size. Although variable frame sizes have been used in existing systems to ensure compatibility with multiple clock systems, a different approach is adopted in the present disclosure. The present disclosure utilizes the additional degrees of freedom provided by the oversampling clock system as disclosed herein to provide a flexible and effective solution. In some embodiments, the actual clock frequency can be inferred based on a beacon signal that forms a part of the frame.

[0153] In some embodiments, a row of data consists of 80 time slots, regardless of the clock frequency and mode of operation. The interpretation of these time slots may depend on the configuration selected, although the various fields will be in the same sequence. At startup, the default data format is set for the longest bus diameter (slowest speed). Fig.16A , illustrating the different fields in each row of data. By varying the interpretation of the various time slots, various tradeoffs between baud rate and bus diameter may be selected. The synchronization pattern repeats at a frequency of once per row of data (e.g., as shown in the figure, the synchronization rate is 3.072MHz). Each row begins with a zero to one transition. This transition is used as a sampling event for the internal delta-sigma converter and is used to lock the PLL / DLL to the bus so that bits can be received. Fig.16A The synchronization mode and simplified row description are illustrated. One advantage of using the zero-to-one event as the sampling event for the delta-sigma converter is that it only contains the jitter from the master clock and not the additional jitter associated with the clock recovery of the slave device. Therefore, due to the requirement of low current consumption of the PLL / DLL, this solution can achieve low jitter for audio sampling even in the presence of higher jitter inside the clock recovery unit in the slave device.

[0154] Each row consists of a synchronization field (frame starts with a logical one and ends with a logical zero), a command field (C for commands from the master), a field for transmitting audio in the forward direction (typically from master to slave), a two-way delay "turnaround" to enable a change in signaling direction (T1), a response field "R" from the slave device (used only when reading from a slave device), a field for transmitting audio in the backward direction (typically from slave to master), and possibly a gap field and ends with the start of a synchronization pattern. The row may also include a forward command (from master to slave) and frame (beacon) field (F) and data fields D0-D4. The number of time slots allocated to each of these fields can vary with the application, but the total number of time slots within a row is a fixed number, for example, 80. To change the number of columns in a row, the _ ... Fig.15 technology (e.g., changing the synchronization rate from 768 to 3072kHz). Figures 16A-16C Represents the default configuration at startup, where the index shown below is the number of the time slot at the beginning of each field.

[0155] The transmission of data will take place on the transmission line. To avoid collisions between data packets from multiple devices, we will distinguish between forward and backward waves. The forward wave starts at the master and is directed away from the master. The backward or reverse wave is the data that has been sent out from the slave device and is traveling in the direction towards the master. During the turnaround period, no device will transmit any information and their drivers are disabled (except for the possibility of active termination for such a system).

[0156] Audio data can travel in both directions on the link, i.e. in the forward direction from the master to the slave and in the backward direction from the slave to the master. If a slave wants to transmit data to another slave located further away from the master than the slave itself, it will send the data in the forward direction, i.e. in the fields marked D0-D7, as Fig. 16B In various embodiments, the system can accommodate control data (register reads and writes), isochronous audio (PDM and PCM), asynchronous audio (PCM), and bulk transfer operations.

[0157] Below, a table lists registers that allow the interface to be fine-tuned to accommodate various bandwidth requirements relative to signal integrity decisions. In some embodiments, after a reset has been applied, the interface will start with default values. In this embodiment, the Tx delay is stored as a two's complement signed value to ensure compatibility with multi-branch configurations, and the Rx delay is stored as a two's complement signed value. Due to hysteresis in the PLL / DLL, there may be a negative offset. If the value of register F is equal to the value of register G, block data will not be transmitted. If the value of register j is equal to the value of register k, block data will not be transmitted. In this embodiment, all register values ​​are counted in half-clock increments, and all register values ​​are positive (single byte) except for the TX and RX delay registers.

[0158] Referring to the table below, the Tx delay is stored as a two's complement signed value to ensure compatibility with multi-drop configurations. The Rx delay is stored as a two's complement signed value and there can be a negative offset due to hysteresis in the PLL. If the value of register F is equal to the value of register G, then the block data will not be transmitted. If the value of register j is equal to the value of register k, then the block data will not be transmitted. All register values ​​are counted in half-clock increments. All register values ​​are positive (single byte) except the TX and RX delay registers.

[0159]

[0160] exist Fig.17 The summary of the frame is illustrated in FIG. The boxes in the first and last columns are driven synchronously by the master device at a rate of 3.072MHz. Some boxes in the lower two rows (e.g., OP, ID, ##, C, FA, SA) represent command fields driven by the master device. The boxes marked as M represent audio data from the master to the slave, and the boxes marked as S may include audio data or responses from the slave to the master. The boxes in the second column marked as 1 may include turnaround delays or logical ones, and the boxes marked as T are turnaround delays from the master to the slave. In the illustrated embodiment, a column (arbitration / counting) is assigned for multi-branch, multi-write applications. Most columns are dedicated to a single device, but can be shared with careful timing control as described herein.

[0161] To save bandwidth, register read and write operations are performed by first updating the address register inside the slave device, after which the actual read or write operation occurs. In this way, repeated read and write operations will not require the address to be transmitted in each command.

[0162] The commands are encoded using redundancy so that at least two errors are required to generate an operation different from that expected, but generally more errors are required before that condition even occurs. The operations have been designed to allow for conservative operation - any single error will result in no operation, rather than attempting to proceed before a possible erroneous operation. The commands are built on the following notation {A, B, C, D}. The notation is defined as follows:

[0163] A={D2, D1, D0}={1, 0, 0}

[0164] B={D2, D1, D0}={0, 1, 0}

[0165] C={D2, D1, D0}={0, 0, 1}

[0166] D={D2, D1, D0}={1, 1, 1}.

[0167] These commands have a Hamming distance of two between them, i.e. it takes two errors to map one correct symbol to another correct symbol. The following values ​​are considered faulty or illegal symbols:

[0168] F1={D2, D1, D0}={0, 1, 1}

[0169] F2={D2, D1, D0}={1, 0, 1}

[0170] F3={D2, D1, D0}={1, 1, 0}

[0171] F4={D2, D1, D0}={0, 0, 0}.

[0172] If any of the illegal symbols are encountered in a command, then this command may be ignored and the intended receiver may respond with a request for attention at the end of this frame. Any ongoing block operation should be suspended, and only non-block operations will continue.

[0173] The command is defined by the OPCODE field. This field can consist of 3 or 6 bits. Reading only 24 bits from memory will use the shortened form of the OPCODE. In other words, when a specific OPCODE for "reading 24 bits" is encountered, the frame should be immediately recognized as a read frame, even before all 6 OPCODE bits are read.

[0174] Block operations are suitable for large-scale transfers of data to and from registers. These transfers have been protected to avoid interfering with any audio transfers by dedicating special fields within the row to these types of transfers. Therefore, audio transfers cannot interfere with block transfers, and vice versa. This is handled by the lowest hardware layer. This ensures that simple programming errors will not crash the bus. It is possible to reduce the time slots allocated for block operations to zero. Even if several errors should occur in the frame, this will ensure that block operations will not occur.

[0175] In one embodiment, all block operations begin with symbol A, followed by one of these values ​​for the second symbol: (i) "A" (stop block operation) - this block will be the second to last block in a series of block operations, and the next frame will be the last frame containing block data, i.e., block transfer will stop one frame of delay; (ii) "B" (defines the starting address of continuous write operations) - data will be stored in the memory, starting with the defined starting address, and each next data word will store the contents of the next memory cell, and the third frame from the current frame will use block transfer, i.e., block transfer will start two delayed frames; (iii) "C" (defines the starting address of continuous read operations) - data will be stored in the memory, starting with the defined starting address, and each next data word will store the contents of the next memory cell, and the third frame from the current frame will use block transfer, i.e., block transfer will start two delayed frames.

[0176] In an alternative embodiment, instead of using a "stop block operation", the number of elements to be copied during a bulk transfer will first be defined along with the starting address. After the bulk operation has begun, the addressed device will perform all operations by itself, and at the end of the bulk transfer, an IRQ ("request for attention") will be generated to let the master know that the transfer is complete. The master may then be able to access the status of the slave device to see if the bulk transfer was successful and check if the CRC value is correct.

[0177] Individual read and write operations work by first defining the starting address for the register operation, after which any later operations will use the previously defined address value to perform the I / O operation. The definition of the address for subsequent register operations is defined by signaling symbol D followed by symbol B.

[0178] Read and write operations work by first defining the starting address of the register operation with address incrementing, after which any later operation will use the previously defined address value to perform the I / O operation. When using this operation, subsequent read or write operations will post-increment the address value inside the device after each read or write operation has been completed. The definition of the address for subsequent register operations with address incrementing is defined by signaling the symbol d followed by the symbol C.

[0179] A single write operation is performed by signaling the symbol d followed by the symbol A. The address used must be defined before using this operation.

[0180] When performing a single read operation, the read operation will block all bits of the second symbol due to the complex timing details of the bus. Therefore, the read operation is completely defined by the first symbol, and the second symbol is ignored (the master will not drive the bus in this case). In addition, the read operation should start immediately after the first symbol (the first three rows in the frame) has been read and interpreted. The read operation is defined by symbol C.

[0181] If the device ID number is 7, this will perform a status read operation where all devices attached to the bus (except the master) will return their status. The three bits returned from each device are as follows (MSB returned first, LSB last):

[0182] D2 D1 D0 Device Status 1 1 1 Not attached to bus or PLL / DLL not locked 1 1 0 Device Existence 1 0 1 Device not ready 1 0 0 Device 3-bit CRC error 0 1 1 Device 8-bit CRC error 0 1 0 Device 24-bit CRC error 0 0 1 IRQ 1 (e.g., bus conflict) 0 0 0 IRQ 2

[0183] If the device ID number is 7, this will perform a status read operation where all devices attached to the bus (except the master) will return their status. The three bits returned from each device are as follows (MSB returned first, LSB last):

[0184] Devices 0-6 can respond in corresponding AG fields with relevant device status data (attached to the bus, IRQ level). Due to the previous value of one on the bus, negative logic (valid event is zero) will have to be used to indicate any change. Only the last 21 bits of the possible 24 are used for this operation. The device can use dynamic address allocation to obtain this 3-bit address or a fixed device address (e.g., pin programming). If dynamic address allocation is used, the device can use address zero as the initial value. If the master sets the ID to zero during reading, it will indicate reading a 24-bit CRC value from the last accessed bulk transfer port. This means that if the device status is being read, the first opcode will be "C" and the second opcode will not be driven.

[0185] Various status flags are provided to return status from all devices attached to the bus, and the status flags include confirmation flags and attention flags. The confirmation flag confirms a successful transaction (e.g., a read or write confirmed by a three-bit CRC value). In order to avoid possible bus conflicts, this has been defined as an effective logic low signal when multiple devices attempt to drive the bus with different values. If a device requests attention, it should drive the time slot to low, otherwise it should not drive any value during the time slot. Since this is a shared bit, all devices can respond to the time slot. The attention flag (e.g., AT) sends a request for attention from any device attached to the bus. In order to avoid possible bus conflicts, this has been defined as an effective logic low signal when multiple devices attempt to drive the bus with different values. If a device requests attention, it should drive the time slot to low, otherwise it should not drive any value during the time slot.

[0186] To avoid a single error causing a block transfer operation, the block transfer will be fully defined in the previous frame. By changing the number of command bits per row, it is possible to transfer large amounts of data to and from registers very quickly, for example, for DSP program uploads. A block transfer will only occur if a column is allocated for the operation, which occurs by writing to the register that defines the start of the block transfer. If the block transfer register is equal to or greater than the turnaround register after it in timing, the block data will not be transferred, even if the block transfer command is issued. This ensures that block data will not accidentally overwrite audio data. An example command table with the encoding of the command is set forth below:

[0187]

[0188] refer to Fig.18A , 18B18C, the block transfer operation will now be described in further detail. A 32-bit address is assigned to the slave device (not incremented on subsequent operations), as illustrated in frame 1802. Due to compact timing, the device ID and initial value in column two can be buffered because the command is completed first after these values ​​have been sent. Next, as illustrated in frame 1804, a 32-bit address is assigned to the slave device (incremented on subsequent operations). As illustrated in frame 1806, a 24-bit read is obtained using the previously assigned address (if ID=address 7, an exception in the command). As illustrated in frame 1808, the read status of all attached devices (ID=7, an exception in the arrival command). The first three bits of the 24-bit returned data are not used and can be rewritten by the last used bulk transfer port. Frame 1810 illustrates the read status from the last bulk transfer operation (an exception in the read command, ID=0)-for example, a 24-bit CRC value is read from the last used bulk transfer port. Frame 1812 illustrates the write 32 bits using the previously assigned address. The slave device will not know that this is a write command up to row 6, which means it will need to buffer the register data in rows 4, 5, and 6 in preparation for a possible write command.

[0189] Fig.18B Frame 1814 in illustrates the initiation of a 32-bit block write transfer operation. The writing of data will first start in two frames later (i.e., not in this frame nor in the next frame). Until the start of the third frame, the frame layout will be the same. Frame 1816 illustrates the transmission of write bulk data (continuous). Frame 1818 illustrates the initiation of a 32-bit block bulk read transfer operation. The reading of register data will first start in the third frame. Until the start of the third frame, the frame layout will be the same as in the previous frame (i.e., the bulk transfer has not yet started). D0-D23 is mapped to devices 0-7. Each device can have up to three bulk transfer ports. A value of 0 indicates that the port will be activated in two frames. Each device is assigned three bits (e.g., device 1 is assigned bits D3-D5, each corresponding to an internal bulk transfer port). Frame 1820 illustrates the transmission of read bulk data (continuous).

[0190] Frame synchronization algorithm

[0191] The main assumption is that the slave device will have obtained synchronization (PLL / DLL locking) after a certain period of time. The slave device can be attached to the bus at any supported speed and provide feedback about its ability. An embodiment for checking whether the slave device has obtained message synchronization before starting communication is provided. In certain embodiments, a single frame message is used. A beacon can be used to indicate the beginning of a frame and can be used for synchronization.

[0192] refer to Fig.19, an embodiment of the frame synchronization algorithm 1900 will now be described. In step 1902, the process waits for the PLL or DLL to lock with the master. In step 1904, the shift register (SHIFT 1) is set to 0xFFFF.FFFF. In step 1906, the first value from the first row is read into the second shift register. The process is repeated on 32 rows to initialize the search register. In some embodiments, each row is repeated at 3.072MHz, which can provide sampling points for PDM and high quality audio. Each frame is repeated on 32 rows, giving a frame repetition frequency of 96kHz. In some embodiments, a beacon indicates the end of a frame and is sent every three frames (at a 48kHz repetition rate).

[0193] Then, repeat the next steps on 64 frames. In step 1908, read the value from shift register 2, which should be the opposite value of the new read value (the comparison performed in step 1910). If not, then reset the position in the first shift register in step 1920, otherwise the process proceeds to step 1912 to update the second shift register, SHIFT 2. Step 1908 shifts two registers and continues to complete 32 rows. Then, repeat the process on 64 frames. By checking the alternating pattern, frame synchronization can be achieved after 64 frames. In other words, instead of checking the actual synchronization position, this algorithm clears all invalid positions until only a single valid position is left. The method guarantees that the slave device will always lock, regardless of any random data that appears in the command column. If the 32-bit register contains more than a single bit that is still set after 64 frames, repeat the method until the invalid position has been cleared.

[0194] In the illustrated embodiment, the only bit in the first shift register that is one represents the frame synchronization position. In some embodiments, if there are more than one bit with a value of one in the first shift register, then an error has occurred and the algorithm should be restarted. This is not expected to happen under normal circumstances (for random data, the probability of this happening is 2 -64 <10 -20 ).

[0195] In one implementation, all fields are oversampled using a master clock. The data row is divided into 80 time slots, and multiple time slots are used to define data on the bus. All fields can be oversampled using a master clock. In this embodiment, the default clock frequency is set to 245.76 MHz, but other frequencies can be used. For slave and master devices, the initial PLL synchronization frequency is set to 3.072 MHz, but other frequencies can be used as described herein.

[0196] The interpretation of these time slots will depend on the configuration chosen, although the individual fields will be in the same sequence. At startup, the default data format is set for the longest bus diameter (slowest speed). Fig. 16C , illustrates an example frame structure showing the different fields in each line of data. By varying the interpretation of the individual time slots, various tradeoffs between baud rate and bus diameter may be selected. The sync pattern repeats at a frequency of one for each line of data. The sync pattern is a zero to one transition.

[0197] In the illustrated embodiment, a row includes a synchronization field (0-1), a turnaround period T1 (during which the master device and any slave device are not active to allow a direction change, the time slot also includes a forward command (master control) and frame information F), a command field (CMD or reply R), a field for the transmission of audio in the forward direction (typically from master to slave), a field for the transmission of bulk register data from the master to the slave B1, a turnaround period T2 for enabling a change in signaling direction, a field for the transmission of audio in the backward direction (typically from slave to master), a field for the transmission of bulk data from the slave to the master B2, and a null value field for data alignment before the start of the next row.

[0198] When the master issues a command in the command field, it will also drive the adjacent T1 field with the same value to ensure better timing tolerance. However, when the master expects a response from the slave device, it will not drive the T1 and Cmd fields. The T2 field is not driven by any device and is allocated for data turnover. When the slave device issues a response in the command field, it will only drive the "Cmd" field, and the adjacent T1 field will be undriven and used for signal turnover. The actual distance from the slave device to the master device may be unknown. Therefore, a command will be issued that will measure the actual delay from the slave device to the master device. The actual delay will be used to optimize timing, such as optimizing the receive eye diagram.

[0199] The number of slots allocated to each of these fields may vary with the application, but in the illustrated embodiment, the total number of slots within a row is 80. The default configuration at startup indicates the number of slots at the beginning of each field. No slots are allocated for bulk transmission at startup.

[0200] Marked as T NThe time slots are used for turnaround delays. The actual data values ​​inside these time slots are undefined. Turnaround delays T1-T2 are allocated to allow data direction changes (i.e., from forward waves to backward waves, and vice versa). The number of bits transmitted from the master and slave devices can vary and should be programmed before any transmission begins. In the example shown above, the master transmits 6 bits to the slave in each row, and the slave transmits 4 bits to the master in each row. This example shows the default configuration, and the bandwidth allocated to the master and slave can be programmed to other configurations. Regardless of the data configuration, the synchronization mode remains fixed. It is possible to significantly increase bandwidth by programming the number of time slots allocated for each data bit and for command turnaround, etc., typically at the expense of higher jitter requirements and shorter maximum bus diameter. This programmability allows system designers to trade off bandwidth for higher signal integrity by deciding how much bandwidth is available for synchronization, commands, and data in each direction. In addition, by programming the conversion rate and output transmission voltage, signal integrity can be optimized while enabling the system to pass EMI requirements.

[0201] When the master issues a command in the command field, it will also drive the adjacent T1 and T2 fields with the same value to ensure better timing margin. However, when the master expects a reply from the slave device, it will not drive the T1, CMD and T2 fields. When the slave device issues a response within the command field, it will only drive the "Cmd" field, and the adjacent T1 and T2 fields will be undriven and used for signal turnaround. The actual distance from the slave device to the master device may be unknown. Therefore, a command will be issued that will measure the actual delay from the slave device to the master device. The actual delay will be used to optimize timing, such as optimizing the receive eye diagram. The master device will measure the slave delay before normal sampling. 1 The sampling is done at / 2 data cells, i.e. at the edge between two data values ​​for latency optimization, while the value for high data integrity will be in the middle of each data cell.

[0202] Oversampling twice can be achieved by using both edges of the clock. When the master issues a command in the command field, it will drive the adjacent "T" field with the same value. When the slave device issues a response within the command field, it will only drive the "R" field, and the adjacent "T" field will be undriven and used for signal turnover. If the bus diameter is short and the bus frequency is low, leakage currents can change the bus value before delay measurements can be made. In this case, it is best to include a bus keeper in the system to ensure that leakage currents will not affect any delay measurements. The output impedance of such a bus keeper will typically be in the range of 1-2kΩ.

[0203] Once the slave device is locked, the slave device should respond by informing the device status. The slave PLL circuit should be able to obtain lock with the master within 1ms, and be able to output a "PLL is locked" signal that will be used by other control circuits. In addition, the PLL should expect a logic signal ("message sync" signal) from the slave command controller. When the "message sync" signal is high and the slave PLL has determined that it is locked, it should change to narrow bandwidth mode. In narrow bandwidth mode, the time gate will only allow the output from the phase detector in a narrow time window around the synchronization edge. If any of these signals is not valid (high), the PLL should be changed to broadband phase detection, and the slave device should not be able to write to the bus (this is done so that it cannot overwrite other devices).

[0204] Audio data can travel in both directions on the link, i.e. in the forward direction from the master to the slave and in the backward direction from the slave to the master. If a slave wants to transmit data to another slave that is located further away from the master than the slave itself, it will send data in the forward direction (i.e. in the field marked "Master Audio").

[0205] Port Programming

[0206] In various embodiments, data transmission is handled through port programming. In order to enable data to be transmitted from any transmit port to any receive port, the data can be treated as a mono channel. Using this method, stereo channels and multi-channel systems will use longer programming sequences than if the channels could be treated as packets. However, this method is simpler and gives more flexibility with respect to arbitrary data transmission.

[0207] All registers associated with a port will have a bank (shadow) register. The selection of the main and shadow registers is achieved by writing to the bank select register. In order to avoid catastrophic changes to the behavior of the bus due to changes in one or more erroneous bank register values, this register has been additionally protected. In other words, in order to change the bank value, a specific 8-bit value needs to be written to a specific register to select bank number one and a different 8-bit value is written with a long Hamming distance between these two words to select bank number 0. The bank register is used to seamlessly change between two or more playback modes without encountering any glitches or distortions when changing from one scene to another. Note that in order to avoid any audio glitches, it may also be necessary to pay attention to packet delays when changing the filter configuration through appropriate buffering.

[0208] In order to be able to freely transfer any data from any transmit port to any receive port, both the transmit and receive ports can freely program the position of the data within the frame. For example, a row variable can allow the selection of the first row of data to be written, and a row increment can be used to select the interval to the next valid row. A column variable can be used to select the first column to be written, and a "last column" variable can be used to select the last column in which data is being written or read. The length of the data from a given data port can also be programmed (e.g., data word length). In some embodiments, data values ​​can extend over more than one frame, and the synchronization of the stream can be programmed. This is typically achieved by using a beacon bit to achieve the synchronization.

[0209] Bulk transfers may require the row start, row increment, column start, and column stop registers to be defined before bulk transfers are to be enabled. Bulk control bits can be used to enable and disable bulk transfer commands. Only ports that support bulk transfers will use this bit, otherwise the value is ignored. Bulk transfers may have an additional register that contains a 24-bit CRC check value of all bits transferred during the last bulk operation performed by the port. Each device may have only a single bulk transfer port operating at the same time, and will generally never have more than one bulk transfer port. The bulk control registers may include a start register (e.g., a 32-bit address), an end register (e.g., a 32-bit address) or a length register (e.g., 32 bits), a flag indicating a single or continuous transfer, and a read / write direction flag. Note that the port must first be enabled to react to the start bulk transfer command. The port enabled during a port transfer is given by a 24-bit word written by the master. During the start of a bulk transfer operation, a 24-bit word is written by the master device. Each device internally assigns these bits to the bulk transfer port (if any is implemented).

[0210] Power consumption

[0211] For short systems with modest bandwidth requirements, it is possible to significantly reduce power consumption by avoiding termination of the link. Instead, the transmitter will be terminated in series with the line impedance. To avoid any reflections from the transmitter side, the transmitter output impedance should also be relatively stable during changing output levels. This can be achieved by having multiple drivers that are activated continuously one at a time so that there will be no time zone where the output impedance will suddenly be very high. Furthermore, if there are only two devices at each end of the transmission line, then problems with reflections will disappear and high speed and low power can be achieved with the unterminated end of the link and a serially terminated transmitter.

[0212] By avoiding parallel termination, the power consumption will be reduced to 2x125μW=250μW by capacitive charging only (based on 250mV signaling, 50pF load and 40Mbit signaling). In practice, we will need to add the power consumption of the receive PLL (e.g., 250μW) and some additional bandwidth for control overhead, but a power budget of less than 1mW is unrealistic.

[0213] In various embodiments, the master should be able to wake up the slave, and the slave should be able to wake up the master. The simplest zero-power wake-up (<1μA) mode will utilize a higher signaling voltage (≈1V) to ensure good signal integrity and power-off of all other circuits. A more complex solution can maintain the same signaling voltage in all modes, but this will require more complex circuits and receiver circuits that are always turned on (100μA). The master will write to all slaves and inform that the bus stop will start in the next frame. For multi-drop buses, this will require the endpoint nodes to disable their terminals at the end of the frame. In the next frame, the master will use a weak driver (≈5kΩ) to drive D+ to Vdd. High impedance can be used to reduce any EMI during the transition. As long as D+ is VDD, it is an indication that the low power state is still valid. From a medium strength driver (≈600Ω) can be used to pull down the D+ line to signal a wake-up event. This will ensure a transition of at least 7ns (15pF load or more). The line will have to be pulled low for at least 50 μs to ensure that the master has registered the event (even if a standard 32.768 kHz low power wake-up clock is used in the master). At most 100 μs later, the slave will disable the pull-down event, and the master will start driving the bus for at least 100 μs after the event has been registered, after which the bus will restart.

[0214] synchronous

[0215] When the system is powered on, the slave device will need to establish synchronization with the master device. This is achieved in the following way: (i) the master will send out a fixed synchronization pattern (zero to one transition) in each row; (ii) the master will define all bits in the frame except for the time slots allocated for command acknowledgement and turnaround; (iii) when the slave device PLL / DLL is in lock with the master, it responds by activating the "slave in lock" bit (see Ear Link, Command section); and (iv) the master device can now program the slave device.

[0216] In one embodiment, a row includes 80 time slots regardless of the clock frequency and power mode. The synchronization pattern is repeated at a frequency of one per row. The synchronization pattern is a zero-to-one transition. Only the first zero-to-one transition in the row / cycle is used by the slave PLL / DLL. Because the command time slot follows the synchronization time slot, it means that there is only a single zero-to-one transition in the row at first, and therefore the synchronization event of the PLL will be uniquely defined. As long as the rising clock edge is used for synchronization, the slave PLL / DLL circuit should be able to obtain a lock with the master within 1ms, and can output an internal "PLL / DLL is in lock" signal that will be used by other control circuits. In addition, the PLL / DLL should expect a logic signal ("message sync" signal) from the slave command controller. When the "message sync" signal is high and the slave PLL / DLL has determined that it is in lock, it should be changed to a narrow bandwidth mode. In narrow bandwidth mode, the time gate will only allow the output from the phase detector to be in a narrow time window around the synchronization edge. If either of these signals is not active (high), the PLL / DLL should change to wideband phase detection (i.e. disable the phase / delay detector window gating logic and disable the slave output transmitter to avoid bus contention). The master should read the device status and thereby detect when the slave has acquired lock. Additionally, this message can be used to optimize the delay timing of the slave device and should be done before starting a port transfer.

[0217] After synchronization has been acquired, a window around the transition (e.g., + / - 3 time slots, half of a synchronization time slot consisting of six time slots) will be open to the PLL / DLL. The reason for using a narrow time window for the PLL is that the output from the phase detector to be integrated by the PLL should not be confused by any data communication on the bus. Therefore, it is necessary to start the PLL with a wide receiver bandwidth, that is, wide in the time domain, and later time gate the input to the PLL integrated unit. The width of the time gate window depends on the width of the time slot, where one time slot is determined by one clock period from the PLL. With an internal clock frequency of about 294.912MHz (3.072MHz x 96), this translates to about + / - 10.2ns for a system that uses 6 time slots to send one synchronization bit. This configuration will accept up to about 727 PSRMS jitter for a peak jitter of about 14 times this value (for 10 -12 bit error rate).

[0218] Where applicable, the various embodiments provided by the present disclosure can be implemented using hardware, software, or a combination of hardware and software. In addition, where applicable, without departing from the spirit of the present disclosure, the various hardware components and / or software components set forth herein can be combined into composite components comprising software, hardware, and / or both. Where applicable, without departing from the scope of the present disclosure, the various hardware components and / or software components set forth herein can be divided into subcomponents comprising software, hardware, or both. In addition, where applicable, it is contemplated that software components can be implemented as hardware components, and vice versa.

[0219] The foregoing disclosure is not intended to limit the present disclosure to the precise form disclosed or to the specific field of use. Therefore, it is contemplated that various alternative embodiments and / or modifications to the present disclosure are possible in light of the present disclosure, whether or not explicitly described or implied herein. Having described the embodiments of the present disclosure as such, one of ordinary skill in the art will recognize that changes may be made in form and detail without departing from the scope of the present disclosure. Therefore, the present disclosure is limited only by the claims.

Claims

1. A system for data communication, comprising: a master device coupled to the multi-drop bus for digital communications using a communication protocol including a plurality of time slots; as well as a first slave device coupled to the multi-drop bus and configured to transmit and receive digital communications with the master device according to the communication protocol; wherein at least one of the time slots is used to define a communication configuration for the first slave device to dynamically optimize bandwidth and / or signal integrity, and wherein intermediate nodes on the multi-drop bus are connected to the multi-drop bus with a short interruption to the traveling wave; and The physical length of the interruption to the transmission line created by the intermediate node is shorter than the shortest wavelength used for signaling.

2. The system of claim 1, wherein the multi-drop bus is a differential data bus terminated at different voltage levels on two lines, thereby facilitating low power operation and low electromagnetic interference.

3. The system of claim 2, wherein power consumption is reduced by operating at a signaling rate greater than a required signaling rate and idling the multi-drop bus for a portion of each cycle.

4. The system of claim 1, wherein the multi-drop bus is a multi-drop differential long length bus configured to receive multiple slave devices using an end transmitter.

5. The system of claim 1, wherein the multi-drop bus is further configured to synchronize two or more connected devices, including identifying time slots that do not change according to an expected fixed pattern and eliminating invalid positions for safe synchronization.

6. The system of claim 1, wherein the system is further configured to facilitate bulk data transmission independent of multi-drop bus digital communication traffic.

7. A system as described in claim 1, wherein the first slave device and the second slave device connected to the bus are timed so that the transmitted message is sent as a sequence of forward-traveling waves or backward-traveling waves, thereby achieving multi-drop high-speed bidirectional communication using terminated transmission lines.

8. The system of claim 1 , wherein delays between devices are measured by charging the bus to a known value, disabling drivers at the beginning and end of the bus so that the bus floats and is not terminated during measurement, waiting for the device to change a level on the bus, and measuring transition delays.

9. The system of claim 1, wherein the system timing is obtained from a fractional PLL provided in the master device and / or the first slave device, and the PLL is dithered by adding an output from a pseudo-random generator to a fractional adder, thereby reducing EMI.

10. The system of claim 1, wherein the pseudo-random generator is configured to scramble the output of one or more data ports, thereby achieving lower EMI by whitening the output spectrum.

11. The system of claim 1, wherein a PLL is used to obtain lock between the master device and the first slave device.

12. The system of claim 11, wherein the PLL includes a time gate that is enabled during initial lock of the PLL and that later allows only synchronization information to pass to prevent the PLL from locking onto random bus traffic.

13. The system of claim 1, wherein the DLL is used to obtain a lock between a master device and one or more slave devices.

14. The system of claim 13, wherein the DLL includes a time gate that is enabled during an initial lock of the DLL and that later allows only synchronization information to pass to prevent the DLL from locking onto random bus traffic.

15. A method for data communication, comprising: providing a master device coupled to the multi-drop bus for digital communication using a communication protocol including a plurality of time slots; coupling a first slave device to the multi-drop bus and configuring the slave device to transmit and receive digital communications with the master device according to the communication protocol; as well as defining a communication configuration for the first slave device using at least one of the time slots to dynamically optimize bandwidth and / or signal integrity, wherein intermediate nodes on the multi-drop bus are connected to the multi-drop bus with a short interruption to the traveling wave; and The physical length of the interruption to the transmission line created by the intermediate node is shorter than the shortest wavelength used for signaling.

16. The method of claim 15, further comprising operating the multi-drop data bus as a differential data bus terminated with opposite polarity, thereby facilitating low power operation and low electromagnetic interference.

17. The method of claim 15, further comprising synchronizing two or more connected devices, including identifying time slots that do not change according to an expected fixed pattern and eliminating invalid positions for secure synchronization.

18. The method of claim 15, wherein the first slave device and the second slave device connected to the bus are timed so that the transmitted message is sent as a sequence of forward-traveling waves or backward-traveling waves, thereby achieving multi-drop high-speed bidirectional communication using terminated transmission lines.

Images