Capacitor array and preparation method thereof, and storage device

Abstract

The present disclosure provides a capacitor array and a preparation method thereof, and a storage device, which belongs to the field of semiconductor technology. The preparation method of the capacitor array includes: providing a substrate including a gap region and multiple capacitor regions; forming a shape defining layer on one side of the substrate, wherein the portion of the shape defining layer in the capacitor region protrudes from the portion in the gap region; forming a first supporting material layer covering the shape defining layer; sequentially forming a first sacrificial layer and a second supporting material layer; forming a capacitor slot in the capacitor region, wherein the capacitor slot passes through the first sacrificial layer, the first supporting material layer, and the shape defining layer; forming a first electrode covering the inner surface of the capacitor slot; sequentially removing part of the second supporting material layer, all of the first sacrificial layer, part of the first supporting material layer, and all of the remaining shape defining layer; forming a dielectric layer covering the first electrode; and forming a second electrode layer covering the dielectric layer. The preparation method of the capacitor array can improve the stability of the capacitor array.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a capacitor array and a preparation method thereof, and a storage device. Background Art

[0002] In order to increase the capacitance of the columnar capacitor, the columnar capacitor often increases the height of the lower electrode to expand the contact area between the lower electrode and the dielectric layer, so that the columnar capacitor has a high aspect ratio. At the same time, a strip-shaped fixed layer can be set in the middle of the lower electrode to improve the stability of the columnar capacitor.

[0003] As the aspect ratio of the columnar capacitor continues to increase, the contact area between the strip-shaped fixed layer and the lower electrode needs to be increased accordingly, otherwise the lower electrode is easily damaged due to insufficient contact area. However, due to the limitations of etching and other processes, it is difficult to increase the contact area between the strip-shaped fixed layer and the lower electrode by increasing the thickness of the strip-shaped fixed layer.

[0004] The above information disclosed in the Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may include information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0005] The purpose of the present disclosure is to provide a capacitor array and a preparation method thereof, and a storage device to improve the stability of the capacitor array.

[0006] In order to achieve the above-mentioned invention object, the present invention adopts the following technical solutions:

[0007] According to a first aspect of the present disclosure, a method for preparing a capacitor array is provided, comprising:

[0008] providing a substrate, the substrate comprising a gap region and a plurality of capacitor regions;

[0009] forming a shape defining layer on one side of the substrate, wherein a portion of the shape defining layer in the capacitor region protrudes from a portion of the shape defining layer in the gap region;

[0010] forming a first supporting material layer covering the shape defining layer;

[0011] forming a first sacrificial layer and a second supporting material layer in sequence on a side of the first supporting material layer away from the substrate;

[0012] forming a capacitor groove in the capacitor region, wherein the capacitor groove opens at the second supporting material layer and penetrates the first sacrificial layer, the first supporting material layer and the shape defining layer;

[0013] forming a first electrode covering the inner surface of the capacitor slot;

[0014] removing a portion of the second support material layer, the entire first sacrificial layer, a portion of the first support material layer, and the entire remaining shape defining layer in sequence;

[0015] forming a dielectric layer covering the first electrode;

[0016] A second electrode layer is formed covering the dielectric layer.

[0017] In an exemplary embodiment of the present disclosure, forming a shape defining layer includes:

[0018] forming a plurality of shape defining layers in sequence, wherein a portion of any shape defining layer in the capacitor region protrudes from a portion of the shape defining layer in the gap region;

[0019] Forming a first support material layer includes:

[0020] After each layer of the shape defining layer is formed, a layer of the first supporting material is formed on the surface of the shape defining layer away from the substrate.

[0021] In an exemplary embodiment of the present disclosure, forming a capacitor groove in the capacitor region includes:

[0022] A capacitor groove is formed in the capacitor region, wherein the capacitor groove opens at the second supporting material layer and penetrates the first sacrificial layer, all the first supporting material layers and all the shape defining layers.

[0023] In an exemplary embodiment of the present disclosure, forming a shape defining layer on one side of the substrate includes:

[0024] forming a second sacrificial material layer on one side of the substrate;

[0025] forming a positioning groove in the capacitor region, wherein the positioning groove penetrates the second sacrificial material layer;

[0026] Filling the positioning groove with a third sacrificial material to form a third sacrificial layer;

[0027] The thickness of the second sacrificial material layer is reduced to form a second sacrificial layer, so that the third sacrificial layer protrudes from the second sacrificial layer.

[0028] In an exemplary embodiment of the present disclosure, forming a second sacrificial material layer on one side of the substrate includes:

[0029] A second sacrificial material layer with a thickness of 600-1500 nm is formed on one side of the substrate.

[0030] In an exemplary embodiment of the present disclosure, reducing the thickness of the second sacrificial material layer to form a second sacrificial layer includes:

[0031] A portion of the second sacrificial material layer is removed from a side of the second sacrificial material layer away from the substrate, so that the remaining second sacrificial material layer forms a second sacrificial layer; wherein the thickness of the removed second sacrificial material layer is 30-150 nm.

[0032] In an exemplary embodiment of the present disclosure, forming a third sacrificial layer includes:

[0033] The positioning groove is filled with a third sacrificial material, and the third sacrificial material is titanium nitride.

[0034] In an exemplary embodiment of the present disclosure, the method for preparing the capacitor array further includes:

[0035] forming a substrate protection layer that can be located between the substrate and the third sacrificial layer;

[0036] Forming a capacitor groove in the capacitor region includes:

[0037] The capacitor groove is formed, and the capacitor groove exposes the substrate protection layer.

[0038] In an exemplary embodiment of the present disclosure, forming a first support material layer includes:

[0039] The first supporting material layer is formed to have a thickness of 15-60 nm.

[0040] In an exemplary embodiment of the present disclosure, forming a capacitor groove in the capacitor region includes:

[0041] The capacitor slot is formed, wherein the capacitor slot is cylindrical in shape, and the height of the capacitor slot is greater than the diameter of the capacitor slot by 15.

[0042] In an exemplary embodiment of the present disclosure, the method for preparing the capacitor array further includes:

[0043] forming a third layer of support material positionable between the substrate and the shape defining layer;

[0044] Forming a capacitor groove in the capacitor region includes:

[0045] The capacitor groove is formed, and the capacitor groove also penetrates the third supporting material layer.

[0046] According to a second aspect of the present disclosure, there is provided a capacitor array, comprising:

[0047] substrate;

[0048] A support structure, the support structure comprising a first support layer and a plurality of support walls; the plurality of support walls are arranged on one side of the base and are in a straight tube shape, and the extension direction of the support walls is perpendicular to the base; the first support layer connects the outer surfaces of each of the support walls;

[0049] A plurality of first electrodes are disposed in the plurality of support walls in a one-to-one correspondence; an outer surface of any of the first electrodes is cooperatively connected with an inner surface of the corresponding support wall;

[0050] a dielectric layer covering at least a portion of the first electrode;

[0051] The second electrode layer is arranged on a side of the dielectric layer away from the first electrode.

[0052] In an exemplary embodiment of the present disclosure, one end of the supporting wall close to the substrate is connected to the first supporting layer.

[0053] In an exemplary embodiment of the present disclosure, a distance between an end of the support wall away from the substrate and a surface of the first support layer away from the substrate is 30-150 nm.

[0054] In an exemplary embodiment of the present disclosure, the support wall is in a circular ring shape in a cross section perpendicular to its extension direction.

[0055] In an exemplary embodiment of the present disclosure, the thickness of the first supporting layer is 15-60 nm.

[0056] In an exemplary embodiment of the present disclosure, the distance between the first supporting layer and the substrate is 450 nm to 1470 nm.

[0057] In an exemplary embodiment of the present disclosure, the material of the first supporting layer is the same as the material of the supporting wall.

[0058] In an exemplary embodiment of the present disclosure, the capacitor array includes multiple layers of the support structure; wherein the first support layers of each layer of the support structure are parallel to each other, and the multiple support walls of each layer of the support structure are aligned one by one; the support walls of each layer of the support structure that are aligned with each other are sleeved on the same first electrode.

[0059] In an exemplary embodiment of the present disclosure, the first electrode is a hollow cylindrical electrode having a closed end, and the closed end of the first electrode is connected to the substrate.

[0060] According to a third aspect of the present disclosure, a storage device is provided, comprising the above-mentioned capacitor array.

[0061] In the preparation method of the capacitor array provided by the present disclosure, since the part of the shape defining layer in the capacitor area protrudes from the part in the gap area, the first supporting material layer may include the following three parts: a first supporting sacrificial layer located in the capacitor area, a supporting wall covering the side of the part of the shape defining layer in the capacitor area, and a first supporting layer connecting each supporting wall. Among them, the thickness of the first supporting sacrificial layer and the first supporting layer are the same, and the height of the supporting wall along the direction perpendicular to the substrate is greater than the thickness of the first supporting layer. Since the capacitor slot is located in the capacitor area, when the first electrode is formed, only the first supporting layer and the supporting wall remain in the first supporting material layer, and the first electrode is cooperatively penetrated in the supporting wall. In this way, the outer surface of the formed first electrode is connected with the supporting wall, and each supporting wall is connected to each other through the first supporting layer. In this way, the first supporting layer fixes the first electrode through the supporting wall, which increases the fixing area of ​​the first supporting layer to the first electrode, and avoids the situation where the first electrode is damaged due to insufficient fixing area of ​​the first supporting layer to the first electrode.

[0062] In the capacitor array and storage device provided by the present disclosure, after the first electrode is prepared, the first support layer can fix the first electrode through the first support wall, thereby increasing the fixing area of ​​the first support layer to the first support wall, thereby increasing the ability of the first electrode to withstand high temperature treatment and liquid surface tension, and increasing the stability of the first electrode, thereby increasing the overall yield of the capacitor array. Therefore, the capacitor array of the present disclosure is easy to prepare, and its preparation yield is high, so its preparation cost is low and its performance is stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0064] Figure 1 It is a schematic diagram of the preparation method of the embodiment of the present disclosure.

[0065] Figure 2 It is a schematic diagram of the top view structure of the substrate of the embodiment of the present disclosure.

[0066] Figure 3 It is a schematic cross-sectional structural diagram of forming a second sacrificial material layer according to an embodiment of the present disclosure.

[0067] Figure 4 It is a schematic cross-sectional structure diagram of forming a positioning groove according to an embodiment of the present disclosure.

[0068] Figure 5 It is a schematic diagram of the cross-sectional structure of forming a substrate protective layer according to an embodiment of the present disclosure.

[0069] Figure 6 It is a schematic cross-sectional structural diagram of forming a third sacrificial material layer according to an embodiment of the present disclosure.

[0070] Figure 7 It is a schematic cross-sectional structural diagram of forming a third sacrificial material layer according to an embodiment of the present disclosure.

[0071] Figure 8 It is a schematic cross-sectional structure diagram of forming a third sacrificial layer according to an embodiment of the present disclosure.

[0072] Fig. 9 It is a schematic cross-sectional structure diagram of forming a second sacrificial layer according to an embodiment of the present disclosure.

[0073] Fig.10 It is a schematic cross-sectional structure diagram of forming a first supporting material layer according to an embodiment of the present disclosure.

[0074] Fig.11 It is a schematic cross-sectional structure diagram of forming a first sacrificial layer and a second supporting material layer according to an embodiment of the present disclosure.

[0075] Fig.12 It is a schematic cross-sectional structure diagram of an embodiment of the present disclosure in which a portion of the first sacrificial layer, a portion of the second supporting material layer and a portion of the first supporting material layer are removed.

[0076] Fig.13 It is a schematic cross-sectional structure diagram of forming a capacitor groove according to an embodiment of the present disclosure.

[0077] Fig.14 It is a schematic cross-sectional structure diagram of forming a first electrode material layer according to an embodiment of the present disclosure.

[0078] Fig.15 It is a schematic cross-sectional structure diagram of forming a first electrode according to an embodiment of the present disclosure.

[0079] Fig.16 It is a schematic diagram of the top view of the first area and the second area of ​​an embodiment of the present disclosure.

[0080] Fig.17 It is a schematic diagram of the cross-sectional structure of forming a first etching gap in an embodiment of the present disclosure.

[0081] Fig.18 It is a schematic cross-sectional structure diagram of an embodiment of the present disclosure in which the first sacrificial layer is removed.

[0082] Fig.19 It is a schematic diagram of the cross-sectional structure of forming a second etching gap in an embodiment of the present disclosure.

[0083] Fig. 20 It is a schematic cross-sectional structure diagram of removing the second sacrificial layer according to an embodiment of the present disclosure.

[0084] Fig.21 It is a schematic diagram of the three-dimensional structure of the support wall and the first electrode in the embodiment of the present disclosure.

[0085] Fig. 22 Schematic diagram of a cross-sectional structure of forming a dielectric layer according to an embodiment of the present disclosure.

[0086] Fig.23 It is a schematic cross-sectional structure diagram of forming a second electrode layer according to an embodiment of the present disclosure.

[0087] Fig.24 It is a schematic cross-sectional structure diagram of forming a filling material layer according to an embodiment of the present disclosure.

[0088] Fig.25 It is a schematic cross-sectional structural diagram of forming a fourth supporting material layer and a multi-layer shape defining layer according to an embodiment of the present disclosure.

[0089] Fig.26 It is a schematic cross-sectional structure diagram of the cooperation between the first supporting layer and the fourth supporting layer and the first electrode according to an embodiment of the present disclosure.

[0090] in, Figure 3 to Figure 15 , Figures 17 to 20 and Figure 22 to Figure 26 The cutting directions are Figure 2 and Fig.16 PP' direction in.

[0091] The main components in the figure are described as follows:

[0092] 100, substrate; 101, connecting electrode; 201, first supporting material layer; 210, first supporting layer; 211, second etching notch; 220, supporting wall; 230, first supporting sacrificial layer; 300, first electrode; 301, first electrode material layer; 400, dielectric layer; 500, second electrode layer; 610, substrate protection layer; 620, second supporting layer; 621, second supporting material layer; 622, first etching notch; 630, third supporting layer; 631, third supporting material layer; 640, fourth supporting layer Support layer; 641, fourth support material layer; 642, third etched notch; 650, filling material layer; 700, shape defining layer; 701, first surface; 702, second surface; 710, second sacrificial material layer; 711, second sacrificial layer; 720, positioning groove; 730, third sacrificial material layer; 731, third sacrificial layer; 732, cavity; 741, first sacrificial layer; 750, capacitor groove; 760, fourth sacrificial material layer; A, gap region; B, capacitor region; C, first region; D, second region. DETAILED DESCRIPTION

[0093] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure.

[0094] In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

[0095] When a structure is “on” another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is “directly” disposed on the other structure, or that the structure is “indirectly” disposed on the other structure via another structure.

[0096] The terms "a", "an", "the" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc. The terms "first" and "second" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0097] In an embodiment of the present disclosure, a method for preparing a capacitor array is provided. Figure 1 As shown, the preparation method of the capacitor array includes:

[0098] Step S110, as Figure 2 As shown, a substrate 100 is provided, and the substrate 100 includes a gap region A and a plurality of capacitor regions B;

[0099] Step S120, as Fig. 9 As shown, a shape defining layer 700 is formed on one side of the substrate 100, and a portion of the shape defining layer 700 in the capacitor region B protrudes from a portion of the shape defining layer 700 in the gap region A;

[0100] Step S130, as Fig.10 As shown, a first support material layer 201 covering the shape defining layer 700 is formed;

[0101] Step S140, as Fig.11 As shown, on the side of the first supporting material layer 201 away from the substrate 100, a first sacrificial layer 741 and a second supporting material layer 621 are sequentially formed;

[0102] Step S150, as Fig.13As shown, a capacitor groove 750 is formed in the capacitor region B, and the capacitor groove 750 opens at the second supporting material layer 621 and penetrates the first sacrificial layer 741, the first supporting material layer 201 and the shape defining layer 700;

[0103] Step S160, as Fig.14 As shown, a first electrode 300 is formed to cover the inner surface of the capacitor groove 750;

[0104] Step S170, as Fig. 20 As shown, part of the second support material layer 621, all of the first sacrificial layer 741, part of the first support material layer 201 and all of the remaining shape defining layer 700 are removed in sequence;

[0105] Step S180, as Fig. 22 As shown, a dielectric layer 400 is formed to cover the first electrode 300;

[0106] Step S190, as Fig.23 As shown, a second electrode layer 500 covering the dielectric layer 400 is formed.

[0107] In the method for preparing the capacitor array provided in the present disclosure, Fig.10 As shown, since the portion of the shape defining layer 700 in the capacitor region B protrudes from the portion in the gap region A, the first supporting material layer 201 may include the following three parts: a first supporting sacrificial layer 230 located in the capacitor region B, a supporting wall 220 covering the side of the portion of the shape defining layer 700 in the capacitor region B, and a first supporting layer 210 connecting the supporting walls 220. The first supporting sacrificial layer 230 and the first supporting layer 210 have the same thickness, and the height of the supporting wall 220 along the direction perpendicular to the substrate 100 is greater than the thickness of the first supporting layer 210. Fig.21 As shown, since the capacitor slot 750 is provided in the capacitor region B, when the first electrode 300 is formed, only the first supporting layer 210 and the supporting wall 220 remain in the first supporting material layer 201, and the first electrode 300 is cooperatively penetrated in the supporting wall 220. In this way, the outer surface of the formed first electrode 300 is cooperatively connected with the supporting wall 220, and each supporting wall 220 is connected to each other through the first supporting layer 210. In this way, the first supporting layer 210 fixes the first electrode 300 through the supporting wall 220, which increases the fixing area of ​​the first supporting layer 210 to the first electrode 300, and avoids the situation where the first electrode 300 is damaged due to insufficient fixing area of ​​the first supporting layer 210 to the first electrode 300.

[0108] The following is a detailed description of the steps of the method for preparing a capacitor array provided in the embodiment of the present disclosure in conjunction with the accompanying drawings:

[0109] In step S110, the substrate 100 may be a substrate 100 formed of glass, plastic, single crystal silicon, polycrystalline silicon or other materials, or may be a substrate 100 provided with a circuit structure. Figure 3 As shown, the substrate 100 may be a semiconductor structure provided with a driving circuit, wherein the driving circuit of the substrate 100 is provided with a connecting electrode 101 in the capacitor region B, and silicon oxide, silicon nitride or other insulating materials are provided in the gap region A. In step S150, the capacitor slot 750 may expose the connecting electrode 101 so that the connecting electrode 101 is electrically connected to the first electrode 300 of the capacitor array in a one-to-one correspondence. Optionally, the connecting electrode 101 may include a metal material such as copper, titanium, tungsten, or may include a semiconductor material such as polysilicon and doped silicon.

[0110] In step S120, Fig. 9 As shown, a shape defining layer 700 is formed; the surface of the shape defining layer 700 in the capacitor region B away from the substrate 100 is defined as a first surface 701, and the surface of the shape defining layer 700 in the gap region A away from the substrate 100 is defined as a second surface 702. The portion of the shape defining layer 700 in the capacitor region B protrudes from the portion of the shape defining layer 700 in the gap region A, and the first surface 701 is located on the side of the second surface 702 away from the substrate 100; in other words, in the capacitor region B, the shape defining layer 700 has a protrusion in the direction away from the substrate 100.

[0111] The shape defining layer 700 may be formed by a variety of different methods. Depending on the respective forming methods, the shape defining layer 700 may include one material or may include a variety of different materials. In one embodiment, the shape defining layer 700 may be formed by the following method:

[0112] Step S210, as Figure 3 As shown, a second sacrificial material layer 710 is formed on one side of the substrate 100;

[0113] Step S220, as Figure 4 As shown, a positioning groove 720 is formed in the capacitor region B, and the positioning groove 720 penetrates the second sacrificial material layer 710;

[0114] Step S230, as Figure 8 As shown, the positioning groove 720 is filled with a third sacrificial material to form a third sacrificial layer 731;

[0115] Step S240, as Fig. 9 As shown, the thickness of the second sacrificial material layer 710 is reduced to form the second sacrificial layer 711 , so that the third sacrificial layer 731 protrudes from the second sacrificial layer 711 . In this way, the second sacrificial layer 711 and the third sacrificial layer 731 constitute the shape defining layer 700 .

[0116] In step S210, the second sacrificial material layer 710 may be silicon oxide, phosphosilicate glass, borophosphosilicate glass or other materials. The thickness of the second sacrificial material layer 710 may be 600 to 1500 nm. Optionally, the second sacrificial material layer 710 may be formed by the following method: a layer of the second sacrificial material is disposed on one side of the substrate 100; and a second sacrificial material layer 710 is obtained with a flat surface and a desired thickness by planarizing by CMP (chemical mechanical polishing).

[0117] In step S220, the positioning groove 720 may be formed by etching, for example, the positioning groove 720 may be formed by dry etching. Figure 4 As shown, the positioning groove 720 may also partially extend to the base 100 .

[0118] Optionally, the positioning groove 720 can be formed by the following photolithography process: forming a photoresist protective layer on the surface of the second sacrificial material layer 710 away from the substrate 100; exposing and developing to transfer the pattern on the mask plate to the photoresist protective layer, so that the remaining photoresist protective layer covers the gap area A and exposes the capacitor area B; dry etching to form the positioning groove 720; and removing the remaining photoresist protective layer.

[0119] In step S230 , a third sacrificial material may be filled in the positioning groove 720 by a CVD (chemical vapor deposition) process to form a third sacrificial material layer 730 ; optionally, the third sacrificial material may be titanium nitride or the like.

[0120] Optionally, the positioning groove 720 is filled with the third sacrificial material, for example Figure 6 As shown, the third sacrificial material is filled into the positioning groove 720, so that the third sacrificial material layer 730 completely closes the notch of the positioning groove 720. Due to the process limitations of filling the third sacrificial material, as shown in FIG. Figure 7 As shown, there may be a cavity 732 in the positioning groove 720 that is covered by the third sacrificial material but not filled with the third sacrificial material, and the slot of the positioning groove 720 has been completely closed by the third sacrificial material. Therefore, continuing to fill the third sacrificial material cannot eliminate the cavity 732. Therefore, this situation also belongs to the situation where the positioning groove 720 is filled with the third sacrificial material.

[0121] like Figure 8 As shown, after the positioning groove 720 is filled with the third sacrificial material, the third sacrificial material layer 730 outside the positioning groove 720 can be removed by a CMP process to form a third sacrificial layer 731; wherein the surface of the third sacrificial layer 731 away from the substrate 100 is flush with the surface of the second sacrificial material layer 710 away from the substrate 100.

[0122] Optional, such as Figure 5As shown, between step S220 and step S230, a substrate protection layer 610 may be formed at the bottom of the positioning groove 720, that is, a substrate protection layer 610 that can be located between the substrate 100 and the third sacrificial layer 731 is formed; in step S150, as shown Fig.13 As shown, when the capacitor groove 750 is formed, the capacitor groove 750 exposes the substrate protection layer 610; the substrate protection layer 610 can prevent the capacitor groove 750 from extending further to the substrate 100, thereby achieving the purpose of protecting the substrate 100 (especially protecting the connecting electrode 101) and locating the bottom of the capacitor groove 750. The material of the substrate protection layer 610 can be titanium, which can be formed by CVD or PVD (physical vapor deposition) methods. It is understandable that although the substrate protection layer 610 will not be removed in step S150, its material itself may change in the capacitor array prepared in the present disclosure. For example, if the material of the connecting electrode 101 is polysilicon and the substrate protection layer 610 is titanium, the titanium in the substrate protection layer 610 can be partially or completely converted into titanium silicide during the heat treatment process of the capacitor array.

[0123] In step S240, if Fig. 9 As shown, a portion of the second sacrificial material layer 710 may be removed from a side of the second sacrificial material layer 710 away from the substrate 100, so that the remaining second sacrificial material layer 710 forms a second sacrificial layer 711. Optionally, the thickness of the removed second sacrificial material layer 710 may be 30-150 nm.

[0124] Optionally, in step S240, a portion of the second sacrificial material layer 710 may be removed by a wet etching process. For example, BHF (buffered hydrofluoric acid solution), DHF (diluted hydrofluoric acid solution), etc. may be selected as an etchant to remove a portion of the second sacrificial material layer 710. DHF may be obtained by mixing a 49% hydrofluoric acid solution with deionized water in a volume ratio of 1:2 to 1:500.

[0125] Of course, the shape defining layer 700 can also be formed by other methods. For example, in one embodiment, the shape defining layer 700 can be formed by the following method: first, a second sacrificial material layer 710 is formed on one side of the substrate 100; then, a photoresist protective layer is formed on the surface of the second sacrificial material layer 710 away from the substrate 100, and the photoresist protective layer covers the capacitor area B and exposes the gap area A; from the side of the second sacrificial material layer 710 away from the substrate 100, a portion of the second sacrificial material layer 710 is removed by etching, so that the thickness of the exposed portion of the second sacrificial material layer 710 is reduced, and the thickness of the portion of the second sacrificial material layer 710 covered by the photoresist protective layer is partially reduced; remove the photoresist protective layer, and the remaining second sacrificial material layer 710 forms the shape defining layer 700.

[0126] For another example, in another embodiment, the shape defining layer 700 may be formed by the following method: first, a second sacrificial material layer 710 is formed on one side of the substrate 100; then, a protrusion material layer is formed on a surface of the second sacrificial material layer 710 away from the substrate 100; and the protrusion material layer is patterned to form a protrusion layer, wherein the protrusion layer covers the capacitor region B and exposes the gap region A. In this way, the second sacrificial material layer 710 and the protrusion layer form the shape defining layer 700.

[0127] In step S130, Fig.10 As shown, a layer of first support material can be deposited on the surface of the shape defining layer 700 away from the substrate 100 to obtain a first support material layer 201 covering the shape defining layer 700. For example, the first support material layer 201 can be formed by LPCVD (low pressure chemical vapor deposition), ALD (atomic layer deposition) or other deposition methods. Optionally, the material of the first support material layer 201 (first support material) can be silicon nitride, silicon carbonitride (SiCN) or other materials. Optionally, the thickness of the first support material layer 201 can be 15 to 60 nm.

[0128] like Fig.10 As shown, since the shape defining layer 700 has a protrusion in the capacitor region B away from the substrate 100, the first supporting material layer 201 may include the following three parts: a first supporting sacrificial layer 230 located in the capacitor region B, a supporting wall 220 covering the side of the portion of the shape defining layer 700 in the capacitor region B, and a first supporting layer 210 connecting the supporting walls 220, wherein the supporting wall 220 connects the first supporting sacrificial layer 230 and the first supporting layer 210. The first supporting sacrificial layer 230 and the first supporting layer 210 have the same thickness.

[0129] In this disclosure, Fig.10 As shown, the thickness of the first support sacrificial layer 230 is , which is the dimension of the first support sacrificial layer 230 in a direction perpendicular to the substrate 100; the thickness of the first support layer 210 is , which is the dimension of the first support layer 210 in a direction perpendicular to the substrate 100. The support wall 220 connects the first support sacrificial layer 230 and the first support layer 210, so that the end of the support wall 220 away from the substrate 100 is flush with the surface of the first support sacrificial layer 230 away from the substrate 100, and the end of the support wall 220 close to the substrate 100 is flush with the surface of the first support layer 210 close to the substrate 100; the shape defining layer 700 has a protrusion in the capacitor region B in a direction away from the substrate 100, so that the surface of the first support layer 210 away from the substrate 100 is located between the surface of the first support sacrificial layer 230 away from the substrate 100 and the substrate 100. Therefore, it can be determined that the height of the support wall 220 in the direction perpendicular to the substrate 100 is greater than the thickness of the first support layer 210.

[0130] Optionally, the distance between one end of the support wall 220 away from the substrate 100 and the surface of the first support layer 210 away from the substrate 100 is 30 to 150 nm; in other words, the distance between one end of the support wall 220 away from the substrate 100 and the surface of the first support layer 210 away from the substrate 100 can be equal to the distance that the third sacrificial layer 731 protrudes from the second sacrificial layer 711.

[0131] In step S140, if Fig.11 As shown, a first sacrificial layer 741 covering the first supporting material layer 201 may be formed first, and then a second supporting material layer 621 covering the first sacrificial layer 741 may be formed.

[0132] The material of the first sacrificial layer 741 may be the same as or different from that of the second sacrificial layer 711, and the thickness of the first sacrificial layer 741 may be the same as or different from that of the second sacrificial layer 711. Optionally, the first sacrificial layer 741 may be formed by the following method: a layer of first sacrificial material is disposed on a side of the first supporting material layer 201 away from the substrate 100, and then planarized by a CMP process to obtain a first sacrificial layer 741 with a flat surface and a desired thickness.

[0133] The material of the second support material layer 621 may be the same as or different from the material of the first support material layer 201, and the thickness of the second support material layer 621 may be the same as or different from the thickness of the first support material layer 201. Optionally, the material of the second support material layer 621 may be silicon nitride, silicon carbonitride (SiCN) or other materials; the thickness of the second support material layer 621 may be 30 to 300 nm. The second support material layer 621 may be formed by LPCVD (low pressure chemical vapor deposition), ALD (atomic layer deposition) or other deposition methods.

[0134] In step S150, the capacitor groove 750 may be formed by etching. In one embodiment, a multi-step etching method may be used to gradually form the capacitor groove 750.

[0135] For example, Fig.12 As shown, the second support material layer 621, the first sacrificial layer 741 and the first support material layer 201 can be removed in sequence in the capacitor region B by dry etching, thereby exposing the third sacrificial layer 731; Fig.13 As shown, the third sacrificial layer 731 is then removed by wet etching to form a capacitor groove 750 that penetrates the first sacrificial layer 741 , the first supporting material layer 201 and the shape defining layer 700 .

[0136] Optionally, when etching the third sacrificial layer 731 , the temperature of the etching solution may be 100 to 250° C., and the etching solution may be a mixture of sulfuric acid and hydrogen peroxide, wherein the volume ratio of sulfuric acid to hydrogen peroxide may be 1:1 to 15:1.

[0137] Optionally, the shape of the capacitor groove 750 may be cylindrical, and the height of the capacitor groove 750: the diameter of the capacitor groove 750>15.

[0138] In step S160, the first electrode 300 covering the inner surface of the capacitor groove 750 may be formed by deposition. Fig.14 As shown, a layer of first electrode 300 material can be deposited by CVD process to form a first electrode material layer 301; Fig.15 As shown, the portion of the first electrode material layer 301 not disposed on the inner surface of the capacitor groove 750 is then removed by etching, and the remaining first electrode material layer 301 covers the inner surface of the capacitor groove 750 to serve as the first electrode 300 of the present disclosure.

[0139] Optionally, the portion of the first electrode material layer 301 not disposed on the inner surface of the capacitor groove 750 may be removed by dry etching. Optionally, the thickness of the first electrode material layer 301 may be 6-18 nm, and the material of the first electrode 300 may be titanium nitride.

[0140] In step S170, the following method may be used to sequentially remove part of the second support material layer 621, all of the first sacrificial layer 741, part of the first support material layer 201 and all of the remaining shape defining layer 700:

[0141] Step S310, as Fig.17 As shown, a portion of the second support material layer 621 is removed by dry etching process to form a plurality of first etching gaps 622 exposing the first sacrificial layer 741, and the remaining second support material layer 621 forms the second support layer 620 of the capacitor array; thus, the second support layer 620 has a plurality of first etching gaps 622;

[0142] Step S320, as Fig.18 As shown, the entire first sacrificial layer 741 is removed by a wet etching process through the first etching gap 622;

[0143] Step S330, as Fig.19 As shown, with the shielding effect of the second supporting layer 620, a dry etching process is performed through the first etching gap 622 to remove part of the first supporting material layer 201, and a plurality of second etching gaps 211 are formed on the first supporting layer 210;

[0144] Step S340, as Fig. 20As shown, the entire second sacrificial layer 711 is removed by wet etching through the first etching gap 622 and the second etching gap 211 .

[0145] So, like Fig. 20 As shown, a first supporting layer 210, a second supporting layer 620, a plurality of supporting walls 220 and a plurality of first electrodes 300 are formed on one side of the substrate 100, wherein one end of the first electrode 300 away from the substrate 100 is connected and fixed by the second supporting layer 620; Fig.21 As shown, a plurality of support walls 220 and a first support layer 210 form a support structure, wherein each first electrode 300 is arranged in each support wall 220 in a one-to-one correspondence, and the outer surface of the first electrode 300 is connected to the inner surface of the support wall 220. Each support wall 220 is connected through the first support layer 210. In this way, the first support layer 210 supports and fixes the first electrode 300 through the support wall 220, which increases the fixing area of ​​the first support layer 210 to the first electrode 300, reduces the risk of collapse and damage of the first electrode 300 due to heat treatment, liquid tension and other factors due to its high aspect ratio, can improve the stability of the first electrode 300, and improve the yield of the capacitor array.

[0146] In step S310, Fig.16 As shown in FIG. 1 (the solid circle is the capacitor region B, and the dotted circle is the second region D), a photoresist layer covering the first electrode 300 and the second supporting material layer 621 can be formed first, and then the photoresist layer is patterned by exposure and development, so that the remaining photoresist layer covers the first region C and exposes a plurality of second regions D; then dry etching is performed to remove the portion of the second supporting material layer 621 exposed to the second region D, thereby forming a plurality of first etching notches 622 on the second supporting material layer 621; and the photoresist layer is removed. Optionally, during the dry etching, a portion of the first sacrificial layer 741 can also be etched to ensure that the portion of the second supporting material layer 621 in the second region D is completely removed.

[0147] Among them, Fig.16 As shown, the first region C and the second region D may satisfy the following conditions: the first region C and the second region D are complementary, and each second region D is isolated from each other by the first region C. Any capacitor region B partially intersects with a second region D, and any second region D partially intersects with at least one capacitor region B. For example, each capacitor region B is arranged in a matrix, and each 2×2 capacitor region B serves as an opening unit. Each opening unit may be corresponding to a second region D, and the second region D partially intersects with the four capacitor regions B of the opening unit.

[0148] In step S320, the etching solution that can be used in the wet etching process includes but is not limited to BHF (hydrofluoric acid buffer), 49% HF or DHF (hydrofluoric acid dilution solution), wherein DHF can be a solution of hydrofluoric acid and deionized water mixed in a ratio of 1:1 to 1:5.

[0149] In step S340 , the conditions of the wet etching process may be the same as or different from those of step S320 .

[0150] In step S180 , the material of the dielectric layer 400 may be a high-K (dielectric constant) material, such as silicon nitride, silicon oxynitride, or the like.

[0151] In step S190, the second electrode layer 500 may be formed by a deposition method, for example, the second electrode layer 500 may be formed by a CVD process. Optionally, the material of the second electrode layer 500 may be the same as or different from the material of the first electrode 300. Optionally, the thickness of the second electrode layer 500 may be the same as or different from the thickness of the first electrode 300.

[0152] It is understandable that if Fig. 20 As shown, the first support layer 210 is provided with a plurality of second etching gaps 211, and the second support layer 620 is provided with a plurality of first etching gaps 622. Thus, in step S180, the dielectric layer 400 can also cover the outer surface of the first electrode 300; in step S190, the second electrode layer 500 can cover the dielectric layer 400 located in the gap region A. Fig. 22 As shown, the dielectric layer 400 covers the outer surface of the first electrode 300, which means that the dielectric layer 400 can be provided on one side of the outer surface of the first electrode 300, and under the action of the dielectric layer 400, there is no exposed part on the outer surface of the first electrode 300, which does not mean that the dielectric layer 400 must be in direct contact with the entire outer surface of the first electrode 300. Obviously, the dielectric layer 400, the support wall 220, and the second support layer 620 together ensure that there is no exposed area on the outer surface of the first electrode 300.

[0153] Thus, according to the method for preparing the capacitor array provided by the present disclosure, Fig.23As shown, the prepared capacitor array includes: a substrate 100, a support structure, a plurality of first electrodes 300, a dielectric layer 400 and a second electrode layer 500. Among them, the support structure includes a first support layer 210 and a plurality of support walls 220; the plurality of support walls 220 are arranged on one side of the substrate 100 and are in a straight tube shape, and the extension direction of the support walls 220 is perpendicular to the substrate 100; the first support layer 210 connects the outer surfaces of each support wall 220; the plurality of first electrodes 300 are arranged in a one-to-one correspondence in the plurality of support walls 220; the outer surface of any first electrode 300 is matched and connected with the inner surface of the corresponding support wall 220; the dielectric layer 400 covers at least part of the first electrode 300; and the second electrode layer 500 is arranged on the side of the dielectric layer 400 away from the first electrode 300.

[0154] In one embodiment, the method for preparing the capacitor array further comprises: Figure 3 As shown, a third support material layer 631 that can be located between the substrate 100 and the shape defining layer 700 is formed; step S150 includes: Fig.13 As shown, a capacitor slot 750 is formed, and the capacitor slot 750 also penetrates the third support material layer 631, so that the remaining third support material layer 631 forms a third support layer 630. In this way, the end of the first electrode 300 close to the substrate 100 can be connected to the third support layer 630, and then fixed by the third support layer 630, thereby improving the stability of the first electrode 300. Optionally, the material of the third support layer 630 can be silicon nitride, silicon carbonitride and other materials. Optionally, the thickness of the third support layer 630 is 10 to 150 nm.

[0155] In one embodiment, if Fig.26 As shown, the first electrode 300 of the capacitor array can be fixed by a plurality of stacked first support layers 210 so as to reduce the length of the unfixed first electrode 300, further improve the stability of the first electrode 300, and further improve the yield of the capacitor array.

[0156] Optionally, multiple layers of first support layers 210 and support walls 220 connected to the first support layers 210 can be formed by sequentially repeating step S120 and step S130, wherein each time step S120 and step S130 are repeated, one more layer of support structure can be generated, and each layer of support structure includes a first support layer 210 and a plurality of support walls 220 connected to the first support layer 210.

[0157] For example, in one embodiment, Fig.25As shown, multiple layers of shape defining layers 700 can be formed in sequence, and the portion of any shape defining layer 700 in the capacitor region B protrudes from the portion of the shape defining layer 700 in the gap region A; after each layer of shape defining layer 700 is formed, a first supporting material layer 201 is formed on the surface of the shape defining layer 700 away from the substrate 100. Accordingly, in step S150, a capacitor slot 750 is formed in the capacitor region B, and the capacitor slot 750 opens at the second supporting material layer 621 and penetrates the first sacrificial layer 741, all first supporting material layers 201 and all shape defining layers 700.

[0158] Of course, if Fig.26 As shown, a fourth supporting layer 640 may be provided between the substrate 100 and the second supporting layer 620. The preparation method of the fourth supporting layer 640 may include: Fig.25 As shown, before step S140, a fourth sacrificial material layer 760 is formed to cover the substrate 100, the third supporting material layer 631 or the first supporting material layer 201, wherein the surface of the fourth sacrificial material layer 760 away from the substrate 100 is a planar structure; wherein the material of the fourth sacrificial material layer 760 can be the same as that of the second sacrificial material layer 710. Then, a fourth supporting material layer 641 is formed on the surface of the fourth sacrificial material layer 760 away from the substrate 100, and the material of the fourth supporting material layer 641 can be the same as that of the first supporting material layer 201.

[0159] Thus, in step S150, the capacitor slot 750 penetrates the fourth sacrificial material layer 760 and the fourth supporting material layer 641, so that the remaining fourth sacrificial material layer 760 forms a fourth sacrificial layer, and the remaining fourth supporting layer 640 forms a fourth supporting layer 640, and the fourth supporting layer 640 is a planar structure without a supporting wall 220. In step S160, the fourth supporting layer 640 is in contact with the outer surface of the first electrode 300, so that the fourth supporting layer 640 can fix the first electrode 300, further improve the stability of the first electrode 300 and further improve the yield of the capacitor array. In step S170, as Fig.26 As shown, a third etching gap 642 may be formed on the fourth supporting layer 640 by dry etching, and the entire fourth sacrificial layer may be removed by wet etching.

[0160] Thus, the first electrode 300 can be fixed between the substrate 100 and the second supporting layer 620 by the first supporting layer 210 and the fourth supporting layer 640. Since the preparation method of the fourth supporting layer 640 is simpler than that of the first supporting layer 210, the preparation cost of the capacitor array can be reduced.

[0161] Optionally, the method for preparing the capacitor array may further include: Fig.24As shown, a filling material layer 650 is formed to cover the second electrode layer 500. Optionally, the material of the filling material layer 650 may be germanium-doped polysilicon.

[0162] It should be noted that, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in the specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc., which shall all be considered as part of the present disclosure.

[0163] The present disclosure also provides a capacitor array, such as Fig.24 As shown, the capacitor array includes a substrate 100, a support structure, a plurality of first electrodes 300, a dielectric layer 400 and a second electrode layer 500. The support structure includes a first support layer 210 and a plurality of support walls 220, wherein the plurality of support walls 220 are arranged on one side of the substrate 100 and are in a straight tube shape, and the extension direction of the support walls 220 is perpendicular to the substrate 100; the first support layer 210 connects the outer surfaces of each support wall 220; the plurality of first electrodes 300 are arranged in a one-to-one correspondence in the plurality of support walls 220; the outer surface of any first electrode 300 is matched and connected with the inner surface of the corresponding support wall 220; the dielectric layer 400 covers at least part of the first electrode 300; and the second electrode layer 500 is arranged on the side of the dielectric layer 400 away from the first electrode 300.

[0164] In the capacitor array provided by the present disclosure, after the first electrode 300 is prepared, the first support layer 210 can fix the first electrode 300 through the first support wall 220, thereby increasing the fixing area of ​​the first support layer 210 to the first support wall 220, thereby increasing the ability of the first electrode 300 to withstand high temperature treatment and liquid surface tension, and increasing the stability of the first electrode 300, thereby increasing the overall yield of the capacitor array. Therefore, the capacitor array of the present disclosure is easy to prepare, and its preparation yield is high, so its preparation cost is low and its performance is stable.

[0165] The capacitor array disclosed in the present invention can be prepared by the capacitor array preparation method described in the above capacitor array preparation method embodiment. Its principle, structure and effect have been discussed in detail in the above capacitor array preparation method embodiment and will not be repeated here.

[0166] In one embodiment, if Fig.24 As shown, one end of the support wall 220 close to the substrate 100 may be connected to the first support layer 210. Optionally, the distance between one end of the support wall 220 away from the substrate 100 and the surface of the first support layer 210 away from the substrate 100 may be 30-150 nm.

[0167] In one embodiment, the support wall 220 may be in a circular shape in a cross section perpendicular to its extending direction.

[0168] In one embodiment, the support wall 220 may be made of silicon nitride, silicon carbonitride (SiCN) or other materials.

[0169] In one embodiment, the thickness of the first supporting layer 210 may be 15-60 nm.

[0170] In one embodiment, the distance between the first supporting layer 210 and the substrate 100 is 450 nm to 1470 nm.

[0171] In one implementation, the material of the first supporting layer 210 may be silicon nitride, silicon carbonitride (SiCN) or other materials.

[0172] In one embodiment, the material of the first supporting layer 210 and the material of the supporting wall 220 are the same.

[0173] In one implementation, a first etching gap 622 may be disposed on the first supporting layer 210 .

[0174] In one embodiment, the first electrode 300 is a hollow columnar electrode having a closed end, and the closed end of the first electrode 300 is connected to the substrate 100 .

[0175] In one embodiment, the capacitor array includes a multi-layer support structure; wherein the first support layers 210 of each layer of the support structure are parallel to each other, and the multiple support walls 220 of each layer of the support structure are aligned one by one; the support walls 220 of each layer of the support structure that are aligned with each other are arranged on the same first electrode 300.

[0176] The present disclosure also provides a storage device, which includes the capacitor array described in the above capacitor array implementation. The storage device can be a static random access memory, a dynamic random access memory or other types of memory, which is not specifically limited in the present disclosure.

[0177] The capacitor array used in the storage device of the embodiment of the present disclosure is the same as the capacitor array in the above-mentioned capacitor array embodiment, and therefore has the same beneficial effects, which will not be described in detail here.

[0178] It should be understood that the present disclosure does not limit its application to the detailed structure and arrangement of the components proposed in this specification. The present disclosure can have other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to utilize the present disclosure.

Claims

1. A method for preparing a capacitor array, characterized in that: include: providing a substrate, the substrate comprising a gap region and a plurality of capacitor regions; forming a shape defining layer on one side of the substrate, wherein a portion of the shape defining layer in the capacitor region protrudes from a portion of the shape defining layer in the gap region; forming a first supporting material layer covering the shape defining layer; forming a first sacrificial layer and a second supporting material layer in sequence on a side of the first supporting material layer away from the substrate; forming a capacitor groove in the capacitor region, wherein the capacitor groove opens at the second supporting material layer and penetrates the first sacrificial layer, the first supporting material layer and the shape defining layer; forming a first electrode covering the inner surface of the capacitor slot; removing a portion of the second support material layer, the entire first sacrificial layer, a portion of the first support material layer, and the entire remaining shape defining layer in sequence; forming a dielectric layer covering the first electrode; A second electrode layer is formed covering the dielectric layer.

2. The method for preparing a capacitor array according to claim 1, characterized in that: Forming the shape defining layer comprises: forming a plurality of shape defining layers in sequence, wherein a portion of any shape defining layer in the capacitor region protrudes from a portion of the shape defining layer in the gap region; Forming a first support material layer includes: After each layer of the shape defining layer is formed, a layer of the first supporting material is formed on the surface of the shape defining layer away from the substrate.

3. The method for preparing a capacitor array according to claim 2, characterized in that: Forming a capacitor groove in the capacitor region includes: A capacitor groove is formed in the capacitor region, wherein the capacitor groove opens at the second supporting material layer and penetrates the first sacrificial layer, all the first supporting material layers and all the shape defining layers.

4. The method for preparing a capacitor array according to claim 1, characterized in that: Forming a shape defining layer on one side of the substrate comprises: forming a second sacrificial material layer on one side of the substrate; forming a positioning groove in the capacitor region, wherein the positioning groove penetrates the second sacrificial material layer; Filling the positioning groove with a third sacrificial material to form a third sacrificial layer; The thickness of the second sacrificial material layer is reduced to form a second sacrificial layer, so that the third sacrificial layer protrudes from the second sacrificial layer.

5. The method for preparing a capacitor array according to claim 4, characterized in that: Forming a second sacrificial material layer on one side of the substrate comprises: A second sacrificial material layer with a thickness of 600-1500 nm is formed on one side of the substrate.

6. The method for preparing a capacitor array according to claim 4, characterized in that: Reducing the thickness of the second sacrificial material layer to form a second sacrificial layer includes: A portion of the second sacrificial material layer is removed from a side of the second sacrificial material layer away from the substrate, so that the remaining second sacrificial material layer forms a second sacrificial layer; wherein the thickness of the removed second sacrificial material layer is 30-150 nm.

7. The method for preparing a capacitor array according to claim 4, characterized in that: Forming the third sacrificial layer includes: The positioning groove is filled with a third sacrificial material, and the third sacrificial material is titanium nitride.

8. The method for preparing a capacitor array according to claim 4, characterized in that: The method for preparing the capacitor array further includes: forming a substrate protection layer that can be located between the substrate and the third sacrificial layer; Forming a capacitor groove in the capacitor region includes: The capacitor groove is formed, and the capacitor groove exposes the substrate protection layer.

9. The method for preparing a capacitor array according to claim 1, characterized in that: Forming a first support material layer includes: The first supporting material layer is formed to have a thickness of 15-60 nm.

10. The method for preparing a capacitor array according to claim 1, characterized in that: Forming a capacitor groove in the capacitor region includes: The capacitor slot is formed, wherein the capacitor slot is cylindrical in shape, and the height of the capacitor slot is greater than the diameter of the capacitor slot by 15.

11. The method for preparing a capacitor array according to claim 1, characterized in that: The method for preparing the capacitor array further includes: forming a third layer of support material positionable between the substrate and the shape defining layer; Forming a capacitor groove in the capacitor region includes: The capacitor groove is formed, and the capacitor groove also penetrates the third supporting material layer.

12. A capacitor array, characterized in that: include: substrate; a support structure, the support structure comprising a first support layer and a plurality of support walls; The plurality of support walls are arranged on one side of the base and are in a straight tube shape, and the extension direction of the support walls is perpendicular to the base; The first supporting layer is connected to the outer surfaces of each of the supporting walls; A plurality of first electrodes are disposed in the plurality of support walls in a one-to-one correspondence; an outer surface of any of the first electrodes is cooperatively connected with an inner surface of the corresponding support wall; a dielectric layer covering at least a portion of the first electrode; The second electrode layer is arranged on a side of the dielectric layer away from the first electrode.

13. The capacitor array according to claim 12, characterized in that: One end of the support wall close to the substrate is connected to the first support layer.

14. The capacitor array according to claim 13, characterized in that: The distance between one end of the support wall away from the substrate and the surface of the first support layer away from the substrate is 30-150 nm.

15. The capacitor array according to claim 12, characterized in that: The support wall is in a circular shape in a cross section perpendicular to its extending direction.

16. The capacitor array according to claim 12, characterized in that: The thickness of the first supporting layer is 15-60 nm.

17. The capacitor array according to claim 12, characterized in that: The distance between the first supporting layer and the substrate is 450nm-1470nm.

18. The capacitor array according to claim 12, characterized in that: The material of the first supporting layer is the same as that of the supporting wall.

19. The capacitor array according to claim 12, characterized in that: The first electrode is a hollow columnar electrode with a closed end, and the closed end of the first electrode is connected to the substrate.

20. The capacitor array according to claim 12, characterized in that: The capacitor array includes multiple layers of the support structure; wherein the first support layers of each layer of the support structure are parallel to each other, and the multiple support walls of each layer of the support structure are aligned one by one; the support walls of each layer of the support structure that are aligned with each other are sleeved on the same first electrode.

21. A storage device, characterized in that: A capacitor array comprising any one of claims 12 to 20.

Images