Integrated circuit, capacitor array of integrated circuit, and method for manufacturing integrated circuit

Abstract

The present application relates to an integrated circuit, an array of capacitors for an integrated circuit, and a method for manufacturing the integrated circuit. The integrated circuit includes a plurality of features arranged horizontally in a two-dimensional (2D) grid. The 2D grid includes a parallelogram unit cell having four grid points and four straight sides between pairs of the four grid points. The parallelogram unit cell has a straight diagonal line spanning between two diagonally opposite grid points among the four grid points. The straight diagonal line is longer than each of the four straight sides. Each feature is located at one of the four grid points and occupies a horizontally elongated maximum horizontal area along a direction horizontally angled relative to each of the four straight sides. Other embodiments are also disclosed, including method embodiments.

Description

Technical Field

[0001] Embodiments disclosed herein relate to integrated circuits, capacitor arrays of integrated circuits, and methods for fabricating integrated circuits. Background Art

[0002] Memory is a type of integrated circuit used to store data in computer systems. Memory can be fabricated in one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which may also be called bit lines, data lines, or sense lines) and access lines (which may also be called word lines). Digit lines conductively interconnect memory cells along the columns of the array, and word lines conductively interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by the combination of digit lines and word lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time without power. Non-volatile memory is typically designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of milliseconds or less. Regardless, the memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered to be "0" or "1." In other systems, at least some individual memory cells can be configured to store information at more than two levels or states.

[0004] Field-effect transistors are a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconducting channel region between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current flow through the channel region is largely blocked. Field-effect transistors may also include additional structures, such as a reversibly programmable charge storage region as part of the gate structure between the gate insulator and the conductive gate.

[0005] Capacitors are another type of electronic component that can be used in memory cells. A capacitor has two electrical conductors separated by an electrically insulating material. Energy, such as an electric field, can be stored electrostatically within such a material. Depending on the composition of the insulating material, the stored field will be either volatile or non-volatile. For example, a capacitor insulator material consisting solely of SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor, which has a ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarization states and can thus comprise the programmable material of a capacitor and / or memory cell. The polarization state of a ferroelectric material can be changed by applying a suitable programming voltage and remains (at least for a certain period of time) after the programming voltage is removed. Each polarization state has a different capacitance for storing charge, which is ideally used for writing (i.e., storing) and reading a memory state, and the polarization state is not reversed until it is desired to do so. Less undesirably, in certain memories having ferroelectric capacitors, the act of reading a memory state can reverse the polarization. Thus, after the polarization state is determined, the memory cell is rewritten to place the memory cell in the pre-read state immediately after its determination. Regardless, due to the bi-stable nature of the ferroelectric material forming part of the capacitor, memory cells incorporating ferroelectric capacitors are ideally non-volatile. Other programmable materials can be used as capacitor insulators to render the capacitor non-volatile. Regardless, a typical goal in the manufacture of capacitors is to maximize the surface area of the capacitor electrodes to maximize the capacitance of the individual capacitors.

[0006] Of course, capacitors and transistors may also be used in integrated circuits other than memory circuits. Summary of the Invention

[0007] In one aspect, the present application provides an integrated circuit comprising: a plurality of features arranged horizontally in a two-dimensional (2D) grid; the 2D grid comprising a parallelogram unit cell having four grid points and four linear sides between pairs of the four grid points, the parallelogram unit cell having a linear diagonal line spanning between two diagonally opposite grid points among the four grid points, the linear diagonal line being longer than each of the four linear sides; and each feature being located at one of the four grid points and occupying a horizontally elongated maximum horizontal area along a direction horizontally angled relative to each of the four linear sides.

[0008] In another aspect, the present application provides an array of capacitors for an integrated circuit, comprising: lower capacitor electrodes horizontally arranged in a two-dimensional (2D) grid, the 2D grid comprising: a parallelogram unit cell having four grid points and four straight sides between pairs of the four grid points, the parallelogram unit cell having a straight diagonal between two diagonally opposite grid points of the four grid points, the straight diagonal being longer than each of the four straight sides; and the lower capacitor electrodes are each located at one of the four grid points and respectively occupy a horizontally elongated maximum horizontal area along a direction horizontally angled relative to each of the four straight sides; a capacitor insulator on top of the lower capacitor electrode; and at least one upper capacitor electrode on top of the capacitor insulator.

[0009] In another aspect, the present application provides a method for fabricating an integrated circuit, comprising: forming a masking material over a target material; forming a plurality of mask openings into at least an outermost portion of the masking material, the mask openings being horizontally arranged into a two-dimensional (2D) grid, the 2D grid comprising a parallelogram unit cell having four grid points and four straight sides between pairs of the four grid points, the parallelogram unit cell having a straight diagonal line spanning between two diagonally opposite grid points among the four grid points, the straight diagonal lines The line is longer than each of the four straight sides, the mask openings are each located at one of the four grid points and respectively occupy an outermost maximum horizontal area; some of the masking material is removed from at least one sidewall of each of the mask openings to horizontally elongate the respective mask openings along a direction horizontally angled relative to each of the four straight sides of the parallelogram unit cell; and after the removing, using the masking material as an etch mask, etching a target opening into the target material through the horizontally elongated mask opening in the masking material. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagrammatic cross-sectional view of a portion of a capacitor array according to an embodiment of the present invention, taken through Figure 2 Intercepted by line 1-1 in.

[0011] Figure 2 It passes through Figure 1 A diagrammatic cross-sectional view taken along line 2-2 in FIG.

[0012] Figure 3 It has Figure 1 and 2 A diagrammatic plan view of a two-dimensional (2D) grid of a capacitor array in FIG.

[0013] Figure 4 yes Figure 3 A magnified view of a portion of the .

[0014] Figure 5 and Figure 3 Same, with the addition of Figure 1 horizontal area of certain parts of the capacitor.

[0015] Figure 6 yes Figure 5 A magnified view of a portion of the .

[0016] Figure 7 corresponds to Figure 5 A diagrammatic plan view of a 2D grid, but Figure 5 The horizontal areas are positioned differently.

[0017] Figure 8 yes Figure 7 A magnified view of a portion of the .

[0018] Figure 9 Yes Figure 5 A diagrammatic plan view of an alternative 2D grid.

[0019] Figure 10 yes Figure 9 A magnified view of a portion of the .

[0020] Figure 11 Yes Figure 5 A diagrammatic plan view of an alternative 2D grid.

[0021] Figure 12 yes Figure 11 A magnified view of a portion of the .

[0022] Figure 13 Yes Figure 5 A diagrammatic plan view of an alternative 2D grid.

[0023] Figure 14 yes Figure 13 A magnified view of a portion of the .

[0024] Figure 15 corresponds to Figure 5 A diagrammatic plan view of a 2D grid, but Figure 5 The horizontal areas are positioned differently.

[0025] Figure 16 yes Figure 15 A magnified view of a portion of the .

[0026] Figure 17 corresponds to Figure 5 A diagrammatic plan view of a 2D grid, but Figure 5 The horizontal areas are positioned differently.

[0027] Figure 18 yes Figure 17 A magnified view of a portion of the .

[0028] Figure 19 is a diagrammatic cross-sectional view of a portion of a substrate construction during a process according to an embodiment of the present invention.

[0029] Figure 20-37 In the process of some embodiments of the present invention Figure 1 Diagrammatical sequence of cross-sections and / or enlarged views of the construction. DETAILED DESCRIPTION

[0030] Embodiments of the present invention encompass methods for manufacturing integrated circuits and integrated circuits independent of the manufacturing methods. An integrated circuit manufactured according to a method embodiment may have any of the properties described herein in the structural embodiments. Figure 1-6 An example integrated circuit according to an embodiment of the present invention is initially described. It shows a construction 10 including an array 12 of capacitors 14. Construction 10 includes a base substrate 13 having any one or more of conductive / conductive / conductive, semiconductive / semiconductive / semiconductive, or insulating / insulator / insulating (i.e., electrically herein) materials. Various materials have been vertically formed above base substrate 13. The materials may be Figure 1 and 2 13. The base substrate 13 may be provided on, around, or within the base substrate 13. For example, other partially fabricated or fully fabricated components of the integrated circuit may be provided somewhere above, around, or within the base substrate 13. Control circuitry and / or other peripheral circuitry for operating components within an array (e.g., a memory array) may also be fabricated, and such circuitry may or may not be completely or partially within the array or sub-array. Furthermore, multiple sub-arrays may be fabricated and operated independently of one another, sequentially, or in other ways. As used herein, a "sub-array" may also be considered an array.

[0031] Access device 15 Figure 21C] memory cell). However, other memory circuits and non-memory circuits are contemplated and whether the circuits are existing or yet to be developed. The example base substrate 13 is shown as including an insulating material 16 (e.g., doped and / or undoped silicon dioxide) having conductive vias 18 extending therethrough for electrically coupling the individual access devices 15 to the individual capacitors 14. An insulating material 20 (e.g., silicon nitride and / or silicon oxynitride) is shown atop the base substrate 13 and includes openings 22 extending therethrough and overlapping the respective conductive vias 18. The material 20 may have acted as an etch stop during fabrication.

[0032] The capacitors 14 each include a lower capacitor electrode 24 , a capacitor insulator 42 atop the lower capacitor electrode 24 , and at least one upper capacitor electrode 44 atop the capacitor insulator 42 . Figure 1 and 2 An example embodiment is shown in which a single upper capacitor electrode 44 is common to multiple capacitors 14 within the array 12. The lower capacitor electrode 24 and the upper capacitor electrode 44 may comprise conductive materials of the same composition or different compositions. Example capacitor insulator materials include one or more of silicon dioxide, silicon nitride, aluminum dioxide, hafnium oxide, and the like, and in one embodiment, the capacitor insulator is a ferroelectric (e.g., one or more of transition metal oxides, zirconium, zirconium oxide, niobium, niobium oxide, hafnium, hafnium oxide, lead zirconium titanate, and barium strontium titanate, and may have dopants therein including one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium, and rare earth elements).

[0033] The example integrated circuit of construction 10 may be viewed as comprising horizontally arranged in a two-dimensional (2D) grid 26 and possibly referenced Figure 3-6 Multiple features 27 are best viewed. In one embodiment, the 2D mesh is a Bravais mesh (i.e., there are no gaps or overlaps within the mesh). Each feature 27 is circuit-operable in the integrated circuit (i.e., in final construction) in one embodiment and, in one embodiment as shown, can be viewed as one of the capacitor electrodes 24, each comprising one of the capacitors 14. Any alternative existing or future-developed circuit-operable features (e.g., electronic components or portions thereof) can be used, such as conductive vias, resistors, transistor gates, etc., and such features need not be vertically elongated. Alternatively, each feature may not be circuit-operable in the integrated circuit, for example, comprising insulating material, void space, etc.

[0034] The example 2D mesh 26 includes parallelogram unit cells 25 ( Figure 3-6 ), which has four grid points 28 and four straight sides 29, 30, 31, and 32 between pairs of four grid points 28 (e.g., a simple polygon enclosing an interior region). In one embodiment and as shown, the parallelogram unit cell 25 has only four grid points 28. Figure 3 and 4 The parallelogram unit cell 25 is shown without the region 38 (see below), and Figure 5 and 6 Region 38 is shown superimposed on parallelogram unit cell 25. Parallelogram unit cell 25 has a straight diagonal line 36 that spans between two diagonally opposite grid points of four grid points 28. Straight diagonal line 36 is longer than each of the four straight sides 29, 30, 31, and 32 (i.e., considered separately). Example parallelogram unit cell 25 has another such straight diagonal line 21. In the example embodiment, each feature 27 and corresponding each lower capacitor electrode 24 is located at one of the four grid points 28 and occupies a horizontally elongated (i.e., having a maximum length greater than a maximum width) maximum horizontal area 38 (e.g., the entire interior area of a simple polygon) along a direction 40 that is horizontally angled relative to each of the four straight sides 29, 30, 31, and 32. In the context of this document, "angle" and "angled" do not include straight angles.

[0035] Figure 1-6 An embodiment is shown in which the parallelogram unit cell 25 has two straight diagonals 36, 21 that are not of equal length, and the direction 40 is along the longer of the two straight diagonals 36 and 21. Alternatively, the direction 40 may be along the shorter of the two straight diagonals 36 and 21 (not shown).

[0036] In one embodiment and as shown, direction 40 is one of: parallel to (not shown) or along (as shown) linear diagonal line 36. Figure 7 and 8An alternative embodiment configuration grid 260a is shown in FIG. Like reference numerals from the embodiments described above have been used where appropriate, with the suffix "a" indicating certain configuration differences. Feature 27a has a horizontally elongated maximum horizontal area 38a along a direction 40a that is neither parallel to nor along any linear diagonal (e.g., 21, 36). In other words, direction 40a is angled with: a) each of the four linear sides 29, 30, 31, 32, and b) all linear diagonals of the parallelogram unit cell 25. Regardless, in some embodiments as shown, the center of each maximum horizontal area 38 / 38a is at its respective one of the grid points 28. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0037] Figure 3-8 An embodiment is shown in which none of the four straight sides 29, 30, 31 or 32 in the 2D grid 26 intersects another of such four straight sides at 90°. Figure 9 and 10 Another example 2D mesh 26b is illustrated, but in this example, it is tilted (e.g., in parallelogram unit cell 25b, no straight sides intersect at 90°, the length of side 32 is equal to the length of side 30, the length of side 29b is equal to the length of side 31b, and the lengths of 31b / 29b are not equal to the lengths of 30 / 32). The same reference numerals as in the above-described embodiments have been used where appropriate, with the suffix "b" indicating certain structural differences. The lengths of straight diagonals 36b and 21b differ from the lengths of 36 and 21, respectively. The example maximum horizontal area 38b of feature 27b is elongated along direction 40b. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0038] Figure 11 and 12 An alternative embodiment 2D grid 26c of a square is shown, and Figure 13 and 14An example embodiment of a rectangular 2D grid 26d is shown. The same reference numerals as in the embodiments described above have been used where appropriate, with the suffixes "c" and "d" indicating certain construction differences. The parallelogram unit cell 25c in the 2D grid 26c has two straight diagonals 36c and 21c of equal length, and four straight sides 29c, 30c, 31c, and 32c. The example maximum horizontal area 38c of feature 27c is elongated along direction 40c. The straight diagonals 36d and 21d in the parallelogram unit cell 25d of the 2D grid 26d have different lengths relative to each other. The example parallelogram unit cell 25d has four straight sides 29d, 30c, 31d, and 32c. The example maximum horizontal area 38d of feature 27d is elongated along direction 40d. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0039] In some embodiments, the respective centers of the maximum horizontal areas do not lie on their corresponding one grid points. Figure 15 and 16 One such embodiment is shown in which the center 35 of each maximum horizontal area 38e is offset from its corresponding one of the grid points 28 in a manner perpendicular to the linear diagonal line 36. Like reference numerals from the embodiments described above have been used where appropriate, with certain constructional differences indicated by the suffix "e" or by different reference numerals. In one such embodiment and as shown, direction 40e is parallel to the linear diagonal line 36, and in one embodiment as shown, the longitudinal center of each of the maximum horizontal areas 38e is at its corresponding one of the grid points 28 (but the transverse center is adjacent to its corresponding one of the grid points 28). Any other attributes or aspects, as shown and / or described herein with respect to other embodiments, may be used.

[0040] Figure 17 and 18 An alternative embodiment is shown in which each maximum horizontal area 38f has a center 35f offset from its corresponding one of the grid points 28 along direction 40. In one embodiment and as shown, direction 40f is along straight diagonal line 36. In addition, the example maximum horizontal areas 38f are shown with their respective transverse centers at their corresponding one of the grid points 28 (but with their longitudinal centers displaced from their corresponding one of the grid points 28). The same reference numerals as in the embodiments described above have been used where appropriate, with the suffix "f" used to indicate certain construction differences. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0041] Embodiments of the present invention encompass methods for fabricating integrated circuits. Figure 19-37 Examples of such method embodiments are described.

[0042] refer to Figure 19, which shows an example pre-construction 10 of any of the configurations / lattices / etc. described above. The same reference numerals have been used for pre-constructions where appropriate. A masking material 50 is formed over a target material 52 over a base substrate 13. Some or all of such materials may be sacrificial. By way of example only, an example masking material includes an anti-reflective coating material (e.g., silicon oxynitride, such as DARC) over a hard mask material (e.g., amorphous carbon). The example target material 52 includes insulating materials 51 and 20, such as one or more of silicon nitride and doped or undoped silicon dioxide. The discussion continues by way of example only to fabricate a structure such as Figure 1-6 The capacitor array shown in , although any other attributes or aspects as shown and / or described herein with respect to other embodiments may additionally or alternatively be used.

[0043] refer to Figure 20-22 , a plurality of mask openings 54 (which may be considered features 27) are formed into at least the outermost portion 55 of the masking material 50, the example mask openings 54 extending only partially into the masking material 50 at this point in the process. In embodiments where the masking material 50 comprises a DARC over carbon, a mask (e.g., photoresist, not shown) having openings therein corresponding to the locations of the mask openings 54 can be used and the mask openings 54 etched through the DARC and stopped on the carbon, thereby forming the mask openings 54. Regardless, the example mask openings 54 are horizontally arranged into a 2D grid 26 comprising parallelogram-shaped unit cells 25 having four grid points 28 and having four straight sides 29, 30, 31, and 32 between pairs of the four grid points ( Figure 22 ). Parallelogram unit cell 25 has straight diagonal lines 36 and / or 21 that span between two diagonally opposite grid points of the four grid points and are longer than each of the four straight sides. Each mask opening 54 is located at one of the four grid points and each occupies the outermost maximum horizontal area 38. For the purposes of the following discussion, mask opening 54 can be considered to include one sidewall 56 and another sidewall 58 that is laterally opposite to one sidewall 56. Alternatively, sidewall 58 can be considered to be one sidewall, and sidewall 56 can be considered to be the other sidewall.

[0044] refer to Figure 23-25 , and in one embodiment, all sidewalls of each mask opening 54 are lined with mask material 60. An example technique for forming mask material 60 as shown is to deposit a conformal layer thereof, followed by anisotropic etching of this layer to substantially remove the layer from above the horizontal surface as shown. Mask material 60 and outermost portion 55 of masking material 50 may have different compositions relative to each other or may have the same composition relative to each other. In one embodiment, mask material 60 has a lateral thickness of at least 25 angstroms.

[0045] Some of the masking material 50 is removed from at least one sidewall 56 and / or 58 of each mask opening 54 to horizontally elongate such mask opening along a direction horizontally angled relative to each of the four linear sides 29, 30, 31, and 32 of the parallelogram unit cell 25. Ideally, such removal action includes one or both of ion beam etching and angled chemical etching. More ideally, such removal action of some of the masking material 50 is from both sidewalls 56 and 58, in one embodiment, such removal actions occurring at different times and in another embodiment occurring simultaneously.

[0046] refer to Figures 26-28 , the mask material 60 is removed from over at least one sidewall 56, 58 of each mask opening 54 (as shown, both sidewalls 56, 58). By way of example, this can occur by ion beam etching and / or angled chemical etching as described above. This is followed by, again by way of example, removing the mask material 60 from over at least one sidewall 56, 58 of each mask opening 54 (as shown, both sidewalls 56, 58). Figures 26-28 The masking material 50 is then removed (ie, sidewalls 56 and 58 are not viewable in any of the parallelogram-shaped unit cells 25) to horizontally elongate each mask opening 54 along a direction 40 that is horizontally angled relative to each of the four linear sides 29, 30, 31, and 32 of the parallelogram-shaped unit cell 25. Example ion beam etching includes directing an ion beam (illustrated by arrow 45) toward at least one of the sidewalls 56, 58 at an angle from the vertical relative to a global average outermost surface 57 of the masking material 50 (e.g., regardless of whether it is planar). Alternatively or in addition, examples of such removal actions include angled chemical etching directed toward at least one of the sidewalls at an angle from the vertical relative to the global average outermost surface 57 of the masking material 50. Regardless, any suitable angle from the vertical can be used, with smaller angles from the vertical being most likely used for mask openings 54 with high or higher aspect ratios, and larger angles from the vertical being used for mask openings 54 with small or lower aspect ratios.

[0047] Thus, and in one embodiment, the act of removing some of masking material 50 from at least one of sidewalls 56 and 58 may at least primarily (i.e., up to and including 100%) comprise chemical etching (e.g., angled chemical etching) that is selective relative to the remaining portion of masking material 60 within each mask opening 54. In another embodiment, the act of removing some of masking material 50 from at least one of sidewalls 56 and 58 may be at least primarily (i.e., up to and including 100%) by non-chemically physically removing (e.g., ion beam etching) masking material 50 from at least one sidewall. Ion beam etching may require removal from two laterally opposing sidewalls at different times, while angled chemical etching may enable simultaneous removal from both laterally opposing sidewalls. Figures 26-28 An example embodiment is shown in which masking material 60 is removed from over both sidewalls 58 and 60 before removing masking material 50 from respective sidewalls 58 and 60 .

[0048] Figures 35-37 An example alternative embodiment is shown in which the masking material openings are elongated and no masking material 60 is used (not shown). Like reference numerals from the above described embodiments have been used where appropriate, with the suffix "h" indicating certain construction differences. Figures 35-37 Shown relative to Figure 20-22 The process occurs, for example, by directing ion beam 45 toward at least one sidewall 56 or 58 (both as shown) at an angle from vertical relative to a global average outermost surface 57 of masking material 50. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0049] In any event, after removing some of the masking material 50 from at least one sidewall 56 and / or 58 of each mask opening 54 to horizontally elongate such mask opening, the masking material 50 serves as an etch mask while etching target openings into the target material 52 through the horizontally elongated mask openings 54 in the masking material 50. Figure 29 and 30 The process is shown wherein all remaining portions (not shown) of the mask material 60 are removed (eg, by etching) from the mask openings 54, and thereafter as shown in FIG. Figure 31 An example embodiment of etching a target opening 64 into the target material 52 is shown in FIG.

[0050] Figures 32-34 An alternative embodiment construction 10g is shown. Like reference numerals from the above described embodiments have been used where appropriate, with the suffix "g" indicating certain construction differences. Figures 32-34 In the mask material 60, some (such as Figure 26 、 2832) is above at least one of the sidewalls (other than sidewalls 56 and 58) of each mask opening 54, target opening 64g is etched into target material 52. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0051] It can then be processed, for example, to produce Figure 1-6 For example, masking material 50 may be removed, followed by forming lower capacitor electrode 24 in target opening 64 / 64g, followed by removing all target material 52, and then depositing material for capacitor insulator 42 and upper capacitor electrode 44. Regardless, in one embodiment, the conductive material is formed within the target opening, and in one embodiment, the target opening is at least primarily (i.e., up to and including 100%) filled by volume with insulating material.

[0052] The above-described processing or construction can be viewed with respect to an array of components formed as or within a single stack or stack of such components, the stack or stack being above or as part of an underlying base substrate (although a single stack / stack may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed anywhere as part of the final construction, and in some embodiments may be below the array (e.g., CMOS below the array). Regardless, one or more additional such stacks / stacks may be provided or fabricated above and / or below the stacks / stacks shown in the figures or described above. Furthermore, the arrays of components in different stacks / stacks may be the same or different relative to each other. Intervening structures may be provided between vertically adjacent stacks / stacks (e.g., additional circuitry and / or dielectric layers). Furthermore, different stacks / stacks may be electrically coupled relative to each other. Multiple stacks / stacks may be fabricated separately and sequentially (e.g., one on top of another), or two or more stacks / stacks may be fabricated substantially simultaneously.

[0053] The assemblies and structures discussed above can be used in integrated circuits / circuits and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic systems can be, for example, any of a wide range of systems including cameras, wireless devices, displays, chipsets, set-top boxes, gaming, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0054] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "above", "bottom", "above", "below", "below", "under", "upward", and "downward" generally refer to a vertical direction. "Horizontal" refers to a general direction along the surface of the main substrate (i.e., within 10 degrees) and can be relative to the substrate being processed during manufacturing, and vertical is a direction generally perpendicular thereto. Reference to "exactly horizontal" refers to a direction along the surface of the main substrate (i.e., not forming a degree with the surface) and can be referenced to when processing the substrate during manufacturing. Furthermore, as used herein, "vertical" and "horizontal" are generally perpendicular directions relative to each other and have nothing to do with the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to a direction that deviates from exactly horizontal by at least 45°. Furthermore, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending", etc., relative to a field effect transistor, are references to the orientation of the channel length of the transistor, along which current flows between the source / drain regions during operation. For bipolar junction transistors, "vertically extending," "vertically extending," "horizontally extending," "horizontally extending," etc., are references to the orientation of the substrate length along which current flows between the emitter and the collector during operation. In some embodiments, any vertically extending component, feature, and / or region extends vertically or within 10° of vertical.

[0055] Furthermore, "directly above," "directly below," and "directly beneath" require at least some lateral overlap (i.e., horizontally) of the two stated areas / materials / components relative to each other. Furthermore, the use of "above" without a preceding "directly" requires only that some portion of the stated area / material / component that is above another stated area / material / component is vertically outward from the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components). Similarly, the use of "below" and "beneath" without a preceding "directly" requires only that some portion of the stated area / material / component that is below / beneath another stated area / material / component is vertically inward from the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components).

[0056] Any of the materials, regions, and structures described herein may be uniform or non-uniform, and in any case may be continuous or discontinuous over any overlying material. When one or more example compositions are provided for any material, the material may comprise, consist essentially of, or consist of the one or more compositions. Furthermore, unless otherwise indicated, each material may be formed using any suitable current or future developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0057] In addition, "thickness" (preceded by a non-directional adjective) used alone is defined as the average straight-line distance perpendicularly through a given material or region from the closest surface of an adjacent material or adjacent region having a different composition. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If a variable thickness is present, then unless otherwise indicated, the thickness refers to the average thickness, and such a material or region will have a minimum thickness and a maximum thickness due to its variable thickness. As used herein, "different composition" only requires that those portions of the two stated materials or regions that can directly abut each other are chemically and / or physically different, for example, when such materials or regions are not uniform. If the two stated materials or regions do not directly abut each other, then when such materials or regions are not uniform, "different composition" only requires that those portions of the two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, a material, region, or structure is "directly abutting" another material, region, or structure when the stated materials, regions, or structures are in at least some physical contact with each other. In contrast, "over," "on," "adjacent," "along," and "against" without being preceded by "directly" encompass "directly against" as well as configurations in which intervening materials, regions, or structures result in no physical, touching contact of the stated materials, regions, or structures relative to one another.

[0058] As used herein, regions / materials / components are "electrically coupled" relative to one another if, during normal operation, electrical current can flow continuously from one region / material / component to another, primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between and electrically coupled to the region-material-component. In contrast, when regions-material-components are referred to as "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled regions-material-components.

[0059] The components of any of the conductive / conductor / conductive materials herein may be metallic materials and / or conductive-doped semiconductive / semiconductive / semiconductive materials. "Metallic material" refers to any one or combination of elemental metals, mixtures or alloys of two or more elemental metals, and any one or more conductive metal compounds.

[0060] As used herein, "selective" with respect to etching, etching, removing, removing, depositing, forming, and / or formed, is such that one stated material acts relative to another stated material in a ratio of at least 2: 1 by volume. Additionally, selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material relative to another stated material or materials for at least the first 75 angstroms at a ratio of at least 2: 1 by volume.

[0061] Unless otherwise indicated, the use of "or" herein includes either or both.

[0062] in conclusion

[0063] In some embodiments, an integrated circuit includes a plurality of features arranged horizontally in a two-dimensional (2D) grid. The 2D grid includes a parallelogram unit cell having four grid points and four straight sides between pairs of the four grid points. The parallelogram unit cell has a straight diagonal line spanning between two diagonally opposite grid points among the four grid points. The straight diagonal line is longer than each of the four straight sides. Each feature is located at one of the four grid points and occupies a horizontally elongated maximum horizontal area along a direction horizontally angled relative to each of the four straight sides.

[0064] In some embodiments, an array of capacitors includes lower capacitor electrodes arranged horizontally in a two-dimensional (2D) grid. The 2D grid includes a parallelogram unit cell having four grid points and four straight sides between pairs of the four grid points. The parallelogram unit cell has a straight diagonal between two diagonally opposite grid points of the four grid points. The straight diagonal is longer than each of the four straight sides. The lower capacitor electrodes are each at one of the four grid points and occupy a horizontally elongated maximum horizontal area along a direction horizontally angled relative to each of the four straight sides. A capacitor insulator is on top of the lower capacitor electrode, and at least one upper capacitor electrode is on top of the capacitor insulator.

[0065] In some embodiments, a method for manufacturing an integrated circuit includes forming a masking material over a target material. A plurality of mask openings are formed into at least an outermost portion of the masking material. The mask openings are arranged horizontally in a two-dimensional (2D) grid. The 2D grid includes a parallelogram unit cell having four grid points and four straight sides between pairs of the four grid points. The parallelogram unit cell has a straight diagonal line spanning between two diagonally opposite grid points among the four grid points. The straight diagonal line is longer than each of the four straight sides. The mask openings are each located at one of the four grid points and each occupy an outermost maximum horizontal area. Some of the masking material is removed from at least one sidewall of each mask opening to horizontally elongate each mask opening along a direction horizontally angled relative to each of the four straight sides of the parallelogram unit cell. After the removal, a target opening is etched into the target material through the horizontally elongated mask openings in the masking material using the masking material as an etch mask.

[0066] As specified, the subject matter disclosed herein has been described in language more or less specific with respect to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes example embodiments. Accordingly, the claims are to be given the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated circuit comprising: Multiple features arranged horizontally into a 2D grid; The 2D grid includes a parallelogram unit cell having four grid points and four linear sides between pairs of the four grid points, the parallelogram unit cell having a linear diagonal line spanning between two diagonally opposite ones of the four grid points, the linear diagonal line being longer than each of the four linear sides; and Each feature included in the plurality of features has a vertical height and is disposed at one of the grid points included in the four grid points, a horizontal cross-section of each of the respective features having a maximum horizontal area, the maximum horizontal area having an enclosing periphery horizontally elongated along a direction horizontally angled relative to each of the four straight sides, each of the respective features included in the plurality of features having a center point of the maximum horizontal area, the enclosing periphery having an outer peripheral shape, the outer peripheral shape including a circular central area and opposing extension areas extending outward from the circular central area along the direction, the outer peripheral shape extending the entire vertical height of the feature. 2 . The integrated circuit according to claim 1 , wherein the direction is parallel to or along a diagonal line of the straight line.

3. The integrated circuit of claim 1 , wherein the direction is angled with: a) each of the four straight sides, and b) all straight diagonals of the parallelogram unit cell. 4 . The integrated circuit of claim 1 , wherein the straight diagonal line is a longer straight diagonal line, and the parallelogram unit cell includes a shorter straight diagonal line spanning between two diagonally opposite grid points among the four grid points. 5 . The integrated circuit of claim 1 , wherein a lateral center of each of the maximum horizontal areas is located at one of the four grid points. 6 . The integrated circuit of claim 1 , wherein a longitudinal center of each of the maximum horizontal areas is located at one of the four grid points. 7 . The integrated circuit of claim 1 , wherein the center of each of the maximum horizontal areas is located at one of the four grid points. 8 . The integrated circuit of claim 1 , wherein a center of each of the maximum horizontal areas does not lie on one of the four grid points.

9. The integrated circuit of claim 1, wherein each of the features included in the plurality of features is circuit-operable in the integrated circuit.

10. The integrated circuit of claim 9, wherein the individual features included in the plurality of features comprise capacitor electrodes of capacitors.

11. The integrated circuit of claim 1, wherein the plurality of features comprises each of the features that is not circuit-operable in the integrated circuit.

12. The integrated circuit of claim 1, wherein the 2D grid is a Bravais grid.

13. A method for manufacturing an integrated circuit, comprising: forming a masking material over the target material; forming a plurality of mask openings into at least an outermost portion of the masking material, the plurality of mask openings being horizontally arranged into a two-dimensional (2D) grid, the 2D grid including parallelogram unit cells having four grid points and four linear sides between pairs of the four grid points, the parallelogram unit cell having a linear diagonal line spanning between two diagonally opposite grid points of the four grid points, the linear diagonal line being longer than each of the four linear sides, the plurality of mask openings including respective mask openings located at one of the four grid points and each occupying an outermost maximum horizontal area; removing some of the masking material from at least one sidewall of each mask opening included in the plurality of mask openings to horizontally elongate the respective mask opening along a direction horizontally angled relative to each of the four linear sides of the parallelogram unit cell; and Following the removing, target openings are simultaneously etched into the target material through horizontally elongated mask openings in the masking material using the masking material as an etch mask. The method of claim 13 , wherein the plurality of mask openings extend only partially into the masking material at least prior to the removing.

15. The method of claim 13, wherein the removing comprises directing an ion beam toward the at least one sidewall at an angle from vertical relative to a global average outermost surface of the masking material.

16. The method of claim 15, wherein the removing is performed at least primarily by chemically etching the masking material from the at least one sidewall.

17. The method of claim 15, wherein the removing is performed at least primarily by non-chemically physically removing the masking material from the at least one sidewall.

18. The method of claim 13, wherein the removing comprises at least primarily angled chemical etching directed toward the at least one sidewall at an angle from vertical relative to a global average outermost surface of the masking material.

19. The method of claim 13, wherein the removing some of the masking material is performed from one sidewall of the respective mask opening and from another sidewall of the respective mask opening that is laterally opposite the one sidewall.

20. The method of claim 19, wherein the removing from the one sidewall and the removing from the other sidewall occur at different times.

21. The method of claim 19, wherein the removing from the one sidewall and the removing from the other sidewall occur simultaneously.

22. The method of claim 13, comprising: prior to said removing some of said masking material from said at least one sidewall of said respective mask opening, lining all sidewalls of said respective mask opening with masking material; and Prior to said removing some of said masking material from said at least one sidewall of said respective mask opening, said masking material is removed from over said at least one sidewall of said respective mask opening.

23. The method of claim 22, wherein the mask material has a lateral thickness of at least 25 angstroms.

24. The method according to claim 22, wherein removing some of the masking material from the one sidewall of each mask opening and from another sidewall of each mask opening that is laterally opposite the one sidewall; and Prior to said removing some of said masking material from said another sidewall of said respective mask opening, said masking material is removed from over said another sidewall of said respective mask opening.

25. The method of claim 22, wherein the mask material and the outermost portion of the masking material have different compositions relative to each other.

26. The method of claim 25, wherein the removing some of the masking material from the at least one sidewall of the respective mask openings at least primarily comprises chemically etching the at least one sidewall selectively relative to a remaining portion of the masking material within the respective mask openings.

27. The method of claim 26, wherein the chemical etching comprises an angled chemical etch directed toward the at least one sidewall at an angle from vertical relative to a global average outermost surface of the masking material.

28. The method of claim 22, wherein the mask material and the outermost portion of the masking material have the same composition relative to each other, and wherein removing some of the masking material from the at least one sidewall of the respective mask openings is at least primarily by non-chemically physically removing the masking material from the at least one sidewall.

29. The method of claim 28, wherein removing some of the masking material from the at least one sidewall of the respective mask openings comprises directing an ion beam toward the at least one sidewall at an angle from vertical relative to a global average outermost surface of the masking material.

30. The method of claim 22, comprising removing any remaining portions of the mask material from the plurality of mask openings before etching the target openings into the target material.

31. The method of claim 22, comprising etching the target opening into the target material while some of the mask material is above at least one of the sidewalls of the respective mask opening.

32. The method of claim 13, comprising forming a conductive material within the target opening.

33. The method of claim 13, comprising filling the target opening at least primarily by volume with an insulating material.

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