Bias circuit system and bias method

Abstract

The present application relates to a bias circuit system and a bias method. The bias circuit system includes an analog circuit and a shift circuit. The analog circuit is used to simulate a circuit structure of a processing circuit system, wherein the processing circuit system is biased by a bias signal to generate multiple output signals according to multiple input signals. The shift circuit is used to increase the potential difference between a first node and a second node in the analog circuit, wherein the first node is used to track the output common mode voltage of the output signal, and the second node is used to output the bias signal.

Description

Technical Field

[0001] The present disclosure relates to a bias circuit system, and more particularly to a bias circuit system and a bias method for providing a bias to a differential input pair circuit. Background Art

[0002] The bias circuit is a very important component for the operation of analog circuits. Through the bias voltage provided by the bias circuit, the analog circuit can be set in the correct operating region (such as the saturation region of the transistor) to perform the pre-set related operations (amplifying signals, voltage-to-current conversion, etc.). Existing bias circuits are mostly implemented as current mirror circuits. However, in situations where the bias voltage required by the analog circuit is too low or the input common-mode voltage is too high, the existing bias circuit itself may be set incorrectly and provide incorrect bias voltage, thereby causing the operation of the analog circuit to fail. Summary of the invention

[0003] In order to solve the above problems, an embodiment of the present disclosure is to provide a bias circuit system, which includes an analog circuit and a shift circuit. The analog circuit is used to simulate a circuit structure of a processing circuit system, wherein the processing circuit system is biased by a bias signal to generate multiple output signals according to multiple input signals. The shift circuit is used to increase the potential difference between a first node and a second node in the analog circuit, wherein the first node is used to track an output common mode voltage of the output signal, and the second node is used to output the bias signal.

[0004] One embodiment of the present disclosure is to provide a bias method, which includes the following operations: simulating the circuit structure of a processing circuit system through an analog circuit, wherein the processing circuit system is biased by a bias signal to generate multiple output signals according to multiple input signals; and increasing the potential difference between a first node and a second node in the analog circuit, wherein the first node is used to track the output common mode voltage of the output signal, and the second node is used to output the bias signal.

[0005] In summary, the signal processing device, bias circuit system and bias method provided in some embodiments of the present disclosure can improve the operating stability of transistors in the bias circuit by increasing the potential difference setting method, and detect the dynamic changes of the node voltage by simulating the circuit structure in the circuit to be biased, so as to improve the accuracy of the bias signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A schematic diagram of a signal processing device according to some embodiments of the present disclosure;

[0007] Figure 2 A circuit diagram of a signal processing device according to some embodiments of the present disclosure;

[0008] Figure 3 A circuit diagram of a signal processing device according to some embodiments of the present disclosure; and

[0009] Figure 4 The figure is a flow chart of a biasing method according to some embodiments of the present disclosure.

[0010] Explanation of symbols

[0011] 100: signal processing device 120: processing circuit system

[0012] 140: Bias circuit system VBN: Bias signal

[0013] VIN, VIP: input signal VON, VOP: output signal

[0014] 142: Analog Circuit 144: Shift Circuit

[0015] N1, N2: Nodes R1, R2: Resistance

[0016] T1~T3, TP: transistors VDD1~VDD3: supply voltage

[0017] 210, 220: Current source circuit IB1, IB2, IBN: Current

[0018] RC1, RC2: resistance VT2, VN1, VM3: voltage

[0019] VCM: Common mode voltage VSHIFT: Potential difference

[0020] M1~M3: Transistors T1-1~T1-2: Transistors

[0021] 400: Biasing method S410, S420: Operation

[0022] VCM_OUT: Output common mode voltage DETAILED DESCRIPTION

[0023] The following is a detailed description of the embodiments with accompanying drawings, but the embodiments provided are not intended to limit the scope of the present disclosure, and the description of the structure and operation is not intended to limit the order of their execution. Any device with equal technical effects produced by the re-combination of components is within the scope of the present disclosure. In addition, the drawings are for illustrative purposes only and are not drawn in their original size. For ease of understanding, the same or similar components in the following description will be indicated by the same symbols.

[0024] In addition, the terms “coupled” or “connected” used herein may refer to two or more elements being in direct physical or electrical contact with each other, or being in indirect physical or electrical contact with each other, or may refer to two or more elements operating or moving with each other.

[0025] In this document, the term "circuitry" may generally refer to a single system formed by one or more circuits. The term "circuit" may generally refer to an object composed of one or more transistors and / or one or more active and passive components connected in a certain manner to process signals.

[0026] Figure 1 Schematic diagram of a signal processing device 100 according to some embodiments of the present disclosure. In different embodiments, the signal processing device 100 can be applied to various types of signal processing circuits, such as current mode logic (CML) circuits, linear equalizers, LC resonant circuits, differential amplifiers, and the like.

[0027] The signal processing device 100 includes a processing circuit system 120 and a bias circuit system 140. The processing circuit system 120 is biased by a bias signal VBN and is used to generate an output signal VOP and an output signal VON according to an input signal VIN and an input signal VIP. In different applications, the processing circuit system 120 can be a part of a CML circuit, an amplifier circuit, an equalizer circuit, or an LC resonant circuit, etc., but the present disclosure is not limited to the above circuits. In some embodiments, the processing circuit system 120 can be any circuit using a differential input pair circuit.

[0028] The bias circuit system 140 is used to generate a bias signal VBN according to an input signal VIN and an input signal VIP. The bias circuit system 140 includes an analog circuit 142 and a shift circuit 144. The analog circuit 142 is used to simulate the circuit structure of the processing circuit system 120 to track the relevant variation on the processing circuit system 120 to generate the bias signal VBN. The shift circuit 144 is used to increase the potential difference between the node N1 and the node N2 in the analog circuit 142, wherein the node N1 is used to track the output end of the processing circuit system 120, and the node N2 is used to output the bias signal VBN. Through the shift circuit 144, the potential of the node N1 and the potential of the node N2 can be more accurate to provide a more accurate bias signal VBN. For detailed descriptions here, please refer to the descriptions in the subsequent paragraphs.

[0029] Reference Figure 2 , Figure 2 FIG. 1 is a circuit diagram of a signal processing device 100 according to some embodiments of the present disclosure. For ease of understanding, Figure 1 and Figure 2 Similar components in the drawings will be designated with the same reference numerals.

[0030] In some embodiments, the “circuit setting” or “circuit structure” mentioned herein may generally refer to the size setting, bias setting and connection relationship between corresponding transistors, but the present disclosure is not limited thereto.

[0031] In this example, the processing circuit system 120 includes a plurality of resistors R1-R2, a transistor M1, a transistor M2 and a transistor M3. The first end of the resistor R1 is used to receive the supply voltage VDD1, and the second end of the resistor R1 (i.e., the output end of the processing circuit system 120) is coupled to the first end (e.g., the drain) of the transistor M1 and is used to generate the output signal VOP. The second end (e.g., the source) of the transistor M1 is coupled to the first end of the transistor M3. The control end (e.g., the gate) of the transistor M1 receives the input signal VIN.

[0032] The first end of the resistor R2 is used to receive the supply voltage VDD1, and the second end of the resistor R2 (i.e., another output end of the processing circuit system 120) is coupled to the first end of the transistor M2 and is used to generate the output signal VON. The second end of the transistor M2 is coupled to the first end of the transistor M3. The control end (e.g., the gate) of the transistor M2 receives the input signal VIP. In some embodiments, the transistors M1-M2 are configured as a differential input pair circuit.

[0033] The second terminal of the transistor M3 is coupled to the ground, and the control terminal of the transistor M3 is used to receive the bias signal VBN to generate a corresponding current IBN to bias the transistors M1 - M2 .

[0034] In this example, the simulation circuit 142 includes transistors T1-T2 and a current source circuit 210. The transistors T1-T2 and the current source circuit 210 are used to simulate the circuit structure of the transistor M1 (and / or the transistor M2) and the transistor M3 to track the variation of the transistor M1 (and / or the transistor M2) and the transistor M3.

[0035] In detail, the first end of the current source circuit 210 receives the supply voltage VDD2, and the second end of the current source circuit 210 is coupled to the first end of the transistor T1 (i.e., the node N1). The current source circuit 210 is used to provide the current IB1 to the transistor T1. The first end of the transistor T1 is also coupled to the shift circuit 144. The control end of the transistor T1 is used to receive the common mode voltage VCM associated with the input signal VIP and the input signal VIN. The second end of the transistor T1 is coupled to the first end of the transistor T2. The second end of the transistor T2 is coupled to the ground. The control end of the transistor T2 is coupled to the node N2 and is used to output the bias signal VBN.

[0036] By this configuration, the voltage VN1 on the node N1 can be used to track the output common mode voltage VCM_OUT of the first ends of the transistors M1 and M2 (i.e., the output end of the processing circuit system 120), and the voltage VT2 of the first end of the transistor T2 is used to track the voltage VM3 of the first end of the transistor M3. In some embodiments, the output common mode voltage VCM_OUT can be half of the sum of the output signal VOP and the output signal VON, that is, VCM_OUT=0.5×(VOP+VON).

[0037] In some embodiments, the bias circuit system 140 further includes resistors RC1 and RC2. The first end of the resistor RC1 receives the input signal VIP, and the first end of the resistor RC2 receives the input signal VIN. The second ends of the resistors RC1 and RC2 are coupled together to generate a common mode voltage VCM associated with the input signal VIP and the input signal VIN. The above-mentioned implementation of generating the common mode voltage VCM is for example only, and the present disclosure is not limited thereto.

[0038] In some embodiments, the circuit settings of the analog circuit 142 are related to the circuit settings of the processing circuit system 120. For example, the transistor M3 is set to generate M times the current IB1 (i.e., the current IBN). Under this condition, the size (e.g., the aspect ratio) of the transistor M3 is M times the size of the transistor T2, and the sum of the size of the transistor M1 and the size of the transistor M2 is the same as M times the size of the transistor T1. In some embodiments, M can be a non-zero positive number.

[0039] The shift circuit 144 includes a transistor T3 and a current source circuit 220. In this example, the transistor T3 operates as a source follower. The first terminal of the transistor T3 receives the supply voltage VDD3, the second terminal of the transistor T3 and the current source circuit 220 are coupled to the node N2, and the control terminal of the transistor T3 is coupled to the node N1. The current source circuit 220 is coupled between the node N2 and the ground, and is used to provide a current IB2 to bias the transistor T3.

[0040] In this example, transistor T3 can provide a potential difference VSHIFT between node N1 and node N2. In this way, the voltage VN1 of node N1 can be stably higher than the bias signal VBN on node N2 by a stable voltage difference. The voltage VN1 can be expressed as: VN1=VBN+VSHIFT. The potential difference VSHIFT is the potential difference between the gate and the source of transistor T3. In some embodiments, the value of this potential difference can be adjusted by adjusting the size of transistor T3 and / or current IB2.

[0041] The above is an example of a source follower implementation, but the present disclosure is not limited thereto. In different embodiments, the shift circuit 144 can also be implemented by other circuits that generate a voltage drop, such as a diode circuit, a resistor circuit, etc.

[0042] Ideally, each of the above transistors T1-T3 and transistors M1-M3 operates in the saturation region to correctly perform the pre-set related operations. When the transistors T1-T3 and transistors M1-M3 operate in the saturation region, the voltage VN1 on the node N1 can track the output common mode voltage VCM_OUT of the output signal VOP and the output signal VON. However, in some related technologies, when the bias circuit does not use the shift circuit 144, the node of a transistor inside the bias circuit (for example, the node N1) is directly connected to the node of another transistor (for example, the node N2) to generate the required bias. In these technologies, the operating region of the transistor (for example, the transistor T1) may be mistakenly changed to the linear region, causing the operating conditions of other transistors to be wrong. For example, in some special cases (e.g., under operating conditions where the common mode voltage VCM is high and the bias signal VBN is low), if the shift circuit 144 is not provided, the voltage VN1 will be close to the voltage VT2, causing the voltage across the two ends of the transistor T1 to be low and erroneously operate in the linear region (or triode region). In this state, the bias signal VBN will be inaccurate and the transistor M3 will not be able to generate the correct current.

[0043] Compared to the above technology, in the embodiment of the present disclosure, the shift circuit 144 can increase the potential of the voltage VN1 to ensure that the transistor T1 can operate correctly in the saturation region, thereby improving the reliability of the signal processing device 100 and the accuracy of the bias signal VBN.

[0044] In some embodiments, the first end of the transistor T3 can directly receive the supply voltage VDD3. In some embodiments, the shift circuit 144 further includes a transistor TP, which is configured as a diode-connected transistor. The first end of the transistor TP receives the supply voltage VDD3, and the second end of the transistor TP and the control end are coupled to the first end of the transistor T3. The transistor TP can be used to prevent the transistor T3 from directly receiving a high voltage (i.e., the supply voltage VDD3), thereby preventing the transistor T3 from latching up. In some embodiments, the transistor TP can also be replaced by other components, such as a resistor, a capacitor, etc., but the present disclosure is not limited thereto.

[0045] Reference Figure 3 , Figure 3 FIG. 1 is a circuit diagram of a signal processing device 100 according to some embodiments of the present disclosure. For ease of understanding, Figures 1 to 3Similar components in the drawings will be designated with the same reference numerals.

[0046] Compared to Figure 2 In this example, the transistor T1 in the analog circuit 142 is replaced by a plurality of transistors T1-1 and T1-2. The setting method of the transistors T1-1 and T1-2 is used to simulate the setting method of the transistors M1 and M2 to detect the dynamic change of the voltage VM3. In some embodiments, the size of the transistor M1 is M times the size of the transistor T1-1, and the size of the transistor M2 is M times the size of the transistor T1-2.

[0047] Specifically, the first end of transistor T1-1 is coupled to node N1, the second end of transistor T1-1 is coupled to the first end of transistor T2, and the control end of transistor T1-1 receives input signal VIN. The first end of transistor T1-2 is coupled to node N1, the second end of transistor T1-2 is coupled to the first end of transistor T2, and the control end of transistor T1-2 receives input signal VIP. The voltage VN1 on node N1 can track the output common mode voltage VCM_OUT of output signal VOP and output signal VON. Since input signal VIN and input signal VIP are AC signals, voltage VM3 will change accordingly with the transient switching of input signal VIN and input signal VIP.

[0048] In this example, through the configuration of transistors T1-1 and T1-2, voltage VT2 can also change with the transient switching of input signal VIN and input signal VIP to more accurately track voltage VM3. In this way, when voltage VM3 changes, voltage VT2 will also change accordingly. In response to the change of voltage VT2, bias signal VBN will also change accordingly to ensure that current IBN can be stable.

[0049] The above embodiments are described by using N-type transistors as examples, but the present disclosure is not limited to the above embodiments. Based on the above embodiments, other embodiments of the present disclosure can also implement corresponding circuits using P-type transistors. Therefore, implementation methods of various types of transistors are within the scope of the present disclosure.

[0050] In some embodiments, the supply voltages VDD1 - VDD3 may be the same voltage. In some embodiments, the supply voltages VDD1 - VDD3 may be different voltages.

[0051] The above embodiments are described using metal oxide semiconductor field effect transistors (MOSFET) as examples, but the present disclosure is not limited to the above embodiments. Based on the above embodiments, other embodiments of the present disclosure may also implement corresponding circuits using other types of field effect transistors. Therefore, implementations of various types of field effect transistors are within the scope of the present disclosure.

[0052] Reference Figure 4 , Figure 4 FIG. 4 is a flow chart of a biasing method 400 according to some embodiments of the present disclosure.

[0053] In operation S410 , the analog circuit 142 simulates the circuit structure of the processing circuit system 120 to generate a bias signal VBN, wherein the processing circuit system 120 is biased by the bias signal VBN to generate an output signal VOP and an output signal VON according to the input signal VIP and the input signal VIN.

[0054] In operation S420 , the potential difference between the node N1 and the node N2 in the analog circuit 142 is increased by the shift circuit 144 , wherein the node N1 tracks the output common mode voltage VCM_OUT of the output signal VON and the output signal VOP, and the node N2 is used to output the bias signal VBN.

[0055] The description of the above operation S410 and operation S420 can refer to the above Figure 1 to Figure 3 The above-mentioned various operations of the bias method 400 are only examples and are not limited to the order of execution of the above-mentioned examples. Without violating the operation mode and scope of the various embodiments of the present disclosure, the various operations under the bias method 400 can be appropriately increased, replaced, omitted or performed in a different order.

[0056] In summary, the signal processing device, bias circuit system and bias method provided in some embodiments of the present disclosure can improve the operating stability of transistors in the bias circuit by increasing the potential difference setting method, and detect the dynamic changes of the node voltage by simulating the circuit structure in the circuit to be biased, so as to improve the accuracy of the bias signal.

[0057] Although the present disclosure has been disclosed in the above embodiments, it does not limit the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be based on what is defined in the claims.

Claims

1. A bias circuit system, comprising: an analog circuit for simulating a circuit structure of a processing circuit system, wherein the processing circuit system is biased by a bias signal to generate a plurality of output signals according to a plurality of input signals; and A shift circuit is used to increase a potential difference between a first node and a second node in the analog circuit. The shift circuit is connected to the first node and the second node of the analog circuit, wherein the first node is used to track an output common mode voltage of the multiple output signals, and the second node is used to output the bias signal.

2. The bias circuit system of claim 1 , wherein the processing circuit system comprises an input pair circuit and a first transistor, the input pair circuit receives the plurality of input signals and generates the plurality of output signals, the first transistor generates a first current to bias the input pair circuit according to the bias signal, and the analog circuit comprises: a second transistor coupled to the first node and used to simulate the input pair circuit, wherein a control terminal of the second transistor is used to receive a common mode voltage associated with the plurality of input signals; and A third transistor is coupled between the second transistor and the ground and is used to simulate the first transistor, wherein a control terminal of the third transistor is coupled to the second node.

3. The bias circuit system of claim 2, wherein the analog circuit further comprises: A first current source circuit is used to provide a second current to bias the second transistor and the third transistor.

4. The bias circuit system of claim 3, wherein the first current is set to be M times the second current, the size of the first transistor is M times the size of the third transistor, the sum of the sizes of the plurality of transistors in the input pair circuit is M times the size of the second transistor, and M is a non-zero positive number.

5. The bias circuit system of claim 1 , wherein the shift circuit comprises: a first transistor for providing the potential difference, wherein a first terminal of the first transistor is used to receive a supply voltage, a second terminal of the first transistor is coupled to the second node, and a control terminal of the first transistor is coupled to the first node; and A current source circuit is coupled between the second node and ground and is used to provide a current to the first transistor.

6. The bias circuit system of claim 5, wherein the shift circuit further comprises: A second transistor, wherein a first terminal of the second transistor receives the supply voltage, and a second terminal and a control terminal of the second transistor are coupled to the first terminal of the first transistor.

7. The bias circuit system of claim 1 , wherein the processing circuit system comprises an input pair circuit and a first transistor, the input pair circuit receives the plurality of input signals and generates the plurality of output signals, the first transistor generates a first current to bias the input pair circuit according to the bias signal, and the analog circuit comprises: a second transistor, wherein a first terminal of the second transistor is coupled to the first node, and a control terminal of the second transistor is used to receive a first input signal among the plurality of input signals; a third transistor, wherein a first terminal of the third transistor is coupled to the first node, a control terminal of the third transistor is used to receive a second input signal among the plurality of input signals, and the second transistor and the third transistor are used to simulate a plurality of transistors of the input pair circuit; as well as A fourth transistor is coupled between a second end of the second transistor, a second end of the third transistor and the ground, and is used to simulate the first transistor, wherein a control end of the fourth transistor is coupled to the second node.

8. A biasing method, comprising: simulating a circuit structure of a processing circuit system by an emulation circuit, wherein the processing circuit system is biased by a bias signal to generate a plurality of output signals according to a plurality of input signals; and A potential difference between a first node and a second node in the analog circuit is increased by a shift circuit, and the shift circuit is connected to the first node and the second node of the analog circuit, wherein the first node is used to track an output common mode voltage of the multiple output signals, and the second node is used to output the bias signal.

9. The bias method of claim 8, wherein the processing circuit system comprises an input pair circuit and a first transistor, the input pair circuit receives the plurality of input signals and generates the plurality of output signals, the first transistor generates a first current to bias the input pair circuit according to the bias signal, and simulating the circuit structure of the processing circuit system by the simulation circuit comprises: simulating the input pair circuit by a second transistor of the simulation circuit, wherein the second transistor is coupled to the first node and a control terminal of the second transistor is used to receive a common mode voltage associated with the plurality of input signals; and The first transistor is simulated by a third transistor of the simulation circuit, wherein the third transistor is coupled between the second transistor and the ground, and a control terminal of the third transistor is coupled to the second node.

10. The bias method of claim 8, wherein the processing circuit system comprises an input pair circuit and a first transistor, the input pair circuit receives the plurality of input signals and generates the plurality of output signals, the first transistor generates a first current to bias the input pair circuit according to the bias signal, and simulating the circuit structure of the processing circuit system by the simulation circuit comprises: A plurality of transistors of the input pair circuit are simulated by a second transistor and a third transistor of the simulation circuit, wherein a first terminal of the second transistor is coupled to the first node, a control terminal of the second transistor is used to receive a first input signal among the plurality of input signals, a first terminal of the third transistor is coupled to the first node, and a control terminal of the third transistor is used to receive a second input signal among the plurality of input signals; and The first transistor is simulated by a fourth transistor of the simulation circuit, wherein the fourth transistor is coupled between a second end of the second transistor, a second end of the third transistor and ground, and a control end of the fourth transistor is coupled to the second node.

Images