Phase-locked loop circuit and setting method thereof, and communication equipment

Abstract

The embodiment of the present invention provides a phase-locked loop circuit and a setting method thereof, and a communication device. The phase-locked loop circuit includes a phase-locked loop main circuit and a phase temperature compensation circuit. According to the phase shift generated by the phase-locked loop main circuit as the temperature changes, at least one phase delay unit of the phase temperature compensation circuit is set to be connected to the phase-locked loop main circuit, and the phase shift generated by the phase delay unit connected to the phase temperature compensation circuit as the temperature changes is used to offset the phase shift generated by the phase-locked loop main circuit as the temperature changes; thereby ensuring that the phase-locked loop circuit does not generate a phase shift or generates a phase shift within a very small range as the temperature changes during operation; when applied to multi-channel communication, since the phase-locked loop circuit of each channel does not generate a phase shift or generates a phase shift within a very small range as the temperature changes, it can be ensured that the phase difference between each channel is as small as possible at any time, thereby fundamentally meeting the synchronization requirements.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a phase-locked loop circuit and a setting method thereof, and communication equipment. Background Art

[0002] And with the development of communication technology, multi-array antenna base stations and multi-transmitting and receiving channel complete machines are the key to 4G and 5G (5 th -Generation, 5th Generation) communication technology; in 5G communication, Space Division Multiple Access (SDMA) is an important example of the application of Maximum Input Minimum Output (Massive MIMO) technology. SDMA uses beamforming technology to concentrate signal energy in a specific direction to propagate, thereby increasing spectrum utilization efficiency and reducing interference to other receivers. Beamforming has strict requirements on the phase difference of signals between multiple channels of the transceiver. For example, the phase difference between multiple channels of the sub 6G 5G base station transceiver should be less than 5°. Due to limitations such as cost and board area, one phase-locked loop circuit is generally used for one channel. Since the phase-locked loop circuit has the characteristic of phase shift as the temperature changes, the phase deviation between multiple channels increases with temperature changes. To solve this problem, in order to meet the requirement that the phase difference between multiple channels is less than the set value (e.g. 5°), the current practice is that the wireless base station system adopts a series of phase detection and adjustment measures to reduce the phase error between channels, and then align the phase of the multi-channel signal; for example, phase detection and alignment control are performed every 30 minutes. This phase detection and alignment processing method requires a large amount of system resources and generates large power consumption, and it cannot guarantee that the phase difference between multiple channels within the detection time interval is less than the set value. Therefore, how to fundamentally ensure multi-channel phase synchronization is a major technical bottleneck in base station applications. Summary of the invention

[0003] The embodiments of the present invention provide a phase-locked loop circuit and a setting method thereof, as well as a communication device, which solve the problem of how to fundamentally achieve multi-channel phase synchronization.

[0004] To solve the above technical problems, an embodiment of the present invention provides a phase-locked loop circuit, including a phase-locked loop main circuit and a phase temperature compensation circuit, wherein the phase temperature compensation circuit includes at least one phase delay unit, and at least one of the phase delay units is connected to the phase-locked loop main circuit, and the phase shift generated by the phase delay unit connected to the phase-locked loop main circuit as the temperature changes, and the phase shift generated by the phase-locked loop main circuit as the temperature changes offset each other.

[0005] To solve the above technical problems, an embodiment of the present invention further provides a phase-locked loop circuit setting method as described above, comprising:

[0006] The phase shift caused by the temperature change of the phase-locked loop main circuit is obtained by simulation;

[0007] Determining a phase delay unit control parameter according to the phase offset;

[0008] According to the control parameters of the phase delay unit, a corresponding number of the phase delay units are controlled to be connected to the phase-locked loop main circuit.

[0009] In order to solve the above technical problem, an embodiment of the present invention further provides a communication device, comprising at least one phase-locked loop circuit as described above.

[0010] Beneficial Effects

[0011] According to the phase-locked loop circuit and its setting method, and communication equipment provided by the embodiments of the present invention, the phase-locked loop circuit includes a phase-locked loop main circuit and a phase temperature compensation circuit. According to the phase shift generated by the phase-locked loop main circuit with temperature changes, at least one phase delay unit of the phase temperature compensation circuit can be set to be connected to the phase-locked loop main circuit, and the phase shift generated by the phase delay unit connected to the phase temperature compensation circuit with temperature changes is used to offset the phase shift generated by the phase-locked loop main circuit with temperature changes; thereby ensuring that the phase-locked loop circuit does not generate a phase shift or generates a phase shift within a very small range as the temperature changes during operation; when the phase-locked loop circuit is applied to a multi-channel scenario, since the phase-locked loop circuits of each channel do not generate a phase shift or generate a phase shift within a very small range as the temperature changes during operation, it can be ensured that the phase difference between each channel is as small as possible at any time, thereby fundamentally and better meeting the requirements of multi-channel communication phase synchronization; and the control operations of detecting and aligning the phases between the channels can be omitted, thereby simultaneously improving resource utilization and saving energy consumption.

[0012] Other features and corresponding beneficial effects of the present invention are described in the latter part of the specification, and it should be understood that at least part of the beneficial effects become obvious from the description in the specification of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Schematic diagram of the phase-locked loop circuit structure of the first embodiment of the present invention;

[0014] Figure 2 This is a schematic diagram of the main circuit structure of a phase-locked loop according to the first embodiment of the present invention;

[0015] Figure 3A schematic diagram of phase delay of a phase-locked loop main circuit according to the first embodiment of the present invention;

[0016] Figure 4 This is another schematic diagram of the phase-locked loop circuit structure of the first embodiment of the present invention;

[0017] Figure 5 A schematic flow chart of a method for setting a phase-locked loop circuit according to a second embodiment of the present invention;

[0018] Figure 6 Schematic diagram of the phase temperature compensation circuit structure of the second embodiment of the present invention;

[0019] Figure 7 The structure of the phase delay unit of the second embodiment of the present invention is shown in FIG. Figure 1 ;

[0020] Figure 8-1 The structure of the phase delay unit of the second embodiment of the present invention is shown in FIG. Figure 2 ;

[0021] Figure 8-2 The structure of the phase delay unit of the second embodiment of the present invention is shown in FIG. Figure 3 ;

[0022] Figure 8-3 The structure of the phase delay unit of the second embodiment of the present invention is shown in FIG. Figure 4 ;

[0023] Fig. 9 This is a schematic diagram of the structure of a phase delay unit control module according to the second embodiment of the present invention;

[0024] Fig.10 A schematic diagram of a calibration process of a phase-locked loop circuit according to a second embodiment of the present invention;

[0025] Figure 11-1 This is a schematic diagram of phase variation with temperature when not compensated according to the second embodiment of the present invention;

[0026] Figure 11-2 This is a schematic diagram of under-compensation according to the second embodiment of the present invention;

[0027] Figure 11-3 This is a schematic diagram of overcompensation according to the second embodiment of the present invention;

[0028] Figure 11-4 This is a schematic diagram of ideal compensation in Embodiment 2 of the present invention;

[0029] Fig.12 A schematic diagram comparing under-compensation and uncompensation in Embodiment 2 of the present invention;

[0030] Figure 13-1 This is a schematic diagram of the phase-locked loop circuit structure of application scenario 1 of embodiment 3 of the present invention;

[0031] Figure 13-2 Schematic diagram of K1 of the reference signal input path in application scenario 1 of embodiment 3 of the present invention;

[0032] Figure 13-3 This is a schematic diagram of K2 of the signal output path of the first application scenario of the third embodiment of the present invention;

[0033] Figure 13-4 Schematic diagram of K3 of feedback signal transmission path in application scenario 1 of embodiment 3 of the present invention;

[0034] Figure 13-5 This is a schematic diagram of Kc3 of the feedback signal transmission path of the phase delay unit in the first application scenario of the third embodiment of the present invention;

[0035] Figure 13-6 A comparative schematic diagram of application scenario 1 of embodiment 3 of the present invention;

[0036] Figure 13-7 This is a Klast schematic diagram of application scenario 1 of embodiment 3 of the present invention;

[0037] Figure 14-1 This is a schematic diagram of a phase-locked loop circuit structure in application scenario 1 of application scenario 2 of embodiment 3 of the present invention;

[0038] Figure 14-2 Schematic diagram of K1 of the reference signal input path in application scenario 2 of embodiment 3 of the present invention;

[0039] Figure 14-3 This is a schematic diagram of the signal output path K2 of the second application scenario of the third embodiment of the present invention;

[0040] Figure 14-4 Schematic diagram of K3 of feedback signal transmission path in application scenario 2 of embodiment 3 of the present invention;

[0041] Figure 14-5 This is a schematic diagram of Kc1 of the phase delay unit in the feedback signal transmission path of the second application scenario of the third embodiment of the present invention;

[0042] Figure 14-6 A comparative schematic diagram of application scenario 2 of embodiment 3 of the present invention;

[0043] Figure 14-7 This is a Klast schematic diagram of application scenario 2 of embodiment 3 of the present invention;

[0044] Figure 15-1 Schematic diagram of K1 of the reference signal input path of application scenario 3 of embodiment 3 of the present invention;

[0045] Figure 15-2 This is a schematic diagram of K2 of the signal output path of the third application scenario of the third embodiment of the present invention;

[0046] Figure 15-3 Schematic diagram of K3 of feedback signal transmission path in application scenario 3 of embodiment 3 of the present invention;

[0047] Figure 15-4 This is a schematic diagram of Kc1 of the phase delay unit in the feedback signal transmission path of the third application scenario of the third embodiment of the present invention;

[0048] Figure 15-5 A comparative schematic diagram of application scenario 3 of embodiment 3 of the present invention;

[0049] Figure 15-6 This is a Klast schematic diagram of application scenario 3 of embodiment 3 of the present invention;

[0050] Figure 16-1 This is a schematic diagram of a phase-locked loop circuit structure in application scenario 1 of application scenario 2 of embodiment 3 of the present invention;

[0051] Figure 16-2 Schematic diagram of K1 of the reference signal input path in application scenario 4 of embodiment 3 of the present invention;

[0052] Figure 16-3 This is a schematic diagram of K2 of the signal output path of the fourth application scenario of the third embodiment of the present invention;

[0053] Figure 16-4 Schematic diagram of K3 of feedback signal transmission path in application scenario 4 of embodiment 3 of the present invention;

[0054] Figure 16-5 This is a schematic diagram of Kc2 of the feedback signal transmission path of the phase delay unit in the fourth application scenario of the third embodiment of the present invention;

[0055] Figure 16-6 A comparative schematic diagram of application scenario 4 of embodiment 3 of the present invention;

[0056] Figure 16-7 This is a Klast schematic diagram of application scenario 4 of embodiment 3 of the present invention;

[0057] Fig.17 This is a schematic diagram of the structure of a base station according to Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the following is a further detailed description of the embodiments of the present invention through specific implementation methods combined with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0059] Embodiment 1:

[0060] In view of the problem that the phase deviation between multiple channels using multiple phase-locked loop circuits gradually increases as the temperature changes due to the phase shift characteristic of the phase-locked loop circuit; the embodiment of the present invention provides a phase-locked loop circuit that can fundamentally realize multi-channel phase synchronization. Figure 1 As shown, the phase-locked loop circuit in this embodiment includes a phase-locked loop main circuit 1 and a phase temperature compensation circuit 2, wherein the phase temperature compensation circuit 2 includes at least one phase delay unit 21, and at least one phase delay unit 21 is connected to the phase-locked loop main circuit 1, and the phase shift generated by the phase delay unit 21 connected to the phase-locked loop main circuit 1 with the temperature change is offset by the phase shift generated by the phase-locked loop main circuit 1 with the temperature change. Thus, it is ensured that the phase-locked loop circuit does not generate a phase shift or generates a phase shift within a very small range as the temperature changes during operation; when the phase-locked loop circuit is applied to a multi-channel scenario, since the phase-locked loop circuits of each channel do not generate a phase shift or generate a phase shift within a very small range as the temperature changes during operation, it can ensure that the phase difference between each channel is as small as possible at any time, thereby fundamentally and better meeting the requirements of multi-channel communication phase synchronization; and the control operation of detecting and aligning the phases between each channel can be omitted, so that resource utilization and energy consumption can be improved at the same time.

[0061] It should be understood that in some application scenarios of the present embodiment, a corresponding number of phase delay units 21 of the phase temperature compensation circuit 2 can be set to be connected to the phase-locked loop main circuit 1 based on but not limited to the phase offset caused by the phase-locked loop main circuit 1 changing with temperature, and the specific setting positions in the phase-locked loop main circuit 1 can also be flexibly set.

[0062] It should be understood that the phase-locked loop main circuit 1 in this embodiment can be various circuits that can realize the functions of the phase-locked loop main circuit. For ease of understanding, this embodiment is described below with an example phase-locked loop main circuit 1, but it should be understood that the structure of the phase-locked loop main circuit 1 in this embodiment is not limited to the structure of the example below.

[0063] See also Figure 2 As shown, the phase-locked loop main circuit 1 in this example includes:

[0064] The frequency detector 11 is used to detect the external reference signal f ref and the feedback signal f output by the programmable frequency divider 15 b The phase difference and frequency difference between them. The implementation circuit of the frequency detector 11 can be flexibly set; for example, in one example, the frequency detector 11 can be composed of two D edge triggers and an AND gate;

[0065] The charge pump 12 is mainly used to convert the logic level representing the phase difference information output by the frequency detector 11 into a current signal, and to charge and discharge the loop filter 13 under the action of the control switch, so that the tuning voltage Vtune of the voltage-controlled oscillator on the capacitor of the loop filter 13 is increased or decreased;

[0066] The loop filter 13 may be, but is not limited to, a passive filter in one example. The loop filter 13 is used to filter out the high-frequency components of the output signal of the charge pump 12, and output an approximate DC voltage Vtune as a control signal of the VCO (Voltage Controlled Oscillator). The implementation circuit of the loop filter 13 can also be flexibly set. For example, in one example, the loop filter 13 may be composed of a capacitor and a resistor.

[0067] The voltage controlled oscillator 14 is a circuit module that controls the output oscillation frequency through the voltage signal input by the loop filter 13. In one example, the voltage controlled oscillator 14 can convert DC power into AC power by, but not limited to, self-excited oscillation, and continuously generate AC signals, whose frequency value is controlled by the voltage control voltage.

[0068] The programmable frequency divider 15 is used to reduce the output signal frequency of the oscillator, so as to compare the output frequency of the oscillator with the reference signal frequency after reducing it to one-Nth, thereby realizing the frequency multiplication function of the phase-locked loop.

[0069] It should be understood that Figure 2 The structure of the phase-locked loop main circuit 1 can be flexibly adjusted or set, and Figure 2 The specific implementation circuits of each module can also be flexibly set.

[0070] Figure 2 When the phase-locked loop main circuit 1 shown is applied to a channel, the phase-locked loop main circuit 1 produces a phase shift as the temperature changes; when multiple channels each use a phase-locked loop main circuit 1, as the temperature changes, the phase difference between the channels is large, and the phase synchronization requirement between the channels cannot be met. Therefore, in this embodiment, Figure 2A corresponding number of phase delay units 21 are connected to the corresponding positions of the phase-locked loop main circuit 1 shown, and the phase shift generated by the temperature change of the connected phase delay unit 21 is used to offset the phase shift generated by the temperature change of the phase-locked loop main circuit 1, so that the phase shift finally output by the phase-locked loop main circuit 1 at different temperatures is 0 or slightly greater than 0, that is, the output phase of the phase-locked loop main circuit 1 is stabilized within a range allowed by the phase synchronization requirement; the circuit is simple to implement, easy to operate, low circuit cost, and the phase change characteristics of the phase-locked loop output are significantly improved; and when the phase-locked loop circuit provided in this embodiment is applied to multiple channels, there is no need to detect the phase between channels and perform alignment control operations, so it can also improve resource utilization and save energy consumption at the same time.

[0071] After experimental research, the overall linear proportional relationship between the phase and temperature of each part in the phase-locked loop main circuit 1 is obtained. Therefore, for ease of understanding, this embodiment uses the phase temperature change slope to characterize the phase offset as an example for explanation. This characteristic of phase changing with temperature is called phase and temperature change slope in this embodiment, which is represented by parameter K, and its unit is ps / ℃. In this example, the total output phase and temperature change slope Kout of the transmission path on the phase-locked loop main circuit 1 itself and the total output phase and temperature change slope Koutc of the phase delay unit 21 connected to the phase-locked loop main circuit 1 on the transmission path satisfy:

[0072] When the value of Kout is negative, the value of Koutc is positive, and when the value of Kout is positive, the value of Koutc is negative, and the absolute value of the sum of Kout and Koutc is less than or equal to the threshold value K0; this ensures that after the compensation of the phase delay unit 21 connected to the main circuit 1 of the phase-locked loop, the final phase and temperature change slope Klast of the phase-locked loop circuit are maintained at about 0, that is:

[0073] Klast=︱Kout+Koutc︱≤K0.

[0074] It should be understood that the value of K0 in this embodiment can be flexibly set according to specific application scenarios and application requirements. For example, the value of K0 can be between 0 ps / °C and 0.5 ps / °C, and the specific value can be flexibly set according to specific requirements.

[0075] According to the above analysis, the signal transmission phase of each module in the phase-locked loop main circuit 1 will change with temperature. The phase-locked loop main circuit 1 can be mainly divided into four parts: reference signal input path, feedforward path, feedback signal transmission path, and signal output path. The change of the feedforward path transmission phase with temperature will not be reflected in the final output signal of the phase-locked loop, and the negative feedback mechanism of the phase-locked loop itself will calibrate it from time to time. Figure 3As shown, the additional delay caused by the phase change of the reference signal input path, the feedback signal transmission path, and the signal output path with the temperature change is represented by the first phase delay, the second phase delay, and the third phase delay, respectively. The phase of the reference signal input path, the feedback signal transmission path, and the signal output path also increases with the increase of temperature, that is, the phase is linearly proportional to the temperature. The phase of the phase delay unit 21 is also linearly proportional to the temperature. Correspondingly, the phase and temperature change slope of the reference signal input path, the feedback signal transmission path, and the signal output path, as well as the total output phase and temperature change slope of the phase delay unit currently connected to the main circuit of the phase-locked loop on the transmission path are K1, K2, K3, and Koutc, respectively.

[0076] In this embodiment, K1 of the reference signal input path and K2 of the signal output path play a superposition role on the final output phase temperature change, and K3 of the feedback signal transmission path plays a subtraction role; therefore, in this example, the total output phase and temperature change slope of the transmission path of the phase-locked loop main circuit 1 itself Kout = K1 + K2 - K3;

[0077] Correspondingly, in this embodiment, the phase and temperature change slopes of the phase delay unit 21 connected to the phase-locked loop main circuit 1 on the reference signal input path, signal output path and feedback signal transmission path are Kc1, Kc2, and Kc3 respectively. The total output phase and temperature change slope of the phase delay unit currently connected to the phase-locked loop main circuit on the transmission path is Koutc=Kc1+Kc2-Kc3.

[0078] When the value of Kout is negative, the value of Koutc is positive, and when the value of Kout is positive, the value of Koutc is negative, so that Kout and Koutc cancel each other out.

[0079] For example, in one scenario, when K1+K2 is much larger than K3, the corresponding adjustment threshold can be set here. When the part of K1+K2 that is larger than K3 is greater than or equal to the adjustment threshold, for example, greater than 0.5, Kout=K1+K2-K3 is greater than 0.5, then Koutc=Kc1+Kc2-Kc3 needs to be a negative number, and Klast=︱Kout+Koutc︱≤K0. When the value of K0 is small, for example, a value near 0, the expression can also be: ︱Kout+Koutc︱≈0. In this application scenario, Kc1+Kc2 is less than Kc3, so that the value of Koutc is negative, and Klast=Kout+Koutc. For example, in one example, assuming Kout = 0.7, Koutc = -0.5, then Klast = 0.7 + (-0.5) = 0.2; in another example, assuming Kout = 0.7, Koutc = -0.7, then Klast = 0.7 + (-0.7) = 0, which is the best effect; in another example, assuming Kout = 0.7, Koutc = -0.8, then Klast = 0.7 + (-0.8) = -0.1. In this way, Koutc is used to achieve first-order compensation of Kout, so that the final output Klast is 0 or a small positive or negative value.

[0080] In this application scenario, when Kout is positive, that is, when Kout is a value greater than 0 and needs to be compensated, in one example, at least one of Kc1 and Kc2 can be set to 0, that is, the phase delay unit 21 is not connected to at least one of the reference signal input path and the signal output path. At this time, the phase delay unit 21 can be set or a corresponding number of phase delay units 21 can be set but not connected to the corresponding path; thereby reducing the use of the phase delay unit 21, improving resource utilization, and reducing costs and control complexity. In other examples, Kc1 and Kc2 can be set to 0, that is, the phase delay unit 21 is not connected to the reference signal input path and the signal output path (at this time, the phase delay unit 21 can be set or a corresponding number of phase delay units 21 can be set but not connected to the corresponding two paths), and the phase delay unit 21 is only connected to the feedback signal transmission path, and the number of connected phase delay units 21 can be flexibly set according to the values ​​of Kout and K0.

[0081] For another example, in another scenario, when K1+K2 is much smaller than K3, the corresponding adjustment threshold can also be set to characterize and determine. When the part of K3 that is larger than K1+K2 is greater than or equal to the adjustment threshold, for example, greater than 1, then Kout=K1+K2-K3 is less than -1, and Koutc=Kc1+Kc2-Kc3 needs to be positive, and Klast=︱Kout+Koutc︱≤K0. When the value of K0 is small, for example, a value near 0, the expression can also be: ︱Kout︱-︱Koutc︱≈0. In this application scenario, Kc1+Kc2 is greater than Kc3, so that the value of Koutc is positive, and Klast=Kout+Koutc. For example, in one example, assuming Kout = -1, Koutc = 0.8, then Klast = -1 + 0.8 = -0.2; in another example, assuming Kout = -1, Koutc = 1, then Klast = -1 + 1 = 0, which is the best effect; in another example, assuming Kout = -1, Koutc = 1.1, then Klast = -1 + 1.1 = 0.1. In this way, Koutc can also be used to achieve first-order compensation of Kout, so that the final output Klast is 0 or a small positive or negative value.

[0082] In this application scenario, when Kout is negative, that is, when Kout is a value less than 0 and compensation is required, in one example, Kc3 can be set to 0, that is, the phase delay unit 21 is not connected to the feedback signal transmission path (at this time, the phase delay unit 21 can be not set corresponding to this path or a corresponding number of phase delay units 21 can be set but not connected), thereby reducing the use of the phase delay unit 21, improving resource utilization, and reducing costs and control complexity. In other examples, any one of Kc1 and Kc2 can be set to 0, that is, the phase delay unit 21 is not connected to the reference signal input path or the signal output path. In this case, the phase delay unit 21 can be connected to the feedback signal transmission path, or it can be not connected; of course, in some examples, the phase delay unit 21 can also be set on the reference signal input path, the signal output path and the feedback signal transmission path at the same time (in this case, the values ​​of Kc1, Kc2, and Kc3 are all greater than 0), and the number of connected phase delay units 21 can be flexibly set according to the values ​​of Kout and K0, as long as the value of Koutc meets the above conditions.

[0083] According to the above analysis, in this embodiment, in order to eliminate the phase offset, the number of phase delay units 21 required to be connected to the phase-locked loop main circuit 1 and the position where the phase delay unit 21 is connected in the phase-locked loop main circuit 1 can be flexibly set according to the specific application scenario and requirements. Figure 4As shown, in some examples of this embodiment, the phase-locked loop circuit may further include a phase delay unit control module 3, which is used to control a corresponding number of phase delay units 21 to be connected to the phase-locked loop main circuit 1 according to the phase delay unit control parameter; wherein the phase delay unit control parameter is determined according to the phase offset generated by the phase-locked loop main circuit 1 as the temperature changes; for example, in one example, it is possible to flexibly determine which paths among the reference signal input path, the signal output path, and the feedback signal transmission path need to be connected to the phase delay unit 21 according to Kout. And the number of phase delay units 21 connected to each path; thereby, the phase offset generated by the phase delay unit connected to the phase temperature compensation circuit as the temperature changes is used to offset the phase offset generated by the phase-locked loop main circuit as the temperature changes; thereby ensuring that the phase-locked loop circuit does not generate a phase offset or generates a phase offset within a very small range as the temperature changes during operation. When the phase-locked loop circuit provided in this embodiment is applied to a multi-channel scenario, since the phase-locked loop circuit of each channel does not produce phase shift or produces phase shift within a very small range as the temperature changes during operation, it can ensure that the phase difference between each channel is as small as possible at any time, thereby fundamentally and better meeting the needs of multi-channel communication phase synchronization; and the control operations of detecting and aligning the phases between the channels can be omitted, thereby simultaneously improving resource utilization and saving energy consumption.

[0084] Embodiment 2:

[0085] For ease of understanding, this embodiment below illustrates the method for setting the phase-locked loop circuit shown in the first embodiment based on the first embodiment above. Figure 5 As shown, including:

[0086] S501: obtaining, by simulation, the phase shift of the phase-locked loop main circuit 1 caused by temperature changes.

[0087] For example, in one example, the phase and temperature change slope K1, K2, and K3 of the reference signal input path, feedback signal transmission path, and signal output path can be simulated based on the collected data, thereby obtaining the total output phase and temperature change slope Kout = K1 + K2 - K3 of the transmission path of the phase-locked loop main circuit 1 itself.

[0088] S502: Determine a phase delay unit control parameter according to the obtained phase offset.

[0089] For example, in one example, it can be determined on which paths among the reference signal input path, the signal output path, and the feedback signal transmission path the phase delay unit 21 needs to be connected; and the number of phase delay units 21 connected on each path; that is, in one example, the phase delay unit control parameters include which paths the phase delay unit 21 needs to be connected and the number of phase delay units 21 connected on each path.

[0090] S503: Control a corresponding number of phase delay units to be connected to a phase-locked loop main circuit according to the phase delay unit control parameters.

[0091] For example, the control parameters of the phase delay unit may include high and low levels, and the high and low levels are controlled by the control switch to connect to the corresponding phase delay unit lock in the phase temperature compensation circuit, so as to achieve the connection of the corresponding number of phase delay units at the corresponding position in the simulation stage.

[0092] It should be understood that the specific structure and total number of the phase delay unit 21 and the phase delay unit control module 3 in this embodiment can be flexibly set according to requirements.

[0093] For example, an example phase temperature compensation circuit can be found in Figure 6 As shown, it includes multiple phase delay units 21, and multiple phase delay units 21 are connected to the circuit through transmission gate logic to form a phase temperature compensation circuit. Each phase delay unit 21 can be composed of two or more stages of inverter circuits, such as Figure 7 It can also be composed of transmission gate units, RC delay units, simple resistor units and other circuits. For several composition methods, please refer to Figure 8-1 , Figure 8-2 and Figure 8-3 As shown; of course, it can also be achieved through other circuit structures.

[0094] For another example, in one example, the structure of the phase delay unit control module 3 is shown in Fig. 9 As shown, it includes a decoding circuit and a transmission gate control logic circuit. The decoding circuit can convert input signals such as v1, v2...vn into ctrl1, ctrl2...ctrl2 n Wait 2 n These control signals are connected to the transmission gate control logic directly or through an inverter, thereby controlling the phase delay unit 21 of the phase temperature compensation circuit to be connected to the phase-locked loop main circuit.

[0095] In other application scenarios of this embodiment, after the phase-locked loop circuit is set based on the above simulation results, the following calibration process may be included to further improve the accuracy and reliability of control. The calibration process provided in this embodiment may include:

[0096] The phase shift caused by the temperature change of the phase delay unit connected to the main circuit of the phase-locked loop is obtained, and the final phase and temperature change slope Klast are output after the phase shift caused by the temperature change of the main circuit of the phase-locked loop is offset.

[0097] According to the final phase offset Klast, it is determined that the number m of phase delay units connected to the main circuit of the phase-locked loop needs to be increased or decreased, and m phase delay units are correspondingly added to the main circuit of the phase-locked loop, or m phase delay units 21 are disconnected from the phase delay units currently connected to the main circuit of the phase-locked loop.

[0098] In this embodiment, the calibration process can be, but is not limited to, testing and calibrating at the stage of chip delivery. For ease of understanding, this embodiment is described below based on the process of testing and calibrating at the stage of chip delivery. Fig.10 As shown, including:

[0099] S1001: Test the final phase and temperature change slope Klast of the phase-locked loop circuit.

[0100] S1002: |Klast|≤K0? (ie, is |Klast| less than or equal to K0); if so, go to S1003; otherwise, go to S1004.

[0101] S1003: |Klast| meets the requirements and the test verification is completed.

[0102] S1004: Klast>0? (i.e., is Klast greater than 0); if so, go to S1005; otherwise, go to S1006;

[0103] S1005: Reduce the corresponding number of phase delay units connected to the reference signal input path and / or signal output path according to the |Klast| value; or increase the corresponding number of phase delay units connected to the feedback signal transmission path, and then go to S1001.

[0104] S1006: according to the |Klast| value, increase the number of phase delay units connected to the reference signal input path and / or the signal output path; or reduce the number of phase delay units connected to the feedback signal transmission path; then go to S1001.

[0105] In one application scenario, when the phase-locked loop circuit is set in the chip or shipped in the form of a separate device, it can be executed Fig.10The calibration process shown. For example, the Klast of the current phase of the phase-locked loop circuit can be obtained by testing at high temperature and low temperature respectively, and then it is determined whether the |Klast| value is small enough and meets the application requirements. If it is satisfied, the calibration ends. If it is not satisfied, it is further determined whether the Klast value is greater than 0. If the Klast value is greater than 0, the number of phase delay units connected to the reference signal input path and / or output path is appropriately reduced according to the |Klast| value, or the number of phase delay units connected to the feedback signal transmission path is increased; if the Klast value is less than 0, the number of phase delay units on the reference signal input path and / or output path is appropriately increased according to the |Klast| value, or the number of phase delay units on the feedback signal transmission path is reduced; then the above verification steps are repeated until the |Klast| value meets the requirements.

[0106] In an example of this embodiment, for a phase-locked loop circuit, the phase and temperature change slope corresponding to the highest temperature and the lowest temperature range in its working environment can be calculated by Figure 5 and Fig.10 The process shown obtains a set of fixed phase delay unit control parameters, which include the paths on which the phase delay unit needs to be connected and the number of phase delay units that need to be connected on each path. In this example, the phase delay unit control module can control the corresponding number of phase delay units to be connected on the corresponding path based on the fixed phase delay unit control parameters, and it can remain unchanged after leaving the factory.

[0107] In another example of the present embodiment, for a phase-locked loop circuit, it can be divided into multiple temperature intervals based on the highest temperature and the lowest temperature in its working environment, and a set of phase delay unit control parameters corresponding to each temperature interval can be obtained based on the test results, that is, a set of phase delay unit control parameters corresponding to one temperature interval; during operation, the phase delay unit control module can obtain the current temperature, and when it is determined that the current temperature falls into another target temperature interval, dynamically control the corresponding number of phase delay units to be connected on the corresponding path based on the phase delay unit control parameters corresponding to the target temperature interval.

[0108] In addition, for ease of understanding, this embodiment uses several situations before and after correction as examples for comparison, and illustrates the structure of the phase-locked loop circuit provided in this embodiment.

[0109] See also Figure 11-1 As shown in the figure, the output phase changes with temperature when the main circuit of the phase-locked loop is not compensated; it can be seen from the figure that the amplitude of the phase change with temperature is large and cannot meet the communication requirements. The waveform phase output by the phase-locked loop circuit provided by this embodiment may change with temperature in the following three situations:

[0110] For under-compensation, please refer to Figure 11-2 As shown, at this time, Klast is a smaller value greater than 0, and the final output phase of the phase-locked loop circuit increases slightly with the increase of temperature;

[0111] For overcompensation, see Figure 11-3 As shown, at this time, Klast is a smaller value less than 0, and the final output phase of the phase-locked loop circuit decreases slightly with the increase of temperature;

[0112] For ideal compensation, see Figure 11-4 As shown, at this time Klast is a value equal to 0. At this time, when the temperature rises or falls, the output phase of the phase-locked loop circuit remains unchanged.

[0113] Below Figure 11-1 and Figure 11-2 The comparison of the phase of the final output of the phase-locked loop circuit and the temperature change slope corresponding to the two cases is used as an example for explanation, see Fig.12 As shown, Fig.12 The coordinate system on the left is Figure 11-1 The corresponding phase and temperature change slope, the coordinate system on the right is Figure 11-2 The corresponding phase and temperature change slope. It can be seen that the slope of the output phase after calibration with temperature change is much smaller than that of the uncalibrated phase-locked loop circuit structure.

[0114] Embodiment three:

[0115] For ease of understanding, this embodiment is described below using several specific application scenarios as examples.

[0116] Application scenario 1:

[0117] In this application scenario, see Figure 13-2 to Figure 13-4 As shown, the relationship between the phase and temperature change slope of the reference signal input path, signal output path and feedback signal transmission path is K1+K2-K3>0. If the phase delay unit is not connected, the final output phase of the phase-locked loop circuit increases with the increase of temperature. In this embodiment, a corresponding number of phase delay units are connected to the feedback signal transmission path to generate the corresponding Kc3, see Figure 13-1 and Figure 13-5 As shown in the figure, the reference signal input path and signal output path are not currently connected to the phase delay unit; the output phase of the connected phase delay unit increases with the increase of temperature. Due to the inherent characteristic that the increase of the phase delay of the feedback signal transmission path of the phase-locked loop circuit will lead to the decrease of the output phase delay of the phase-locked loop circuit, the connected phase delay unit can be used with the help of simulation calibration and offline calibration to eventually reduce the characteristic that the output phase of the phase-locked loop increases with the increase of temperature, that is, Klast = K1 + K2-K3-Kc3. In this application scenario, Figure 5 and Fig.10 The simulation calibration and offline calibration shown in the figure control the corresponding number of phase delay units to access the feedback signal transmission path through the phase delay unit control module to adjust the coefficient Kc3. Under the action of Kc3, Klast=K1+K2-K3-Kc3≈0 is achieved, where the comparison diagram of K1, K2, K3, and Kc3 can be found in Figure 13-6 As shown, the Klast obtained after offset is shown in Figure 13-7 As shown, at this time, the output phase of the phase-locked loop circuit increases slightly with the increase of temperature, but is much smaller than K1+K2-K3.

[0118] Application scenario 2:

[0119] In this application scenario, see Figure 14-2 to Figure 14-4 As shown, the relationship between the phase and temperature change slope of the reference signal input path, signal output path and feedback signal transmission path is K1+K2-K3<0. If the phase delay unit is not connected, the final output phase of the phase-locked loop circuit decreases as the temperature increases. In this embodiment, a corresponding number of phase delay units are connected to the reference signal input path to generate the corresponding Kc1, see Figure 14-1 and Figure 14-5 As shown, the signal output path and feedback signal transmission path are not currently connected to the phase delay unit (the phase delay unit can also be connected as needed); the output phase of the connected phase delay unit increases with the increase of temperature. Due to the inherent characteristic that the increase of the phase delay of the reference signal input path of the phase-locked loop circuit will lead to the increase of the output phase delay of the phase-locked loop circuit, the connected phase delay unit can be used with the help of simulation calibration and offline calibration to eventually reduce the characteristic that the output phase of the phase-locked loop decreases with the increase of temperature, that is, Klast = K1 + K2-K3 + Kc1. In this application scenario, Figure 5 and Fig.10 The simulation calibration and offline calibration shown in the figure control the corresponding number of phase delay units to access the reference signal input path through the phase delay unit control module to adjust the coefficient Kc1. Under the action of Kc1, Klast=K1+K2-K3+Kc1≈0 is achieved, where the comparison diagram of K1, K2, K3, and Kc1 can be found in Figure 14-6 As shown, the Klast obtained after offset is shown in Figure 14-7 (Schematic diagram of under-compensation).

[0120] Application scenario three:

[0121] In this application scenario, see Figure 15-1 to Figure 15-3As shown, the relationship between the phase and temperature change slope of the reference signal input path, signal output path and feedback signal transmission path is K1+K2-K3<0. If the phase delay unit is not connected, the final output phase of the phase-locked loop circuit decreases as the temperature increases. In this embodiment, a corresponding number of phase delay units are connected to the reference signal input path to generate the corresponding Kc1, see Figure 15-4 As shown, the signal output path and feedback signal transmission path are not currently connected to the phase delay unit (the phase delay unit can also be connected as needed); the output phase of the connected phase delay unit increases with the increase of temperature. Due to the inherent characteristic that the increase of the phase delay of the reference signal input path of the phase-locked loop circuit will lead to the increase of the output phase delay of the phase-locked loop circuit, the connected phase delay unit can be used with the help of simulation calibration and offline calibration to eventually reduce the characteristic that the output phase of the phase-locked loop decreases with the increase of temperature, that is, Klast = K1 + K2-K3 + Kc1. In this application scenario, Figure 5 and Fig.10 The simulation calibration and offline calibration shown in the figure control the corresponding number of phase delay units to access the reference signal input path through the phase delay unit control module to adjust the coefficient Kc1. Under the action of Kc1, Klast=K1+K2-K3+Kc1≈0 is achieved, where the comparison diagram of K1, K2, K3, and Kc1 can be found in Figure 15-5 As shown, the Klast obtained after offset is shown in Figure 15-6 (This is a schematic diagram of overcompensation). At this time, the phase-locked loop output phase decreases slightly as the temperature rises.

[0122] Application scenario 4:

[0123] In this application scenario, see Figure 16-2 to Figure 16-4 As shown, the relationship between the phase and temperature change slope of the reference signal input path, signal output path and feedback signal transmission path is K1+K2-K3<0. If the phase delay unit is not connected, the final output phase of the phase-locked loop circuit decreases as the temperature increases. In this embodiment, a corresponding number of phase delay units are connected to the signal output path to generate the corresponding Kc2, see Figure 16-1 and Figure 16-5 As shown, the reference signal input path and feedback signal transmission path are not currently connected to the phase delay unit (the phase delay unit can also be connected as needed); the output phase of the connected phase delay unit increases with the increase of temperature. Due to the inherent characteristic that the increase of the phase delay of the reference signal input path of the phase-locked loop circuit will lead to the increase of the output phase delay of the phase-locked loop circuit, the connected phase delay unit can be used with the help of simulation calibration and offline calibration to eventually reduce the characteristic that the output phase of the phase-locked loop decreases with the increase of temperature, that is, Klast = K1 + K2-K3 + Kc2. In this application scenario, Figure 5 and Fig.10The simulation calibration and offline calibration shown in the figure control the corresponding number of phase delay units to access the signal output path through the phase delay unit control module to adjust the coefficient Kc2. Under the action of Kc2, Klast=K1+K2-K3+Kc2≈0 is achieved, where the comparison diagram of K1, K2, K3, and Kc2 can be found in Figure 16-6 As shown, the Klast obtained after offset is shown in Figure 16-7 As shown in Figure 1, the phase-locked loop output phase increases slightly with the temperature increase, but is much smaller than K1+K2-K3.

[0124] Embodiment 4:

[0125] This embodiment also provides a communication device, which may be, but is not limited to, a base station or various transceivers, and includes at least one phase-locked loop circuit as shown in the above embodiments. In one example, when the communication device adopts multi-channel communication, one phase-locked loop circuit may be used for each channel, or multiple channels may share one phase-locked loop circuit.

[0126] For ease of understanding, in one example of this embodiment, the communication device is used as a base station for illustration. It should be understood that the base station in this embodiment may be a cabinet-type macro base station, a distributed base station, or a multi-mode base station. Fig.17 As shown, the base station in this example includes a baseband unit (Building Base band Unit, BBU) 171, a radio remote unit (Radio Remote Unit, RRU) 172 and an antenna 173, wherein:

[0127] The baseband unit 171 is responsible for centralized control and management of the entire base station system, completing uplink and downlink baseband processing functions, and providing a physical interface with the radio frequency unit and the transmission network to complete information interaction. Fig.17As shown, the baseband unit 171 may include a baseband processing unit 1712, a main control unit 1711, a transmission interface unit 1713, etc. Among them, the main control unit 1711 mainly implements the control management, signaling processing, data transmission, interactive control, system clock provision and other functions of the baseband unit; the baseband processing unit 1712 is used to complete baseband protocol processing such as signal coding modulation, resource scheduling, and data encapsulation, and provide an interface between the baseband unit and the radio frequency remote unit; the transmission interface unit 1713 is responsible for providing a transmission interface connected to the core network. In this example, the above-mentioned logical function units can be distributed on different physical boards or integrated on the same board. Optionally, the baseband unit 171 can adopt a baseband master control integrated type or a baseband master control separated type. For the baseband master control integrated type, the master control, transmission, and baseband are integrated into a design, that is, the baseband processing unit is integrated with the main control unit and the transmission interface unit on a physical board. This architecture has higher reliability, lower latency, higher resource sharing and scheduling efficiency, and lower power consumption. For the baseband and main control separation type, the baseband processing unit and the main control unit are distributed on different boards, corresponding to the baseband board and the main control board. The separation architecture supports free combination between boards and facilitates flexible expansion of the baseband. The specific settings can be flexibly adopted according to needs.

[0128] The radio remote unit 172 communicates with the BBU through the baseband radio frequency interface to complete the conversion between baseband signals and radio frequency signals. Fig.17 As shown, an example of a radio remote unit 172 mainly includes an interface unit 1721, an uplink signal processing unit 1724, a downlink signal processing unit 1722, a power amplifier unit 1723, a low noise amplifier unit 1725, a duplexer unit 1726, etc., which constitute a downlink signal processing link and an uplink signal processing link. Among them, the interface unit 1721 provides a fronthaul interface with the baseband unit, receives and sends baseband IQ signals; the downlink signal processing unit 1722 completes signal up-conversion, digital-to-analog conversion, radio frequency modulation and other signal processing functions; the uplink signal processing unit 1724 mainly completes signal filtering, mixing, analog-to-digital conversion, down-conversion and other functions; the power amplifier unit 1723 is used to amplify the downlink signal and send it through the antenna 173; the low noise amplifier unit 1725 is used to amplify the uplink signal received by the antenna 173 and send it to the uplink signal processing unit 1724 for processing; the duplexer unit 1726 supports the multiplexing of transmit and receive signals and filters the transmit and receive signals.

[0129] In addition, it should be understood that the base station in this embodiment may also adopt a CU (Central Unint, central unit) -DU (Distributed Unit, distributed unit) architecture, where DU is a distributed access point, responsible for completing the underlying baseband protocol and radio frequency processing functions, and CU is a central unit, responsible for processing high-level protocol functions and centrally managing multiple DUs. CU and DU jointly complete the baseband and radio frequency processing functions of the base station.

[0130] It can be seen that those skilled in the art should understand that all or some of the steps, systems, and functional modules / units in the above disclosed methods can be implemented as software (which can be implemented with computer program code executable by a computing device), firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component can have multiple functions, or a function or step can be performed by several physical components in cooperation. Some or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit.

[0131] In addition, it is well known to those skilled in the art that communication media generally contain computer readable instructions, data structures, computer program modules or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery media. Therefore, the present invention is not limited to any specific hardware and software combination.

[0132] The above contents are further detailed descriptions of the embodiments of the present invention in combination with specific implementation methods, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A phase-locked loop circuit, characterized in that: It includes a phase-locked loop main circuit and a phase temperature compensation circuit, wherein the phase temperature compensation circuit includes at least one phase delay unit, and at least one of the phase delay units is connected to the phase-locked loop main circuit, and the phase shift generated by the phase delay unit connected to the phase-locked loop main circuit as the temperature changes, and the phase shift generated by the phase-locked loop main circuit as the temperature changes offset each other; The total output phase and temperature variation slope Kout of the transmission path on the phase-locked loop main circuit and the total output phase and temperature variation slope Koutc of the phase delay unit connected to the phase-locked loop main circuit on the transmission path satisfy the following relationship: When the value of Kout is negative, the value of Koutc is positive, and when the value of Kout is positive, the value of Koutc is negative, and the absolute value of the sum of Kout and Koutc is less than or equal to a threshold value K0.

2. The phase-locked loop circuit according to claim 1, characterized in that: The transmission path includes a reference signal input path, a signal output path and a feedback signal transmission path, the phase and temperature change slopes of the reference signal input path, the signal output path and the feedback signal transmission path are K1, K2 and K3 respectively, and Kout=K1+K2-K3; The phase and temperature variation slopes of the phase delay unit connected to the phase-locked loop main circuit on the reference signal input path, signal output path and feedback signal transmission path are Kc1, Kc2 and Kc3 respectively, and Koutc=Kc1+Kc2-Kc3.

3. The phase-locked loop circuit according to claim 2, characterized in that: When the value of Kout is positive, at least one of Kc1 and Kc2 is zero.

4. The phase-locked loop circuit according to claim 3, characterized in that: When the value of Kout is positive, Kc1 and Kc2 are both zero.

5. The phase-locked loop circuit according to any one of claims 2 to 4, characterized in that: When the value of Kout is negative, Kc3 is 0.

6. The phase-locked loop circuit according to any one of claims 2 to 4, characterized in that: When the value of Kout is negative, Kc1 or Kc2 is 0.

7. The phase-locked loop circuit according to any one of claims 1 to 4, characterized in that: It also includes a phase delay unit control module, which is used to control a corresponding number of phase delay units to be connected to the phase-locked loop main circuit according to the phase delay unit control parameters; the phase delay unit control parameters are determined according to the phase offset caused by the phase-locked loop main circuit changing with temperature.

8. A method for setting a phase-locked loop circuit according to any one of claims 1 to 7, comprising: The phase shift caused by the temperature change of the phase-locked loop main circuit is obtained by simulation; Determining a phase delay unit control parameter according to the phase offset; Control a corresponding number of the phase delay units to access the phase-locked loop main circuit according to the phase delay unit control parameters; The total output phase and temperature variation slope Kout of the transmission path on the phase-locked loop main circuit and the total output phase and temperature variation slope Koutc of the phase delay unit connected to the phase-locked loop main circuit on the transmission path satisfy the following relationship: When the value of Kout is negative, the value of Koutc is positive, and when the value of Kout is positive, the value of Koutc is negative, and the absolute value of the sum of Kout and Koutc is less than or equal to a threshold value K0.

9. The phase-locked loop circuit setting method according to claim 8, characterized in that: After the corresponding number of the phase delay units are controlled to be connected to the phase-locked loop main circuit according to the phase delay unit control parameter, the following calibration process is also included: Acquire a phase shift generated by a phase delay unit connected to the phase-locked loop main circuit as the temperature changes, and output a final phase shift after the phase shift generated by the phase-locked loop main circuit as the temperature changes is offset by each other; According to the final phase offset, it is determined that the number m of phase delay units connected to the phase-locked loop main circuit needs to be increased or decreased, and m phase delay units are correspondingly added to the phase-locked loop main circuit, or m phase delay units are disconnected from the phase delay units currently connected to the phase-locked loop main circuit.

10. A communication device, characterized in that: Comprising at least one phase-locked loop circuit according to any one of claims 1-7.

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