Digital interface circuit for analog-to-digital converter

Abstract

An embodiment of the present invention relates to a digital interface circuit for an analog-to-digital converter. The digital interface circuit includes: a queue block configured to be coupled between an analog-to-digital converter (ADC) and a direct memory access (DMA) controller of a processor, wherein the queue block includes a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command according to a first control bit of the first command to generate a modified first command; and send the modified first command to the ADC.

Description

Technical Field

[0001] The present invention relates generally to analog-to-digital (A / D) conversion systems and, in particular embodiments, to A / D conversion systems having digital interface circuits. Background Art

[0002] Analog-to-digital converters (ADCs) are widely used in electronic systems to convert analog signals such as voltage or current into digital signals for processing in digital systems. Various types of ADCs are available, such as direct conversion ADCs, successive approximation register ADCs (SAR ADCs), Σ-Δ ADCs, etc.

[0003] An analog-to-digital (A / D) conversion system includes at least one ADC and may include other functional modules, such as a multiplexer for selecting analog channels connected to and converted by the ADC. The A / D conversion system may additionally include a controller (e.g., a processor) to control the operation of the A / D conversion system. Effective communication between the controller and the ADC is a challenge because transmitting control commands and converted digital data between the controller and the ADC may consume a large amount of controller resources. An analog-to-digital conversion system for achieving effective communication between the controller and the ADC is needed in the field. Summary of the invention

[0004] In some embodiments, an analog-to-digital conversion system includes: an analog-to-digital converter (ADC); a multiplexer, wherein the multiplexer has multiple input channels configured to be coupled to multiple analog input signals, wherein output terminals of the multiplexer are coupled to input terminals of the ADC; and a digital interface circuit configured to be coupled between the ADC and a processor, wherein the digital interface circuit is configured to: receive a command sequence from the processor, wherein each command in the command sequence includes a channel number indicating an input channel of the multiplexer, wherein the channel numbers contained in the command sequence define a channel sequence; store the command sequence in a command first-in-first-out (FIFO) buffer of the digital interface circuit; send the command sequence stored in the command FIFO buffer to the ADC for a first time to control the operation of the ADC, wherein the analog input signals at the input channels of the multiplexer specified by the channel sequence are converted into digital data in sequence for the first time; send the command sequence stored in the command FIFO buffer to the ADC for a second time, wherein the analog input signals at the input channels of the multiplexer specified by the channel sequence are converted into digital data in sequence for the second time.

[0005] In some embodiments, the digital interface circuit includes: a queue block configured to be coupled between an analog-to-digital converter (ADC) and a direct memory access (DMA) controller of a processor, wherein the queue block includes a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command according to a first control bit of the first command to generate a modified first command; and send the modified first command to the ADC.

[0006] In some embodiments, a method for operating an analog-to-digital conversion system includes: sending a command sequence from a processor to a queue block, wherein the queue block is coupled between the processor and an analog-to-digital converter (ADC), the ADC is coupled to a multiplexer, and the multiplexer has multiple input channels connected to multiple analog input signals, wherein each command in the command sequence includes a control bit indicating a channel number, a channel repetition factor, and a channel delay number; decoding the control bit of each command by the queue block to obtain the channel number, the channel repetition factor, and the channel delay number in each command; generating a modified command sequence by the queue block by modifying each command according to the control bit of each command; and sending the modified command sequence by the queue block to the ADC to control the operation of the ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Details of one or more embodiments of the present invention are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the present invention will become apparent from the description and drawings, as well as from the claims. In the accompanying drawings, like reference numerals generally refer to like components throughout the various views, which are generally not re-described for the sake of brevity. For a more complete understanding of the present invention, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 illustrates a block diagram of an analog-to-digital (A / D) conversion system according to an embodiment;

[0009] Figure 2 FIG. 1 shows a schematic diagram of an embodiment of the present invention. Figure 1 The bus architecture of the A / D conversion system shown;

[0010] Figure 3 FIG. 1 shows a schematic diagram of an embodiment of the present invention. Figure 1 A more detailed block diagram of the A / D conversion system shown;

[0011] Figure 4 illustrates the structure of a command frame according to an embodiment;

[0012] Figures 5A to 5C FIG. 1 is a diagram illustrating a method according to some embodiments of the present invention. Figure 1 Different scan mode operations of the A / D conversion system shown;

[0013] Fig. 6A and 6B FIG. 1 shows a schematic diagram of an embodiment of the present invention. Figure 1 Channel oversampling operation of the A / D conversion system shown;

[0014] Fig. 7A and 7B FIG. 1 shows a schematic diagram of an embodiment of the present invention. Figure 1 The programmable delay operation of the A / D conversion system shown;

[0015] Fig. 8A and 8B FIG. 1 is a diagram illustrating a method according to another embodiment of the present invention. Figure 1 The programmable delay operation of the A / D conversion system shown;

[0016] Fig. 9 FIG. 1 shows a schematic diagram of an embodiment of the present invention. Figure 1 Direct memory access (DMA) operation of the A / D conversion system shown; and

[0017] Fig.10 A flow chart of a method of operating an A / D conversion system according to an embodiment is shown. DETAILED DESCRIPTION

[0018] The manufacture and use of the current preferred embodiment will be discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be implemented in a variety of specific environments. The specific embodiments discussed only illustrate the specific way to manufacture and use the present invention, and do not limit the scope of the present invention.

[0019] The present invention will be described with respect to exemplary embodiments in a specific context, namely, in the context of an analog-to-digital (A / D) conversion system having a digital interface circuit coupled between a controller of the A / D conversion system and an analog-to-digital converter (ADC) of the A / D conversion system.

[0020] Figure 1 A block diagram of an analog-to-digital (A / D) conversion system 500 according to an embodiment is shown. The A / D conversion system 500 includes an analog-to-digital converter (ADC) 100, a multiplexer 200, a digital interface block 300 (which may also be referred to as a digital interface circuit or an ADC queue block), and a controller 400. In the description herein, the ADC 100 may be referred to as a successive approximation ADC (SAR ADC) with the understanding that the SAR ADC is merely a non-limiting example of the ADC 100, and any other suitable type of ADC may also be used as the ADC 100.

[0021] like Figure 1As shown, the ADC 100 includes an analog block 101 that converts an analog input signal at an input terminal 102 of the analog block 101 into digital data (also referred to as a digital sample). The ADC 100 also includes a digital block 103 for controlling the operation of the analog block 101 and for communicating with other blocks in the A / D conversion system 500, such as the controller 400 and the digital interface block 300. The digital block 103 includes a control logic 105 that provides control signals, such as a sampling clock signal, an enable / disable signal for the analog block 101, and a channel selection signal for the multiplexer 200. The digital block 103 also includes various interfaces, such as a bus interface 107 for communicating with the controller 400 and a custom interface for communicating with the digital interface block 300. A plurality of trigger signals 121 are coupled to the ADC 100 for various functions such as interrupt requests and triggers. Figure 1 Also shown are various control / data paths (e.g., 111, 113, 117, 119, 143, and 147) between the functional blocks of ADC 100, and between ADC 100 and other functional blocks. The control / data paths can be bidirectional or unidirectional, and can be a single-bit control / data path or a multi-bit control / data path depending on the signal type.

[0022] Still refer to Figure 1 , the multiplexer 200 has a plurality of input channels 201 (also referred to as ADC channels), each of which is configured to be connected to an analog input signal (e.g., a voltage signal or a current signal). According to a control signal from the control path 111, one of the input channels 201 is selected and sent to an output terminal 203 of the multiplexer 200. The output terminal 203 is connected to the input terminal 102 of the ADC 100. Since the signal at the input channel of the multiplexer 200 is converted into digital data by the ADC 100, it is considered that the input channel of the multiplexer 200 (also referred to as ADC channel) is also converted by the ADC 100.

[0023] The controller 400 (also referred to as a processor) may be or include a central processing unit (CPU), a digital signal processor (DSP), a microcontroller (μ-controller), etc. The controller 400 controls the operation of the ADC 100 (and the multiplexer 200) by sending commands to the ADC 100 and / or by setting control bits in a control register of the ADC 100 via the bus interface 107 or the custom interface 109. For example, the controller 400 may set the ADC 100 to a single channel conversion mode, in which an analog signal at a specific channel of the multiplexer 200 is selected and converted to a digital stream at a specific sampling frequency. As another example, the controller 400 may set the ADC 100 to a scan mode, in which the controller selects a channel list of the multiplexer 200 and converts the analog signals at the channels into digital data in sequence in the order in which the channels appear in the channel list at each scan. In some embodiments, the controller 400 controls the scan mode operation of the ADC 100 by setting the control register of the ADC 100 via the bus interface 107 and / or sending the control command to the ADC 100 via the bus interface 107, however, the scan mode operation controlled via the bus interface 107 may have limited functionality, for example, the channel list may not be flexible, and the channel numbers in the channel list may have to be in increasing order, for example. In addition, it may be difficult to implement enhanced features such as programmable channel delay and channel oversampling (described in more detail below) via the bus interface 107. These and other enhanced features of the ADC 100 are supported and easily implemented using the digital interface block 300 and the custom interface 109, the details of which are discussed below.

[0024] Figure 1Further illustrated is a digital interface block 300, which is also referred to as a digital interface circuit or ADC queue block. The digital interface block 300 is coupled between the controller 400 and the ADC 100 and serves to improve the communication efficiency between the controller 400 and the ADC 100 and to support various enhanced features of the ADC, such as flexible channel sorting in a channel list, programmable channel delay, and channel oversampling. In some embodiments, the digital interface block 300 receives commands (also referred to as measurement commands) from the controller 400 and stores the commands in a buffer of the digital interface block 300. Next, the digital interface block 300 decodes the control bits embedded in the command, generates a modified command based on the control bits, and sends the modified command to the ADC 100 to control the operation of the ADC 100. The digital interface block 300 also receives and stores converted digital data from the ADC 100, and, in the illustrated embodiment, sends the digital data to the controller 400 using direct memory access (DMA) transfer. The digital interface block 300 communicates with the controller 400 via a data / control path 141. Further details of the digital interface block 300 are discussed below.

[0025] Figure 2 FIG. 1 shows a schematic diagram of an embodiment of the present invention. Figure 1 The bus architecture of the A / D conversion system 500 is shown in FIG. Figure 2 Not all components of the A / D conversion system 500 are shown in FIG.

[0026] exist Figure 2 In the example of , the controller 400 includes a control / logic unit (e.g., an arithmetic logic unit (ALU) and a control unit (CU)), a data memory, a code memory, and an AIPS block. The control / logic unit accesses the data memory, the code memory, and the AIPS block via an AMBA high-performance bus (AHB) 211, where AMBA stands for Advanced Microcontroller Bus Architecture, which is an open standard on-chip interconnect specification. The AIPS block serves as a bridge (e.g., an interface) between the AHB 211 and a peripheral bus (such as an AMBA Advanced Peripheral Bus (APB) 213). The ADC 100 and the digital interface block 300 are connected to the AMBA APB 213.

[0027] Figure 3 FIG. 1 shows a schematic diagram of an embodiment of the present invention. Figure 1 FIG. 5 is a block diagram of the A / D conversion system 500 in more detail. Note that for clarity, Figure 3 Not all components of the A / D conversion system 500 are shown in FIG.

[0028] refer to Figure 3 , some functional blocks of the controller 400 are illustrated above the dashed line 402. For example, Figure 3The system random access memory (RAM) of the controller 400 is shown, which may be or include Figure 2 Code memory and / or data memory in the Figure 3 In the example of , the system RAM has two applications running in parallel in two application buffers (e.g., Q0 application buffer and Q1 application buffer). The Q0 application buffer and the Q1 application buffer are similar to each other in that they are two instances of an application buffer. Each application buffer has a command buffer 401 and a data buffer 403, wherein the command buffer 401 stores commands sent from the controller 400 to the digital interface block 300, and the data buffer 403 stores digital data (converted by the ADC 100) sent from the digital interface block 300 to the controller 400. The command buffer 401 and the data buffer 403 can be, for example, a first-in, first-out (FIFO) buffer.

[0029] exist Figure 3 , the command buffer 401 is coupled to the DMA controller 405 of the controller 400, and the data buffer 403 is coupled to the DMA controller 407 of the controller 400. The DMA controllers 405 and 407 are used to transfer commands or data between the controller 400 and the digital interface block 300. Figure 3 Further illustrated is an interface block 409 of the controller 400 , which the controller 400 may use to set certain control registers of the digital interface block 300 , such as the global register 317 .

[0030] Still reference Figure 3 , the digital interface block 300 includes one or more queue blocks 301 (e.g., 301A and 301B). In some embodiments, the one or more queue blocks 301 are instances of the same hardware block (e.g., queue block) and thus have the same or similar structure. Figure 3 In the example of FIG. 4 , two queue blocks 301A and 301B are illustrated, each queue block being coupled to a corresponding application buffer in the controller 400 . Figure 3 The number of queue blocks in the digital interface block 300 shown is illustrative and non-limiting, and, as those skilled in the art will readily appreciate, any suitable number of queue blocks may be implemented in the digital interface block 300. These and other variations are fully intended to be included within the scope of the present disclosure.

[0031] exist Figure 3In the embodiment, the queue block 301 (e.g., 301A or 301B) includes a command queue 305, a data queue 309, and an optional auxiliary data queue 315. The queue block 301 also has a DMA command register 303 coupled between the command queue 305 and the DMA controller 405, and has a DMA data register 307 coupled between the data queue 309 and the DMA controller 407. The DMA command register 303 and the DMA data register 307 each include multiple DMA registers to support DMA burst mode transfers. In an embodiment where the queue block 301 includes the auxiliary data queue 315, the queue block 301 further includes an auxiliary data queue interface 313 for interacting between the auxiliary data queue 315 and another functional block (not shown) that processes digital samples from the ADC 100. In some embodiments, the command queue 305, the data queue 309, and the auxiliary data queue 315 are implemented as FIFO buffers.

[0032] Figure 3 The queue block 301 in includes queue registers 311 , which can be used to set properties specific to the queue block 301 and control the operation of the queue block 301 . Figure 3 Further illustrated is a global register 317 which can be used to set properties common to all queue blocks 301 and control the operation of the digital interface block 300. In addition, the digital interface block 300 includes an arbitration and interface block 319 which arbitrates access priorities between the queue blocks 301 and serves as an interface between the ADC 100 and the digital interface block 300. Figure 3 Further illustrated is an ADC digital bus interface 411 , which may be part of the controller 400 and may be used by the controller 400 to set control registers of the ADC 100 .

[0033] Figure 4 The structure of a command frame according to an embodiment is shown in the figure. The command frame shows various bit fields of the command sent from the controller 400 to the digital interface block 300. Figure 4 In the command frame, the first line shows the name of the bit field, the second line shows the bit position within the command frame, and the third line shows the default value of the bit in the command frame.

[0034] exist Figure 4 In the example of , each command frame has 32 bits, and the 32 bits are divided into different bit fields with different definitions. For example, bits 0-7 of the command define ADC_CH_NUM[7:0], which indicates the ADC channel number controlled by the command (e.g., to be converted by ADC 100). Figure 4The command frame can support up to 256 ADC channels. Bits 16-19 define CMD_DLY[3:0] and bit 28 defines DLY_CFG, where CMD_DLY[3:0] and DL_CFG determine the value of the programmable channel delay before the ADC channel indicated by ADC_CH_NUM[7:0] is converted. Bits 20-22 define CMD_RPT[0:2], which indicates the channel oversampling factor (also known as the channel repetition factor). Bits 24-26 define SEQ_TYPE[2:0], which indicates the sequence type of the command sequence stored in the command queue 305. Bit 31 defines LAST_CMD, which indicates whether the current command is the last command in the command sequence. Certain bits in the command are reserved bits (marked as RSVD). The details of the various bit fields and their use for controlling the operation of ADC 100 are discussed below. Those skilled in the art will readily appreciate that Figure 4 The command frame structures shown are non-limiting examples only, and other command frame structures are possible and are fully intended to be included within the scope of the present disclosure.

[0035] Figures 5A to 5C FIG. 1 is a diagram illustrating a method according to some embodiments of the present invention. Figure 1 The A / D conversion system 500 is shown to operate in different scanning modes. In particular, Figure 5A , 5B 5C illustrate the triggered scanning mode, the triggered once scanning mode and the non-triggered scanning mode, respectively.

[0036] refer to Figure 5A , the controller 400 sends the measurement command sequence from the command buffer 401 (see Figure 3 ) is sent to the command queue 305 of the corresponding queue block 301 to enable the ADC 100 to operate in the triggered scanning mode. The transmission of the measurement command sequence from the controller 400 to the command queue 305 is completed by the DMA controller 405, and its details will be referred to below. Fig. 9 In scan mode, a measurement command sequence can be executed multiple times, also known as being executed in multiple scans.

[0037] exist Figure 5A In the example of FIG. 1 , the measurement command sequence includes four measurement commands, such as CMD0, CMD1, CMD2, and CMD3. Each measurement command includes a bit field ADC_CH_NUM[7:0] (see Figure 4), which indicates the ADC channel number of the measurement command. The channel number in each measurement command defines a channel sequence (also called a channel list), which indicates the ADC channels to be converted into digital data and the order in which the ADC channels are converted. Note that the channel number in each measurement command can be any valid channel number, and the channel sequence can include channel numbers arranged in any order. For example, the channel numbers in the four commands CDM0, CMD1, CMD2, and CMD3 can be 1, 10, 3, and 2, respectively, which means that the analog signals at ADC channels 1, 10, 3, and 2 are sequentially converted into digital data in this order during each scan in the scan mode.

[0038] In some embodiments, the bit field SEQ_TYPE[2:0] of the first measurement command CMD0 is checked by the digital interface block 300 (e.g., by the queue block 301) to determine the scan mode, and the digital interface block 300 ignores the bit field SEQ_TYPE[2:0] in subsequent commands in the command sequence. The three bits of SEQ_TYPE[2:0] can define up to eight different scan modes. In the illustrated embodiment, at least three scan modes are defined by SEQ_TYPE[2:0], for example, a triggered scan mode, a triggered once scan mode, and a non-triggered scan mode. Figure 5A In the example of FIG. 1 , the bit field SEQ_TYPE[2:0] of the first measurement command has a predetermined value corresponding to the triggered scanning mode.

[0039] In the triggered scan mode, the digital interface block 300 (see Figure 3 ) before starting to execute the measurement command sequence stored in the command queue 305, wait for a trigger signal. The trigger signal is a hardware signal, and in an embodiment, is, for example, a rising edge or a falling edge of a control signal. In another embodiment, the trigger signal is a bit in a control register, and thus, the controller 400 can trigger the queue block 301 by setting the control bit in the control register to a predetermined value (e.g., changing the bit value from 0 to 1).

[0040] Once the digital interface block 300 detects a trigger signal, it communicates with the user via the custom interface 109 (see Figure 1 ) sends the measurement command sequence to the ADC 100 in order. Since the command queue 305 is a FIFO buffer, the measurement command sequence stored in the command queue 305 is sent to the ADC 100 in the order in which it is received. In an embodiment where a measurement command indicating channel delay or channel oversampling is required, the queue block 301 may modify the measurement command before sending it to the ADC 100, the details of which will be referred to below. Figures 6A to 6B , 7A to 7B and 8A to 8B. For simplicity, Figure 5A , 5BThe examples illustrated in 5C assume that the measurement command does not indicate channel delay and channel oversampling.

[0041] In the trigger scan mode, after the measurement command sequence has been executed once, the digital interface block 300 waits for the next trigger signal, and the measurement command sequence is still stored in the queue block 301. When the next trigger signal arrives, the digital interface block 300 executes the measurement command sequence again by sending the measurement command to the ADC 100 via the custom interface 109. For example, when the measurement command sequence is executed once by setting the control register of the digital interface block 300 (e.g., Figure 3 The end of the scan mode is triggered when the STOP scan command is sent from the controller 400 to the digital interface block 300 by the control bit 311 in the bit field 311. Once the STOP SCAN command is received, the current measurement command sequence continues to be executed until the last command (e.g., indicated by the bit field LAST_CMD) is sent to the ADC 100, then the command queue 305 is reset, and the scan mode is reset.

[0042] In some embodiments, when the custom interface 109 receives a measurement command, the custom interface 109 decodes (e.g., interprets) various control bits in the measurement command and generates corresponding control signals to control the operation of the analog block 101 of the ADC 100 and the operation of the multiplexer 200, so that the analog signal at the input channel of the multiplexer 200 indicated by the channel number ADC_CH_NUM[7:0] is converted into a digital value by the ADC 100. Then, the converted digital value is sent back to the data queue 309 of the queue block 301 via the custom interface 109 (see Figure 3 ). The custom interface 109 is a private interface between the ADC 100 and the digital interface block 300, which ensures low-latency data transmission between the ADC 100 and the digital interface block 300, and ensures that the transmission of the measurement command is not affected by other bus transmissions. In some embodiments, when the controller 400 controls the operation of the ADC 100 through the digital interface block 300, the digital interface 300 decodes the measurement command from the controller 400, modifies the measurement command and sends the modified measurement command to the control logic 105 via the custom interface 109. The control logic 105 generates a control signal according to the modified measurement command to control the operation of the analog block 101 and the operation of the multiplexer 200.

[0043] FIG. 5 illustrates a diagram according to an embodiment Figure 1 The A / D conversion system 500 shown operates in a trigger-once scan mode. Figure 5B In the example of FIG. 1 , the bit field SEQ_TYPE[2:0] of the first measurement command in the measurement command sequence has a value corresponding to the trigger once scan mode. The trigger once scan mode is similar to Figure 5A The trigger scan mode is set to 100, but after the digital interface block 300 receives the first trigger signal, the measurement command sequence is executed, and the measurement command sequence is repeatedly executed without checking for additional trigger signals until the digital interface block 300 receives a STOP SCAN command. The response of the digital interface block 300 to the STOP SCAN command is the same as described above for Figure 5A The responses discussed were identical, so the details will not be repeated.

[0044] Figure 5C FIG. 1 shows a schematic diagram of an embodiment of the present invention. Figure 1 The A / D conversion system 500 is shown to operate in a non-triggered scanning mode. Figure 5C In the example of , SEQ_TYPE[2:0] of the first measurement command in the measurement command sequence has a value corresponding to the non-triggered scan mode. In the non-triggered scan mode, the digital interface block 300 does not require a trigger to execute the measurement command sequence. Instead, once the first measurement command is loaded (e.g., written) into the command queue 305, execution of the measurement command sequence begins. The measurement command sequence is repeatedly executed until the digital interface block 300 receives a STOP SCAN command. The response of the digital interface block 300 to the STOP SCAN command is the same as described above for Figure 5A The responses discussed were identical, so the details will not be repeated.

[0045] Advantages of the above-described scan mode operation include a flexible channel list for channel scanning, which allows any number of ADC channels to be converted by the ADC 100 in any order. This flexibility may not be available without the digital interface block 300. In addition, since the measurement command sequence remains in the command queue 305 after each scan, the controller 400 only needs to send the measurement command sequence to the command queue 305 once, and the measurement command sequence stored in the command queue 305 can be used multiple times in the scan mode operation. This can be achieved by implementing the command queue 305 as a FIFO buffer, and reading commands from the FIFO buffer can be achieved by changing the address of the data pointer of the FIFO buffer without changing (e.g., losing) the contents stored in the FIFO buffer. Compared to the reference method in which the controller 400 needs to send the measurement command sequence to the ADC 100 for each scan, the currently disclosed A / D conversion system 500 saves a lot of resources for the controller 400 and significantly reduces the data traffic on the bus of the A / D conversion system 500. For example, the DMA controller 405 (see Figure 3 ) transfers a command sequence from the controller's command buffer 401 to the command queue 305 only once, and the DMA controller 405 is stopped after the last command in the command sequence is stored in the command queue 305.

[0046] Fig. 6A and 6B FIG. 1 shows a schematic diagram of an embodiment of the present invention. Figure 1 Channel oversampling operation of the A / D conversion system shown. In some applications, it may be advantageous to sample (e.g., convert) an ADC channel multiple times during each scan of a scan mode operation. For example, the ADC channel may be sampled multiple times to obtain multiple ADC samples (e.g., multiple digital data) in each scan, and the multiple ADC samples may be averaged to obtain ADC samples with less noise, thereby improving the quality of the ADC output.

[0047] Fig. 6A The diagram shows a measurement command sequence that includes three commands. The first command has a channel number of 1 and a channel oversampling factor of 4; the second command has a channel number of 8 and a channel oversampling factor of 2; the third command has a channel number of 12 and a channel oversampling factor of 0. The channel oversampling factor is determined by the bit field CMD_RPT[2:0] of each command (see Figure 4 ) defines a value from 0 to 7. In some embodiments, the queue block 301 repeats each command up to CMD_RPT times, and thus sends each command to the custom interface 109 of the ADC 100 a total of CMD_RPT+1 times, where CMD_RPT is the value of the bit field CMD_RPT[2:0]. The repeated command may be referred to as a modified command of the original command, and the above operation may be described as: the queue block 301 modifies the original command (e.g., by repetition) to generate a modified command and sends the modified command to the custom interface 109 of the ADC 100.

[0048] Reference now Figure 6B , which shows the modification command sequence sent from the queue block 301 to the custom interface 109 of the ADC 100. Fig. 6A For example, the first command is sent to ADC 100 5 (4+1=5) times, the second command is sent to ADC 100 3 (2+1=3) times, and the third command is sent to ADC 100 1 (0+1=1) times, which causes ADC channel 1 to be sampled 5 times in each scan, ADC channel 8 to be sampled 3 times in each scan, and ADC channel 12 to be sampled 1 time in each scan. As an example, consider an A / D conversion system 500 with a sampling frequency of 1 MHz for ADC 100. For Fig. 6AIn the illustrated command sequence, during each scan, ADC 100 can generate five consecutive digital samples with, for example, 12-bit resolution for ADC channel 1, and these five digital samples can be spaced 1 μs apart from each other. In addition, during each scan, ADC 100 can generate, for example, three 12-bit digital samples for ADC channel 8, and these three digital samples can be spaced 1 μs apart from each other. In addition, during each scan, ADC 100 can generate, for example, one 12-bit digital sample for ADC channel 12. Therefore, in this example, Fig. 6A The measurement command sequence in is executed in 9μs and generates 9 digital samples. Assuming that the trigger scan mode with a trigger frequency of 1KHz is selected, another 9 digital samples are generated about 1ms after the first 9 digital samples are generated. The sampling process is repeated until the STOP SCAN is received.

[0049] Fig. 7A and 7B FIG. 1 shows a schematic diagram of an embodiment of the present invention. Figure 1 Programmable delay operation of the A / D conversion system 500 shown. In some applications, it may be advantageous to add some spacing (e.g., time delay) between two adjacent ADC channels in a channel sequence. This spacing may need to be programmable for different applications. Without the present disclosure, such a requirement is difficult to accommodate in an A / D conversion system. Without the present disclosure, a non-ideal solution may require sending dummy commands (e.g., commands that take time to execute but do nothing) between measurement commands. However, this non-ideal solution increases the command buffer 401 (see Figure 3 ) and the memory space occupied by both the command queue 305, and more DMA requests and more bus cycles are required for transmitting the pseudo command. The programmable delay operation described herein meets the above requirements with significantly reduced memory usage, fewer DMA requests and fewer bus cycles.

[0050] Fig. 7A An example measurement command sequence with three commands is shown. The first measurement command has a channel number of 1 and a channel delay value of 3 (defined by the bit field CMD_DLY[3:0]); the second measurement command has a channel number of 8 and a channel delay value of 0; and the third measurement command has a channel number of 12 and a channel delay value of 5. Fig. 7A and 7B In the example, the DLY_CFG bit in the command is set to a value indicating a linear delay (e.g., "1"), which means that the amount of delay added is CMD_DLY×ΔT, where CMD_DLY is the value represented by the bit field CMD_DLY[3:0] and ΔT is a predetermined time period.

[0051] Figure 7B3 shows the modified command sent from the queue block 301 to the custom interface 109 of the ADC 100. Figure 7B As shown, the queue block 301 modifies each command by adding a variable delay specified by the channel delay value in front of each command. This can be achieved by using a hardware delay block (not shown separately) within the digital interface block 300, delaying each command by a specified channel delay (e.g., CMD_DLY×ΔT), and then sending the delayed command to the custom interface 109 of the ADC 100. In other words, the digital interface block 300 modifies the command sequence by changing the interval between commands (e.g., by adding different time delays), or by adding a variable time delay in front of each command, and sends the modified command to the custom interface 109 of the ADC 100.

[0052] Fig. 8A and 8B FIG. 1 is a diagram illustrating a method according to another embodiment of the present invention. Figure 1 The programmable delay operation of the A / D conversion system is shown. Fig. 8A and 8B The examples in Fig. 7A and 7B The example in is similar, but the DLY_CFG bit in the command is set to a value indicating an exponential delay (e.g., "0"), which means the amount of delay added is 2. CMD_DLY × ΔT, where CMD_DLY is the value represented by the bit field CMD_DLY[3:0] and ΔT is the predetermined time period.

[0053] Fig. 8A shows the measurement command sequence, and Figure 8B 1 shows a modified command sequence sent to the custom interface 109 of the ADC 100, wherein the modified command sequence has a variable delay added in front of each measurement command. Note that, as will be readily appreciated by a skilled person, Figures 6A to 6B , 7A to 7B and 8A to 8B can be used with the channel oversampling operation and channel delay operation illustrated in Figures 5A to 5C The scanning operations shown are combined.

[0054] Fig. 9 FIG. 1 shows a schematic diagram of an embodiment of the present invention. Figure 1 The direct memory access (DMA) operation of the A / D conversion system shown. In particular, Fig. 9 The FIFO buffer and DMA registers of the queue block 301 used for DMA transfers between the controller 400 and the queue block 301 are shown. Note that DMA transfers can be used to transfer commands from the controller 400 to the command queue 305 (see Figure 3), or can be used to transfer ADC digital samples from data queue 309 to controller 400. As discussed below, Fig. 9 Used to illustrate the two types of DMA transfers.

[0055] For example, for a DMA transfer from controller 400 to command queue 305, Fig. 9 The FIFO buffer shown on the left is the command queue 305, Fig. 9 The register shown on the right is the DMA command register 303. As a non-limiting example, Fig. 9 Four DMA command registers are illustrated in FIG, and any suitable number of DMA registers may be used. In order to transfer commands from the controller 400 to the command queue 305, the digital interface block 300 checks the number of free entries (e.g., unoccupied entries) in the command queue 305. As an example, the entries in the command queue 305 may be 32-bit or 64-bit memory cells. The number of free entries in the command queue 305 may be tracked by an indicator referred to as a watermark level. When the number of free entries in the command queue 305 is equal to or greater than the number of DMA command registers (e.g., four), the queue block 301 sends a DMA request to the DMA controller 405. In response, the DMA controller 405 starts a burst mode DMA transfer to transfer, for example, four commands to the DMA command register 303, which are then stored in the command queue 305. Note that more than one DMA command register 303 allows burst mode DMA transfers, which not only improves the efficiency of the DMA transfers (e.g., fewer DMA requests, fewer bus cycles), but also allows multiple measurement commands (e.g., four) to be transmitted without being interrupted by another DMA transfer with a higher priority.

[0056] For DMA transfers from data queue 309 to controller 400, Fig. 9 The FIFO buffer shown on the left is the data queue 309, Fig. 9The register shown on the right is the DMA data register 307. Similar to the above discussion, since more than one DMA data register 307 is available, burst mode DMA transfers are supported, which allows multiple ADC samples (e.g., four) to be transferred from the data queue 309 to the controller 400 without being interrupted by another DMA transfer with a higher priority. In some embodiments, to transfer ADC samples from the data queue 309 to the controller 400, the digital interface block 300 checks the number of new entries (e.g., new or unsent ADC samples that need to be sent to the controller 400) in the data queue 309. When the number of new entries is equal to or greater than the number of DMA data registers (e.g., four), the queue block 301 loads, for example, four ADC samples into the DMA data register 307 and sends a DMA request to the DMA controller 407. In response, the DMA controller 407 starts a burst mode DMA transfer to transfer, for example, four ADC samples to the controller 400.

[0057] Fig.10 The flowchart of the method of operating the A / D conversion system according to the embodiment is shown. It should be understood that Fig.10 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the following may be added, removed, replaced, rearranged, and repeated: Fig.10 The steps shown.

[0058] refer to Fig.10 In step 1010, a command sequence is sent from a processor to a queue block, wherein the queue block is coupled between the processor and an analog-to-digital converter (ADC), the ADC is coupled to a multiplexer, and the multiplexer has a plurality of input channels connected to a plurality of analog input signals, wherein each command in the command sequence includes a control bit indicating a channel number, a channel repetition factor, and a channel delay number. In step 1020, the queue block decodes the control bit of each command to obtain the channel number, the channel repetition factor, and the channel delay number in each command. In step 1030, the queue block generates a modified command sequence by modifying each command according to the control bit of each command. In step 1040, the queue block sends the modified command sequence to the ADC to control the operation of the ADC.

[0059] Embodiments can achieve advantages. For example, various scan modes allow any number of ADC channels to be converted into digital data in any order. Each ADC channel can be sampled multiple times during each scan, and a programmable delay can be inserted before each ADC channel is converted. These enhanced functions (which may not have been available before) can be implemented without increasing memory footprint or increasing bus cycles. For example, a queue block in a digital interface block decodes the control bit of a measurement command and modifies each measurement command according to the channel delay value and channel oversampling factor indicated by the control bit. The modified command is then sent to the ADC to control the operation of the ADC. Due to the structure of the disclosed A / D conversion system, it is only necessary to transmit the command sequence from the controller to the queue block once, which reduces the number of DMA requests and the bus cycles used for DMA transfers. As another example, the queue block of the digital interface block has more than one DMA register (e.g., a DMA command register or a DMA data register) to support burst mode DMA transfers, which improves the efficiency of DMA transfers and ensures that the measurement command (or ADC data) is transmitted in each burst mode transfer without being interrupted by other higher priority DMA transfers.

[0060] Example embodiments of the invention are summarized here. Other embodiments are also contemplated based on the entire specification and claims herein.

[0061] Example 1: In an embodiment, an analog-to-digital conversion system includes: an analog-to-digital converter (ADC); a multiplexer, wherein the multiplexer has multiple input channels configured to be coupled to multiple analog input signals, wherein output terminals of the multiplexer are coupled to input terminals of the ADC; and a digital interface circuit configured to be coupled between the ADC and a processor, wherein the digital interface circuit is configured to: receive a command sequence from the processor, wherein each command in the command sequence includes a channel number indicating an input channel of the multiplexer, wherein the channel numbers contained in the command sequence define a channel sequence; store the command sequence in a command first-in-first-out (FIFO) buffer of the digital interface circuit; send the command sequence stored in the command FIFO buffer to the ADC for a first time to control the operation of the ADC, wherein the analog input signals at the input channels of the multiplexer specified by the channel sequence are converted into digital data in sequence for the first time; send the command sequence stored in the command FIFO buffer to the ADC for a second time, wherein the analog input signals at the input channels of the multiplexer specified by the channel sequence are converted into digital data in sequence for the second time.

[0062] Example 2: An analog-to-digital conversion system according to Example 1, wherein sending the command sequence stored in the command FIFO buffer to the ADC for the first time includes: receiving a first trigger signal by the digital interface circuit; and in response to receiving the first trigger signal, sending the command sequence stored in the command FIFO buffer to the ADC for the first time by the digital interface circuit.

[0063] Example 3: An analog-to-digital conversion system according to Example 2, wherein sending the command sequence stored in the command FIFO buffer to the ADC for a second time includes: receiving a second trigger signal by the digital interface circuit; and in response to receiving the second trigger signal, sending the command sequence stored in the command FIFO buffer to the ADC for a second time by the digital interface circuit.

[0064] Example 4: An analog-to-digital conversion system according to Example 2, wherein sending the command sequence stored in the command FIFO buffer to the ADC for the second time includes: after the command sequence stored in the command FIFO buffer is sent to the ADC for the first time, the digital interface circuit sends the command sequence stored in the command FIFO buffer to the ADC for the second time without waiting for another trigger signal.

[0065] Example 5: An analog-to-digital conversion system according to Example 4, wherein the digital interface circuit is further configured to: check the status bit of a control register of the digital interface circuit; and in response to detecting that the status bit of the control register is set to a predetermined value, stop sending the command sequence stored in the command FIFO buffer to the ADC.

[0066] Example 6: The analog-to-digital conversion system according to Example 1, wherein the digital interface circuit is configured to start sending commands stored in the command FIFO buffer to the ADC immediately after storing the first command of the command sequence in the command FIFO buffer without checking for a trigger signal.

[0067] Example 7: An analog-to-digital conversion system according to Example 1, wherein each command in the command sequence further includes a control bit indicating a channel oversampling factor N, wherein the digital interface circuit is configured to send each command to the ADC N+1 times, so that for each command sequence, the analog input signal at the input channel indicated by the channel number of each command is converted into digital data N+1 times.

[0068] Example 8: An analog-to-digital conversion system according to Example 1, wherein each command in the command sequence further includes a control bit indicating a predetermined delay period, wherein the digital interface circuit is configured to: modify the command sequence by inserting a predetermined delay period before each command; and send the modified command sequence to the ADC so that conversion of the analog input signal at the input channel indicated by the channel number of each command is delayed by the predetermined delay period.

[0069] Example 9: The analog-to-digital conversion system of Example 1, wherein the digital interface circuit is configured to be coupled between the ADC and a first direct memory access (DMA) controller of the processor.

[0070] Example 10: An analog-to-digital conversion system according to Example 9, wherein the digital interface circuit further includes a first number of DMA command registers coupled between the first DMA controller and the command FIFO buffer, wherein the digital interface circuit is configured to: determine whether the number of free entries in the command FIFO buffer is equal to or greater than the first number of DMA command registers; and in response to determining that the number of free entries in the command FIFO buffer is equal to or greater than the first number of DMA command registers, send a DMA request to the first DMA controller to transfer the first number of commands to the DMA command registers in burst mode operation.

[0071] Example 11: An analog-to-digital conversion system according to Example 10, wherein the digital interface circuit further includes: a data FIFO buffer for storing converted digital data from the ADC; and a second number of DMA data registers configured to be coupled between the data FIFO buffer and a second DMA controller of the processor.

[0072] Example 12: An analog-to-digital conversion system according to Example 11, wherein the digital interface circuit is configured to: determine whether the number of new data entries in the data FIFO buffer is equal to or greater than the second number of DMA data registers; and in response to determining that the number of new data entries in the data FIFO buffer is equal to or greater than the second number of DMA data registers, send a DMA request to a second DMA controller to transfer the second number of new data entries to the processor in burst mode operation.

[0073] Example 13: A digital interface circuit includes: a queue block configured to be coupled between an analog-to-digital converter (ADC) and a direct memory access (DMA) controller of a processor, wherein the queue block includes a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command according to a first control bit of the first command to generate a modified first command; and send the modified first command to the ADC.

[0074] Example 14: The digital interface circuit of Example 13, wherein the first control bit of the first command comprises an oversampling factor N, wherein modifying the first command comprises repeating the first command N times.

[0075] Example 15: The digital interface circuit of Example 13, wherein the first control bit of the first command includes a delay T, wherein modifying the first command includes adding the delay T before the first command.

[0076] Example 16: A digital interface circuit according to Example 13, wherein the queue block further includes a first number of DMA command registers configured to be coupled between the DMA controller and the queue block, wherein the queue block is configured to: determine the number of free entries in the command buffer; and in response to determining that the number of free entries in the command buffer is equal to or greater than the first number of DMA command registers, request a DMA transfer from the DMA controller to transmit the first number of commands in burst mode operation.

[0077] Example 17: A digital interface circuit according to Example 13, wherein the queue block further includes a data buffer, wherein the queue block is further configured to: receive one or more digital samples from the ADC; store the one or more digital samples in the data buffer; and send the one or more digital samples to the processor via another DMA controller of the processor.

[0078] Example 18: A method for operating an analog-to-digital conversion system includes: sending a command sequence from a processor to a queue block, wherein the queue block is coupled between the processor and an analog-to-digital converter (ADC), the ADC is coupled to a multiplexer, and the multiplexer has multiple input channels connected to multiple analog input signals, wherein each command in the command sequence includes a control bit, the control bit indicating a channel number, a channel repetition factor, and a channel delay number; decoding the control bit of each command by the queue block to obtain the channel number, the channel repetition factor, and the channel delay number in each command; generating a modified command sequence by the queue block by modifying each command according to the control bit of each command; and sending the modified command sequence by the queue block to the ADC to control the operation of the ADC.

[0079] Example 19: The method of Example 18, wherein generating, by the queue block, the modified command sequence comprises: adding a predetermined delay period to each command according to a channel delay number, or repeating each command a number of times according to a channel repetition factor.

[0080] Example 20: The method according to Example 18 further includes: an analog signal at an input channel of a multiplexer indicated by a channel number is converted into a digital value by an ADC for a first number of times, wherein the first number of times is indicated by a channel repetition factor, and wherein a delay indicated by a channel delay number is inserted before the analog signal is converted.

[0081] Although the present invention has been described with reference to illustrative embodiments, the description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the exemplary embodiments and other embodiments of the present invention will be apparent to those skilled in the art with reference to the specification. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. An analog-to-digital conversion system, comprising: Analog-to-digital converter (ADC); a multiplexer, wherein the multiplexer has a plurality of input channels configured to be coupled to a plurality of analog input signals, wherein output terminals of the multiplexer are coupled to input terminals of the ADC; as well as A digital interface circuit is configured to be coupled between the ADC and the processor, wherein the digital interface circuit is configured to: receiving a command sequence from the processor, wherein each command in the command sequence includes a channel number indicating an input channel of the multiplexer, wherein the channel numbers included in the command sequence define a channel sequence; storing the command sequence in a command first-in-first-out (FIFO) buffer of the digital interface circuit; sending the command sequence stored in the command FIFO buffer to the ADC for the first time to control the operation of the ADC, wherein analog input signals at the input channels of the multiplexer specified by the channel sequence are sequentially converted into digital data for the first time; The command sequence stored in the command FIFO buffer is sent to the ADC for a second time, wherein the analog input signals at the input channels of the multiplexer specified by the channel sequence are sequentially converted into digital data for a second time.

2. The analog-to-digital conversion system according to claim 1, wherein sending the command sequence stored in the command FIFO buffer to the ADC for the first time comprises: receiving a first trigger signal through the digital interface circuit; as well as In response to receiving the first trigger signal, the command sequence stored in the command FIFO buffer is sent to the ADC for the first time through the digital interface circuit.

3. The analog-to-digital conversion system according to claim 2, wherein sending the command sequence stored in the command FIFO buffer to the ADC for the second time comprises: receiving a second trigger signal through the digital interface circuit; as well as In response to receiving the second trigger signal, the command sequence stored in the command FIFO buffer is sent to the ADC for the second time through the digital interface circuit.

4. The analog-to-digital conversion system according to claim 2, wherein sending the command sequence stored in the command FIFO buffer to the ADC for the second time comprises: After the command sequence stored in the command FIFO buffer is sent to the ADC for the first time, the command sequence stored in the command FIFO buffer is sent to the ADC for the second time through the digital interface circuit without waiting for another trigger signal.

5. The analog-to-digital conversion system according to claim 4, wherein the digital interface circuit is further configured to: checking a status bit of a control register of the digital interface circuit; and In response to detecting that the status bit of the control register is set to a predetermined value, sending the command sequence stored in the command FIFO buffer to the ADC is stopped.

6. The analog-to-digital conversion system of claim 1 , wherein the digital interface circuit is configured to immediately start sending commands stored in the command FIFO buffer to the ADC after a first command of the command sequence is stored in the command FIFO buffer without checking for a trigger signal.

7. An analog-to-digital conversion system according to claim 1, wherein each command in the command sequence further includes a control bit indicating a channel oversampling factor N, wherein the digital interface circuit is configured to send each command to the ADC up to N+1 times, so that for each command sequence, the analog input signal at the input channel indicated by the channel number of each command is converted into digital data up to N+1 times.

8. The analog-to-digital conversion system of claim 1 , wherein each command in the command sequence further comprises a control bit indicating a predetermined delay period, wherein the digital interface circuit is configured to: modifying the sequence of commands by inserting the predetermined delay period before each command; The modified command sequence is sent to the ADC such that conversion of the analog input signal at the input channel indicated by the channel number of each command is delayed by the predetermined delay period.

9. The analog-to-digital conversion system of claim 1, wherein the digital interface circuit is configured to be coupled between the ADC and a first direct memory access (DMA) controller of the processor.

10. The analog-to-digital conversion system of claim 9, wherein the digital interface circuit further comprises a first number of DMA command registers coupled between a first DMA controller and the command FIFO buffer, wherein the digital interface circuit is configured to: determining whether the number of free entries in the command FIFO buffer is equal to or greater than the first number of DMA command registers; and In response to determining that the number of free entries in the command FIFO buffer is equal to or greater than the first number of DMA command registers, a DMA request is sent to the first DMA controller for transferring the first number of commands to the DMA command registers in burst mode operation.

11. The analog-to-digital conversion system according to claim 10, wherein the digital interface circuit further comprises: a data FIFO buffer for storing converted digital data from the ADC; as well as A second number of DMA data registers are configured to be coupled between the data FIFO buffer and a second DMA controller of the processor.

12. The analog-to-digital conversion system according to claim 11, wherein the digital interface circuit is configured as: determining whether the number of new data entries in the data FIFO buffer is equal to or greater than the second number of DMA data registers; and In response to determining that the number of new data entries in the data FIFO buffer is equal to or greater than the second number of DMA data registers, a DMA request is sent to the second DMA controller for transferring the second number of new data entries to the processor in a burst mode operation.

13. A digital interface circuit comprising: A queue block is configured to be coupled between an analog-to-digital converter (ADC) and a direct memory access (DMA) controller of a processor, wherein the queue block includes a command buffer, and the queue block is configured to: receiving a first command from the DMA controller; storing the first command in the command buffer; modifying the first command according to the first control bit of the first command to generate a modified first command; and The modified first command is sent to the ADC.

14. The digital interface circuit of claim 13, wherein the first control bit of the first command comprises an oversampling factor N, wherein modifying the first command comprises: The first command is repeated N times.

15. The digital interface circuit of claim 13, wherein the first control bit of the first command comprises a delay T, wherein modifying the first command comprises: The delay T is preceded by the first command.

16. The digital interface circuit of claim 13, wherein the queue block further comprises a first number of DMA command registers configured to be coupled between the DMA controller and the queue block, wherein the queue block is configured to: determining the number of free entries in the command buffer; and In response to determining that the number of free entries in the command buffer is equal to or greater than the first number of DMA command registers, a DMA transfer is requested from the DMA controller for transferring the first number of commands in a burst mode operation.

17. The digital interface circuit of claim 13, wherein the queue block further comprises a data buffer, wherein the queue block is further configured to: receiving one or more digital samples from the ADC; storing the one or more digital samples in the data buffer; and The one or more digital samples are sent to the processor via another DMA controller of the processor.

18. A method of operating an analog-to-digital conversion system, the method comprising: sending a command sequence from a processor to a queue block, wherein the queue block is coupled between the processor and an analog-to-digital converter (ADC), the ADC is coupled to a multiplexer, and the multiplexer has a plurality of input channels connected to a plurality of analog input signals, wherein each command in the command sequence includes a control bit indicating a channel number, a channel repetition factor, and a channel delay number; The queue block decodes the control bit of each command to obtain the channel number, the channel repetition factor and the channel delay number in each command; Generating a modified command sequence by the queue block by modifying each command according to the control bit of each command; as well as The modified command sequence is sent by the queue block to the ADC to control the operation of the ADC.

19. The method of claim 18, wherein generating, by the queue block, the modified command sequence comprises: A predetermined delay period is added to each command according to the channel delay number, or each command is repeated a number of times according to the channel repetition factor.

20. The method of claim 18, further comprising: An analog signal at an input channel of the multiplexer indicated by the channel number is converted into a digital value by the ADC a first number of times, wherein the first number of times is indicated by the channel repetition factor, wherein a delay indicated by the channel delay number is inserted before converting the analog signal.

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