A high-speed multi-layer planar circuit board

Abstract

The present invention provides a high-speed multi-layer planar circuit board, the circuit board includes at least one stacking unit, wherein the stacking unit includes a ground layer, a power layer and a mixed layer, the power layer is arranged between the ground layer and the mixed layer, and the mixed layer is used to arrange ground wires and signal wires; each of the stacking units is provided with at least one power via perpendicular to the circuit board, and each power via is provided with at least one accompanying power ground hole parallel to the power via; the power via and the accompanying power ground hole both penetrate the stacking unit, and one end of the power via and the accompanying power ground hole both extend to the surface layer of the circuit board closest to the power layer; the power via is connected to the power layer in the stacking unit, and the accompanying power ground hole is respectively connected to the ground layer, the mixed layer in the stacking unit, and the ground layer and the mixed layer extending therethrough. Through the present invention, the problem of poor suppression of fundamental harmonics and higher harmonics and board edge radiation of power supply noise caused by multi-chip modules is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-speed multi-layer planar circuit board. Background Art

[0002] Planar circuit boards are the main carriers of components in electronic products. Modern electronic products with complex control communications and multimedia functions generally use high-frequency processors and high-speed digital buses. The forms of planar circuit boards as carriers include: multi-layer printed circuit boards, circuit substrates for large chip packaging, circuit substrates for multi-chip modules, etc.

[0003] Usually, the power supply, ground, and signal of these planar circuit boards are arranged on designated plane layers, and multiple metal planes with different properties and dielectric intervals are stacked and finally bonded into a planar circuit board. Different numbers of vias pass through the plane layers to achieve electrical connection. Multilayer circuit boards generally refer to 6 or more metal layers, with more routing impedance options, better wiring density, isolation, and electromagnetic protection capabilities. Electrical devices such as ICs, crystal oscillators, SOC chips, and decoupling capacitors are arranged on the surface of the planar circuit board.

[0004] The power plane, ground plane and dielectric interlayer can be equivalent to a planar waveguide, which has electrical modes related to its physical size and dielectric parameters, namely electrical resonance characteristics. When the power noise current from the electrical device, such as power ripple, simultaneous switching noise (SSN) caused by high-speed digital signals, is injected into the power plane from the surface through the ground plane, the noise current is excited into electromagnetic waves. The excited frequency and its intensity are related to the position of the via in the plane. Electromagnetic waves propagate to the edge of the plane through the planar waveguide, and other nearby power planes and signal traces will be disturbed; when these electromagnetic waves finally reach the edge of the circuit board, they radiate outward through the equivalent slot antenna at the edge of the board, causing far-field electromagnetic interference (EMI) radiation. The frequency band range and intensity upper limit of EMI radiation for various current applications are regulated by corresponding international / national / industry standards. At present, the upper frequency limit of automotive-grade EMI radiation (CISPR25) is 2.5GHz. In the future, the CISPR standard organization plans to increase this upper limit to 400GHz.

[0005] Typical examples of power supply noise interference and excessive radiation include DDR-SDRAM. DDR-SDRAM has a high clock frequency (DDR2 main frequency is greater than 400MHz), a large number of parallel bus lines such as clock / data / address, and a large signal swing. As a result, the clock base frequency and high-order harmonic energy are quite large, which is a strong interference source. Even if the clock and signal lines are arranged on the inner layer of the PCB, the noise can still be propagated by the power ground plane waveguide, causing interference to the surrounding power supply and signals, causing considerable EMI radiation. The best solution is to control the energy spectrum density of the noise source, such as using spread spectrum clocking (SSC). However, when the system's main control chip does not support DDR spread spectrum applications, other means must be used to deal with it. In practice, the common method of suppressing power supply ground noise is to use chip capacitors to decouple the power supply ground. Due to the lead inductance and wiring inductance of the chip capacitor itself, it can only suppress power supply ground noise below 100MHz, and the suppression effect on DDR base frequency and high-order harmonics is not obvious.

[0006] Another example is the obvious board edge radiation caused by the power supply noise of the circuit substrate used in large chip packaging and multi-chip modules. The equivalent flat antenna formed by the poorly grounded metal cover and the ground plane can easily radiate this noise energy. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide a high-speed multi-layer planar circuit board, which is used to solve the problem that the main control chip of the existing system does not support spread spectrum application, and the chip capacitor has poor suppression effect on the fundamental harmonics and higher harmonics of strong interference signals such as clocks, resulting in the board edge radiation of the power supply noise of the printed circuit board, large packaging substrate and multi-chip module.

[0008] The present invention provides a high-speed multi-layer planar circuit board, the circuit board comprising at least one stacking unit, wherein:

[0009] The stacking unit comprises a ground layer, a power layer and a mixed layer, wherein the power layer is arranged between the ground layer and the mixed layer, and the mixed layer is used for arranging ground wires and signal wires;

[0010] Each of the stacked units is provided with at least one power via hole perpendicular to the circuit board, and each of the power via holes is provided with at least one power ground hole parallel to the power via hole;

[0011] The power via and the accompanying power ground hole both penetrate the stacking unit, and one end of each of the power via and the accompanying power ground hole extends to the surface layer of the circuit board closest to the power layer;

[0012] The power via is connected to the power layer in the stack unit, and the accompanying power ground via is respectively connected to the ground layer, the mixed layer and the ground layer and the mixed layer extending through the stack unit.

[0013] Furthermore, a plurality of accompanying power ground holes are arranged beside the power via hole, and the distances between the plurality of accompanying power ground holes and the power via hole are all equal.

[0014] Furthermore, the high-frequency element connected to the power supply layer in the stacking unit is arranged on the surface layer of the circuit board closest to the ground layer in the stacking unit.

[0015] Furthermore, the outer edge of the power layer wraps around an annular fence ground hole, and the annular fence ground hole is arranged between the ground layer and the mixed layer of the stacking unit where the power layer is located.

[0016] Furthermore, the outer edge of the circuit board is wrapped with an absorbing material or a grounded metal foil layer.

[0017] Furthermore, the circuit board includes two stacking units and the number of layers is an even number greater than eight, and all layers in the circuit board are vertically symmetrically arranged.

[0018] Furthermore, the circuit board includes two or more laminated units;

[0019] The power via hole and the accompanying power ground hole in each stacking unit are through holes, and the other ends of the power via hole and the accompanying power ground hole extend to the surface layer of the circuit board farthest from the power layer;

[0020] The accompanying power source ground hole is connected to the grounding layer and the mixed layer through which it extends;

[0021] The high-frequency element and the surface-mounted high-frequency decoupling capacitor connected to the power layer in the stacking unit are arranged on the surface layer of the circuit board closest to the ground layer in the stacking unit.

[0022] Furthermore, the circuit board includes two or more laminated units;

[0023] The power via hole and the power-ground via hole in each stacking unit are both blind holes, and the other end of the power via hole is terminated at the stacking unit.

[0024] Furthermore, the high-frequency components and surface-mount decoupling capacitors connected to the power layer in each stacking unit are arranged on the surface layer of the circuit board closest to the ground layer in the stacking unit.

[0025] The implementation of the present invention has the following beneficial effects:

[0026] Through the present invention, a stacking unit based on a ground layer, a power layer and a mixed layer is arranged in the circuit board, and a power via and a companion power ground via are arranged in the circuit board. Starting from the noise source, the intensity of electromagnetic waves caused by the excitation of the power via is suppressed, and omnidirectional noise suppression is achieved. The main control chip of the existing system does not support spread spectrum application, and the chip capacitor has a poor suppression effect on the fundamental harmonics and higher harmonics of strong interference signals such as clocks, resulting in the board edge radiation of the power noise of the printed circuit board, the large packaging substrate and the multi-chip module. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 4 is a structural diagram of a stacking unit provided in an embodiment of the present invention.

[0029] Figure 2 It is a top view of the power layer of the power ground hole combination provided by an embodiment of the present invention.

[0030] Figure 3 It is a cross-sectional view of a circuit board with an outer edge of the circuit board wrapped with an absorbing material or a grounding metal foil layer provided by an embodiment of the present invention.

[0031] Figure 4 It is a structural diagram of a high-speed multi-layer planar circuit board provided by an embodiment of the present invention.

[0032] Figure 5 It is a structural diagram of a high-speed multi-layer planar circuit board provided by an embodiment of the present invention.

[0033] Figure 6 It is a curve diagram of the simulation result of the isolation of the power supply ground hole combination provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0034] This patent sets up a stacking unit for a circuit board, each stacking unit includes a ground layer, a power layer and a mixed layer, power vias and companion power vias are set for the stacking unit, and high-frequency components and high-frequency decoupling capacitors are set on the surface of the circuit board close to the power layer. The specific implementation method is further explained below in conjunction with the drawings and examples.

[0035] An embodiment of a high-speed multi-layer planar circuit board provided by the present invention will be described in detail below.

[0036] like Figure 1As shown, an embodiment of the present invention provides a stacking unit, which includes a ground layer 11, a power layer 12 and a mixed layer 13, wherein the power layer 12 is arranged between the ground layer 11 and the mixed layer 13, and the mixed layer 13 is used for arranging ground wires and signal wires.

[0037] It should be noted that the mixed layer 13 is also used to arrange the ground wire and can be regarded as a grounding layer; the upper and lower grounding layers wrap the power layer 12 to minimize the vertical electromagnetic wave emission and propagation, and at the same time form double planar decoupling capacitors between the power ground, which has the effect of reducing noise.

[0038] A power via 14 perpendicular to the high-speed multi-layer planar circuit board is provided in the stacking unit, and the power via 14 penetrates the stacking unit and is connected to the power layer 12 in the stacking unit; a companion power ground hole 15 parallel to the power via 14 is provided next to the power via 14, and the companion power ground hole 15 also penetrates the stacking unit and is respectively connected to the grounding layer 11 and the mixed layer 13 in the stacking unit; in this embodiment, the connection between the companion power ground hole 15 and the mixed layer 13 is actually the connection between the companion power ground hole 14 and the grounding part in the mixed layer 13.

[0039] It should be noted that a power ground hole 15 is arranged next to the power via 14. Next means that the power ground hole 15 is arranged around the power via 14. The distance between the two is generally not more than 1 / 20 of the wavelength corresponding to the highest frequency of the target noise suppression. If the highest frequency of the target noise suppression is 3GHz (wavelength = 100mm), the corresponding distance between the holes should not exceed 5mm.

[0040] like Figure 2 As shown, the embodiment of the present invention provides a power layer of a power ground hole combination. Through the top view of the power layer, combinations 51, 52 and 53 of power vias 14 and accompanying power ground holes 15 can be seen. The ratios of the power vias 14 and the accompanying power ground holes 15 in the combinations 51, 52 and 53 are 1:1, 1:2 and 1:3, respectively. It can be known that at least one accompanying power ground hole 15 is arranged next to each power via 14;

[0041] The electromagnetic wave intensity caused by the forward current of the power via 14 and the reverse current of the companion power ground hole 15 is partially offset, reducing the horizontal electromagnetic wave emission; in addition, the power via 14 and the companion power ground hole 15 are combined to be equivalent to a broadband decoupling capacitor, which suppresses the resonant mode of the above-mentioned combination position area; the closer the distance between the power via 14 and the companion power ground hole 15, the smaller the current loop area, the smaller the equivalent loop inductance, and the stronger the suppression ability; the same power via 14 and the multiple companion power ground holes 15 arranged next to the same power via 14 are at the same distance, and the noise suppression effect is better at this time.

[0042] like Figure 3As shown, an embodiment of the present invention provides a circuit board, which includes a ground layer 11, a power layer 12 and a mixed layer 13, and an outer edge is wrapped with an absorbing material 61 or a grounded metal foil layer 61 for shielding electromagnetic interference.

[0043] like Figure 4 As shown, an embodiment of the present invention provides a high-speed multi-layer planar circuit board, the circuit board has eight layers in total, including a first stacking unit, a second stacking unit, a signal layer 16 and a signal layer 26, including two stacking units in total;

[0044] The first stacking unit includes a ground layer 11, a power layer 12 and a mixed layer 13, and the second stacking unit includes a ground layer 21, a power layer 22 and a mixed layer 23. In the circuit board, the ground layer 11 is symmetrical with the ground layer 21, the power layer 12 is symmetrical with the power layer 22, the mixed layer 13 is symmetrical with the mixed layer 23, the signal layer 16 is symmetrical with the signal layer 26, and all layers in the circuit board are symmetrically arranged up and down.

[0045] It should be noted that all layers of the circuit board are arranged symmetrically, which is beneficial to reducing noise interference.

[0046] The power via 14 in the first stacking unit passes through the first stacking unit and is connected to the power layer 12 in the first stacking unit, and one end of the power via 14 extends to the surface layer of the circuit board closest to the power layer 12, that is, the signal layer 16 in this embodiment; a companion power ground hole 15 is arranged next to the power via 14 in the first stacking unit, and one end of the companion power ground hole 15 extends to the surface layer of the circuit board closest to the power layer 12, that is, the signal layer 16 in this embodiment, and is respectively connected to the ground layer 11 and the mixed layer 13 in the first stacking unit and the ground layer and the mixed layer extended through, but in this embodiment, one end of the companion power ground hole 15 extends through the first stacking unit without a ground layer and a mixed layer.

[0047] The power via 14 and the accompanying power ground hole 15 in the first stacking unit are both through holes, and the other ends of the power via 14 and the accompanying power ground hole 15 extend to the surface layer of the circuit board farthest from the power layer 12. In this embodiment, the surface layer of the circuit board farthest from the power layer 12 is the signal layer 26.

[0048] The power via 15 is connected to the grounding layer 21 and the mixed layer 23 extending therethrough, while the power via 14 is not connected to the power layer 22 because different power layers provide power with different voltages or frequencies, the power is individual, and the ground is common.

[0049] The high frequency element 17 and the surface mounted high frequency decoupling capacitor 18 connected to the power layer 12 in the first stacking unit are arranged on the surface layer of the circuit board closest to the ground layer 11 in the first stacking unit, that is, the signal layer 16.

[0050] It should be noted that the circuit board has two surface layers, one on the top and one on the bottom. Specifically in this embodiment, the surface layers of the circuit board are signal layer 16 and signal layer 26. The high-frequency component 17 is arranged on the surface layer of the circuit board closest to the ground layer 11 of the stacking unit where the connected power layer 12 is located. The purpose is to make the via distance between the high-frequency component 17 and the surface-mounted high-frequency decoupling capacitor 18 and the power layer 12 as short as possible; because the shorter the via, the smaller the inductance, and the inductance hinders the high-frequency signal from flowing back. Therefore, the high-frequency noise source, high-frequency decoupling capacitor and other high-frequency related devices are placed on the same surface so that the high-frequency noise can flow back more effectively.

[0051] The surface-mounted low-frequency decoupling capacitor 19 connected to the power layer 12 in the first stacking unit is arranged on the surface layer of the circuit board farthest from the ground layer 11 in the first stacking unit, that is, on the signal layer 26; low-frequency components and surface-mounted low-frequency decoupling capacitors can be placed on the surface layer of any circuit board, and for the sake of convenience of management, they should be placed separately from high-frequency components as much as possible.

[0052] It should be noted that a circuit board can be provided with more than two of the stacking units, but there must be a stacking unit placed in the middle of the circuit board, which will inevitably cause the power board in the stacking unit to be too far away from the surface of the circuit board, resulting in the power via being too long and high-frequency noise being difficult to control.

[0053] It should also be noted that the power layer 12 has two types of graphic fillings, indicating that the same power layer can be composed of more than two power sources, including power sources with different voltages or power sources with different frequencies.

[0054] like Figure 5 As shown, an embodiment of the present invention provides a high-speed multi-layer planar circuit board, the circuit board has ten layers, including a first stacking unit, a second stacking unit, a signal layer 16, a signal layer 26, a mixed layer 31 and a mixed layer 32, including two stacking units in total;

[0055] The first stacking unit includes a ground layer 11, a power layer 12 and a mixed layer 13, and the second stacking unit includes a ground layer 21, a power layer 22 and a mixed layer 23. In the circuit board, the ground layer 11 is symmetrical with the ground layer 21, the power layer 12 is symmetrical with the power layer 22, the mixed layer 13 is symmetrical with the mixed layer 23, the signal layer 16 is symmetrical with the signal layer 26, and the mixed layer 31 is symmetrical with the mixed layer 32. All layers in the circuit board are symmetrically arranged up and down.

[0056] The two power vias 14 in the first stacking unit both penetrate the first stacking unit and are connected to the power layer 12 in the first stacking unit, and one end of the power via 14 extends to the surface layer of the circuit board closest to the power layer 12, that is, the mixed layer 31 in this embodiment; a companion power ground hole 15 is arranged next to each power via 14 in the first stacking unit, and one end of the companion power ground hole 15 extends to the surface layer of the circuit board closest to the power layer 12, that is, the mixed layer 31 in this embodiment, and is respectively connected to the grounding layer 11, the mixed layer 13 in the first stacking unit and the mixed layer 31 extending outside the first stacking unit. If the companion power ground hole 15 extends through the grounding layer, it also needs to be connected. In this embodiment, one end of the companion power ground hole 15 does not extend through the grounding layer.

[0057] The power via 14 and the power ground via 15 in the first stacking unit are both blind holes. The other end of the power via 14 ends at the first stacking unit and does not extend to the second stacking unit. The purpose is to isolate and form two power domains to reduce noise.

[0058] The high-frequency element 17 connected to the power layer 12 in the first stack unit and the surface-mounted high-frequency decoupling capacitor 18 are arranged on the surface layer of the circuit board closest to the ground layer 11 in the first stack unit, that is, the mixed layer 31; because the power domain is isolated, the surface-mounted low-frequency decoupling capacitors 19 are all arranged on the surface layer of the circuit board closest to the ground layer 11 in the stack unit ( Figure 5 The surface-mounted low-frequency decoupling capacitor 19 is not marked in the figure); in short, the high-frequency component 17, the surface-mounted high-frequency decoupling capacitor 18, and the surface-mounted low-frequency decoupling capacitor 19 are all arranged on the surface layer of the circuit board closest to the ground layer 11 in the first stacking unit, and the surface-mounted decoupling capacitor includes the surface-mounted high-frequency decoupling capacitor 17 and the surface-mounted low-frequency decoupling capacitor 18.

[0059] The high-frequency element 27 connected to the power layer 22 in the second stacking unit is arranged on the surface layer of the circuit board closest to the ground layer 21 in the second stacking unit, that is, the mixed layer 32. Similarly, the surface-mount decoupling capacitor connected to the power layer 22 is also arranged on the mixed layer 32.

[0060] For the power layer 12 in the first stacking unit, the outer edge of the power layer 12 is wrapped with an annular fence ground hole 41, and the annular fence ground hole 41 is arranged between the grounding layer 11 and the mixed layer 13 of the first stacking unit where the power layer 12 is located; for the second stacking unit, an annular fence ground hole is also set between the grounding layer 21 and the mixed layer 23; the purpose of setting the annular fence ground hole is to reduce the horizontal diffusion of the electromagnetic radiation of the power layer.

[0061] like Figure 6As shown, the embodiment of the present invention provides interference curves under different combinations of power vias and accompanying power ground holes. In the same circuit board, the isolation between the power injection position and another power supply on the same board is obtained by simulation. It can be seen from the figure that as the number of accompanying power ground holes set for the power vias increases, the interference degree of the common board is gradually reduced;

[0062] refer to Figure 6 It can be seen that providing power vias and accompanying power ground vias can not only reduce interference in a stacking unit, but also reduce interference between multiple power boards.

[0063] The implementation of the present invention has the following beneficial effects:

[0064] Through the present invention, a stacking unit based on a ground layer, a power layer and a mixed layer is arranged in the circuit board, and power vias and accompanying power ground holes are arranged in the circuit board. Starting from the noise source, the electromagnetic wave intensity caused by the excitation of the power vias is suppressed, and omnidirectional noise suppression is achieved; further, high-frequency components and surface-mounted decoupling components are arranged on the surface of the circuit board closest to the power board, and a ring-shaped ground hole fence is arranged for each power board to reduce electromagnetic interference in vertical and horizontal directions; the problem of board edge radiation of power supply noise of printed circuit boards, large packaging substrates and multi-chip modules caused by the main control chip of the existing system not supporting spread spectrum application and the chip capacitor having poor suppression effect on the fundamental harmonics and higher harmonics of strong interference signals such as clocks is solved.

[0065] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A high-speed multi-layer planar circuit board, characterized in that: The circuit board comprises at least one stacking unit, wherein: The stacking unit comprises a ground layer, a power layer and a mixed layer, wherein the power layer is arranged between the ground layer and the mixed layer, and the mixed layer is used for arranging ground wires and signal wires; Each of the stacked units is provided with at least one power via hole perpendicular to the circuit board, and each of the power via holes is provided with at least one power ground hole parallel to the power via hole; The power via and the accompanying power ground hole both penetrate the stacking unit, and one end of each of the power via and the accompanying power ground hole extends to the surface layer of the circuit board closest to the power layer; The power via is connected to the power layer in the stack unit, and the accompanying power ground via is respectively connected to the ground layer, the mixed layer and the ground layer and the mixed layer extending through the stack unit; The outer edge of the power layer wraps around the annular fence ground hole, and the annular fence ground hole is arranged between the ground layer and the mixed layer of the stacking unit where the power layer is located.

2. The circuit board according to claim 1, characterized in that: A plurality of accompanying power ground holes are arranged beside the power via hole, and the distances from the plurality of accompanying power ground holes to the power via hole are all equal.

3. The circuit board according to claim 1, characterized in that: The high-frequency element connected to the power supply layer in the stacking unit is arranged on the surface layer of the circuit board closest to the ground layer in the stacking unit.

4. The circuit board according to claim 1, characterized in that: The outer edge of the circuit board is wrapped with a wave absorbing material or a grounding metal foil layer.

5. The circuit board according to any one of claims 1 to 4, characterized in that: The circuit board includes two stacking units and the number of layers is an even number greater than eight, and all layers in the circuit board are symmetrically arranged up and down.

6. The circuit board according to claim 1, wherein: The circuit board includes two or more laminated units; The power via hole and the accompanying power ground hole in each stacking unit are through holes, and the other ends of the power via hole and the accompanying power ground hole extend to the surface layer of the circuit board farthest from the power layer; The accompanying power source ground hole is connected to the grounding layer and the mixed layer through which it extends; The high-frequency element and the surface-mounted high-frequency decoupling capacitor connected to the power layer in the stacking unit are arranged on the surface layer of the circuit board closest to the ground layer in the stacking unit.

7. The circuit board according to claim 6, characterized in that: The surface mounted low frequency decoupling capacitor connected to the power layer in the stacking unit is arranged on the surface layer of the circuit board farthest from the ground layer in the stacking unit.

8. The circuit board according to claim 1, wherein: The circuit board includes two or more laminated units; The power via hole and the power-ground via hole in each stacking unit are both blind holes, and the other end of the power via hole is terminated at the stacking unit.

9. The circuit board according to claim 8, characterized in that: The high-frequency components and surface-mount decoupling capacitors connected to the power layer in each stacked unit are arranged on the surface layer of the circuit board closest to the ground layer in the stacked unit.

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