Semiconductor devices

Abstract

The present invention discloses a semiconductor device, which includes a first conductive type transistor and a second conductive type transistor, wherein the first conductive type and the second conductive type are different from each other, and each of the first conductive type transistor and the second conductive type transistor includes: (i) a metal gate electrode including a plurality of metal layers, and (ii) a metal gate electrode sidewall spacer, the distance between the sidewall of the metal gate electrode of the first conductive type transistor and the corresponding sidewall spacer of the metal gate electrode of the first conductive type transistor is greater than the distance between the sidewall of the metal gate electrode of the second conductive type transistor and the corresponding sidewall spacer of the metal gate electrode of the second conductive type transistor, and the gate length of the metal gate electrode of the first conductive type transistor is different from the gate length of the metal gate electrode of the second conductive type transistor. The present invention can provide a semiconductor device having a fine structure and capable of optimizing the gate length.

Description

[0001] This application is a divisional application of patent application No. 201810372155.6, filed on October 21, 2011, with the invention name “Semiconductor Device”.

[0002] This application was filed when the National Intellectual Property Administration believed that the patent application with application number 201810372155.6 did not meet the unity requirement. Specifically, it involves the fourth examination opinion notice of the patent application with application number 201810372155.6, which was issued on June 30, 2020 and the serial number is 2020062402364530.

[0003] In addition, the patent application with application number 201810372155.6 is a divisional application of the patent application with application number 201510969631.9, the application date of which is October 21, 2011, and the name of the invention is “Semiconductor device”.

[0004] In addition, the patent application with application number 201510969631.9 is a divisional application of the patent application with application number 201110322857.1, and its application date is October 21, 2011, and the name of the invention is "Semiconductor device and semiconductor device manufacturing method".

[0005] CROSS-REFERENCE TO RELATED APPLICATIONS

[0006] The present application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2010-243251 filed in the Japan Patent Office on Oct. 29, 2010, which is hereby incorporated by reference in its entirety. Technical Field

[0007] The present invention relates to a semiconductor device using a metal gate electrode and a method for manufacturing the semiconductor device. Background Art

[0008] In the related art, according to Moore's law, the integration of semiconductor devices doubles every 18 to 24 months. However, the gate tunnel leakage current near the 90nm node cannot be ignored, so the thinning of the gate oxide film of MOSFET has almost completely stopped. In addition, the reduction of gate length is slow because it is difficult to control the short channel effect.

[0009] Therefore, it is difficult to improve the performance of the MOSFET itself, and mechanical stress such as dual stress liner (DSL) or buried SiGe has been used to achieve engineering to improve mobility at or after the 90nm node. The mechanical stress technology considered in manufacturing is mainly used before the 45nm node. After the 45nm node, the scaling technology of the gate oxide film has begun to progress by increasing the dielectric constant of the gate oxide film with the HKMG structure, which uses a high dielectric constant (HK: high k) and a metal gate (MG) electrode.

[0010] The HKMG structure is mainly manufactured using two methods, such as a gate-first method and a gate-last method.

[0011] In the gate-first method, only the HKMG structure is used to replace the polysilicon gate structure or the SiON gate insulating film structure in the related art, so the structure is relatively simple.

[0012] On the other hand, in the gate-last method, the polysilicon pseudo gate electrode structure initially formed is replaced with the HKMG structure after the interlayer insulating layer is removed (for example, refer to patent document JP-A-2007-134432). Therefore, this manufacturing method is very different from the semiconductor device manufacturing method in the related art. In the gate-last structure, there are many cases where metals with different work functions are used in NMOS and PMOS using the same high-k (HK) insulating layer. In addition, since very fine patterns are processed, it is best to arrange the patterned gate length according to a constant rule for ease of manufacturing.

[0013] here, Fig.14 A semiconductor device having a HKMG structure in the related art is shown. In addition, Figures 15A to 15C A gate-last manufacturing process as a manufacturing method of a semiconductor device having an HKMG structure in the related art is shown.

[0014] Fig.14The semiconductor device 60 shown in the figure includes: a semiconductor substrate 61 provided with a predetermined element isolation region and a diffusion region; a gate electrode 62 and a gate electrode 63 formed on the semiconductor substrate 61; and an interlayer insulating layer 64. The gate electrode 62 has a metal gate electrode 68 formed on the semiconductor substrate 61, and an HK insulating layer 65, a WF (work function) metal layer 66 for Pfet, and a WF (work function) metal layer 67 for Nfet are provided between the metal gate electrode 68 and the semiconductor substrate 61. The gate electrode 63 has a metal gate electrode 68 formed on the semiconductor substrate 61, and an HK insulating layer 65 and a WF (work function) metal layer 67 for Nfet are provided between the metal gate electrode 68 and the semiconductor substrate 61. In addition, the gate electrode 62 and the gate electrode 63 each have a sidewall spacer 69 formed at the sidewall of the metal gate electrode 68.

[0015] Next, we will explain Fig.14 A method for manufacturing a semiconductor device 60 is shown.

[0016] First, if Fig.15A As shown, a gate insulating film 72 and a dummy gate electrode 71 are formed on a semiconductor substrate 61. The formation process of the dummy gate electrode 71 is as follows. The gate insulating film 72 is formed on the semiconductor substrate 61 by, for example, dry oxidation (O2, 700°C), and then a dummy gate electrode material layer is formed on the gate insulating film 72 by a method such as a CVD method. Next, a resist pattern is formed on the dummy gate electrode material layer by photolithography. The gate insulating film 72 and the above-mentioned dummy gate electrode material layer are anisotropically etched using the resist pattern as a mask to form a dummy gate electrode 71. At this time, since a very fine pattern is being processed, the resist pattern formed on the dummy gate electrode material layer by photolithography is formed to have a specific size for ease of manufacturing.

[0017] Next, a Si3N4 layer or the like is formed by a plasma CVD method, and then the Si3N4 layer is etched back to form a sidewall spacer 69 at the sidewall of the dummy gate electrode 71. Then, an interlayer insulating layer 64 covering the dummy gate electrode 71 and the sidewall spacer 69 is formed on the semiconductor substrate 61, and the interlayer insulating layer 64 is planarized by a CMP method.

[0018] Then, if Fig. 15B As shown, the dummy gate electrode 71 is removed by dry etching or wet etching, thereby forming an opening inside the sidewall spacer 69.

[0019] Then, if Fig. 15CAs shown, an HK insulating layer 65, a Pfet WF metal layer 66, and an Nfet WF metal layer 67 are formed in the trench formed after the dummy gate electrode is removed. Then, a low-resistance gate material is buried in the trench formed after the dummy gate electrode is removed, and the interlayer insulating layer 64 is planarized by CMP, thereby forming a metal gate electrode 68.

[0020] Through the above process, it is possible to produce Fig.14 A semiconductor device with a HKMG structure in the related art is shown.

[0021] However, in advanced CMOS, there is a situation where the gate length of NMOS and PMOS is optimized in order to reduce the gate capacitance. The gate length is optimized to have the smallest possible value within the range allowed by the short channel effect. However, in the case of using photolithography to form very fine patterns, if the gate lengths of the dummy gates in NMOS and PMOS are different, the burden in the photolithography process will be significantly increased, and thus the manufacturing cost will be increased. In other words, it is difficult to manufacture the optimal gate length so that the patterned gate length is arranged according to a constant rule.

[0022] In addition, in the planar type structure of the related art, the gate length is defined at the bottom of the gate electrode. However, in the fin structure that may be adopted after the 22nm generation, the shape of the gate sidewall also affects the gate length. In other words, when the sidewall of the gate electrode is tapered or there is roughness in the sidewall, the gate length varies. In particular, when the effective gate width is increased by increasing the height of the fin, the difference in gate length will become a big problem in processing. Summary of the invention

[0023] Therefore, an object of the present invention is to provide a semiconductor device having a fine structure and capable of optimizing a gate length in the semiconductor device, and also to provide a method for manufacturing such a semiconductor device.

[0024] One embodiment of the present invention is to provide a semiconductor device, which includes a first conductivity type transistor and a second conductivity type transistor, wherein the first conductivity type and the second conductivity type are different from each other, and each of the first conductivity type transistor and the second conductivity type transistor includes: (i) a metal gate electrode including a plurality of metal layers, and (ii) a metal gate electrode sidewall spacer, the distance between the side wall of the metal gate electrode of the first conductivity type transistor and the corresponding sidewall spacer of the metal gate electrode of the first conductivity type transistor is greater than the distance between the side wall of the metal gate electrode of the second conductivity type transistor and the corresponding sidewall spacer of the metal gate electrode of the second conductivity type transistor, and the gate length of the metal gate electrode of the first conductivity type transistor is different from the gate length of the metal gate electrode of the second conductivity type transistor.

[0025] Here, the offset spacer is formed in any one of the first conductivity type transistor and the second conductivity type transistor. Alternatively, the offset spacer has different thicknesses in both the first conductivity type transistor and the second conductivity type transistor.

[0026] Another embodiment of the present invention is to provide a semiconductor device, which includes: a first transistor, which includes (a) a first metal gate electrode, the first metal gate electrode includes at least a first metal layer and a second metal layer, (b) a first sidewall spacer, and (c) an offset spacer, the offset spacer is located between the sidewall of the first metal gate electrode and the first sidewall spacer; and a second transistor, which includes (a) a second metal gate electrode, the second metal gate electrode includes at least a first metal layer and a second metal layer, and (b) a second sidewall spacer, wherein the distance between one of the sidewalls of the first metal gate electrode and the corresponding one of the first sidewall spacers is not equal to the distance between one of the sidewalls of the second metal gate electrode and the corresponding one of the second sidewall spacers, and the gate length of the first metal gate electrode is different from the gate length of the second metal gate electrode.

[0027] Another embodiment of the present invention is to provide a semiconductor device, comprising: a gate insulating film, which is made of a high dielectric constant material and is formed on a substrate; a WF metal layer, which is formed on the gate insulating film; a buried metal layer, which is formed on the WF metal layer; an offset spacer, which is formed at the side wall of the buried metal layer on the WF metal layer; and a sidewall spacer, which is formed at the side wall of the buried metal layer, and the offset spacer is located between the sidewall spacer and the buried metal layer.

[0028] Another embodiment of the present invention is to provide a method for manufacturing a semiconductor device, the manufacturing method comprising the following steps: forming a first conductive semiconductor region and a second conductive semiconductor region on a substrate. In addition, the semiconductor device manufacturing method also includes the following steps in the first conductive semiconductor region and the second conductive semiconductor region: forming a dummy gate electrode on the substrate; forming a sidewall spacer at the sidewall of the dummy gate electrode; then forming an interlayer insulating layer so that the sidewall spacer is buried in the interlayer insulating layer and the upper surface of the dummy gate electrode is exposed; and removing the dummy gate electrode. In addition, the manufacturing method also includes the following steps: forming an offset spacer at the inner wall of the sidewall spacer in any one of the first conductive semiconductor region and the second conductive semiconductor region, or forming an offset spacer of different thickness at the inner wall of the sidewall spacer in both the first conductive semiconductor region and the second conductive semiconductor region. In addition, the manufacturing method also includes the following steps: forming a gate insulating film made of a high dielectric constant material on the substrate exposed in the sidewall spacer; and forming a metal gate electrode on the gate insulating film.

[0029] Another embodiment of the present invention is to provide a method for manufacturing a semiconductor device, the manufacturing method comprising the following steps: forming a dummy gate electrode on a substrate; forming a sidewall spacer at the side wall of the dummy gate electrode; forming an interlayer insulating layer so that the sidewall spacer is buried in the interlayer insulating layer and the upper surface of the dummy gate electrode is exposed; removing the dummy gate electrode; forming a gate insulating film made of a high dielectric constant material on the substrate exposed in the sidewall spacer and at the inner wall of the sidewall spacer; forming an offset spacer at the side wall of the gate insulating film; and forming a metal gate electrode on the gate insulating film and at the inner wall of the offset spacer.

[0030] Yet another embodiment of the present invention is to provide a method for manufacturing a semiconductor device, the method comprising the following steps: forming a gate insulating film made of a high dielectric constant material on a substrate; forming a WF metal layer on the gate insulating film; forming a dummy gate electrode on the WF metal layer; forming a sidewall spacer at the side wall of the dummy gate electrode; forming an interlayer insulating layer so that the sidewall spacer is buried in the interlayer insulating layer and the upper surface of the dummy gate electrode is exposed; removing the dummy gate electrode; forming an offset spacer on the WF metal layer exposed in the sidewall spacer and at the inner wall of the sidewall spacer; and forming a buried metal layer on the gate insulating film and at the inner wall side of the offset spacer.

[0031] In the semiconductor device of each embodiment of the present invention and the semiconductor device manufacturing method of each embodiment of the present invention, the gate length of the transistor is limited by the offset spacer formed between the metal gate electrode and the sidewall spacer. Therefore, regardless of the size of the area on the inner wall side of the sidewall spacer, the formation area of ​​the metal gate electrode can be controlled to an arbitrary size by the offset spacer. Therefore, the gate length of the semiconductor device in which a fine pattern is formed can be optimized.

[0032] According to the embodiments of the present invention, a semiconductor device having a fine structure and capable of optimizing a gate length can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 The diagram shows the structure of a semiconductor device according to a first embodiment of the present invention.

[0034] FIG. 2A to FIG. 2C The diagram shows the manufacturing process of the semiconductor device according to the first embodiment.

[0035] FIG. 3A to FIG. 3C The diagram shows the manufacturing process of the semiconductor device according to the first embodiment.

[0036] FIG. 4A to FIG. 4C The diagram shows the manufacturing process of the semiconductor device according to the first embodiment.

[0037] Figure 5 The structure of a semiconductor device according to a second embodiment of the present invention is shown in the figure.

[0038] FIG. 6A to FIG. 6C The diagram shows the manufacturing process of the semiconductor device according to the second embodiment.

[0039] FIG. 7A to FIG. 7C The diagram shows the manufacturing process of the semiconductor device according to the second embodiment.

[0040] Figure 8 The structure of a semiconductor device according to a third embodiment of the present invention is shown in the figure.

[0041] 9A to 9C The diagram shows a manufacturing process of the semiconductor device according to the third embodiment.

[0042] FIG. 10A to FIG. 10C The diagram shows a manufacturing process of the semiconductor device according to the third embodiment.

[0043] Fig.11A is a plan view illustrating the structure of a semiconductor device according to a fourth embodiment of the present invention; Fig. 11B is a cross-sectional view illustrating the structure of a semiconductor device according to a fourth embodiment of the present invention.

[0044] FIG. 12A to FIG. 12CThe diagram shows the manufacturing process of the semiconductor device according to the fourth embodiment.

[0045] FIG. 13A to FIG. 13C The diagram shows the manufacturing process of the semiconductor device according to the fourth embodiment.

[0046] Fig.14 The structure of a semiconductor device in the related art is illustrated.

[0047] FIG. 15A to FIG. 15C The diagram shows a manufacturing process of a semiconductor device in the related art. DETAILED DESCRIPTION

[0048] Hereinafter, preferred embodiments for carrying out the present invention will be described; however, the present invention is not limited to the following examples.

[0049] In addition, the description will be given in the following order.

[0050] 1. Semiconductor Device According to First Embodiment

[0051] 2. Semiconductor Device Manufacturing Method of First Embodiment

[0052] 3. Semiconductor Device According to Second Embodiment

[0053] 4. Semiconductor Device Manufacturing Method of Second Embodiment

[0054] 5. Semiconductor Device According to Third Embodiment

[0055] 6. Semiconductor Device Manufacturing Method According to the Third Embodiment

[0056] 7. Semiconductor device according to fourth embodiment (fin type)

[0057] 8. Method for manufacturing semiconductor device (fin type) according to fourth embodiment

[0058] 1. Semiconductor Device According to First Embodiment

[0059] Figure 1 is a schematic structural diagram of a semiconductor device according to a first embodiment. Figure 1 The semiconductor device 10 shown includes an N-type FET (Field Effect Transistor) region (hereinafter referred to as Nfet region) and a P-type FET region (hereinafter referred to as Pfet region) having a planar structure, and the semiconductor device 10 has a structure in which an offset spacer is formed in one of the gate electrodes. In addition, in the following description, the first conductivity type of the semiconductor device is the P type, and the second conductivity type of the semiconductor device is the N type.

[0060] Figure 1 The semiconductor device 10 shown is provided with an element separation portion 12 made of silicon oxide or the like and used to separate the active region on a semiconductor base 11 formed of, for example, a silicon substrate or the like. In addition, an N-well region 13 is formed in the active region of the Pfet region, and a P-well region 14 is formed in the active region of the Nfet region.

[0061] In the Nfet region, a buried metal layer 18 is formed on the semiconductor substrate 11, and a HK insulating layer 15 and a WF (work function) metal layer 17 for Nfet are provided between the semiconductor substrate 11 and the buried metal layer 18. In addition, in the Pfet region, a buried metal layer 18 is formed on the semiconductor substrate 11, and a HK insulating layer 15, a WF metal layer 16 for Pfet, and a WF metal layer 17 for Nfet are provided between the semiconductor substrate 11 and the buried metal layer 18.

[0062] The semiconductor device 10 has a metal gate electrode formed of a Pfet WF metal layer 16 or a Nfet WF metal layer 17 and a buried metal layer 18 .

[0063] The HK insulating layer 15 is a high-k insulating layer having a higher dielectric constant than that of silicon oxide. As the high-k layer, HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, PbScTaO, etc. can be used. In addition, the HK insulating layer 15 and the silicon oxide film can form a gate insulating film together.

[0064] The buried metal layer 18 is made of a pure metal material, an alloy or a metal compound, and is made of, for example, Ti, Al, Cu, W or an alloy containing the above metals.

[0065] In the Nfet region and the Pfet region, a sidewall spacer 21 is formed at the sidewall of the buried metal layer 18. In addition, in the Pfet region, an offset spacer 19 is formed at the inner wall of the sidewall spacer 21 of the metal gate electrode. Therefore, the Pfet region has a multilayer body formed of the offset spacer 19, the HK insulating layer 15, the Pfet WF metal layer 16, and the Nfet WF metal layer 17 from the inner wall of the sidewall spacer 21. In addition, the buried metal layer 18 is formed at the inner side surrounded by the above-mentioned multilayer body.

[0066] The side wall spacer 21 is made of SiN or SiO2, etc., and is formed of a single layer or a multilayer. In addition, the offset spacer 19 uses SiN or SiO2, etc.

[0067] In order to adjust the gate lengths of the Nfet region and the Pfet region, the offset spacer 19 is formed.

[0068] The opening of the sidewall spacer 21 in the Nfet region and the opening of the sidewall spacer 21 in the Pfet region are preferably formed to the same size. This is because: in the case of processing fine patterns, in order to facilitate manufacturing, it is desired to design the patterning according to a constant rule. The size of the opening of the sidewall spacer 21 is determined by patterning the gate electrode in the photolithography process, so the same pattern is preferred. In particular, when forming the gate electrode, the length of the gate in the longitudinal direction becomes miniaturized. Therefore, the lengths of the gate electrodes in the longitudinal direction of the gate in both the Nfet region and the Pfet region are formed to be the same as each other, thereby reducing the burden in the photolithography process.

[0069] However, if the photolithography process is performed using the same pattern in both the Nfet region and the Pfet region, it may not be possible to optimize the gate length to match the respective diffusion layer profiles. Therefore, the size of the opening is adjusted by forming an offset spacer 19 inside the opening of the sidewall spacer 21. The offset spacer 19 is formed on the inner wall of the sidewall spacer 21, so that the formation range of the Pfet WF metal layer 16 inside the opening can be adjusted. Therefore, the gate length can be optimized with an arbitrary length.

[0070] exist Figure 1 In the semiconductor device 10 shown, the gate length of the Pfet region having the offset spacer 19 is smaller than the gate length of the Nfet region without the offset spacer 19. In addition, in addition to forming the offset spacer only in the Pfet region, the offset spacer may be formed in both the Pfet region and the Nfet region. In the case where the offset spacer is formed in both the Pfet region and the Nfet region, there is no particular limitation on the thickness of the offset spacer in both the Pfet region and the Nfet region. For example, an offset spacer having the same thickness may be formed in both the Pfet region and the Nfet region, or an offset spacer having different thicknesses may be formed. In particular, in order to optimize the gate length in each MOS, the thickness of the offset spacer is preferably adjusted in both the Pfet region and the Nfet region.

[0071] In the semiconductor substrate 11 located on both sides of the buried metal layer 18 and directly below the sidewall spacer 21, a source / drain 23 as a P-type impurity diffusion region or a source / drain 24 as an N-type impurity diffusion region is formed. The source / drain 23 and the source / drain 24 are formed with a lightly doped drain (Lightly Doped Drain; LDD) and a halo (not shown). In addition, the surface layer of the source / drain 23 and the source / drain 24 exposed from the sidewall spacer 21 becomes silicide. The silicide of the source / drain 23 and the source / drain 24 is formed of, for example, cobalt silicide, nickel silicide or platinum silicide.

[0072] In the semiconductor device of the first embodiment, an offset spacer is formed on the side of the buried metal layer and the WF metal layer. Therefore, the gate length can be arbitrarily set by changing the thickness of the offset spacer. In this way, even if the dummy gate electrode and the sidewall spacer are formed in the same pattern in the photolithography process, the semiconductor device can be constructed to have an optimized gate length in each region.

[0073] 2. Semiconductor Device Manufacturing Method of First Embodiment

[0074] Next, the method for manufacturing the semiconductor device according to the first embodiment will be described.

[0075] Forming the element separation portion

[0076] First, SiO2 and Si3N4 are sequentially formed on a semiconductor substrate 11 formed of a silicon substrate. In addition, the resist is patterned at the portion for forming the active region. The Si3N4, SiO2 and semiconductor substrate 11 are sequentially etched using the formed resist pattern as a mask to form a groove (groove region). At this time, the above etching is performed until the depth of the groove of the semiconductor substrate 11 becomes 350 to 400 nm. The region where the Si3N4 is patterned becomes the active region, and the above groove region becomes the field oxide film.

[0077] Thereafter, the groove region is buried in SiO2. For example, a high-density plasma CVD method can be used to form a dense film with good step coverage. The surface is flattened by chemical mechanical polishing (CMP). The CMP is used to polish until the SiO2 film formed on the Si3N4 in the Si3N4 region is removed.

[0078] Next, the Si3N4 is removed using, for example, hot phosphoric acid, thereby forming the active region.

[0079] On the surface of the portion for forming the active region, a 10 nm SiO2 (sacrificial oxide film) is formed. In the Nfet formation region, an ion implantation process for forming a P-well region or a buried layer for suppressing punch-through is performed, and an ion implantation process for adjusting the threshold voltage (Vth) is performed, thereby forming an Nfet channel region. In addition, in the Pfet formation region, an ion implantation process for forming an N-well region or a buried layer for suppressing punch-through is performed, and an ion implantation process for adjusting the threshold voltage (Vth) is performed, thereby forming a Pfet channel region.

[0080] Through the above process, Figure 2A As shown, an N-well region 13 , a P-well region 14 , and an element separation portion 12 separating the two regions are formed on a semiconductor substrate 11 .

[0081] Forming a dummy gate electrode

[0082] Next, if Figure 2B As shown, a dummy gate electrode is formed on the N-well region 13 and the P-well region 14 of the semiconductor substrate 11 .

[0083] First, a sacrificial oxide film that is provided on the semiconductor substrate 11 when the active region is formed is separated from the semiconductor substrate 11 using a hydrogen fluoride (HF) solution. After separation, a gate insulating film 26 having a thickness of about 1 to 3 nm is formed by dry oxidation (O2, 700°C). As an oxidizing gas, in addition to dry O2, a mixed gas such as H2 / O2, N2O and NO can be used. In addition, a furnace annealing treatment or a rapid thermal annealing (RTA) treatment can be used.

[0084] Next, a pseudo gate electrode material layer is formed by CVD. For example, a pseudo gate electrode material layer is formed on the gate insulating film 26 by depositing polysilicon or amorphous silicon with a thickness of 50 to 100 nm. Next, a Si3N4 with a thickness of 50 to 100 nm is deposited as a hard mask by low pressure chemical vapor deposition (LP-CVD). After the deposition, an electrode pattern is formed on the Si3N4 hard mask by a photolithography process, and then the gate insulating film 26 and the pseudo gate electrode material layer are anisotropically etched by using the hard mask pattern. The pseudo gate electrode material layer is patterned, so as to form a gate insulating film 26 having a thickness of 50 to 100 nm. Figure 2B As shown, a gate insulating film 26 and a dummy gate electrode 25 are formed on the semiconductor substrate 11 .

[0085] In both the Nfet region and the Pfet region, the pattern of the dummy gate electrode is formed into the same shape. When processing fine patterns, in order to facilitate manufacturing in the photolithography process, it is desired to design the patterning according to a constant rule. Therefore, the dummy gate electrodes in both the Nfet region and the Pfet region are formed into the same pattern, thereby reducing the burden in the photolithography process. In particular, when forming the gate electrode, the length in the longitudinal direction of the gate becomes miniaturized, so the length of the dummy gate electrode in the longitudinal direction of the gate is preferably formed into the same pattern.

[0086] Forming a diffusion area

[0087] Next, if Figure 2C As shown, a sidewall spacer 21 is formed at the sidewall of the dummy gate electrode 25 , thereby forming a P-type source / drain 23 in the N-well region 13 and an N-type source / drain 24 in the P-well region 14 .

[0088] First, in the range of 3-5keV and 5-20×10 14 / cm 2 BF2 + Ions are implanted into the Pfet region to form the PLDD region. 14 / cm 2 Under the condition of + Ions are implanted into the Nfet region to form the NLDD region.

[0089] In addition, in order to suppress the short channel effect, when forming the LDD, a so-called halo ring with an impurity concentration higher than that of the well is also injected into the source / drain. For example, the Nfet region is divided into four regions and B (boron) is used at 12keV, 3×10 13 / cm 2 The Pfet region was divided into four regions and ion implantation was performed at an angle of 70 keV, 2 × 10 13 / cm 2 and 45° under the conditions of inclined ion implantation.

[0090] Forming side wall spacers

[0091] Next, the sidewall spacers 21 are formed at the sidewalls of the dummy gate electrode 25 .

[0092] Si3N4 is deposited on the semiconductor substrate 11 with a thickness of 50 to 150 nm by plasma CVD so as to cover the dummy gate electrode 25. Thereafter, anisotropic etching is performed to etch back the Si3N4 layer, thereby forming the sidewall spacer 21 at the sidewall of the dummy gate electrode 25. At this time, the Si3N4 serving as a hard mask for the dummy gate electrode 25 is retained.

[0093] Forming a diffusion area

[0094] Next, at 5-10 keV and 1-2×10 15 / cm 2 BF2 + Ions are implanted into the N-well region 13 to form a P-type source / drain 23. In addition, at 40-50 keV and 1-2×10 15 / cm 2 Under the condition of + Ions are implanted into the P-well region 14 to form an N-type source / drain 24. After the above ion implantation, the impurities are activated by RTA (rapid thermal annealing) at 1000° C. for 5 seconds to form Figure 2C MOSFET shown.

[0095] After forming the MOSFET, the so-called SALICIDE (Self-Aligned silicide) technology is used to reduce the resistance of the source / drain 23 and the source / drain 24. For example, Ni is deposited on the semiconductor substrate 11 to a thickness of 6 to 8 nm by sputtering. RTA is performed at 300 to 500° C. for 10 seconds to form silicide (NiSi) only on the Si of the source / drain 23 and the source / drain 24. After the silicide is formed, the unreacted Ni is removed by a chemical solution such as H2SO4 / H2O2.

[0096] Next, SiN is formed to a thickness of 10 to 100 nm as a contact etching stopper layer (not shown). Two types of SiN may be formed separately to apply different mechanical stresses to NMOS and PMOS in the transistor.

[0097] In addition, SiO2 with a thickness of 100 to 1000 nm is deposited on the semiconductor substrate 11 as an interlayer insulating layer 22 covering the dummy gate electrode 25 and the sidewall spacer 21. Figure 3A As shown, the upper portion of the dummy gate electrode 25 is exposed by planarization using a CMP method.

[0098] Remove the dummy gate electrode

[0099] Next, if Figure 3BAs shown, the dummy gate electrode 25 is removed, thereby forming an opening inside the sidewall spacer 21. When the dummy gate electrode 25 is formed of polysilicon or amorphous silicon, the dummy gate electrode 25 is removed by dry etching or wet etching using tetramethyl ammonium hydroxide (TMAH). At this time, SiO2 formed as a gate insulating film under the dummy gate electrode 25 is also removed by wet etching or the like.

[0100] Forming an offset spacer

[0101] Next, if Figure 3C As shown, an offset spacer 19 is formed at the inner wall of the sidewall spacer 21 in the Pfet region.

[0102] First, an offset spacer material in the range of 1 to 20 nm is formed on the entire surface of the semiconductor substrate 11. In addition, the offset spacer material layer is etched back by anisotropic etching to form an offset spacer 19 at the inner wall of the trench formed after the dummy gate electrode is removed. The offset spacer material is SiN or SiO2.

[0103] After the offset spacer 19 is formed, a resist layer is formed over the entire surface of the semiconductor substrate 11, and a resist pattern is formed, which is used to form an opening in the groove formed after the dummy gate electrode is removed in the Nfet region. The offset spacer formed at the inner wall of the sidewall spacer 21 in the Nfet region is removed by a wet etching method using, for example, an HF solution. For example, in the case where the offset spacer 19 is made of SiO2, the upper part of the interlayer insulating layer 22 is etched away together with the offset spacer material layer by etching back to a thickness of about 10nm; however, this degree of etching does not cause any particular problem in the structure of the semiconductor device.

[0104] In addition, for example, in the above-mentioned dummy gate removal process, only the dummy gate electrode 25 is removed and the gate insulating film 26 is retained. In the offset spacer formation process, an offset spacer material layer is formed on the entire surface of the semiconductor substrate 11 (including the dummy gate electrode 25) using SiN. In addition, the offset spacer material layer is etched back by anisotropic etching, thereby etching away the offset spacer in the Nfet region. After the offset spacer 19 is formed in the Pfet region, the gate insulating film 26 is removed.

[0105] In the above method, the sidewall spacers are made of SiN, thereby preventing the upper portion of the interlayer insulating layer 22 from being etched away when the offset spacer material layer is etched.

[0106] Furthermore, since the surface of the semiconductor substrate 11 is not exposed from the trench formed after the dummy gate electrode is removed when the offset spacer material layer is etched, damage to the semiconductor substrate 11 due to etching can be suppressed.

[0107] Forming HK insulation layer

[0108] Next, if Figure 4A As shown, the gate insulating layer is formed using the HK insulating layer 15 .

[0109] The HK insulating layer 15 is formed over the entire surface of the semiconductor substrate 11 by an atomic layer deposition (ALD) method or the like. For example, HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, PbScTaO, or the like is used to form the HK insulating layer 15. In addition, there are cases where the bottom layer of the HK insulating layer 15 mainly includes SiO2. In this case, the SiO2 is removed by plasma oxidation.

[0110] Forming WF metal layer

[0111] After forming the HK insulating layer 15, a WF (work function) metal layer is formed. The WF metal layer is used to form a single metal electrode or separate metal electrodes in the Nfet region and the Pfet region. Here, the case where different WF metal layers are formed in the Nfet region and the Pfet region will be described.

[0112] First, the WF metal layer 16 for Pfet is formed.

[0113] like Figure 4A As shown, a Pfet WF metal layer 16 with a thickness of 1 to 20 nm is formed on the HK insulating layer 15 over the entire surface of the semiconductor substrate 11 by CVD, PVD or ALD. The optimum work function of the Pfet WF metal layer 16 is 5.2 eV, and a material with a work function value close to this value is used. For example, an alloy containing Ru, Pd, Pt, Co, Ni, or Mo is used, or an oxide, TiN, or the like is used.

[0114] Next, the Pfet WF metal layer 16 is removed from the Nfet region by dry etching or wet etching. At this time, the HK insulating layer 15 in the Nfet region is not removed but remains. For example, a resist pattern or the like is formed on a portion of the Pfet WF metal layer 16 to be retained in the Pfet region, and the Pfet WF metal layer 16 in the Nfet region is etched away using the resist pattern as a mask. In the case of using TiN to form the Pfet WF metal layer 16, for example, ammonia hydrogen peroxide is used to remove the Pfet WF metal layer 16 from the Nfet region.

[0115] Next, if Figure 4B As shown, a Nfet WF metal layer 17 with a thickness of 1 to 20 nm is formed on the Pfet WF metal layer 16 and the HK insulating layer 15 by CVD, PVD or ALD. The optimal work function of the Nfet WF metal layer 17 is 4.0 eV, and a material with a work function value close to this value is used. For example, an alloy containing Hf, Zr, Ti, Ta, Al, or a carbide, HfSi, etc. is used.

[0116] Buried Gate Metal

[0117] After forming the Pfet WF metal layer 16 and the Nfet WF metal layer 17, as shown in FIG. Figure 4C As shown, a low resistance gate material is buried in the trench formed after the dummy gate electrode is removed, thereby forming a buried metal layer 18. As the low resistance gate material, for example, Ti, Al, Cu, W or an alloy containing the above metals is used.

[0118] As described above, after the offset spacer 19, the HK insulating layer 15, etc. are formed in the groove formed after the dummy gate electrode is removed, a low-resistance gate material is buried in the groove to form a low-resistance gate material layer, thereby obtaining a buried metal layer 18. In addition, the low-resistance gate material layer, the Nfet WF metal layer 17, the Pfet WF metal layer 16, and the HK insulating layer 15 on the interlayer insulating layer 22 are removed by the CMP method, thereby performing planarization. That is, when the buried metal layer 18 is formed, the Nfet WF metal layer 17, the Pfet WF metal layer 16, and the HK insulating layer 15 continuously formed on the interlayer insulating layer 22 are removed, so that the above layers remain only in the above groove.

[0119] Through such a process, low-resistance gate material remains only in the groove formed after the dummy gate electrode is removed, thereby forming a buried metal layer 18. In addition, in this process, the Nfet WF metal layer 17, the Pfet WF metal layer 16 and the buried metal layer 18 form a metal gate electrode.

[0120] Through the above process, it is possible to produce Figure 1 The semiconductor device 10 is shown. According to the present manufacturing method, only one step of photolithography process for removing the offset spacer 19 from the Nfet region is added to the manufacturing method of the gate-last structure in the related art, thereby manufacturing the semiconductor device of the first embodiment.

[0121] 3. Semiconductor Device According to Second Embodiment

[0122] Figure 5 is a schematic structural diagram of a semiconductor device according to a second embodiment. Figure 5 In the semiconductor device 20 shown in FIG. Figure 1 The same constituent elements as those of the semiconductor device 10 of the first embodiment are given the same reference numerals, and their description will be omitted.

[0123] Figure 5 The semiconductor device 20 shown is provided with an element separation portion 12 made of silicon oxide or the like and used to separate an active region on a semiconductor base 11 formed of, for example, a silicon substrate or the like. In addition, an N-well region 13 is formed in the active region of the Pfet region, and a P-well region 14 is formed in the active region of the Nfet region.

[0124] In the Nfet region, a buried metal layer 18 is formed on the semiconductor substrate 11, and a HK insulating layer 15 and a Nfet WF (work function) metal layer 17 are formed between the semiconductor substrate 11 and the buried metal layer 18. In addition, in the Pfet region, a buried metal layer 18 is formed on the semiconductor substrate 11, and a HK insulating layer 15, a Pfet WF metal layer 16, and a Nfet WF metal layer 17 are formed between the semiconductor substrate 11 and the buried metal layer 18.

[0125] The semiconductor device 20 has a metal gate electrode formed of a Pfet WF metal layer 16 or a Nfet WF metal layer 17 and a buried metal layer 18 .

[0126] The HK insulating layer 15 is a high-k insulating layer with a higher dielectric constant than that of silicon oxide. As the high-k layer, HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, PbScTaO, etc. can be used. In addition, the HK insulating layer 15 and the silicon oxide film can form a gate insulating film together.

[0127] The buried metal layer 18 is made of a pure metal material, an alloy or a metal compound, and is made of, for example, Ti, Al, Cu, W or an alloy containing the above metals.

[0128] In the Nfet region and the Pfet region, a sidewall spacer 21 is formed at the sidewall of the buried metal layer 18. In addition, in the Pfet region, an offset spacer 19 is formed at the sidewall of the buried metal layer 18 and between the HK insulating layer 15 and the Pfet WF metal layer 16. Therefore, the Pfet region has a multilayer body formed of the HK insulating layer 15, the offset spacer 19, the Pfet WF metal layer 16, and the Nfet WF metal layer 17 from the inner wall of the sidewall spacer 21. In addition, the buried metal layer 18 is formed at the inner side surrounded by the above-mentioned multilayer body.

[0129] The side wall spacer 21 is made of SiN or SiO2, etc., and is formed of a single layer or a multilayer. In addition, the offset spacer 19 uses SiN or SiO2, etc.

[0130] In the Pfet region, the gate length is determined by the formation range of the Pfet WF metal layer 16. Therefore, by forming the Pfet WF metal layer 16 at the inner wall of the HK insulating layer 15 via the offset spacer 19 (that is, the offset spacer 19 is located between the inner wall of the HK insulating layer 15 and the Pfet WF metal layer 16), the formation range of the Pfet WF metal layer 16 can be controlled. By setting the offset spacer 19 to an arbitrary thickness, the Pfet WF metal layer 16 can be formed in an arbitrary size within the opening of the sidewall spacer 21. Therefore, an arbitrary gate length can be set without depending on the size of the opening of the sidewall spacer 21.

[0131] In addition, in addition to Figure 5 In addition to the offset spacers formed only in the Pfet region, the offset spacers may also be formed in both the Pfet region and the Nfet region. In addition, by changing the thickness of the offset spacers in the Pfet region and the Nfet region, each gate length can be optimized.

[0132] In the semiconductor substrate 11 located on both sides of the buried metal layer 18 and directly below the sidewall spacer 21, a source / drain 23 as a P-type impurity diffusion region or a source / drain 24 as an N-type impurity diffusion region is formed. The source / drain 23 and the source / drain 24 form a lightly doped drain (Lightly Doped Drain; LDD) and a halo (neither shown in the figure). In addition, the surface layer of the source / drain 23 and the source / drain 24 exposed from the sidewall spacer 21 becomes silicide. The silicide of the source / drain 23 and the source / drain 24 is formed of, for example, cobalt silicide, nickel silicide or platinum silicide.

[0133] In the semiconductor device of the second embodiment, an offset spacer is formed between the side surfaces of the buried metal layer and the WF metal layer and the side surfaces of the HK insulating layer. Therefore, by changing the thickness of the offset spacer, the formation range of the WF metal layer can be arbitrarily set. Therefore, the gate length can be arbitrarily set using the offset spacer. In this way, even if the dummy gate electrodes are formed into the same pattern in the photolithography process, the semiconductor device can be constructed to have an optimized gate length in each region.

[0134] 4. Semiconductor Device Manufacturing Method of Second Embodiment

[0135] Next, a method for manufacturing a semiconductor device according to the second embodiment will be described.

[0136] In the semiconductor device manufacturing method similar to the first embodiment, Figure 3B The dummy gate electrode removal step shown can realize the semiconductor device manufacturing method of the second embodiment. Therefore, the manufacturing method after the dummy gate electrode is removed will be described below.

[0137] Forming HK insulation layer

[0138] like Fig. 6A As shown, a semiconductor substrate 11 is provided: in the semiconductor substrate 11, a groove is formed in the inner wall of the sidewall spacer 21 after the dummy gate electrode is removed, and an interlayer insulating layer 22, a source / drain 23 and a source / drain 24, an N-well region 13 and a P-well region 14 are formed.

[0139] Next, if Figure 6B As shown, the HK insulating layer 15 is formed over the entire surface of the semiconductor body 11 (including the inner wall sides of the sidewall spacers 21 and the interlayer insulating layer 22 in the Nfet region and the Pfet region).

[0140] The HK insulating layer 15 is formed by an atomic layer deposition (ALD) method or the like. The HK insulating layer 15 is formed using, for example, HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, and PbScTaO. In addition, there are cases where SiO2 is formed as a gate insulating film at the bottom layer of the HK insulating layer 15. In this case, the SiO2 is removed by plasma oxidation.

[0141] Forming an offset spacer

[0142] First, an offset spacer material with a thickness of 1 to 20 nm is formed on the entire surface of the HK insulating layer 15. Figure 6CAs shown in FIG. 1 , the offset spacer material layer is etched back by anisotropic etching, thereby forming an offset spacer 19 only at the inner wall of the trench formed after the dummy gate electrode is removed. Here, in both the Nfet region and the Pfet region, the offset spacer 19 is formed at the inner wall of the trench formed after the dummy gate electrode is removed. SiN or SiO2 or the like is used as the offset spacer material.

[0143] Forming WF metal layer

[0144] After the offset spacers 19 are formed in both the Nfet region and the Pfet region or in only one of the Nfet region and the Pfet region, the Pfet WF (work function) metal layer 16 is formed.

[0145] like Fig. 7A As shown, a Pfet WF metal layer 16 with a thickness of 1 to 20 nm is formed on the HK insulating layer 15 over the entire surface of the semiconductor substrate 11 by CVD, PVD or ALD. The optimum work function of the Pfet WF metal layer 16 is 5.2 eV, and a material with a work function value close to this value is used. For example, an alloy containing Ru, Pd, Pt, Co, Ni, or Mo is used, or an oxide, TiN, or the like is used.

[0146] Next, the Pfet WF metal layer 16 is removed from the Nfet region by dry etching or wet etching. At this time, the HK insulating layer 15 in the Nfet region is not removed but remains. For example, a resist pattern or the like is formed on a portion of the Pfet WF metal layer 16 to be retained in the Pfet region, and the Pfet WF metal layer 16 in the Nfet region is etched away using the resist pattern as a mask. In the case of forming TiN as the Pfet WF metal layer 16, the Pfet WF metal layer 16 is removed from the Nfet region using, for example, ammonia-hydrogen peroxide.

[0147] After the Pfet WF metal layer 16 is removed from the Nfet region, the offset spacer 19 (formed at the inner wall of the trench formed after the dummy gate electrode is removed) is removed from the Nfet region. For example, a wet etching method using an HF solution is adopted and the Pfet WF metal layer 16 is used as a mask to remove the offset spacer 19 formed in the Nfet region. Therefore, the offset spacer 19 is removed from the Nfet region without adding a process such as a photolithography process for forming a pattern mask, so that the offset spacer 19 can be left only in the Pfet region.

[0148] Next, if Figure 7BAs shown, a Nfet WF metal layer 17 having a thickness of 1 to 20 nm is formed on the Pfet WF metal layer 16 and the HK insulating layer 15 by using a CVD method, a PVD method or an ALD method.

[0149] The optimum work function of the Nfet WF metal layer 17 is 4.0 eV, and a material having a work function value close to this value is used, for example, an alloy containing Hf, Zr, Ti, Ta, Al, or carbide, HfSi, etc. is used.

[0150] Buried Gate Metal

[0151] After forming the Pfet WF metal layer 16 and the Nfet WF metal layer 17, as shown in FIG. Figure 7C As shown, a low resistance gate material is buried in the trench formed after the dummy gate electrode is removed, thereby forming a buried metal layer 18. As the low resistance gate material, for example, Ti, Al, Cu, W or an alloy containing the above metals is used.

[0152] As described above, after the dummy gate electrode is removed, the HK insulating layer 15, the offset spacer 19, the Pfet WF metal layer 16, the Nfet WF metal layer 17, and the low-resistance gate material buried in the above-mentioned trench are formed to obtain the buried metal layer 18. In addition, the low-resistance gate material layer, the Nfet WF metal layer 17, the Pfet WF metal layer 16, and the HK insulating layer 15 on the interlayer insulating layer 22 are removed by the CMP method, thereby performing planarization.

[0153] Through such a process, low-resistance gate material remains only in the groove formed after the dummy gate electrode is removed, thereby forming a buried metal layer 18. In addition, in this process, the Nfet WF metal layer 17, the Pfet WF metal layer 16 and the buried metal layer 18 form a metal gate electrode.

[0154] Through the above process, it is possible to produce Figure 5 The semiconductor device 20 shown in the figure. In this manufacturing method, the offset spacer can be removed from the Pfet region immediately after the Pfet WF metal layer is removed. Therefore, compared with the manufacturing method of the first embodiment, it is not necessary to perform a photolithography process for removing the offset spacer 19 from the Nfet region, so that the semiconductor device can be manufactured through a simple manufacturing process.

[0155] 5. Semiconductor Device According to Third Embodiment

[0156] Figure 8 is a schematic structural diagram of a semiconductor device according to a third embodiment. Figure 8 The semiconductor device 30 shown in FIG. Figure 1The same constituent elements as those of the semiconductor device 10 of the first embodiment are given the same reference numerals, and their description will be omitted.

[0157] Figure 8 The semiconductor device 30 shown is provided with an element separation portion 12 made of silicon oxide or the like and used to separate active regions on a semiconductor base 11 formed of, for example, a silicon substrate or the like. In addition, an N-well region 13 is formed in the active region of the PMOS region, and a P-well region 14 is formed in the active region of the NMOS region.

[0158] In the Nfet region, a buried metal layer 18 is formed on the semiconductor substrate 11, and a HK insulating layer 15 and a WF (work function) metal layer 17 for Nfet are formed between the semiconductor substrate 11 and the buried metal layer 18. In addition, in the Pfet region, a buried metal layer 18 is formed on the semiconductor substrate 11, and a HK insulating layer 15 and a WF metal layer 16 for Pfet are formed between the semiconductor substrate 11 and the buried metal layer 18.

[0159] The semiconductor device 30 has a metal gate electrode formed of a Pfet WF metal layer 16 or a Nfet WF metal layer 17 and a buried metal layer 18 .

[0160] The HK insulating layer 15 is a high-k insulating layer with a higher dielectric constant than that of silicon oxide. As the high-k layer, HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, PbScTaO, etc. can be used. In addition, the HK insulating layer 15 and the silicon oxide film can form a gate insulating film together.

[0161] The buried metal layer 18 is made of a pure metal material, an alloy or a metal compound, and is made of, for example, Ti, Al, Cu, W or an alloy containing the above metals.

[0162] In the Nfet region and the Pfet region, a sidewall spacer 21 is formed at the sidewall of the buried metal layer 18. In addition, in the Pfet region, an offset spacer 19 is formed between the HK insulating layer 15 and the Pfet WF metal layer 16 and at the sidewall of the buried metal layer 18. The sidewall spacer 21 is made of SiN or SiO2, etc., and is formed of a single layer or multiple layers. In addition, SiN or SiO2, etc. is used for the offset spacer 19.

[0163] In the Nfet region, a source / drain 24 as an N-type impurity diffusion region is formed in the semiconductor substrate 11 located on both sides of the buried metal layer 18 and directly below the sidewall spacer 21. In addition, in the Pfet region, a raised source / drain portion 27 formed of an epitaxial layer and a source / drain 23 as a P-type impurity diffusion region are formed at positions located on both sides of the buried metal layer 18 and directly below the sidewall spacer 21. The source / drain 23 and the source / drain 24 are formed with LDD and a halo ring (not shown).

[0164] The surface layers of the source / drain 23 and the source / drain 24 and the raised source / drain portion 27 exposed from the sidewall spacer 21 are converted into silicide. The silicide is formed of, for example, cobalt silicide, nickel silicide, or platinum silicide.

[0165] In the Nfet region of the semiconductor device 30 of the third embodiment, only the HK insulating layer 15 and the Nfet WF metal layer 17 are formed at the bottom of the buried metal layer 18. In addition, in the Pfet region, only the HK insulating layer 15 and the Pfet WF metal layer 16 are formed at the bottom of the buried metal layer 18. In addition, the offset spacer 19 is formed on the HK insulating layer 15 and the Pfet WF metal layer 16 and between the metal gate electrode and the sidewall spacer 21.

[0166] Since the offset spacer 19 is formed on the Pfet WF metal layer 16 in the Pfet region of the semiconductor device 30 of the third embodiment, the offset spacer 19 does not affect the formation range of the Pfet WF metal layer 16. Accordingly, it is difficult to adjust the gate length by forming the offset spacer 19. However, by forming an inverted T-shaped gate formed by the Pfet WF metal layer 16 and the metal gate electrode, the gate side wall fringing capacitance can be reduced. In particular, in recent years' stress technology, for example, in the case of applying implanted SiGe to PMOS and implanted SiC to NMOS, the formation of an inverted T-shaped gate can improve the increase in capacitance between gate diffusion layers.

[0167] 6. Semiconductor Device Manufacturing Method According to the Third Embodiment

[0168] Next, a method for manufacturing a semiconductor device according to the third embodiment will be described.

[0169] Forming the element separation portion

[0170] First, if Fig. 9A As shown, an element separation portion 12 is formed in the semiconductor substrate 11 to separate the N-well region 13 from the P-well region 14. Figure 2AThe element separation portion forming step is performed in the same manner as shown.

[0171] Forming HK insulating layer, WF metal layer and dummy gate electrode

[0172] First, a sacrificial oxide film disposed on the semiconductor substrate 11 when the active region is formed is separated from the semiconductor substrate 11 using a hydrogen fluoride (HF) solution. After separation, the HK insulating layer 15 is formed using an atomic layer deposition (ALD) method or the like. The HK insulating layer 15 is formed using HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, and PbScTaO or the like. In addition, there are cases where the bottom layer of the HK insulating layer 15 mainly includes SiO2. In this case, the SiO2 is removed by plasma oxidation.

[0173] Next, a WF (work function) metal layer is formed on the HK insulating layer 15. The WF metal layer is used to form a single metal electrode or separate metal electrodes in NMOS and PMOS. Next, the case of forming different types of WF metal layers in NMOS and PMOS will be described.

[0174] In the Nfet region, a Nfet WF metal layer 17 is formed on the HK insulating layer 15. In addition, in the Pfet region, a Pfet WF metal layer 16 is formed on the HK insulating layer 15.

[0175] The WF metal layer 16 for Pfet and the WF metal layer 17 for Nfet are formed in the range of 1 to 20 nm using TiN by CVD, PVD or ALD. The optimal work function of the WF metal layer 16 for Pfet is 5.2 eV, and a material with a work function value close to this value is used. For example, an alloy containing Ru, Pd, Pt, Co, Ni, Mo, or an oxide, TiN, etc. is used. The optimal work function of the WF metal layer 17 for Nfet is 4.0 eV, and a material with a work function value close to this value is used. For example, an alloy containing Hf, Zr, Ti, Ta, Al, or a carbide, HfSi, etc. is used.

[0176] After forming the WF metal layer 16 for Pfet and the WF metal layer 17 for Nfet, a dummy gate electrode material layer is formed. For example, by depositing polycrystalline silicon or amorphous silicon with a thickness of 50 to 100 nm using a CVD method, a dummy gate electrode material layer is formed on the WF metal layer 16 for Pfet and the WF metal layer 17 for Nfet. Next, a low-pressure chemical vapor deposition (LP-CVD) method is used to deposit Si3N4 with a thickness of, for example, 50 to 100 nm as a hard mask. After the deposition, an electrode pattern is formed on the Si3N4 hard mask using a photolithography process, and then the hard mask pattern is used to anisotropically etch the HK insulating layer 15, the WF metal layer 16 for Pfet, the WF metal layer 17 for Nfet, and the dummy gate electrode material layer. The dummy gate electrode material layer is patterned, so that Fig. 9B As shown, HK insulating layer 15, Nfet WF metal layer 17 and dummy gate electrode 25 are formed in the Nfet region of semiconductor substrate 11. HK insulating layer 15, Pfet WF metal layer 16 and dummy gate electrode 25 are also formed in the Pfet region of semiconductor substrate 11.

[0177] Forming a raised source and drain portion

[0178] Next, if Fig. 9C As shown, sidewall spacers 21 are formed at the sidewalls of dummy gate electrode 25. In addition, P-type source / drain 23 and elevated source / drain portion 27 are formed in N-well region 13, and N-type source / drain 24 is formed in P-well region 14.

[0179] First, the elevated source-drain portion 27 is formed in the Pfet region.

[0180] In other words, a SiN layer covering the dummy gate electrode 25 is formed on the semiconductor substrate 11. Next, a resist pattern is formed to open the Pfet region. The SiN layer is etched back from the resist opening by anisotropic etching, thereby forming a dummy sidewall spacer at the sidewall of the dummy gate electrode 25.

[0181] After the dummy sidewall spacers are formed and the semiconductor substrate 11 of the resist opening is etched, SiGe is selectively grown to form an epitaxial growth layer (epi layer).

[0182] After forming the epi layer made of SiGe, the dummy sidewall spacers and the SiN layer remaining at positions other than the Pfet region are removed, thereby forming the elevated source-drain portion 27 .

[0183] Forming a diffusion area

[0184] In the range of 3-5keV and 5-20×10 14 / cm 2 BF2 + Ions are implanted into the PMOS region to form the PLDD region. 14 / cm 2 Under the condition of + Ions are implanted into the NMOS region to form the NLDD region.

[0185] In addition, in order to suppress the short channel effect, when forming the LDD, a so-called halo ring with an impurity concentration higher than that of the well is also injected into the source / drain. For example, the Nfet region is divided into four regions and B (boron) is used at 12keV, 3×10 13 / cm 2 The Pfet region was divided into four regions and ion implanted at 70 keV, 2×10 13 / cm 2 And inclined ion implantation is performed under 45° conditions.

[0186] Forming side wall spacers

[0187] Next, the sidewall spacers 21 are formed at the sidewalls of the dummy gate electrode 25 .

[0188] Si3N4 is deposited on the semiconductor substrate 11 with a thickness of 50 to 150 nm by plasma CVD to cover the dummy gate electrode 25. Thereafter, anisotropic etching is performed to etch back the Si3N4 layer, thereby forming the sidewall spacer 21 at the sidewall of the dummy gate electrode 25. At this time, the Si3N4 serving as a hard mask for the dummy gate electrode 25 remains.

[0189] Forming a diffusion area

[0190] Next, at 5-10 keV and 1-2×10 15 / cm 2 BF2 + Ions are implanted into the N-well region 13 to form a P-type source / drain 23. + The ion implantation process forms a P-type region composed of B (boron) in the entire region of the raised source and drain portion 27. In addition, at 40 to 50 keV and 1 to 2×10 15 / cm 2 Under the condition of +Ions are implanted into the P-well region 14 to form an N-type source / drain 24. After the ion implantation process, the impurities are activated using RTA (rapid thermal annealing) at 1000° C. for 5 seconds to form Fig. 9C MOSFET shown.

[0191] After forming the MOSFET, the so-called SALICIDE (Self-Aligned Silicide) technology is used to reduce the resistance of the source / drain 23 and the source / drain 24. For example, Ni is deposited on the semiconductor substrate 11 with a thickness of 6 to 8 nm by sputtering. RTA is performed under the conditions of 300 to 500° C. and 10 seconds to form silicide (NiSi) only on the Si of the source / drain 23 and the source / drain 24. After the silicide is formed, the unreacted Ni is removed by a chemical solution such as H2SO4 / H2O2.

[0192] Next, SiN is formed to a thickness of 10 to 100 nm as a contact etching stopper layer (not shown). Two types of SiN may be formed separately to apply different mechanical stresses to NMOS and PMOS in the transistor.

[0193] Furthermore, SiO2 is deposited on the semiconductor substrate 11 to a thickness of 100 to 1000 nm as an interlayer insulating layer 22 covering the dummy gate electrode 25, the sidewall spacer 21, and the elevated source and drain portion 27. The upper portion of the dummy gate electrode 25 is exposed by planarization using a CMP method.

[0194] Remove the dummy gate electrode

[0195] Next, if Fig. 10A As shown, the dummy gate electrode 25 is removed to form an opening inside the sidewall spacer 21. When the dummy gate electrode 25 is formed of polysilicon or amorphous silicon, the dummy gate electrode 25 is removed by dry etching or wet etching using tetramethylammonium hydroxide (TMAH).

[0196] Forming an offset spacer

[0197] Next, if Fig. 10B As shown, an offset spacer 19 is formed on the Pfet WF metal layer 16 at the inner wall of the sidewall spacer 21 in the Pfet region.

[0198] A WF metal layer 16 for Pfet or a WF metal layer 17 for Nfet is present at the bottom of the trench formed after the dummy gate electrode is removed. An offset spacer material in the range of 1 to 20 nm is formed to cover the trench formed after the dummy gate electrode is removed. In addition, anisotropic etching is performed to etch back, thereby forming an offset spacer at the inner wall of the trench formed after the dummy gate electrode is removed. The material of the offset spacer is SiN or SiO2, etc.

[0199] Thereafter, the offset spacers are removed from the Nfet region by a wet etching method using an HF solution.

[0200] Buried Gate Metal

[0201] After forming the offset spacer 19, as shown in FIG. Fig. 10C As shown, a low resistance gate material is buried in the trench formed after the dummy gate electrode is removed, thereby forming a buried metal layer 18. As the low resistance gate material, for example, Ti, Al, Cu, W or an alloy containing the above metals is used.

[0202] After forming the offset spacer 19 in the groove formed after removing the dummy gate electrode, a low-resistance gate material is buried in the groove to form a low-resistance gate material layer on the Pfet WF metal layer 16 or the Nfet WF metal layer 17, thereby obtaining a buried metal layer 18. In addition, the low-resistance gate material layer on the interlayer insulating layer 22 is removed by the CMP method, thereby performing planarization. Through such a process, the low-resistance gate material remains only in the groove formed after removing the dummy gate electrode, thereby forming a buried metal layer 18.

[0203] Through the above process, it is possible to produce Figure 8 The semiconductor device 30 shown. According to the present manufacturing method, the WF metal layer 16 for Pfet is formed in the groove formed after the dummy gate electrode is removed before the offset spacer 19. Therefore, the purpose of forming the offset spacer 19 is not to adjust the gate length but to reduce the gate sidewall edge capacitance. Since the offset spacer 19 is formed between the metal gate electrode and the sidewall spacer 21, the area of ​​the metal gate electrode is formed to be smaller than the area of ​​the WF metal layer 16 for Pfet, so that an inverted T-shaped gate is formed by the WF metal layer 16 for Pfet and the metal gate electrode. In particular, in recent years' stress technology, for example, when implanted SiGe is applied to PMOS and implanted SiC is applied to NMOS, the formation of an inverted T-shaped gate can improve the increase in capacitance between gate diffusion layers.

[0204] 7. Semiconductor Device According to Fourth Embodiment

[0205] Fig.11A and Fig. 11B is a schematic structural diagram of a semiconductor device according to a fourth embodiment. Fig.11A is a plan view of a semiconductor device according to a fourth embodiment, Fig. 11B It is along Fig.11A A cross-sectional view of the semiconductor device taken along line AA′. Fig.11A and Fig. 11B The semiconductor device 40 shown includes an Nfet region and a Pfet region having a fin structure. In addition, in the structure of the semiconductor device 40, an offset spacer is formed in one gate electrode. In addition, in the following description, the first conductivity type of the semiconductor device is P type, and the second conductivity type of the semiconductor device is N type.

[0206] exist Fig.11A In the semiconductor device 40 shown, thin semiconductor layers (fins) 42 and 43 are formed in a raised manner in the Pfet region and the Nfet region, respectively. In addition, the channel region of the fin 42 and the channel region of the fin 43 are covered with a gate electrode 44. In this way, a fin-type field effect transistor (finFET) having a structure in which the gate electrode 44 is inserted into the channel region of the fin 42 and the channel region of the fin 43 from both sides is formed. For example, an oxide insulating layer 41 is formed on a semiconductor base formed of a silicon substrate (not shown), and thin semiconductor layers (fins) 42 and 43 raised from the oxide insulating layer 41 are formed. In addition, the fin 42 in the Pfet region has a source / drain in which a P-type impurity is diffused, and the fin 43 in the Nfet region has a source / drain in which an N-type impurity is diffused.

[0207] Next, we will explain Fig. 11B The structure of the gate electrode 44 of the semiconductor device 40 is shown.

[0208] The gate electrode 44 is formed in a U shape and covers the channel regions of the fins 42 and 43 from one side to the other. The structure of the gate electrode of the semiconductor device 40 is different in the Pfet region and the Nfet region.

[0209] In the Pfet region, a buried metal layer 48 is formed on the oxide insulating layer 41, and a HK insulating layer 45, a Pfet WF metal layer 46, and a Nfet WF metal layer 47 are formed between the oxide insulating layer 41 and the buried metal layer 48. In addition, in the Nfet region, a buried metal layer 48 is formed on the oxide insulating layer 41, and a HK insulating layer 45 and a Nfet WF (work function) metal layer 47 are formed between the oxide insulating layer 41 and the buried metal layer 48.

[0210] The semiconductor device 40 includes a metal gate electrode 44 formed of a Pfet WF metal layer 46 or a Nfet WF metal layer 47 and a buried metal layer 48 .

[0211] The HK insulating layer 45 is a high-k insulating layer with a higher dielectric constant than that of silicon oxide. As the high-k layer, HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, PbScTaO, etc. can be used. In addition, the HK insulating layer 45 and the silicon oxide film can form a gate insulating film together.

[0212] The buried metal layer 48 is made of a pure metal material, an alloy, or a metal compound, and is made of, for example, Ti, Al, Cu, W, or an alloy containing the above metals.

[0213] In both the Nfet region and the Pfet region, a sidewall spacer 51 is formed at the sidewall of the buried metal layer 48. In addition, in the Pfet region, an offset spacer 49 is formed at the lower portion of the inner wall of the HK insulating layer 45 and the sidewall spacer 51. Therefore, the Pfet region has a multilayer body formed of the offset spacer 49, the HK insulating layer 45, the Pfet WF metal layer 46, and the Nfet WF metal layer 47 from the inner wall of the sidewall spacer 51. In addition, the buried metal layer 48 is formed at the inner side surrounded by the above-mentioned multilayer body.

[0214] The side wall spacer 51 is made of SiN or SiO2, etc., and is formed of a single layer or a multilayer. In addition, the offset spacer 49 uses SiN or SiO2, etc.

[0215] The offset spacer 49 is formed only at the lower portion of the inner wall of the sidewall spacer 51. In addition, the offset spacer 49 is formed to a position higher than the upper portion of the fin 42. Therefore, in the portion where the fin 42 is formed, the HK insulating layer 45, the Pfet WF metal layer 46, and the sidewall spacer 51 are connected to the fin 42 only via the offset spacer 49.

[0216] The size of the opening of the sidewall spacer is determined by patterning the gate electrode in a photolithography process, and therefore the same pattern is preferred.

[0217] This is because: in the case of processing fine patterns, it is desirable to design the patterning according to a constant rule for ease of manufacturing. In both the Nfet region and the Pfet region, the opening of the sidewall spacer is preferably formed to have the same size. However, if the opening of the sidewall spacer in both the Nfet region and the Pfet region is the same as each other, it may not be possible to optimize the gate length to match the respective diffusion layer profiles.

[0218] Therefore, the size of the opening is adjusted by forming an offset spacer 49 inside the opening of the sidewall spacer. The gate length of the Pfet region can be adjusted by forming the offset spacer 49 between the Pfet WF metal layer 46 and the sidewall spacer 51. In addition, in the above-mentioned opening, the formation range of the Pfet WF metal layer 46 is adjusted using the offset spacer 49, so that the gate length can be optimized at an arbitrary length.

[0219] In addition, in the case of a fin-type semiconductor device, the gate electrode bottom and gate sidewall shape affect the gate length. Therefore, when the inner wall of the sidewall spacer where the gate electrode is formed is tapered or there is roughness in the sidewall, the gate length is different, making it difficult to optimize.

[0220] On the other hand, in the semiconductor device of the fourth embodiment, an offset spacer 49 is formed at the inner wall side of the sidewall spacer 51, specifically, between the sidewall spacer 51 and the HK insulating layer 45 or between the HK insulating layer 45 and the Pfet WF metal layer 46. With such a structure, for example, in the case where there is roughness in the inner wall of the sidewall spacer 51, the inner wall of the sidewall spacer 51 where the fin 42 is formed can be flattened by the offset spacer 49. In addition, for example, even if the inner wall of the sidewall spacer 51 is tapered, the inner wall of those portions where the fin 42 is formed can be made vertical by forming the offset spacer 49, thereby enabling adjustment of the gate length.

[0221] In addition, in addition to Fig. 11B In addition to forming the offset spacer only in the Pfet region as shown, the offset spacer can also be formed in both the Pfet region and the Nfet region. In this case, by changing the thickness of the offset spacer in the Pfet region and the Nfet region, the respective gate lengths can be arbitrarily set.

[0222] As shown in the semiconductor device of the fourth embodiment, the gate electrode structure of the semiconductor device having the same planar structure as that of the first or second embodiment can be applied to a semiconductor device having a fin structure. In addition, the gate length can be optimized by changing the thickness of the offset spacer. Therefore, even if the dummy gate electrode and the sidewall spacer are formed into the same pattern in the photolithography process, the semiconductor device can be configured to have an optimized gate length in each region.

[0223] 8. Semiconductor device manufacturing method according to the fourth embodiment

[0224] Next, a semiconductor device manufacturing method according to a fourth embodiment will be described. The semiconductor device manufacturing method according to the fourth embodiment can be performed using the same process except that the semiconductor device manufacturing method according to the first embodiment described above is applied to a fin-type semiconductor device. In the following description, detailed descriptions of the same processes as those in the semiconductor device manufacturing method according to the first embodiment will be omitted.

[0225] Forming the fin

[0226] First, if Fig. 12A As shown, fins 42 and fins 43 are formed on oxide insulating layer 41 .

[0227] The fin 42 is formed in the Pfet region by a method well known in the art. In addition, the fin 43 is formed in the Nfet region. For example, a semiconductor layer such as silicon is deposited, and ions of P-type impurities or N-type impurities are implanted into the semiconductor layer to form source / drain electrodes, and etching is performed to give it a predetermined fin shape.

[0228] Forming a dummy gate electrode

[0229] Next, a gate insulating film and a dummy gate electrode are formed in the Nfet region and the Pfet region of the oxide insulating layer 41 .

[0230] First, a gate insulating film with a thickness of 1 to 3 nm is formed on the surface of the fin 42 and the fin 43 by dry oxidation (O2, 700°C). Next, a pseudo gate electrode material layer is formed by a CVD method. For example, a pseudo gate electrode material layer is formed on the oxide insulating layer 41 by depositing polycrystalline silicon or amorphous silicon with a thickness of 50 to 100 nm. After the deposition, a resist pattern is formed by a photolithography process, and then the pseudo gate electrode material layer is anisotropically etched using the hard mask pattern. The pseudo gate electrode material layer is patterned so that Fig. 12A A dummy gate electrode 53 is formed on the oxide insulating layer 41 as shown.

[0231] Forming side wall spacers

[0232] Next, the sidewall spacers 51 are formed at the sidewalls of the dummy gate electrode 53 .

[0233] Si3N4 is deposited on the oxide insulating layer 41 by plasma CVD to a thickness of 50 to 150 nm to cover the dummy gate electrode 53. Thereafter, the Si3N4 layer is anisotropically etched back to form sidewall spacers 51 at the sidewalls of the dummy gate electrode 53.

[0234] In addition, SiO2 with a thickness of 100 to 1000 nm is deposited on the oxide insulating layer 41 as an interlayer insulating layer 52 covering the dummy gate electrode 53 and the sidewall spacer 51. Fig. 12B As shown, planarization is performed using a CMP method to expose the upper portion of the dummy gate electrode 53 .

[0235] Remove the dummy gate electrode

[0236] Next, if Fig. 12C As shown, the dummy gate electrode 53 is removed, thereby forming an opening inside the sidewall spacer 51, thereby exposing the fin 42 and the fin 43. In the case where the dummy gate electrode 53 is formed of polysilicon or amorphous silicon, the dummy gate electrode 53 is removed by a dry etching method or a wet etching method using tetramethyl ammonium hydroxide (TMAH). At this time, SiO2 formed as a gate insulating film under the dummy gate electrode 53 is also removed by a wet etching method or the like.

[0237] Forming an offset spacer

[0238] Next, if Fig.13A As shown, in the trench formed after the dummy gate electrode is removed in the Pfet region, an offset spacer 49 is formed at the inner wall of the sidewall spacer 51.

[0239] First, an offset spacer material in the range of 1 to 20 nm is formed over the entire surface of the oxide insulating layer 41 (inside the inner wall opening of the sidewall spacer 51 and on the exposed fins 42 and 43). SiN or SiO2 is used as the offset spacer material. In addition, the offset spacer material layer is etched back by anisotropic etching.

[0240] In the process of etching back the offset spacer material layer, over-etching is performed until the offset spacer material layer formed at the sidewalls of the fins 42 and 43 exposed from the openings of the sidewall spacers 51 is removed. By such etching, the offset spacers 49 can be formed only at the inner wall sides of the sidewall spacers 51, and no offset spacers are left at the sidewalls of the fins 42 and 43.

[0241] At this time, the height of the dummy gate electrode 53 and the height of the sidewall spacer 51 need to be formed to be more than twice the height of the fin. With a height more than twice the height of the fin, when overetching is performed until the offset spacer material layer formed on the sidewalls of the fins 42 and 43 is removed, the offset spacer 49 can be left with a height higher than the formation height of the fins 42 and 43 in the sidewall spacer 51.

[0242] In addition, in the same manner as the semiconductor device manufacturing method of the first embodiment, the gate insulating layer may be removed after the offset spacer 49 is formed, instead of removing the gate insulating film in the process of removing the dummy gate electrode.

[0243] After the offset spacer 49 is formed, a resist layer is formed over the entire surface of the oxide insulating layer 41, and a resist pattern is formed for forming an opening in the Nfet region in the trench formed after the dummy gate electrode is removed. The offset spacer formed at the inner wall of the sidewall spacer 51 in the Nfet region is removed by wet etching using an HF solution.

[0244] Forming HK insulation layer

[0245] Next, if Fig. 13B As shown, the gate insulating layer is formed using the HK insulating layer 45 .

[0246] The HK insulating layer 45 is formed on the entire surface of the interlayer insulating layer 52 by an atomic layer deposition (ALD) method or the like so as to cover the opening of the sidewall spacer 51. The HK insulating layer 45 is formed using, for example, HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, PbScTaO, or the like.

[0247] Forming WF metal layer

[0248] After forming the HK insulating layer 45, a WF (work function) metal layer is formed. The WF metal layer is used to form a single metal electrode or separate metal electrodes in NMOS and PMOS. Here, the case of forming different WF metal layers in NMOS and PMOS will be explained.

[0249] First, a WF metal layer 46 for Pfet is formed.

[0250] like Fig. 13B As shown, a Pfet WF metal layer 46 with a thickness of 1 to 20 nm is formed on the HK insulating layer 45 by CVD, PVD or ALD. The optimum work function of the Pfet WF metal layer 46 is 5.2 eV, and a material with a work function value close to this value is used. For example, an alloy containing Ru, Pd, Pt, Co, Ni, or Mo, or an oxide, TiN, etc. is used.

[0251] Next, the Pfet WF metal layer 46 is removed from the Nfet region by dry etching or wet etching. At this time, the HK insulating layer 45 in the Nfet region is not removed but remains. For example, a resist pattern is formed on a portion of the Pfet region where the Pfet WF metal layer 46 is to be retained, and the Pfet WF metal layer 46 in the Nfet region is etched away using the resist pattern as a mask. In the case of forming TiN as the Pfet WF metal layer 46, the Pfet WF metal layer 46 is removed from the Nfet region using, for example, ammonia-hydrogen peroxide.

[0252] Next, a Nfet WF metal layer 47 is formed in a range of 1 to 20 nm on the Pfet WF metal layer 46 and the HK insulating layer 45 by CVD, PVD or ALD. The optimal work function of the Nfet WF metal layer 47 is 4.0 eV, and a material with a work function value close to this value is used. For example, an alloy containing Hf, Zr, Ti, Ta, Al, or carbide, HfSi, etc. is used.

[0253] Buried Gate Metal

[0254] After forming the Pfet WF metal layer 46 and the Nfet WF metal layer 47, as shown in FIG. Fig. 13C As shown, a low resistance gate material is buried in the trench formed after the dummy gate electrode is removed, thereby forming a buried metal layer 48. As the low resistance gate material, for example, Ti, Al, Cu, W, or an alloy containing the above metals is used.

[0255] As described above, after the offset spacer 49, the HK insulating layer 45, the Pfet WF metal layer 46, and the Nfet WF metal layer 47 are formed in the trench formed after the dummy gate electrode is removed, a low-resistance gate material is buried in the trench to form a low-resistance gate material layer, thereby obtaining a buried metal layer 48. In addition, the low-resistance gate material layer, the Nfet WF metal layer 47, the Pfet WF metal layer 46, and the HK insulating layer 45 on the interlayer insulating layer 52 are removed by the CMP method, thereby performing planarization.

[0256] Through such a process, the low-resistance gate material is left only in the groove formed after the dummy gate electrode is removed, thereby forming the buried metal layer 48. In addition, in this process, when the buried metal layer 48 is formed, the Nfet WF metal layer 47, the Pfet WF metal layer 46 and the HK insulating layer 45 continuously formed on the interlayer insulating layer 52 are removed, and the Nfet WF metal layer 47, the Pfet WF metal layer 46 and the HK insulating layer 45 are left only in the above-mentioned groove.

[0257] Through the above process, it is possible to produce Fig.11A and Fig. 11B The semiconductor device 40 shown. According to the present manufacturing method, by adding a step for forming a fin-type semiconductor layer, a fin-type semiconductor device can be manufactured according to the same manufacturing process as the manufacturing process of the first embodiment. In addition, the gate length can be optimized by forming an offset spacer between the inner wall of the sidewall spacer and the WF metal layer.

[0258] Although in the semiconductor device of the fourth embodiment, the offset spacers are formed between the inner wall of the sidewall spacer and the HK insulating layer in the same manner as in the first embodiment, there is no particular limitation on the formation position of the offset spacers as long as the offset spacers are located between the inner wall of the sidewall spacer and the WF metal layer. For example, in the same manner as in the semiconductor device of the second embodiment, the offset spacers may be formed between the HK insulating layer and the WF metal layer on the inner side of the inner wall of the sidewall spacer.

[0259] In this case, if you refer to Fig. 12C As described above, the dummy gate electrode is removed, and then the HK insulating layer is formed in the trench formed after the dummy gate electrode is removed. Fig.13A As described above, after forming an offset spacer material layer having a height more than twice the height of the fin on the HK insulating layer, the offset spacer material is etched back to form an offset spacer only on the inner wall side of the sidewall spacer. Fig. 13B and Fig. 13C As described above, a WF metal layer and a buried metal layer are formed in the above-mentioned groove. In this way, by applying the semiconductor device manufacturing method of the second embodiment to the semiconductor device manufacturing method of the fourth embodiment, a fin-type semiconductor device in which an offset spacer is formed between the HK insulating layer and the WF metal layer can be manufactured.

[0260] The present invention is not limited to the structures described in the above-mentioned embodiments, and various modifications and changes can be made within the scope not departing from the structure of the present invention.

Claims

1. A semiconductor device comprising a first transistor and a second transistor, The first transistor and the second transistor each include: a gate insulating film formed on a substrate; a metal gate electrode formed on the gate insulating film; as well as a sidewall spacer formed at a sidewall of the metal gate electrode, wherein, in any one of the first transistor and the second transistor, an offset spacer is formed between the side wall of the metal gate electrode and the inner wall of the side wall spacer, Each of the first transistor and the second transistor includes a fin-type field effect transistor having a fin, and the offset spacer is formed only at a lower portion of an inner wall of the sidewall spacer and is formed up to a position higher than an upper portion of the fin.

2. The semiconductor device according to claim 1, wherein The offset spacers are formed with different thicknesses in the first transistor and the second transistor.

3. The semiconductor device according to claim 1, wherein The first transistor is of a first conductivity type, and the second transistor is of a second conductivity type, which is different from the first conductivity type.

4. The semiconductor device according to claim 1, wherein The distance between the sidewall spacers in the first transistor in the longitudinal direction of the gate is the same as the distance between the sidewall spacers in the second transistor in the longitudinal direction of the gate.

5. The semiconductor device according to claim 1, wherein The distance between the side wall of the metal gate electrode of the first transistor and the corresponding side wall spacer of the metal gate electrode of the first transistor is greater than the distance between the side wall of the metal gate electrode of the second transistor and the corresponding side wall spacer of the metal gate electrode of the second transistor.

6. The semiconductor device according to claim 1, wherein The offset spacers include silicon nitride.

7. The semiconductor device according to claim 1, wherein The metal gate electrode and the offset spacer are arranged on a channel portion of the fin field effect transistor.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The metal gate electrode of the first transistor includes a buried metal layer and a WF metal layer.

9. The semiconductor device according to any one of claims 1 to 7, wherein: The metal gate electrode of the second transistor includes a buried metal layer and a WF metal layer.

10. The semiconductor device according to any one of claims 1 to 7, wherein: The metal gate electrode includes a plurality of metal layers, and the plurality of metal layers includes at least a first metal layer and a second metal layer.

11. The semiconductor device according to claim 10, wherein The first metal layer includes W.

12. The semiconductor device according to claim 10, wherein: The first metal layer is a buried metal layer.

13. The semiconductor device according to claim 10, wherein: The second metal layer includes TiN.

14. The semiconductor device according to claim 10, wherein: The plurality of metal layers of the metal gate electrode of the first transistor further include a third metal layer, the third metal layer including at least titanium (Ti), aluminum (Al), and carbon (C).

15. The semiconductor device according to claim 14, wherein: The third metal layer includes carbides of Ti and Al.

16. The semiconductor device according to any one of claims 1 to 7, wherein: The offset spacer includes at least silicon (Si) and oxygen (O).

17. The semiconductor device according to claim 1, wherein: A gate length of the metal gate electrode of the first transistor is smaller than a gate length of the metal gate electrode of the second transistor.

18. The semiconductor device according to claim 1, wherein The first transistor is a P-type field effect transistor; and The second transistor is an N-type field effect transistor.

19. The semiconductor device according to claim 1, further comprising: a substrate carrying the first transistor and the second transistor; as well as An element isolation region is in the substrate, and the element isolation region is located between the first transistor and the second transistor.

20. The semiconductor device according to claim 1, further comprising: An insulating film is located between a side wall of one of the metal gate electrodes and the side wall spacer corresponding to the metal gate electrode.

21. The semiconductor device according to claim 20, wherein: The insulating film is made of a high dielectric constant material.

22. The semiconductor device according to claim 21, wherein The insulating film includes a combination of HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, or PbScTaO.

23. The semiconductor device according to claim 8, wherein The WF metal layer of the first transistor is formed on the gate insulating film, the buried metal layer is formed on the WF metal layer of the first transistor, and the offset spacer is formed at a sidewall of the buried metal layer on the WF metal layer of the first transistor.

24. The semiconductor device according to claim 7, wherein: The sidewall spacer is in contact with the fin.

25. The semiconductor device according to claim 1, wherein The sidewall spacers and the offset spacers include N and Si.

26. The semiconductor device according to claim 1, further comprising: An interlayer insulating layer is adjacent to the sidewall spacer.

27. The semiconductor device according to claim 1, wherein Each of the sidewall spacers and the offset spacers of the first transistor is formed of a single layer.

28. The semiconductor device according to claim 1, wherein The sidewall spacer includes multiple layers.

29. The semiconductor device according to claim 24, wherein: In the first transistor, a distance between a sidewall of the metal gate electrode and the sidewall spacer adjacent to the sidewall is smaller at a top of the sidewall than at a bottom of the sidewall.

30. The semiconductor device according to claim 29, wherein A top portion of the metal gate electrode of the first transistor is arranged to be higher than a top portion of the offset spacer of the first transistor.

31. The semiconductor device according to claim 30, wherein: A height of the sidewall spacer of the first transistor is at least twice a height of the fin of the first transistor.

32. The semiconductor device according to claim 14, wherein: The third metal layer in the first transistor and the third metal layer in the second transistor are deposited in a same deposition step.

33. The semiconductor device according to claim 14, wherein: The first metal layer, the third metal layer and the second metal layer are sequentially arranged in the first transistor.

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