A digital passive phase shifter with gain flattening

Abstract

The present invention relates to a gain flattened digital passive phase shifter, comprising a main phase shifter, a buffer, a gain flatness adjustment amplifier and a digital control circuit. A differential radio frequency signal enters the main phase shifter for phase shifting, then passes through the buffer, and then adjusts the gain flatness through the gain flatness adjustment amplifier and outputs it; a digital control signal is simultaneously transmitted to the main phase shifter and the digital control circuit, the control signal transmitted to the main phase shifter generates the required phase shift, and the control signal transmitted to the digital control circuit is converted into a gain flatness control signal for controlling the gain flatness adjustment amplifier through the digital control circuit. The present application adds a digital control circuit, a buffer and a gain flatness adjustment amplifier to keep the gain curve of the overall circuit flat and consistent in all phase shift states; the control signal of the main phase shifter is also used to control the digital control circuit, so the design does not add an additional control interface and has a high degree of integration.

Description

Technical Field

[0001] The invention relates to the field of radio frequency microwave integrated circuit design, and in particular to a gain flattened digital passive phase shifter. Background Art

[0002] As a key component in the phased array system, the phase shifter has a decisive influence on the performance of the phased array system. Since a phased array system is equipped with a large number of phase shifters in the transceiver link, low-cost, low-power, small-volume, and light-weight phase shifters are essential. Traditional phase shifters mostly use compound processes, which have high electron mobility and passive device Q values, low insertion loss, but high cost. The use of silicon processes can greatly reduce costs, and digital and analog circuits can be integrated on the same die, thereby increasing the integration and reliability of the phased array system. According to the control method, phase shifters can be divided into analog phase shifters and digital phase shifters. The former can provide continuously changing phase shifts with low insertion loss; the latter can provide a set of discrete phase shifts, is not easily affected by noise on the control voltage and ambient temperature, and is more widely used. According to the device type, phase shifters can be divided into active phase shifters and passive phase shifters. The former has a smaller area; the latter has lower power consumption, a larger dynamic range, and higher linearity.

[0003] Digital passive phase shifters are generally formed by cascading switch networks. Each stage uses a switch to switch the high / bandpass branch or the low-pass branch. The phase difference between the two branches is the phase shift of the stage. The total phase shift is obtained by controlling the switching state of each stage. For different branches, the gain (towards frequency) curve is different: the high-pass branch has a gain curve with high-pass characteristics, that is, low low-frequency gain and high high-frequency gain; the low-pass branch is the opposite; the bandpass branch has a gain curve with bandpass characteristics, which is relatively flat within the band. The overall gain curve is the superposition of the gain curves of each stage. Therefore, the disadvantage of this structure is that the gain curve cannot remain flat and consistent under different switching states, resulting in a narrow working bandwidth of the phase shifter, affecting the performance of the entire phased array system. Summary of the invention

[0004] In order to solve the existing technical problems, the present invention provides a digital passive phase shifter with flat gain which does not increase the system insertion loss, does not affect the input impedance, and does not add an additional control interface.

[0005] The specific contents of the present invention are as follows: A gain flattened digital passive phase shifter comprises a main phase shifter, a buffer, a gain flatness adjustment amplifier and a digital control circuit. A differential radio frequency signal enters the main phase shifter for phase shifting, passes through the buffer, and then adjusts the gain flatness through the gain flatness adjustment amplifier and outputs the signal. A digital control signal is simultaneously transmitted to the main phase shifter and the digital control circuit. The control signal transmitted to the main phase shifter generates a required phase shift, and the control signal transmitted to the digital control circuit is converted into a gain flatness control signal for controlling the gain flatness adjustment amplifier through the digital control circuit.

[0006] Furthermore, the main phase shifter includes two half-circuits, each half-circuit includes M-level phase shift units, and the phase shift values ​​of each unit are 180°, 90°, ... (180 / 2 M-1 )°.

[0007] Furthermore, each phase shift unit includes a high-pass / band-pass branch or a high-pass / low-pass branch. The phase shift unit selects the branch by a switch, and the phase shift unit of each level is switched to achieve a step from 0° to 360° (180 / 2 M-1 )° phase shift.

[0008] Furthermore, the switch includes a series MOS tube structure, and each stage of the phase shift unit corresponds to a control bit. When the control bit is at a high level, the high-pass branch or the band-pass branch of the corresponding stage of the phase shift unit is enabled; when the control bit is at a low level, the low-pass branch of the corresponding stage of the phase shift unit is enabled.

[0009] Further, the buffer includes MOS tubes M9 to M12, resistors R1, R2 and capacitors C1, C2; the source of MOS tubes M9 and M10 is connected to the drain of MOS tubes M11 and M12 and the positive end of capacitors C1 and C2, the drain of MOS tubes M9 and M10 is connected to the power supply, the source of MOS tubes M11 and M12 is grounded, and the gate is connected to the bias power supply V bias The positive ends of resistors R1 and R2 are connected to the gates of MOS tubes M9 and M10, and the negative ends are connected to the power supply. The signal enters from the gates of M9 and M10, flows out from the sources of M9 and M10, and is output to the subsequent circuit through capacitors C1 and C2.

[0010] Furthermore, the gain flatness adjustment amplifier includes a common source amplifier structure in the form of feedback, and the high-frequency gain is adjusted by a switch capacitor connected in parallel to the load end, and the low-frequency gain is adjusted by a switch capacitor connected in series to the input end.

[0011] Furthermore, the gain flatness adjustment amplifier includes a gain flatness control switch and a gain flatness adjustment capacitor, and the gain flatness control switch controls the bypass and gating of the gain flatness adjustment capacitor.

[0012] Furthermore, the input signal of the digital control circuit is the control signal of the main phase shifter, and the output signal is the switch control signal of the gain flatness adjustment amplifier, and the switch control signal controls the switch capacitor connected in parallel at the load end and the switch capacitor connected in series at the input end respectively.

[0013] The gain-flattened digital passive phase shifter of the present application keeps the gain curve of the overall circuit flat and consistent in all phase shift states by adding a digital control circuit, a buffer and a gain flatness adjustment amplifier; the control signal of the main phase shifter is also used to control the digital control circuit, so the design does not add any additional control interface and has a high degree of integration; the buffer makes the phase shifter less susceptible to the influence of the subsequent circuit and keeps the input impedance of the overall circuit unchanged; the gain flatness adjustment amplifier is not only used to adjust the gain flatness, but also can compensate for the insertion loss of the main phase shifter and the buffer, so the insertion loss of the overall circuit will not be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The specific implementation of the present invention will be further explained below in conjunction with the accompanying drawings.

[0015] Figure 1 It is a structural schematic diagram of a gain flattening digital passive phase shifter of the present invention;

[0016] Figure 2 is a schematic diagram of the main phase shifter in the present invention;

[0017] Figure 3 It is the principle diagram of the buffer in the present invention;

[0018] Figure 4 The schematic diagram of the gain flatness adjustment amplifier in the present invention;

[0019] Figure 5 It is the principle diagram of the digital control circuit in the present invention;

[0020] Figure 6 A gain comparison simulation diagram of the overall circuit of the present invention and the main phase shifter;

[0021] Figure 7 It is a simulation diagram comparing the relative gain RMS of the overall circuit of the present invention and the main phase shifter. DETAILED DESCRIPTION

[0022] like Figure 1As shown, this embodiment discloses a gain flattened digital passive phase shifter, including a main phase shifter, a buffer, a gain flatness adjustment amplifier and a digital control circuit. The differential RF signal enters from the main phase shifter, passes through the buffer and the gain flatness adjustment amplifier to reach the output, and the six-bit digital control signal is simultaneously transmitted to the main phase shifter and the digital control circuit. The former is used to generate the required phase shift, and the latter generates a set of control signals through the digital control circuit and transmits them to the gain flatness adjustment amplifier to control its adjustment state, wherein:

[0023] The main phase shifter is used to achieve phase shifting; it is composed of M-stage phase shifting units cascaded, and each stage adopts a high / low pass or band / low pass structure;

[0024] The buffer is used to isolate the main phase shifter and the gain flatness adjustment amplifier and provide a stable load for the main phase shifter; it adopts a source follower structure;

[0025] A gain flatness adjustment amplifier is used to adjust the gain flatness of the overall circuit and compensate for the insertion loss of the main phase shifter and the buffer. The amplifier adjusts the gain flatness by connecting a switched capacitor in series at the input end and connecting a switched capacitor in parallel at the load.

[0026] The digital control circuit is used to control the gain flatness adjustment amplifier to make the gain curve of the overall circuit flat and consistent; the digital control circuit is composed of logic gate circuits.

[0027] This embodiment is preferred, such as Figure 2 As shown, the main phase shifter adopts a fully differential structure, including two identical half-side circuits, and the RF signal Rf in After passing through the two half-side circuits, it is converted into the output signal RF out The structure of the half-side circuit is as follows:

[0028] It includes M-stage phase shifting units connected in cascade, and the phase shifting values ​​of each phase shifting unit are 180°, 90°, etc. (180 / 2 M-1 )°, and the value of M is generally 4 to 6. The phase shift unit includes a high / low pass structure and a band / low pass structure, and each phase shift unit is controlled by a switch.

[0029] In this embodiment, the value of M is 6, and the half-side circuit has 6 levels of phase shift units. According to the flow direction of the signal, the phase shift values ​​of each phase shift unit are 90°, 45°, 11.25°, 5.625°, 22.5° and 180° respectively. Among them, the 90° and 180° phase shift units adopt a high / low pass structure, and the other units adopt a band / low pass structure. The high-pass structure includes two capacitors connected in series between the input and output terminals and an inductor grounded between the two capacitors. The low-pass structure includes an inductor between the input and output terminals and a grounded capacitor at both ends of the inductor. The band-pass structure includes a capacitor and an inductor connected in series between the input and output terminals. Each phase shift unit corresponds to a control bit, with a total of V b180 、V b90 、V b45 、V b22 、V bl1 and V b5 The six control bits correspond to phase shift units with phase shift values ​​of 180°, 90°, 45°, 22.5°, 11.25°, and 5.625°, respectively.

[0030] The switches of the main phase shifter include two paths, each of which includes a MOS tube in a series-parallel structure. The series tube is used to control the on-off of the branch, and the parallel tube is used to improve the reverse isolation. Taking the switches at both ends of the 45° phase shift unit as an example, its structure is as follows:

[0031] The switch includes two paths (upper path and lower path), which are connected to the bandpass structure and the low-pass structure respectively. The switch includes MOS tubes M1~M8, of which M1~M4 are series tubes used to control the on and off of the branch, and M5~M8 are parallel tubes used to improve reverse isolation. The gate and substrate of MOS tubes M1~M8 are each connected to a large resistor to reduce insertion loss and improve linearity. The gate control position of MOS tubes M1 and M2 in the upper path and MOS tubes M7 and M8 in the lower path is V b45 , the control bits of MOS tubes M5 and M6 in the upper path and MOS tubes M7 and M8 in the lower path are When the control bit V b45 When it is at a high level, M1, M2, M7 and M8 are turned on, M3, M4, M5 and M6 are turned off, the upper branch of the unit, i.e. the passband branch, is enabled, and the lower branch, i.e. the low-pass branch, is disconnected; when the control bit is at a low level, M1, M2, M7 and M8 are turned off, M3, M4, M5 and M6 are turned on, the upper branch of the unit is enabled, and the lower branch is disconnected.

[0032] The digital passive phase shifter structure has low power consumption, high linearity, and is insensitive to noise on the control voltage and ambient temperature; the fully differential structure can suppress common-mode interference and greatly reduce the impact of the ground line on the performance of the phase shifter; the main phase shifter adopts a fully differential structure, and the half-side circuit consists of six phase shifting units; each phase shifting unit adopts a high / low pass or band / low pass structure, and switches the state through a MOS switch; the MOS switch adopts a series-parallel structure, and the parallel tubes are used to improve the reverse isolation; the gate and substrate of each MOS tube in the MOS switch are each connected to a large resistor to reduce insertion loss and improve linearity.

[0033] like Figure 3 As shown, the buffer of this embodiment adopts a fully differential source follower structure, including MOS tubes M9 to M12, resistors R1, R2 and capacitors C1, C2. The source of the source follower tubes M9 and M10 is connected to the drain of the current source tubes M11 and M12 and the positive end of the output DC blocking capacitors C1 and C2, the drain of M9 and M10 is connected to the power supply, the source of M11 and M12 is grounded, and the gate is connected to the bias power supply V bias ; The positive ends of the bias resistors R1 and R2 are connected to the gates of M9 and M10, and the negative ends are connected to the power supply; the signal enters from the gates of M9 and M10, flows out from the sources of M9 and M10 and is output to the subsequent circuit through the DC blocking capacitors C1 and C2.

[0034] Buffer The buffer adopts a fully differential source follower structure with high isolation, which can reduce the impact of the subsequent circuit on the main phase shifter, provide a stable load for the main phase shifter, and have strong load-carrying capacity.

[0035] like Figure 4 As shown, the gain flatness adjustment amplifier of this embodiment adopts a common source amplifier structure in the form of feedback. M18 to M23 in the figure are gain flatness control switches, which are controlled by V ctr10 、V ctrl1 and V ctrl2 Control on and off, capacitors C5~C10 are gain flatness adjustment capacitors; M13 and M14 are common source amplifiers, providing transconductance; M15 and M16 are cascode tubes, used to improve gain, bandwidth and reverse isolation; M17 is a tail current tube, which provides a constant current for the amplifier, making its performance less susceptible to process angle, temperature and power supply voltage; R F1 and R F2 is the feedback resistor; C3, C4, C F1 and C F2 is a DC blocking capacitor, L1 and L2 are load inductors;

[0036] The positive terminal of the RF input is connected to the positive terminal of capacitor C7 and the source of M20. The negative terminal of capacitor C7 is connected to the drain of M20, the source of M19 and the positive terminal of C6. The negative terminal of C6 is connected to the drain of M19 and the positive terminal of C3. The gate of M19 is connected to V ctrl1 , the gate of M20 is connected to V ctrl2 The negative terminal of the RF input is connected to the positive terminal of capacitor C10 and the source of M23. The negative terminal of capacitor C10 is connected to the drain of M23, the source of M22 and the positive terminal of C9. The negative terminal of C9 is connected to the drain of M22 and the positive terminal of C4. The gate of M22 is connected to V ctrl1 , the gate of M23 is connected to V ctrl2 The negative terminal of C3 is connected to C F1 The positive terminal is connected to the gate of M13, C F1 The negative terminal of R F1 The positive terminal of RF1 is connected to the drain of M15, the positive terminal of C5 and the positive terminal of L1, and the source of M15 is connected to the drain of M13. The negative terminal of C4 is connected to C F2 The positive terminal is connected to the gate of M14, C F2 The negative terminal of R F2 The positive end of RF2 is connected to the drain of M16, the positive end of C8 and the positive end of L2, and the source of M16 is connected to the drain of M14. The sources of M13 and M14 are connected to the drain of M17, the source of M17 is grounded, and the gate of M17 is connected to the bias voltage V bias1 The gates of M15 and M16 are connected to voltage V bias2 The negative terminals of L1 and L2 are connected to the power supply; the negative terminal of C5 is connected to the drain of M18, the source of M18 is grounded, and the gate of M18 is connected to the control voltage V ctrl0 ; The negative terminal of C8 is connected to the drain of M21, the source of M21 is grounded, and the gate of M21 is connected to the control voltage V ctrl0 .

[0037] C5~C10 are controlled by M18~M23 respectively, and the control method is as follows: When V ctrl0 is high level, M18 and M21 are turned on, C5 and C8 are connected to the circuit, resonating with the load inductance. At this time, the high-frequency gain of the amplifier is low; when V ctrl0 is low, M18 and M21 are turned off, and the high-frequency gain of the amplifier is high. ctrl1 is high level, M19 and M22 are turned on, C6 and C9 are short-circuited, and the low-frequency gain of the circuit is high; when V ctrl1 is low level, M19 and M22 are turned off, C6 and C9 are connected to the circuit, and the low-frequency gain of the circuit is low. ctrl2 The control of the circuit is related to V ctrl1 The three control bits above are used to control the high and low frequency gain of the amplifier, that is, to control its gain flatness.

[0038] The gain flatness adjustment amplifier adopts a resistor feedback common source amplifier structure with a tail current source. The switched capacitor in parallel at the load end is used to adjust the high-frequency gain, and the switched capacitor in series at the input end is used to adjust the low-frequency gain; the feedback structure makes it have better stability; the tail current tube makes the amplifier less susceptible to the influence of process angle, temperature and power supply voltage; the cascode tube is used to improve the bandwidth, reverse phase isolation and gain of the amplifier.

[0039] like Figure 5 As shown, the digital control circuit is used to control the gain flatness adjustment amplifier, and its input is M (M=6) digital signals, which are also used to control the phase shift of the main phase shifter; the output of the digital control circuit is N (N=3)-bit digital signals, which are used to control the gain flatness adjustment amplifier.

[0040] The digital control circuit of this embodiment generates a control signal V ctrl0 、V ctrl1 、V ctrl2 The principles are shown in the figure. Control bit V b22 、V b45 、V b180 The output of the AND gate and the control bit V b45 , V b180 After passing through the output of the AND gate, the control signal V is obtained through the output of the AND gate. ctrl0 . Control bit V b22 、V b45 , The output of the AND gate and Then pass through the AND gate to get V ctrl1 . V b45 With V b90 After the output of the AND gate, V b5 With V b22 With V b45 After the output of the AND gate, V bl1 With V b22 With V b45 After the output of the AND gate, the four are output through the AND gate to obtain the control signal V ctrl2 .

[0041] The digital control circuit realizes input of 6-bit digital signal and output of 3-bit digital signal, and the output signal is used to control the gain flatness adjustment amplifier. The input signal is the control signal of the main phase shifter, thereby determining the gain (with frequency) curve of the main phase shifter; the output 3-bit control signal determines the gain curve of the gain flatness adjustment amplifier. The function of this digital circuit is to make the gain curve of the amplifier compensate for the gain curve of the main phase shifter in all phase shift states, so that the gain curve of the overall circuit remains flat and consistent.

[0042] In this embodiment, the phase shift state of the main phase shifter is controlled by six control bits, a total of 2 6 =64 states, corresponding to 64 gain curves, there are differences between the curves, for example, the maximum difference may reach 4-5dB at a certain frequency, for each gain curve, the gain flatness adjustment amplifier has a corresponding gain curve to compensate each other, so that the gain curve of the overall circuit remains relatively flat, while ensuring that the difference between the 64 gain curves of the overall circuit is small, the difference between the curves can be measured by the relative gain root mean square, the smaller the value, the lower the discreteness between the curves, that is, the better the consistency of the curves. From the above description, it can be seen that the gain flatness adjustment amplifier should have 64 states to correspond to the 64 states of the main phase shifter, but in fact, the difference between any two of the 64 curves of the main phase shifter is not very large, that is, multiple curves of the main phase shifter correspond to one curve of the flatness adjustment amplifier, so the control bits of the amplifier do not need to be as many as six bits, and the amplifier of this embodiment uses three bits for control. Through simulation and calculation, the truth table between the six control bits of the main phase shifter and the three control bits of the amplifier can be obtained under the best condition (that is, the overall circuit gain curve is the flattest and the curve discreteness is the lowest), and the digital control circuit is designed according to the truth table.

[0043] Finally, the main phase shifter and the overall circuit are simulated separately. The simulation comparison of gain curves is shown in the attached figure. Figure 6 As shown in the figure, it can be seen that the gain of the overall circuit is improved, and the discreteness of the gain curve is reduced, which is more obvious at low frequencies. The relative gain RMS value simulation comparison diagram is shown in the attached figure. Figure 7 As shown, this value reflects the discreteness of the gain curve. It can be seen that the discreteness of the gain curve of the overall circuit is basically smaller than that of the main phase shifter in the entire frequency band. At low frequencies, this value is almost reduced by half, reflecting the advantages of the present application.

[0044] Many specific details are described in the above description to facilitate a full understanding of the present invention. However, the above description is only a preferred embodiment of the present invention. The present invention can be implemented in many other ways different from those described herein, so the present invention is not limited to the specific implementation disclosed above. At the same time, any person familiar with the art can make many possible changes and modifications to the technical solution of the present invention using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A gain flattened digital passive phase shifter, characterized in that: The invention comprises a main phase shifter, a buffer, a gain flatness adjustment amplifier and a digital control circuit. A differential radio frequency signal enters the main phase shifter for phase shifting, passes through the buffer, and then adjusts the gain flatness through the gain flatness adjustment amplifier and outputs the signal. A digital control signal is simultaneously transmitted to the main phase shifter and the digital control circuit. The control signal transmitted to the main phase shifter generates a required phase shift. The control signal transmitted to the digital control circuit is converted into a gain flatness control signal for controlling the gain flatness adjustment amplifier through the digital control circuit. The gain flatness adjustment amplifier comprises a common source amplifier structure in the form of feedback. The high-frequency gain is adjusted through a switch capacitor connected in parallel to the load end, and the low-frequency gain is adjusted through a switch capacitor connected in series to the input end. The gain flatness adjustment amplifier comprises a gain flatness control switch and a gain flatness adjustment capacitor. The gain flatness control switch controls the bypass and gating of the gain flatness adjustment capacitor.

2. The gain-flattened digital passive phase shifter according to claim 1, characterized in that: The main phase shifter includes two half-circuits, each of which includes M-level phase shift units, and the phase shift values ​​of each unit are 180°, 90°, ... (180 / 2 M-1 )°.

3. The gain-flattened digital passive phase shifter according to claim 2, characterized in that: Each phase shift unit includes a high-pass / bandpass branch or a high-pass / low-pass branch. The phase shift unit selects the branch through a switch, and the phase shift unit is switched to achieve a step from 0° to 360° (180 / 2 M-1 )° phase shift.

4. The gain-flattened digital passive phase shifter according to claim 3, characterized in that: The switch includes a series MOS tube structure, and each phase shift unit corresponds to a control bit. When the control bit is at a high level, the high-pass branch or the band-pass branch of the corresponding phase shift unit is enabled, and when the control bit is at a low level, the low-pass branch of the corresponding phase shift unit is enabled.

5. The gain-flattened digital passive phase shifter according to claim 1, characterized in that: The buffer includes MOS tubes M9-M12, resistors R1, R2 and capacitors C1, C2; the source of MOS tubes M9 and M10 is connected to the drain of MOS tubes M11 and M12 and the positive end of capacitors C1 and C2, the drain of MOS tubes M9 and M10 is connected to the power supply, the source of MOS tubes M11 and M12 is grounded, and the gate is connected to the bias power supply V bias The positive ends of resistors R1 and R2 are connected to the gates of MOS tubes M9 and M10, and the negative ends are connected to the power supply. The signal enters from the gates of M9 and M10, flows out from the sources of M9 and M10, and is output to the subsequent circuit through capacitors C1 and C2.

6. The gain-flattened digital passive phase shifter according to claim 1, characterized in that: The input signal of the digital control circuit is the control signal of the main phase shifter, and the output signal is the switch control signal of the gain flatness adjustment amplifier. The switch control signal controls the switch capacitor connected in parallel at the load end and the switch capacitor connected in series at the input end respectively.

Images