Drive device for driving a power semiconductor switch

Abstract

A drive device for driving a power semiconductor switch, having a drive circuit with a monolithically configured drive circuit and a control circuit, an output drive terminal which is conductively connected to the drive circuit, the drive device having exactly this one output drive terminal for driving the power semiconductor switch, the drive circuit being designed to generate a drive voltage at the output drive terminal for switching on and off the power semiconductor switch, having a second voltage value for switching on the power semiconductor switch and a first voltage value which is lower in comparison for switching off the power semiconductor switch, the control circuit, when a switching-off command is received, driving the drive circuit such that it reduces the drive voltage from the second voltage value to the first voltage value, wherein the control circuit drives the drive circuit such that the duration until the drive voltage is reduced to the first voltage value depends on at least one operating state signal, when the output drive terminal is conductively connected to a control terminal of the power semiconductor switch via a current path.

Description

TECHNICAL FIELD

[0001] The invention relates to a control device for controlling a power semiconductor switch. BACKGROUND

[0002] It is known from DE 10 2010 018 997 A1 to control a power semiconductor switch with a control device having a monolithically integrated control circuit for controlling the power semiconductor switch. Disadvantageously, in the case of a desired opening of the power semiconductor switch, the time profile of the opening process of the power semiconductor switch cannot be influenced or controlled by the control device, and the time profile always proceeds uniformly.

[0003] In Figure 1 The control device 1'having a control circuit 2 monolithically integrated in a chip 3 for controlling a power semiconductor switch T is known as prior art from the inside. The chip 3 is arranged in an IC housing 4. The control circuit 2 has three drive circuits TR1, TR2 and TR3 and a control circuit ST for controlling the three drive circuits TR1, TR2 and TR3 for controlling the power semiconductor switch T. The three drive circuits TR1, TR2 and TR3 are each in conductive connection with an output control terminal AS1, AS2, AS3 assigned to them for controlling the conduction of the power semiconductor switch T. The three output control terminals AS1, AS2, AS3 are in conductive connection with a control terminal G of the power semiconductor switch T via the respectively assigned current path SP1, SP2, SP3. The respective current path SP1, SP2 or SP3 has an electrical control terminal connected in series to the respective current path SP1, SP2 or SP3. The drive circuit TR1 is configured to generate a control voltage Ua1 at the output control terminal AS1 having a second voltage value for switching on the power semiconductor switch T. The drive circuit TR2 or TR3 is respectively configured to generate a control voltage Ua2 or Ua3 at the output control terminal AS2 or AS3 having a uniform first voltage value below the second voltage value for switching off the power semiconductor switch T.

[0004] The control device 1'also has a switching signal input terminal SE in conductive connection with the control circuit ST for receiving an on command EB for switching on the power semiconductor switch T and for receiving an off command AB for switching off the power semiconductor switch T. Furthermore, the control device 1'has at least one operating state input terminal BS in conductive connection with the control circuit ST for receiving at least one operating state signal, for example a power semiconductor switch load voltage Uce applied between the load current terminals C and E of the power semiconductor switch T, in which the power semiconductor switch T Figure 1The control circuit ST is configured to drive the drive circuits TR1, TR2 and TR3 upon receipt of a turn-off command AB when the output drive terminals AS2 and AS3 are electrically connected with the control terminal G of the power semiconductor switch T via the current paths SP2 and SP3 in such a way that no drive voltage Ua1 is generated any more from the drive circuit TR1 and, depending on the at least one operating state signal Uce, Udc, I, TS, either a drive voltage Ua2 is generated by the drive circuit TR2 or a drive voltage Ua3 is generated by the drive circuit TR3. The control terminal series resistor Rv3 has a higher resistance value than the control terminal series resistor Rv2, so that, for example, when the current I flowing through the power semiconductor switch T exceeds a limit value, the drive voltage Ua3 is generated by the drive circuit TR3, so that the power semiconductor switch T is turned off slowly in order to reduce the voltage peak that occurs in the power semiconductor switch load voltage Uce due to the parasitic inductance of the electrical circuit when the power semiconductor switch T is turned off and, thus, the voltage stress of the power semiconductor switch T is reduced. When the current I flowing through the power semiconductor switch T does not exceed the limit value, the drive voltage Ua2 is generated by the drive circuit TR2, so that the power semiconductor switch T is turned off quickly in order to minimize the switching losses that occur when the power semiconductor switch T is turned off. It is thus possible to turn off the power semiconductor switch T in an optimized manner depending on the at least one operating state signal. The time profile of the turn-off process of the power semiconductor switch T is thus influenced or controlled by the drive device 1 '. It is disadvantageous here that the drive device 1'requires three output drive terminals AS1, AS2, AS3 for driving the power semiconductor switch T, which requires a relatively large IC housing 4 from which the three pins that form the output drive terminals AS1, AS2, AS3 in connection therewith protrude. Furthermore, three control terminal series resistors Rv1, Rv2, Rv3 are required for implementing the power semiconductor switch device 6', which has a high space requirement for the power semiconductor switch device 6' with the drive device 1 ', the three control terminal series resistors Rv1, Rv2, Rv3 and the power semiconductor switch T. SUMMARY

[0005] It is the task of the present application to provide a drive device for driving a power semiconductor switch that saves space and with which the duration of the turn-off process of the power semiconductor switch can be controlled.

[0006] The task is solved by a drive device for driving a power semiconductor switch, having a drive circuit with a monolithically integrated drive circuit and a monolithically integrated control circuit, the control circuit driving the drive circuit, an output drive terminal for driving the power semiconductor switch in electrically conductive connection with the drive circuit, wherein the output drive terminal is designed for an electrically conductive connection with a control terminal of the power semiconductor switch via a current path, wherein the drive device has exactly this one output drive terminal for driving the power semiconductor switch, wherein the drive circuit is designed for generating a drive voltage for switching on and switching off the power semiconductor switch at the output drive terminal, wherein the drive voltage has a second voltage value for switching on the power semiconductor switch and a first voltage value for switching off the power semiconductor switch, which is lower than the second voltage value, a switch signal input terminal in electrically conductive connection with the control circuit for receiving a switch-on command for switching on the power semiconductor switch and for receiving a switch-off command for switching off the power semiconductor switch, and at least one operating state input terminal in electrically conductive connection with the control circuit for receiving at least one operating state signal, wherein, when the output drive terminal is in electrically conductive connection with the control terminal of the power semiconductor switch via the current path, the control circuit is designed for driving the drive circuit upon receipt of the switch-off command, so that the drive circuit reduces the drive voltage from the second voltage value to the first voltage value, wherein, in this case, the control circuit drives the drive circuit in such a way that the duration until the drive voltage is reduced to the first voltage value depends on the at least one operating state signal.

[0007] It has proven advantageous for reducing the drive voltage from the second voltage value to the first voltage value that the drive circuit has a first voltage source, a first and a second semiconductor switch, and a switch-off resistor, wherein the first voltage source is in electrically conductive connection with a first load terminal of the first semiconductor switch, and a second load terminal of the first semiconductor switch is in electrically conductive connection with the output drive terminal via the switch-off resistor, wherein the second semiconductor switch is electrically connected in parallel with the switch-off resistor, wherein the control circuit is designed for switching on or switching off the second semiconductor switch during the switching-off process of the power semiconductor switch depending on the at least one operating state signal. Thereby, it is ensured that the drive voltage is reliably reduced from the second voltage value to the first voltage value by the drive circuit.

[0008] It has furthermore proven advantageous for reducing the drive voltage from the second voltage value to the first voltage value that the drive circuit has a first and a second current source, which are electrically connected in parallel with one another and in electrically conductive connection with the output drive terminal, wherein the control circuit is designed for switching on or switching off the first and / or the second current source during the switching-off process of the power semiconductor switch depending on the at least one operating state signal. Thereby, it is ensured that the drive voltage is reliably reduced from the second voltage value to the first voltage value by the drive circuit.

[0009] It has proven advantageous in this regard that the first current source is configured to generate a higher current than the second current source. Thereby, a very different duration until the drive voltage is reduced to the first voltage value can be achieved in a simple manner and method.

[0010] It has furthermore proven advantageous that, in order to reduce the drive voltage from the second voltage value to the first voltage value, the drive circuit has a first voltage source and a first and a second MOSFET, wherein the first load current terminals of the first and the second MOSFET are in electrically conductive connection with the first voltage source and the second load current terminals of the first and the second MOSFET are in electrically conductive connection with the output drive terminal, wherein the control circuit is configured to switch on or switch off the first and / or the second MOSFET depending on the at least one operating state signal during the turn-off process of the power semiconductor switch. Thereby, a drive circuit is provided, the construction of which can be realized particularly simply and reliably in monolithic integration.

[0011] It has proven advantageous in this regard that the transconductance of the second MOSFET is smaller than the transconductance of the first MOSFET. Thus, with the same drive voltage, the current capacity of the second MOSFET for charging reversal of the input capacitance of the power semiconductor switch is lower than the current capacity of the first MOSFET for charging reversal of the input capacitance of the power semiconductor switch. This can be achieved, for example, by configuring the transistor width of the second MOSFET to be shorter than the transistor width of the first MOSFET. Thereby, a very different duration until the drive voltage is reduced to the first voltage value can be achieved in a simple manner and method.

[0012] It has furthermore proven advantageous that, when the output drive terminal is in electrically conductive connection with the control terminal of the power semiconductor switch via the current path, the control circuit is configured for driving the drive circuit upon receipt of a turn-on instruction, such that the drive circuit increases the drive voltage from the first voltage value to the second voltage value, wherein, here, the control circuit drives the drive circuit such that the duration until the drive voltage is increased to the second voltage value depends on the at least one operating state signal. Thereby, additionally also the duration of the turn-on process of the power semiconductor switch and thus the turn-on speed of the power semiconductor switch can be matched to the current operating state in a targeted manner.

[0013] It has proven advantageous in addition for the drive circuit to have a second voltage source, a third and a fourth semiconductor switch and an on-resistor in order to increase the drive voltage from the first voltage value to the second voltage value, wherein the second voltage source is in conductive connection with the first load terminal of the third semiconductor switch and the second load terminal of the third semiconductor switch is in conductive connection with the output drive terminal via the on-resistor, wherein the fourth semiconductor switch is electrically parallel to the on-resistor, wherein the control circuit is configured to switch on or off the fourth semiconductor switch in dependence on the at least one operating state signal during the switching-on process of the power semiconductor switch. Thereby, it is made possible for the drive circuit to reliably increase the drive voltage from the first voltage value to the first voltage value.

[0014] It has proven advantageous in addition for the drive circuit to have a third and a fourth current source, which are electrically parallel to one another and in conductive connection with the output drive terminal, in order to increase the drive voltage from the first voltage value to the second voltage value, wherein the control circuit is configured to switch on or off the third and / or fourth current source in dependence on the at least one operating state signal during the switching-on process of the power semiconductor switch. Thereby, it is made possible for the drive circuit to reliably increase the drive voltage from the first voltage value to the first voltage value.

[0015] It has proven advantageous in this regard for the third current source to be configured for generating a higher current than the fourth current source. Thereby, it is possible in a simple manner and method to achieve a very different duration until the drive voltage is increased to the second voltage value.

[0016] It has proven advantageous in addition for the drive circuit to have a second voltage source and a third and a fourth MOSFET in order to increase the drive voltage from the first voltage value to the second voltage value, wherein the first load current terminals of the third and fourth MOSFET are in conductive connection with the second voltage source and the second load current terminals of the third and fourth MOSFET are in conductive connection with the output drive terminal, wherein the control circuit is configured to switch on or off the third and / or fourth MOSFET in dependence on the at least one operating state signal during the switching-on process of the power semiconductor switch. Thereby, it is provided for a drive circuit whose monolithic integrated constructional solution can be realized particularly simply and reliably.

[0017] It has proven advantageous in this regard that the transconductance of the fourth MOSFET is smaller than the transconductance of the third MOSFET. Thus, at the same drive voltage, the current capacity of the fourth MOSFET for charging reversal of the input capacitance of the power semiconductor switch is lower than the current capacity of the third MOSFET for charging reversal of the input capacitance of the power semiconductor switch. This can be achieved, for example, by configuring the transistor width of the fourth MOSFET to be shorter than the transistor width of the third MOSFET. Thereby, a very different duration until the drive voltage is reduced to the first voltage value can be achieved in a simple manner and method.

[0018] It has furthermore proven advantageous that the control circuit and the drive circuit are configured monolithically in a common chip. Thereby, a particularly space-saving drive device for driving a power semiconductor switch is provided.

[0019] It has furthermore proven advantageous that the control circuit and the drive circuit are arranged in a common IC housing, and that the output drive terminal, the at least one operating state input terminal and the switch signal input terminal are present in the form of electrically conductive pins or bumps which project from the IC housing. Thereby, a particularly space-saving drive device for driving a power semiconductor switch is provided.

[0020] Furthermore, a power semiconductor switch device having a drive device, a current path and a power semiconductor switch according to the application has proven advantageous, wherein exactly one output drive terminal of the drive device for driving the power semiconductor switch is electrically conductively connected to the control terminal of the power semiconductor switch via the current path. Thereby, a particularly space-saving power semiconductor switch device is provided, which has a drive device for driving the power semiconductor switch, by means of which the duration of the turn-off process of the power semiconductor switch can be controlled. BRIEF DESCRIPTION OF DRAWINGS

[0021] Embodiments of the application are explained below with reference to the following drawings. In which:

[0022] Figure 1 A known power semiconductor switch device as described above is shown, which has a known drive device, a three-terminal control resistor and a power semiconductor switch, wherein the drive device is electrically conductively connected to the control terminal of the power semiconductor switch via the three-terminal control resistor;

[0023] Figure 2 A power semiconductor switch device is shown, which has a drive device configuration according to the application, a control terminal resistor and a power semiconductor switch, wherein the drive device is electrically conductively connected to the control terminal of the power semiconductor switch via the control terminal resistor;

[0024] Figure 3 A power semiconductor switching device is shown, which has a further drive arrangement configuration according to the invention, an electrical control terminal series resistance and a power semiconductor switch, wherein the drive arrangement is in electrically conductive connection with the control terminal of the power semiconductor switch via the control terminal series resistance;

[0025] Figure 4 A power semiconductor switching device is shown, which has a further drive arrangement configuration according to the invention, an electrical control terminal series resistance and a power semiconductor switch, wherein the drive arrangement is in electrically conductive connection with the control terminal of the power semiconductor switch via the control terminal series resistance; and

[0026] Figure 5 Two time curves of a drive voltage in the turn-off process of a power semiconductor switch are shown. DETAILED DESCRIPTION

[0027] Figures 2 to 4 A power semiconductor switching device 6 is shown, which has a drive arrangement 1 according to the invention, an electrical control terminal series resistance Rv and a power semiconductor switch T, respectively. The power semiconductor switch T is present in the form of a transistor, for example an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In the scope of this embodiment, the power semiconductor switch T is present in the form of an IGBT, wherein a first load current terminal C of the power semiconductor switch T is present in the form of a collector terminal of the IGBT, and a second load current terminal E of the power semiconductor switch T is present in the form of an emitter terminal of the IGBT, and a control terminal G of the power semiconductor switch T is present in the form of a gate terminal of the IGBT.

[0028] The drive arrangement 1 is used to drive the power semiconductor switch T and has a drive circuit 2, which has a drive circuit TR of monolithic integrated configuration and a control circuit ST of monolithic integrated configuration, which drives the drive circuit TR. The control circuit ST and the drive circuit TR are preferably monolithically integrated in a common chip 3.

[0029] The drive arrangement 1 also has an output drive terminal AS, which is in electrically conductive connection with the drive circuit TR, for driving the power semiconductor switch T, wherein the output drive terminal AS is provided for being in electrically conductive connection with the control terminal G of the power semiconductor switch T via the current path SP. The drive arrangement 1 has exactly this one output drive terminal AS for driving the power semiconductor switch T. Thus, in contrast to the drive arrangement according to Figure 1In contrast to the known control device 1', the control device 1 according to the application has, in addition to the output control terminal AS, no further output control terminal for controlling the power semiconductor switch T which is arranged to be electrically connected to the control terminal G of the power semiconductor switch T via a further current path. The current path SP preferably has a control terminal series resistor Rv which is electrically connected between the output control terminal AS and the control terminal G of the power semiconductor switch T. The current path SP can also merely exist in the form of an electrical line which connects the output control terminal AS and the control terminal G of the power semiconductor switch T in a directly electrically conductive manner.

[0030] The drive circuit TR is designed to generate, at the output drive terminal AS, a control voltage Ua for switching on and switching off the power semiconductor switch T, wherein, as is exemplary shown in Figure 5

[0031] The control device 1 also has a switching signal input terminal SE which is electrically connected to the control circuit ST in order to receive an on command EB for switching on the power semiconductor switch T and in order to receive an off command AB for switching off the power semiconductor switch T. The on command EB can exist, for example, in the form of a logic "1", while the off command AB can exist, for example, in the form of a logic "0".

[0032] The control device 1 also has at least one operating state input terminal BS which is electrically connected to the control circuit ST and which is used to receive at least one operating state signal Uce, Udc, I, TS, such as, for example, the power semiconductor switch load voltage Uce which is applied between the first and second load current terminals C and E of the power semiconductor switch T, the intermediate circuit voltage Udc of a converter half-bridge in which the power semiconductor switch T is electrically connected (not shown in the drawing), the load current I which flows through the power semiconductor switch T and / or the temperature TS of the power semiconductor switch T. In an embodiment, the control device 1 receives four operating state signals Uce, Udc, I, TS, wherein each operating state signal Uce, Udc, I, TS is assigned an operating state input terminal BS. Furthermore, in order to electrically potential-tie the control circuit 2, the control device 1 also has a ground terminal MS which is electrically connected to the control circuit 2. The ground terminal MS is arranged to be electrically connected to the second load current terminal E of the power semiconductor switch T. The operating state signals Udc, I and TS are generated by corresponding sensors which are not shown in the drawing for reasons of clarity.

[0033] ​Preferably, the control circuit ST and the drive circuit TR are arranged in a common IC housing 4, and the output activation terminal AS, the at least one operating state input terminal BS and the switching signal input terminal SE are present, preferably in the form of electrically conductive pins or bumps, which project from the IC housing 4. Furthermore, the ground terminal MS is also preferably present in the form of an electrically conductive pin or bump, which projects from the IC housing 4.

[0034] The control circuit ST is configured for, when the output activation terminal AS is electrically conductively connected to the control terminal G of the power semiconductor switch T via the current path SP, activating the drive circuit TR upon receipt of the deactivation command AB, such that the drive circuit reduces the activation voltage Ua from the second voltage value Uv2 to the first voltage value Uv1. Here, the control circuit ST activates the drive circuit TR by means of the control signal S in such a way that the duration until the activation voltage Ua is reduced to the first voltage value Uv1 depends on the at least one operating state signal Uce, Udc, I, TS. The control circuit ST can for example activate the drive circuit TR in such a way that the duration until the activation voltage Ua is reduced to the first voltage value Uv1 is longer (for example duration T2 in Fig. 2) when the power semiconductor switch load voltage Uce exceeds a boundary value in the on state of the power semiconductor switch T, and / or when the intermediate circuit voltage Udc exceeds a boundary value, and / or when the load current I flowing through the power semiconductor switch T exceeds a boundary value, and / or when the temperature TS of the power semiconductor switch T exceeds a boundary value, and otherwise shorter (for example duration T1 in Fig. 2). The duration of the deactivation process of the power semiconductor switch T can thus be controlled by the activation device 1 in dependence on the operating state. Figure 5 Figure 5 The duration of the deactivation process of the power semiconductor switch T can thus be controlled by the activation device 1 in dependence on the operating state.

[0035] In a critical operating state in which a high voltage load of the power semiconductor switch T occurs or is expected to occur upon deactivation of the power semiconductor switch T, the duration of the deactivation process of the power semiconductor switch T is preferably chosen to be relatively long (for example duration T2) in order to reduce the voltage peak of the power semiconductor switch load voltage Uce due to the parasitic inductance of the electrical lines during the deactivation process of the power semiconductor switch T and thus to reduce the voltage load of the power semiconductor switch T. In a normal operating state in which no high voltage load of the power semiconductor switch T occurs or is expected to occur upon deactivation of the power semiconductor switch T, the duration of the deactivation process of the power semiconductor switch T is preferably chosen to be relatively short (for example duration T1) in order to reduce the electrical switching losses of the power semiconductor switch T.

[0036] Since the activation device 1 has only one output activation terminal AS for activating the power semiconductor switch T, but no further output terminals for activating further power semiconductor switches T, the activation device 1 can be designed in a particularly simple manner. The activation device 1 can for example be designed as a single-chip device. Figure 1 ​The three output activation terminals AS1, AS2 and AS3 are thus of the kind as in the prior art, so that the activation device 1 is constructed very space-savingly. The IC housing 4 can be constructed significantly smaller than in the prior art, since two pins or bumps required for the construction of the output activation terminals are dispensed with.

[0037] Preferably, when the output activation terminal AS is electrically conductively connected with the control terminal G of the power semiconductor switch T via the current path SP, the control circuit ST is constructed for activating the drive circuit TR by means of the control signal S upon receipt of the on command EB, so that the drive circuit increases the activation voltage Ua from the first voltage value Uv1 to the second voltage value Uv2, wherein here the control circuit ST activates the drive circuit TR so that the duration until the activation voltage Ua is increased to the second voltage value Uv2 depends on at least one operating state signal Uce, Udc, I, TS. In this way, the duration of the on process of the power semiconductor switch T can also be controlled by the activation device 1 depending on the operating state in a similar manner as described above during the off process of the power semiconductor switch T. In the critical operating states in which a high electrical stress of the power semiconductor switch T occurs or is expected to occur when the power semiconductor switch T is on, the duration of the on process of the power semiconductor switch T is preferably selected to be relatively long, while in the normal operating states in which no high electrical stress occurs or is expected to occur when the power semiconductor switch T is on, the duration of the on process of the power semiconductor switch T is preferably selected to be relatively short, in order to reduce the electrical switching losses of the power semiconductor switch T.

[0038] In an embodiment according to Figure 2 In order to reduce the activation voltage Ua from the second voltage value Uv2 to the first voltage value Uv1, the drive circuit TR has a first voltage source Q1, a first and a second semiconductor switch T1 and T2 and an off resistance Ra. The first voltage source Q1 is electrically conductively connected with a first load terminal of the first semiconductor switch T1, while a second load terminal of the first semiconductor switch T1 is electrically conductively connected with the output activation terminal AS via the off resistance Ra. The second semiconductor switch T2 is electrically connected in parallel with the off resistance Ra. The control circuit ST is constructed for switching on or off the second semiconductor switch T2 depending on at least one operating state signal Uce, Udc, I, TS when the power semiconductor switch T is off. Furthermore, the control circuit ST is constructed for switching off the third semiconductor switch T3 and switching on the first semiconductor switch T1 upon receipt of the off command AB.

[0039] In an embodiment according to Figure 2In the embodiment shown in Fig. 1, the drive circuit TR has a first voltage source Q1, a first and a second semiconductor switch T1 and T2 and an on-resistance Re in order to raise the drive voltage Ua from the first voltage value Uv1 to the second voltage value Uv2. The first voltage source Q1 is conductively connected with the first load terminal of the first semiconductor switch T1, while the second load terminal of the first semiconductor switch T1 is conductively connected with the output drive terminal AS via the on-resistance Re. The second semiconductor switch T2 is electrically connected in parallel to the on-resistance Re. The control circuit ST is configured to turn on or turn off the second semiconductor switch T2 in dependence on at least one operating state signal Uce, Udc, I, TS when turning on the power semiconductor switch T. Furthermore, the control circuit ST is configured for turning off the first semiconductor switch T1 and turning on the second semiconductor switch T2 when receiving the turn-on command EB.

[0040] Here, the turning on and turning off of the semiconductor switches T1, T2, T3 and T4 is controlled by the control circuit ST by means of control signals S.

[0041] Figure 5 In the embodiment shown in Fig. 1, the drive circuit TR has a first voltage source Q1, a first and a second semiconductor switch T1 and T2 and an on-resistance Re in order to raise the drive voltage Ua from the first voltage value Uv1 to the second voltage value Uv2. The first voltage source Q1 is conductively connected with the first load terminal of the first semiconductor switch T1, while the second load terminal of the first semiconductor switch T1 is conductively connected with the output drive terminal AS via the on-resistance Re. The second semiconductor switch T2 is electrically connected in parallel to the on-resistance Re. The control circuit ST is configured to turn on or turn off the second semiconductor switch T2 in dependence on at least one operating state signal Uce, Udc, I, TS when turning on the power semiconductor switch T. Furthermore, the control circuit ST is configured for turning off the first semiconductor switch T1 and turning on the second semiconductor switch T2 when receiving the turn-on command EB. Figure 2 Fig. 2 shows two time curves of the drive voltage Ua during the turning off of the power semiconductor switch T in the case of the embodiment according to Fig. 1. Until the time point t1, the drive voltage Ua has the second voltage value Uv2, here 15 V, so that the power semiconductor switch T is turned on. For this purpose, the first semiconductor switch T1 is turned off, while the third and the fourth semiconductor switch T3 and T4 are turned on. At the time point t1, the control circuit ST receives the turn-off command AB for turning off the power semiconductor switch T. As a result, at the time point t1 the third semiconductor switch T3 is turned off by the control circuit ST, and in the case of a normal operating state the first and the second semiconductor switch T1 and T2 are turned on, so that the gate-emitter capacitance of the power semiconductor switch T is discharged quickly, since essentially only the on-resistance of the first and the second semiconductor switch T1 and T2 acts as internal resistance of the drive circuit TR. A time duration T1 is obtained until the drive voltage Ua drops to the first voltage value Uv1. Figure 5 Fig. 2 shows two time curves of the drive voltage Ua during the turning off of the power semiconductor switch T in the case of the embodiment according to Fig. 1. Until the time point t1, the drive voltage Ua has the second voltage value Uv2, here 15 V, so that the power semiconductor switch T is turned on. For this purpose, the first semiconductor switch T1 is turned off, while the third and the fourth semiconductor switch T3 and T4 are turned on. At the time point t1, the control circuit ST receives the turn-off command AB for turning off the power semiconductor switch T. As a result, at the time point t1 the third semiconductor switch T3 is turned off by the control circuit ST, and in the case of a normal operating state the first and the second semiconductor switch T1 and T2 are turned on, so that the gate-emitter capacitance of the power semiconductor switch T is discharged quickly, since essentially only the on-resistance of the first and the second semiconductor switch T1 and T2 acts as internal resistance of the drive circuit TR. A time duration T1 is obtained until the drive voltage Ua drops to the first voltage value Uv1. Figure 5The curve of the control voltage Ua is shown by a dashed line. At the point in time t3, the control voltage Ua has the first voltage value Uvl, here -8 V. A significantly longer duration T2 until the control voltage Ua is reduced to the first voltage value Uvl is obtained compared to the duration Tl. The turn-off speed of the power semiconductor switch T is thus lower in the critical operating state than in the normal operating state.

[0042] In the case of a turn-on process of the power semiconductor switch T, the fourth semiconductor switch T4 is turned on in a similar manner depending on the operating state, that is to say depending on the at least one operating state signal Uce, Udc, I, TS.

[0043] It should be noted that, in order to reduce the control voltage Ua, the drive circuit TR according to Figure 2 The drive circuit TR of the power semiconductor switch device 6 according to

[0044] In the case of a turn-on process of the power semiconductor switch T, the fourth semiconductor switch T4 is turned on in a similar manner depending on the operating state, that is to say depending on the at least one operating state signal Uce, Udc, I, TS. Figure 3 In the case of a turn-off process of the power semiconductor switch T, the fourth semiconductor switch T4 is turned off in a similar manner depending on the operating state, that is to say depending on the at least one operating state signal Uce, Udc, I, TS.

[0045] In the case of a turn-off process of the power semiconductor switch T, the fourth semiconductor switch T4 is turned off in a similar manner depending on the operating state, that is to say depending on the at least one operating state signal Uce, Udc, I, TS. Figure 3In the embodiment of Fig. 1, in order to increase the drive voltage Ua from the first voltage value Uv1 to the second voltage value Uv2, the drive circuit TR has a third and a fourth current source S3 and S4, which are electrically connected in parallel to each other and are electrically connected to the output drive terminal AS. The control circuit ST is configured to switch on or off the third and / or fourth current source S3, S4 in dependence on at least one operating state signal Uce, Udc, I, TS during the switching process of the power semiconductor switch T. The third current source S3 is preferably configured to generate a higher current than the fourth current source S4.

[0046] In the scope of this embodiment, the third current I3 generated by the third current source S3 is higher than the fourth current I4 generated by the fourth current source S4. The third and fourth current sources S3 and S4 are electrically connected to the second voltage source Q2 for supplying energy thereto. In the case of a critical operating state, in order to switch on the power semiconductor switch T, only the fourth current source S4 can be switched on by the control circuit ST, for example, so that the duration until the drive voltage Ua is increased to the second voltage value Uv2 is relatively long. In the case of a normal operating state, in order to switch on the power semiconductor switch T, only the third current source S3 or both the third and fourth current sources S3 and S4 can be switched on by the control circuit ST, for example, so that the duration until the drive voltage Ua is increased to the second voltage value Uv2 is short and, thus, the power semiconductor switch T is switched on with a high switching speed.

[0047] Furthermore, the control circuit ST is configured for switching off the third and fourth current sources S3 and S4 upon receipt of a switching-off command AB. Furthermore, the control circuit ST is configured for switching off the first and second current sources S1 and S2 upon receipt of a switching-on command EB.

[0048] The switching on and off of the current sources S1, S2, S3 and S4 is controlled here by the control circuit ST by means of a control signal S.

[0049] It should be noted that, in order to decrease or increase the drive voltage Ua, the power semiconductor switch device 6 according to Figure 3 The drive circuit TR of the power semiconductor switch device 6 according to

[0050] It should be noted that, in addition to the changed drive circuit TR, the power semiconductor switch device 6 according to Figure 3 The power semiconductor switch device 6 according to Figure 2 The power semiconductor switch device 6 according to

[0051] In the power semiconductor switch device 6 according to Figure 4In an embodiment of the drive circuit TR, in order to reduce the drive voltage Ua from the second voltage value Uv2 to the first voltage value Uv1, the drive circuit TR has a first voltage source Q1 and a first and a second MOSFET M1 and M2. The first load current terminals of the first and the second MOSFET M1 and M2 are conductively connected with the first voltage source Q1, and the second load current terminals of the first and the second MOSFET M1 and M2 are conductively connected with the output drive terminal AS. The control circuit ST is configured to switch on or off the first and / or the second MOSFET M1, M2 depending on at least one operating state signal Uce, Udc, I, TS during the turn-off of the power semiconductor switch T. In the scope of this embodiment, the transconductance (Δ drain current / Δ gate-source voltage of a MOSFET) of the second MOSFET M2 is smaller than the transconductance of the first MOSFET M1. In the case of a critical operating state, in order to turn off the power semiconductor switch T, only the second MOSFET M2 can be switched on by the control circuit ST, for example, so that the duration until the drive voltage Ua is reduced to the first voltage value Uv1 is relatively long. In the case of a normal operating state, in order to turn off the power semiconductor switch T, only the first MOSFET M1 or the first and the second MOSFET M1 and M2 can be switched on by the control circuit ST, for example, so that the duration until the drive voltage Ua is reduced to the first voltage value Uv1 is short and, thus, the power semiconductor switch T is turned off with a high turn-off speed.

[0052] In accordance with Figure 4In an embodiment of the power semiconductor switching device 6, in order to increase the drive voltage Ua from the first voltage value Uv1 to the second voltage value Uv2, the drive circuit TR has a second voltage source Q2 and a third and a fourth MOSFET M3 and M4. The first load current terminals of the third and fourth MOSFET M3 and M4 are conductively connected to the second voltage source Q2. The second load current terminals of the third and fourth MOSFET M3 and M4 are conductively connected to the output drive terminal AS. The control circuit TR is configured to switch on or switch off the third and / or fourth MOSFET M3, M4 in dependence on at least one operating state signal Uce, Udc, I, TS during the switching-on of the power semiconductor switch T. In the scope of this embodiment, the transconductance of the fourth MOSFET M4 is smaller than the transconductance of the third MOSFET M3. In the case of a critical operating state, in order to switch on the power semiconductor switch T, only the fourth MOSFET M4 can be switched on by the control circuit ST, for example, so that the duration until the drive voltage Ua is increased to the second voltage value Uv2 is relatively long. In the case of a normal operating state, in order to switch on the power semiconductor switch T, only the third MOSFET M3 or the third and fourth MOSFET M3 and M4 can be switched on by the control circuit ST, for example, so that the duration until the drive voltage Ua is increased to the second voltage value Uv2 is short and, therefore, the power semiconductor switch T is switched on with a high switching-on speed.

[0053] Furthermore, the control circuit ST is configured for switching off the third and fourth MOSFET M3 and M4 upon receipt of a switching-off command AB. Furthermore, the control circuit ST is configured for switching off the first and second MOSFET M1 and M2 upon receipt of a switching-on command EB.

[0054] The switching on and off of the MOSFET M1, M2, M3 and M4 is controlled by the control circuit ST by means of a control signal S.

[0055] It should be noted that, in order to decrease or increase the drive voltage Ua, according to Figure 4 The drive circuit TR of the power semiconductor switching device 6 according to

[0056] It should be noted that, in addition to the changed drive circuit TR, the power semiconductor switching device 6 according to Figure 4 The power semiconductor switching device 6 according to Figure 2 The power semiconductor switching device 6 according to

[0057] In all embodiments, the power semiconductor switching device 6 has a control device 1 according to the application, a current path SP and a power semiconductor switch T, wherein exactly one output control terminal AS of the control device 1 for controlling the power semiconductor switch T is conductively connected via the current path SP with a control terminal G of the power semiconductor switch T. In addition to this output control terminal AS, the control device 1 has no further output control terminal for controlling the power semiconductor switch T which is connected via a further current path with the control terminal G of the power semiconductor switch T.

[0058] It should also be noted that, in the sense of the present application, output control terminals which are conductively connected to one another and thus have the same electrical potential are regarded as one output control terminal AS.

[0059] It should also be noted that, of course, the features of the different embodiments of the present application can be arbitrarily combined with one another without leaving the scope of the present application, as far as they are not mutually exclusive.

Claims

1. Drive device for driving a power semiconductor switch (T), the drive device having: a drive circuit (2) having a drive circuit (TR) of monolithic integrated construction and a control circuit (ST) of monolithic integrated construction, the control circuit driving the drive circuit (TR); an output activation terminal (AS) for activating the power semiconductor switch (T) in electrically conductive connection with the drive circuit (TR), wherein the output drive terminal (AS) being provided for an electrically conductive connection with a control terminal (G) of the power semiconductor switch (T) via a current path (SP), wherein the drive device (1) has exactly this one output drive terminal (AS) for driving the power semiconductor switch (T), wherein the drive circuit (TR) is configured for generating a drive voltage (Ua) for switching on and switching off the power semiconductor switch (T) at the output drive terminal (AS), wherein the drive voltage (Ua) has a second voltage value (Uv2) for switching on the power semiconductor switch (T) and a first voltage value (Uv1) for switching off the power semiconductor switch (T) which is lower relative to the second voltage value (Uv2); a switch signal input terminal (SE) for electrically conductive connection with the control circuit (ST) for receiving a switch-on command (EB) for switching on the power semiconductor switch (T) and for receiving a switch-off command (AB) for switching off the power semiconductor switch (T); and at least one operating state input terminal (BS) for electrically conductive connection with the control circuit (ST) for receiving at least one operating state signal of a power semiconductor switch load voltage (Uce) applied between first and second load current terminals (C) and (E) of the power semiconductor switch (T), an intermediate circuit voltage (Udc) of a current transformer half-bridge to which the power semiconductor switch (T) is electrically connected, a load current (I) flowing through the power semiconductor switch (T) and / or a temperature (TS) of the power semiconductor switch (T); wherein, when the output drive terminal (AS) is electrically conductively connected with the control terminal (G) of the power semiconductor switch (T) via the current path (SP), the control circuit (ST) is configured for driving the drive circuit (TR) upon receipt of a switch-off command (AB) such that the drive circuit reduces the drive voltage (Ua) from the second voltage value (Uv2) to the first voltage value (Uv1), wherein here the control circuit (ST) drives the drive circuit (TR) such that a duration until the drive voltage (Ua) is reduced to the first voltage value (Uv1) depends on the at least one operating state signal.

2. The drive control device according to claim 1, characterized by To reduce the drive voltage (Ua) from the second voltage value (Uv2) to the first voltage value (Uv1), the drive circuit (TR) has a first voltage source (Q1), a first semiconductor switch (T1), a second semiconductor switch (T2) and a shutdown resistor (Ra), wherein the first voltage source (Q1) is in electrically conductive connection with a first load terminal of the first semiconductor switch (T1), and a second load terminal of the first semiconductor switch (T1) is in electrically conductive connection with the output drive terminal (AS) via the shutdown resistor (Ra), wherein the second semiconductor switch (T2) is electrically parallel to the shutdown resistor (Ra), wherein the control circuit (ST) is configured to switch on or off the second semiconductor switch (T2) in dependence on the at least one operating state signal during the switching off of the power semiconductor switch (T).

3. The drive control device according to claim 1, wherein To reduce the drive voltage (Ua) from the second voltage value (Uv2) to the first voltage value (Uv1), the drive circuit (TR) has a first current source (S1) and a second current source (S2), which are electrically parallel to one another and in electrically conductive connection with the output drive terminal (AS), wherein the control circuit (ST) is configured to switch on or off the first current source (S1) and / or the second current source (S2) in dependence on the at least one operating state signal during the switching off of the power semiconductor switch (T).

4. The drive control device according to claim 3, wherein The first current source (S1) is configured to generate a higher current than the second current source (S2).

5. The drive control device according to claim 1, wherein To reduce the drive voltage (Ua) from the second voltage value (Uv2) to the first voltage value (Uv1), the drive circuit (TR) has a first voltage source (Q1) and a first MOSFET (M1) and a second MOSFET (M2), wherein the first current load terminals of the first MOSFET (M1) and the second MOSFET (M2) are in electrically conductive connection with the first voltage source (Q1), and the second current load terminals of the first MOSFET (M1) and the second MOSFET (M2) are in electrically conductive connection with the output drive terminal (AS), wherein the control circuit (ST) is configured to switch on or off the first MOSFET (M1) and / or the second MOSFET (M2) in dependence on the at least one operating state signal during the switching off of the power semiconductor switch (T).

6. The drive control device according to claim 5, wherein The transconductance of the second MOSFET (M2) is less than the transconductance of the first MOSFET (M1).

7. The actuation device according to any one of claims 1 to 6, characterized in that When the output activation terminal (AS) is electrically conductively connected with the control terminal (G) of the power semiconductor switch (T) via the current path (SP), the control circuit (ST) is configured to activate the drive circuit (TR) upon receipt of an activation command (EB) such that the drive circuit increases the drive voltage (Ua) from the first voltage value (Uv1) to the second voltage value (Uv2), wherein the control circuit (ST) activates the drive circuit (TR) such that the duration until the drive voltage (Ua) is increased to the second voltage value (Uv2) depends on the at least one operating state signal.

8. The drive control device according to claim 7, wherein In order to increase the drive voltage (Ua) from the first voltage value (Uv1) to the second voltage value (Uv2), the drive circuit (TR) has a second voltage source (Q2), a third semiconductor switch (T3) and a fourth semiconductor switch (T4) and an activation resistance (Re), wherein the second voltage source (Q2) is electrically conductively connected with a first load terminal of the third semiconductor switch (T3), and a second load terminal of the third semiconductor switch (T3) is electrically conductively connected with the output activation terminal (AS) via the activation resistance (Re), wherein the fourth semiconductor switch (T4) is electrically connected in parallel with the activation resistance (Re), wherein the control circuit (ST) is configured to activate or deactivate the fourth semiconductor switch (T4) depending on the at least one operating state signal during the activation of the power semiconductor switch (T).

9. The drive control device according to claim 7, wherein In order to increase the drive voltage (Ua) from the first voltage value (Uv1) to the second voltage value (Uv2), the drive circuit (TR) has a third current source (S3) and a fourth current source (S4), which are electrically connected in parallel with one another and are electrically conductively connected with the output activation terminal (AS), wherein the control circuit (ST) is configured to activate or deactivate the third current source (S3) and / or the fourth current source (S4) depending on the at least one operating state signal during the activation of the power semiconductor switch (T).

10. The drive control device according to claim 9, wherein The third current source (S3) is configured to generate a higher current than the fourth current source (S4).

11. The drive control device according to claim 7, wherein In order to increase the drive voltage (Ua) from the first voltage value (Uv1) to the second voltage value (Uv2), the drive circuit (TR) has a second voltage source (Q2) and a third MOSFET (M3) and a fourth MOSFET (M4), wherein the first load current terminals of the third MOSFET (M3) and the fourth MOSFET (M4) are conductively connected to the second voltage source (Q2), and the second load current terminals of the third MOSFET (M3) and the fourth MOSFET (M4) are conductively connected to the output drive terminal (AS), wherein the control circuit (ST) is configured to switch on or off the third MOSFET (M3) and / or the fourth MOSFET (M4) in dependence on the at least one operating state signal during the conduction of the power semiconductor switch (T).

12. The drive control device according to claim 11, wherein The transconductance of the fourth MOSFET (M4) is smaller than the transconductance of the third MOSFET (M3).

13. The driver of any one of claims 1 to 6, wherein, The control circuit (ST) and the drive circuit (TR) are monolithically integrated in a common chip (3).

14. The driver of any one of claims 1 to 6, wherein, The control circuit (ST) and the drive circuit (TR) are arranged in a common IC housing (4), and the output drive terminal (AS), the at least one operating state input terminal (BS) and the switch signal input terminal (SE) are present in the form of conductive pins or bumps which project from the IC housing (4).

15. Power semiconductor switching device having a drive arrangement (1) according to any one of claims 1 to 14, a current path (SP) and a power semiconductor switch (T), wherein Exactly one output drive terminal (AS) of the drive device for driving the power semiconductor switch (T) is conductively connected to the control terminal (G) of the power semiconductor switch (T) via the current path (SP).

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