Electroabsorption modulator

Abstract

An optoelectronic device comprises: a silicon-on-insulator (SOI) substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; a waveguide region, wherein a portion of the silicon device layer and a portion of the BOX layer below the portion of the device layer have been removed, the portion of the BOX layer having been replaced with a layer of crystalline oxide on top of silicon and a silicon layer; and a waveguide structure, which is directly located on top of the crystalline oxide layer, the waveguide structure comprising a P-doped region and an N-doped region, the P-doped region and the N-doped region having an intrinsic region therebetween, thereby producing a PIN junction, and a bias voltage can be applied across the PIN junction to produce a modulation region.

Description

Technical Field

[0001] The present invention relates to electro-absorption modulators and, more particularly, to electro-absorption modulators for use on silicon-on-insulator platforms. Background Art

[0002] As the field of silicon photonics advances, there is an increasing desire for improvements not only in the functionality of optoelectronic devices such as electro-absorption modulators, but also in the ease and reliability with which such devices can be manufactured.

[0003] SiGeSn is a known material and can be integrated on a SOI platform to fabricate an EAM that functions in the O-band (wavelength of 1260-1360 nm). Typically, a Ge buffer is used to enable the SiGeSn material to grow on a silicon substrate, since SiGeSn cannot be grown epitaxially directly onto a silicon substrate.

[0004] It is known that crystalline oxide layers can be grown on silicon. For example, Gottlob et al. in Solid-State Electronics 50 (2006) 979-985 disclose Gd2O3 grown on (001) oriented silicon by a modified epitaxial process. Examples of crystalline REO multilayer structures grown on Si (111) are shown in the ECS journal Solid State Science and Technology, 1 (5) P246-P249 (2012). Osten et al. in Phys. Stat. Sol. (a) 205, No. 4, 695-707 (2008) describe the use of crystalline REO in silicon structures. Crystalline oxides can include Er2O3, Gd2O3 and other rare earth oxide materials, as well as SrTiO3 (STO), BaTiO3 (BTO), La2O3 (LAO) and other perovskite oxide materials having the general chemical formula ABO3 or A2BO4. Summary of the invention

[0005] Therefore, in a first aspect, some embodiments of the present invention aim to solve the above problem by providing an electro-absorption modulator (EAM) according to the first aspect, the EAM comprising:

[0006] A silicon-on-insulator (SOI) substrate, the substrate comprising:

[0007] Silicon support layer;

[0008] a buried oxide (BOX) layer on top of the silicon support layer; and

[0009] a silicon device layer on top of the BOX layer;

[0010] a waveguide region in which a portion of a silicon device layer and a portion of a BOX layer below the portion of the device layer have been removed, the portion of the BOX layer having been replaced with a layer of crystalline oxide and a layer of silicon on top of the silicon; and

[0011] A waveguide structure is directly located on top of the crystalline oxide layer, the waveguide structure includes a P-doped region and an N-doped region, with an intrinsic region in between the P-doped region and the N-doped region, thereby generating a PIN junction, and a bias can be applied across the PIN junction to generate a modulation region.

[0012] The purpose of the regrown silicon epitaxial layer is to enable the grown crystalline oxide layer to remain thin (ie, thinner than the original BOX layer), but still be flush with the top of the adjacent BOX layer.

[0013] In this way, an EAM with reduced optical losses is provided, as the crystalline oxide layer provides a means of avoiding the use of a Ge buffer layer and thus avoiding the associated optical losses. As described below, it is also relatively convenient to manufacture the EAM in a manner that is compatible with existing EAM manufacturing processes.

[0014] Optionally, the waveguide structure is made of one or more of the following bulk materials: SiGeSn, SiGe, InGaAs, AlInGaAs and InGaAsP, or the following quantum well stacking materials: SiGe multiple quantum well (SiGeMQW), AlInGaAs MQW, InGaAsP MQW and InGaNAs MQW. Optionally, the waveguide structure is made of one or more of the following bulk materials: SiGeSn, SiGe, InGaAs and InGaAsP, or the following quantum well stacking materials: SiGe multiple quantum well (SiGe MQW), AlInGaAs MQW, InGaAsP MQW and InGaNAs MQW.

[0015] In some examples, the crystalline oxide layer is a crystalline rare earth oxide (CREO). In some examples, the crystalline oxide layer can be a perovskite oxide, such as strontium titanate (STO), barium titanate (BTO), or lanthanum aluminate (LAO).

[0016] CREO is an isolating material that has little light absorption and can be grown epitaxially on a silicon substrate with a (111) orientation. SiGeSn can be grown epitaxially on CREO, as can the other waveguide materials listed above. Thus, the layer of CREO acts as a transition layer, epitaxially growing SiGeSn (or other waveguide material) on top of the silicon replacement layer that has replaced the BOX layer.

[0017] Since the electro-absorption medium of SiGeSn (or other waveguide materials listed above) has a higher refractive index than the refractive index of the silicon optical transmission medium, in conventional EAM structures, the uniform and continuous silicon layer above the BOX layer and below the waveguide material must be thin to keep the coupling efficiency between the optical transmission medium and the electro-absorption medium high. Typically, the thickness of the silicon layer is 0.2 µm. In actual EAM manufacturing using a 3 µm SOI platform, it is very difficult to achieve a uniform silicon layer of 0.2 µm on top of the BOX with a high yield by etching down the 3 µm silicon cover, which makes the high-density, high-yield, low-cost integration of the EAM with other components on the SOI very challenging.

[0018] Therefore, some embodiments of the present invention also introduce a new EAM structure that does not have such difficulties in practical device manufacturing and is suitable for high-density, high-yield and low-cost photonic integration on SOI platform.

[0019] In some embodiments, the disclosed structures are not limited to EAMs, but also cover other optoelectronic devices such as lasers or photodetectors.

[0020] Optional features of some embodiments of the present invention will now be described. These optional features are applicable alone or in any combination with any aspect of the embodiments of the present invention.

[0021] Optionally, the crystalline oxide layer has a thickness of 20 nm-400 nm. In some embodiments, the crystalline oxide layer may have a thickness of no greater than 50 nm.

[0022] Optionally, the silicon support layer is Si(111) and the replacement silicon layer is Si(111)

[0023] Optionally, the crystalline oxide layer may have a (111) orientation, although other orientations are also contemplated.

[0024] Optionally, the waveguide structure is a rib waveguide comprising: a waveguide ridge on a plate, wherein a first plate portion is on a first side of the ridge and a second plate portion is on a second side of the ridge, wherein the waveguide ridge, the first plate portion and the second plate portion are all formed of the same material as each other.

[0025] SiGeSn generally has an inverted T-shaped cross section taken in a direction perpendicular or substantially perpendicular to the longitudinal axis of the ridge waveguide.

[0026] Optionally, the waveguide structure is a rib waveguide, the rib waveguide comprising:

[0027] A SiGeSn waveguide ridge on a SiGeSn slab with a first SiGeSn slab portion on a first side of the ridge and a second SiGeSn slab portion on a second side of the ridge.

[0028] SiGeSn generally has an inverted T-shaped cross section taken in a direction perpendicular or substantially perpendicular to the longitudinal axis of the ridge waveguide.

[0029] Optionally, the P-doped region is located at the first plate, and the N-doped region is located at the second plate.

[0030] Optionally, the P-doped region extends into a first sidewall of the ridge and / or wherein the N-doped region extends into a second sidewall of the ridge.

[0031] Optionally, the EAM further comprises a first metal contact at the first plate electrically connected to the P-doped region and a second metal contact at the second plate portion electrically connected to the N-doped region.

[0032] Optionally, the P-doped region and the N-doped region are located in a layer, one layer above the other, wherein the intrinsic layer is located between the P-doped region and the N-doped region. For example, the waveguide structure can be a rib waveguide, which includes: a waveguide ridge on a plate, the waveguide ridge is formed by a plurality of layers stacked in a vertical direction (i.e., a direction away from the silicon substrate), wherein the first layer of the plurality of layers is an N-doped region, and the second layer of the plurality of layers is a P-doped region. In such an example, a first metal contact can be connected to the P-doped region, and a second metal contact can be connected to the N-doped region, and the second metal contact can extend upward along the sidewall of the waveguide structure and across its uppermost surface so as to connect to the upper surface of the N-doped region. Although in this example, the N-doped region is above the P-doped region, the opposite is certainly possible. Such an arrangement in which one doped layer of the PIN junction is above the other doped layer can be referred to as a vertical PIN junction. In contrast, an arrangement in which both doped regions extend upward along the respective sidewalls of the waveguide can be referred to as a horizontal PIN junction.

[0033] Optionally, the SOI substrate is a 3 µm SOI platform.

[0034] Optionally, for the quantum well stack material, the waveguide structure is a rib waveguide, the rib waveguide comprising: an MQW waveguide ridge on a slab with a buffer layer, the buffer layer being a P (or N) doped region; an N (or P) doped region on top of the MQW waveguide ridge;

[0035] The waveguide typically has an inverted T-shaped cross-section taken in a direction perpendicular or substantially perpendicular to the longitudinal axis of the ridge waveguide.

[0036] Optionally, the EAM further comprises a first metal contact at the plate electrically connected to the P (or N) doped region and a second metal contact at the top of the waveguide electrically connected to the N (or P) doped region.

[0037] The quantum well material may take the form of a multiple quantum well stack including a vertical PIN structure that is fabricated in situ during the material epitaxial process.

[0038] Optionally, the SOI substrate is a 1 µm SOI platform.

[0039] According to a second aspect, some embodiments of the present invention provide a method of manufacturing an electro-absorption modulator (EAM), the method comprising:

[0040] Providing a silicon-on-insulator substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer;

[0041] etching through the BOX layer and a portion of the silicon device layer to create a cavity in the substrate exposing a portion of the silicon support layer;

[0042] epitaxially growing a replacement layer of silicon on top of the exposed portion of the silicon support layer;

[0043] epitaxially growing a layer of crystalline oxide on top of the replacement layer of silicon, the replacement layer of silicon and the crystalline oxide layer replacing portions of the BOX layer that have been etched away;

[0044] epitaxially growing a layer of a first material on top of the crystalline oxide layer; and

[0045] A waveguide structure is fabricated within the layer of the first material, the waveguide structure comprising a P-doped region and an N-doped region with an intrinsic region therebetween, thereby creating a PIN junction across which a bias can be applied to function as a modulation region.

[0046] Optionally, the first material is one or more of the following materials: SiGeSn, SiGe, InGaAs, AlInGaAs, InGaAsP, SiGe multiple quantum well (SiGe MQW), AlInGaAs MQW, InGaAsP MQW and InGaNAs MQW. Optionally, the first material is one or more of the following materials: SiGeSn, SiGe, InGaAs, InGaAsP, SiGe multiple quantum well (SiGeMQW), AlInGaAs MQW, InGaAsP MQW and InGaNAs MQW.

[0047] Optionally, the replacement silicon layer will extend so as not to be higher than the upper surface of the box layer in the original SOI substrate.Then, a crystalline oxide layer may be grown so that the upper surface of the crystalline oxide layer is flush with the upper surface of the BOX layer in the adjacent portion of the SOI substrate.

[0048] In this way, a method is provided that enables crystalline oxide and SiGeSn to be realized on SOI platforms using a process flow that is compatible with existing EAM manufacturing processes. This is particularly relevant to 3 um or 1 um SOI platforms.

[0049] In some examples, the crystalline oxide layer is a crystalline rare earth oxide (CREO). In some examples, the crystalline oxide layer can be a perovskite oxide, such as strontium titanate (STO), barium titanate (BTO), or lanthanum aluminate (LAO).

[0050] Optionally, the step of manufacturing the waveguide structure comprises:

[0051] The first material layer is etched to form a rib waveguide including a ridge on a plate, the plate including a first plate portion on a first side of the ridge and a second plate portion on a second side of the ridge.

[0052] The SiGeSn rib waveguide generally has an inverted T-shaped cross section taken in a direction perpendicular or substantially perpendicular to the longitudinal axis of the rib waveguide.

[0053] Optionally, the P-doped region is located at the first plate portion, and the N-doped region is located at the second plate portion.

[0054] Optionally, the P-doped region extends into a first sidewall of the ridge and / or wherein the N-doped region extends into a second sidewall of the ridge.

[0055] Optionally, the P-doped region and the N-doped region are located in a layer, one layer above the other, wherein the intrinsic layer is located between the P-doped region and the N-doped region. For example, the waveguide structure can be a rib waveguide, which includes: a waveguide ridge on a plate, the waveguide ridge is formed by a plurality of layers stacked in a vertical direction (i.e., a direction away from the silicon substrate), wherein the first layer of the plurality of layers is an N-doped region, and the second layer of the plurality of layers is a P-doped region. In such an example, a first metal contact can be connected to the P-doped region, and a second metal contact can be connected to the N-doped region, and the second metal contact can extend upward along the side wall of the waveguide structure and across its uppermost surface so as to be connected to the upper surface of the N-doped region. Although in this example, the N-doped region is above the P-doped region, the opposite is certainly possible. Such an arrangement in which one doped layer of the PIN junction is above the other doped layer can be referred to as a vertical PIN junction. In contrast, an arrangement in which both doped regions extend upward along the respective side walls of the waveguide can be referred to as a horizontal PIN junction.

[0056] Optionally, the silicon support layer is Si(111); and the alternative silicon is Si(111), and the crystalline oxide may be (111) oriented.

[0057] According to a third aspect, some embodiments of the present invention provide an optoelectronic device, the optoelectronic device comprising:

[0058] A silicon-on-insulator (SOI) substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer;

[0059] a waveguide region in which a portion of a silicon device layer and a portion of a BOX layer below the portion of the device layer have been removed, the portion of the BOX layer having been replaced with a layer of crystalline oxide and a layer of silicon on top of the silicon; and

[0060] A waveguide structure is directly located on top of the crystalline oxide layer, the waveguide structure includes a P-doped region and an N-doped region, with an intrinsic region in between the P-doped region and the N-doped region, thereby generating a PIN junction, and a bias can be applied across the PIN junction to generate a modulation region.

[0061] Optionally, the optoelectronic device is an EAM or a laser, or a photodetector.

[0062] Optionally, the waveguide device is an AlInGaAs MQW waveguide structure.

[0063] Optionally, the AlInGaAs MQW is an InP-based AlInGaAs MQW.

[0064] According to a fourth aspect, some embodiments of the present invention provide a method of manufacturing an optoelectronic device, the method comprising:

[0065] Providing a silicon-on-insulator substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer;

[0066] etching through the BOX layer and a portion of the silicon device layer to create a cavity in the substrate exposing a portion of the silicon support layer;

[0067] epitaxially growing a replacement layer of silicon on top of the exposed portion of the silicon support layer;

[0068] epitaxially growing a layer of crystalline oxide on top of the replacement layer of silicon, the replacement layer of silicon and the crystalline oxide layer replacing the portion of the BOX layer that has been etched away;

[0069] epitaxially growing a layer of a first material on top of the crystalline oxide layer; and

[0070] A waveguide structure is fabricated within the layer of the first material, the waveguide structure comprising a P-doped region and an N-doped region with an intrinsic region therebetween, thereby producing a PIN junction across which a bias can be applied to function as a modulation region.

[0071] It will be appreciated that optional features discussed in relation to the first and second aspects may also be applicable to aspects of the third and fourth aspects.

[0072] In a fifth aspect, some embodiments of the present invention provide an electro-absorption modulator (EAM), the EAM comprising:

[0073] Silicon on insulator SOI substrate, comprising:

[0074] Silicon support layer;

[0075] a buried oxide BOX layer on top of the silicon support layer; and

[0076] a silicon device layer on top of the BOX layer;

[0077] a waveguide region in which a portion of a silicon device layer, a portion of a BOX layer below the portion of the device layer, and a portion of a silicon support layer below the portion of the BOX layer have been removed, at least a portion of the portion of the silicon support layer having been replaced with a layer of crystalline oxide on top of the remaining silicon support layer; and

[0078] A waveguide structure is directly located on top of the crystalline oxide layer, the waveguide structure including a P-doped region and an N-doped region with an intrinsic region therebetween, thereby creating a PIN junction across which a bias can be applied to create a modulation region.

[0079] The portion of the silicon support layer and at least a portion of the BOX layer may have been replaced with a layer of crystalline oxide.

[0080] A passive waveguide provided in the silicon device layer and adjacent to the waveguide region is coupled to the waveguide via a bridge waveguide. The bridge waveguide may include a liner channel filled with a fill material having a refractive index similar to the refractive index of a material forming a sidewall adjacent to the bridge waveguide. The liner may be formed of silicon nitride. A lowermost surface of the sidewall of the channel and a top surface of a portion of the liner located in the matrix of the channel may be aligned with a top surface of the buried oxide layer. The liner may have a thickness of at least 200 nm and no greater than 280 nm. The fill material may be amorphous silicon.

[0081] The waveguide structure may be formed of a plurality of layers, wherein at least one layer of the plurality of layers may be formed of indium phosphide.

[0082] In a sixth aspect, some embodiments of the present invention provide a method of manufacturing an electro-absorption modulator (EAM), the method comprising:

[0083] A silicon-on-insulator substrate is provided, the substrate comprising:

[0084] Silicon support layer;

[0085] a buried oxide BOX layer on top of the silicon support layer, and a silicon device layer on top of the BOX layer;

[0086] etching through the silicon device layer, the BOX layer, and a portion of the silicon support layer to create a cavity in the substrate exposing a portion of the silicon support layer;

[0087] epitaxially growing a layer of crystalline oxide on top of the exposed portion of the silicon support layer, the crystalline oxide layer replacing a portion of the silicon support layer that has been etched away;

[0088] epitaxially growing a layer of a first material on top of the crystalline layer; and

[0089] A waveguide structure is fabricated within the layer of the first material, the waveguide structure comprising a P-doped region and an N-doped region with an intrinsic region therebetween, thereby creating a PIN junction across which a bias can be applied to function as a modulation region.

[0090] The step of manufacturing a waveguide structure may include the following sub-steps:

[0091] etching one or more channels adjacent to the first material to remove any edge defects thereof;

[0092] lining one or more channels with a liner to provide a liner channel; and

[0093] The pad channel is filled with a fill material having a refractive index similar to that of a material forming the sidewalls such that the fill material forms a bridge waveguide in the channel between the passive waveguide and the waveguide structure in the silicon device layer.

[0094] The liner may be formed of silicon nitride. The liner may have a thickness of at least 200 nm and no greater than 280 nm. The filling material with which the liner channel is filled may include amorphous silicon.

[0095] Further optional features of some embodiments of the invention are set out below. BRIEF DESCRIPTION OF THE DRAWINGS

[0096] Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0097] Figures 1A-1C A schematic diagram of an EAM is shown, comprising: Figure 1ATop view in the figure; along the direction of light propagation (in Figure 1A 1B) taken along a direction perpendicular or substantially perpendicular to the propagation direction (in Figure 1A A second cross-sectional view taken along line BB' is shown in FIG.

[0098] Figures 2A-2M shows example steps in an embodiment of a method of manufacturing an EAM according to some embodiments of the present invention;

[0099] Figure 3A and 3B A schematic diagram of an alternative EAM along the direction of light propagation and in cross-section is shown. The top view of the EAM is not shown, but the top view of the EAM has the same structure as the EAM except that SiGeSn has been replaced by SiGe. Figure 1A The structure is similar to the structure of;

[0100] Figure 4A and 4B Schematic representation along the direction of light propagation and in cross-section of a further alternative EAM comprising a quantum well material exhibiting a quantum confined Stark effect (QCSE) is shown. Figure 4C Examples of thicknesses of layers in quantum well materials are shown;

[0101] Figures 5A-5N Shown according to Figure 4A and 4B Example steps in an embodiment of a method of manufacturing an EAM of an embodiment;

[0102] Fig. 6A and 6B shows a schematic diagram along the direction of light propagation and in cross-section of an alternative further EAM comprising a quantum well material exhibiting a quantum confined Stark effect (QCSE);

[0103] Figure 7 A schematic diagram of an EAM is shown;

[0104] Figures 8A-8D Shows Figure 7 Various cross-sectional views of the EAM.

[0105] Figure 9a -9w(ii) shows that according to Figure 7-8D Example steps in an embodiment of a method of manufacturing an EAM on a 1 µm SOI platform; and

[0106] Figure 10a-10v Shown according to Figure 7-8D Example steps in an embodiment of a method of manufacturing a variant EAM on a 3 µm SOI platform. DETAILED DESCRIPTION

[0107] Reference below Figures 1A-1C Embodiments of an electro-absorption modulator (EAM) according to the present invention are described.

[0108] The EAM is fabricated on a silicon-on-insulator (SOI) substrate consisting of:

[0109] A silicon support layer 101; a buried oxide (BOX) layer 102 on top of the silicon support layer; and a silicon device layer 103 on top of the BOX layer. In the embodiment shown, the silicon support layer 101 is crystalline silicon with a (111) crystal orientation. The silicon device layer 103 may be a 3 µm device layer.

[0110] Within the waveguide region 121, a portion of the silicon device layer 103 and a portion of the box layer 102 below the portion of the silicon device layer have been removed. The resulting cavity houses a SiGeSn waveguide structure 124, which is located directly on top of a substrate consisting of epitaxially grown silicon 122 (the "replacement silicon layer") and a thin film of crystalline rare earth oxide (CREO) 123 located directly on top of the epitaxially grown silicon. The replacement layer of silicon has the same orientation as the crystal orientation of the silicon support layer, which in this case is the (111) orientation. CREO has a similar lattice constant to Si in the (111) orientation, which means not only that it can be epitaxially grown directly onto the replacement silicon layer, but also that a SiGeSn layer can be epitaxially grown directly onto the CREO layer. The combined height of the replacement silicon layer and CREO is the same or similar to the total height of the BOX layer (i.e., the distance from the lower surface contacting the silicon support layer 101 to the upper surface contacting the silicon device layer 103).

[0111] The waveguide structure takes the form of a rib waveguide, which means that its cross section perpendicular or substantially perpendicular to the direction of light propagation has an inverted T-shape. Figure 2H The rib waveguide is grown in one epitaxial growth phase and etched into shape, but can be considered to be made of a SiGeSn ridge portion 204 on top of a SiGeSn slab. The resulting shape thus includes a first slab portion 202 at a first side of the ridge, and a second slab portion 203 at a second side of the ridge opposite the first slab portion.

[0112] A P-doped region 250 is located at the first plate portion 202 and extends along a first sidewall 212 of the waveguide ridge, thereby creating an "L-shaped" dopant region. Similarly, an N-doped region 251 is located at the second plate portion 203 and extends along a second sidewall 213 of the waveguide ridge, the second sidewall being opposite and parallel to the first sidewall. An intrinsic region 214 of the SiGeSn waveguide is sandwiched between the first and second sidewalls, which creates a PIN junction across which a bias can be applied for controlling the optical properties of the SiGeSn and thereby for modulating the optical signal passing through the modulator.

[0113] At the first plate portion 202, the P-doped region includes a sub-region having a P dopant concentration greater than the P dopant concentration of the rest of the P-doped region. A first metal contact 222 in the form of a strip electrode is located on top of the highly doped sub-region for applying a bias voltage. Similarly, a sub-region having an N dopant concentration greater than the N dopant concentration of the rest of the N-doped region is located at the second plate portion 203. A second metal contact 223 in the form of a strip electrode is located on top of the highly doped sub-region. The strip electrode can be made of any suitable metal such as aluminum.

[0114] Examples of suitable dopants include boron for P and P+ dopants and phosphorus for N and N+ dopants. Examples of suitable dopant concentrations include: 1-5E18 cm -3 The P dopant concentration is greater than 1E19cm -3 P+ dopant concentration; and 1-5E18cm -3 N dopant concentration, and greater than 1E19cm -3 N+ dopant concentration.

[0115] The EAM can be easily integrated onto a standard SOI chip, for example, with a 3 µm silicon device layer. The present embodiment is particularly relevant to a 3 µm silicon-on-insulator chip with a Si (111) handle wafer. When integrated onto an SOI chip, the waveguide structure 121 couples with the output waveguide and the input waveguide within the silicon device layer of the SOI chip.

[0116] Now refer to Figures 2A-2M An example method for making the EAM described above is described.

[0117] In the initial step, Figure 2A As shown in FIG. 1 , a silicon-on-insulator substrate comprises: a silicon support layer 101 ; a buried oxide (BOX) layer 102 on top of the silicon support layer; and a silicon device layer 103 on top of the BOX layer.

[0118] A hard mask 141 is applied to the SOI, which exposes only a portion of the silicon device layer. A suitable etchant known in the art is then applied to etch the uncovered portion of the silicon device layer and a portion of the BOX layer directly below the BOX layer, leaving a cavity at the base of which a portion of the silicon support layer is left exposed ( Figure 2B ).

[0119] A replacement layer of silicon 142 is then epitaxially grown from the exposed portion of the silicon support layer at the base of the cavity ( Figure 2C ), so that there is no or very little lattice mismatch between the original upper surface of a portion of the silicon substrate layer and the replacement silicon layer.

[0120] In the subsequent steps ( Figure 2D ), further photolithography is performed to apply an additional mask 143 extending over the first and second sidewalls 144, 145 of the cavity.

[0121] Once the additional mask has been applied, a layer of CREO123 is epitaxially grown on the replacement silicon layer ( Figure 2E ), the CREO layer has a lattice constant similar to the replacement silicon layer. In the embodiment shown, the CREO is grown directly onto an epitaxially grown Si (111) replacement layer.

[0122] The cavity is then filled by direct epitaxial growth of SiGeSn 146 onto the CREO layer ( Figure 2F Subsequent polishing is used to produce an upper surface of the SiGeSn material that is flat and flush with the upper surface of the silicon device layer 103 of the adjacent area of ​​the SOI chip ( Figure 2G ).

[0123] In a subsequent step, a further hard mask is applied and the SiGeSn material is etched accordingly, resulting in two channels separated by a ridge structure. The etching does not extend to the full depth of the SiGeSn material, leaving a rib waveguide structure having a ridge portion 204, a first plate portion 202 on a first side of the ridge structure 204 and a second plate portion 203 on a second side of the ridge structure ( Figure 2H ).

[0124] Once the SiGeSn waveguide structure 204 has been fabricated, dopants are applied ( Fig.2I , Figure 2J ) to produce the P and N doped regions of the device. First, the P doped region 250 ( Fig.2I); the initial step of the operation is to apply photoresist to all areas except the first plate portion. The gap left by the patterning of the photoresist intentionally extends over the ridge of the waveguide, rather than terminating at the sidewall, so that the area at the top of the ridge is left uncovered by the resist, thereby facilitating alignment. In this way, in one step, dopants can be applied to cover the P-doped region 250 that extends across the first portion of the plate and also across the first sidewall of the ridge. Typically, this involves applying the dopant at an angle, such as 45 degrees, relative to the sidewalls of the waveguide ridge.

[0125] The process is then repeated on the other side of the waveguide ridge ( Figure 2J ) to produce an N-doped region 251. The previous photoresist is removed and a subsequent photoresist is applied to cover all areas except the second plate portion. In this case, the gap left by the patterning of the photoresist intentionally extends over the ridge on the second side of the waveguide ridge, rather than terminating at the second sidewall of the waveguide, so that the area at the top of the ridge is left uncovered by the resist, thereby facilitating alignment. In this way, in one step, dopants can be applied to cover the P-doped region 250, which extends across the first portion of the plate and also across the first sidewall of the ridge. Typically, this involves applying the dopant at an angle such as 45 degrees relative to the sidewall of the waveguide ridge. At this stage in the method, the waveguide structure exhibits an L-shaped N-doped region extending along the entire length of the first plate portion and up the first sidewall of the ridge, and an L-shaped P-doped region extending along the entire length of the second plate portion and up the second sidewall of the ridge. An intrinsic region is left between the P and N-doped sidewalls, thereby producing a PIN junction.

[0126] A subsequent dopant step is performed to produce more concentrated P+ and N+ doped sub-regions in each of the first and second plates, respectively. Figure 2K and 2L ). Each of the sub-regions is narrower than the lateral dimensions of each of the first and second plate portions. Each of the sub-regions is produced by photoresist patterning and subsequent implantation with appropriate dopants. This time, the dopants are usually applied in a vertical direction, i.e. in a direction parallel to the sidewalls of the waveguide ridge. After implantation, an annealing is performed at 630°C for 10 seconds.

[0127] Examples of suitable dopants include boron (P dopant) and phosphorus or arsenic (N dopants).

[0128] In the final step of the manufacturing process ( Figure 2M ), after the via opening step, a metal strip electrode is deposited onto each of the more intensively doped sub-regions, thereby providing electrical contact for applying a bias across the PIN junction.

[0129] Below about Figure 3A and3B An alternative embodiment of an EAM according to the invention is described in which like reference numerals correspond to features described above in relation to the earlier embodiment. Figure 3A and 3B This embodiment and Figures 1A-1C The embodiment of 304 differs in that the rib waveguide is grown from SiGe instead of SiGeSn. In more detail, the rib waveguide comprises a ridge portion 304 on top of a SiGe slab. Thus, the resulting shape comprises a first slab portion at a first side of the ridge, and a second slab portion at a second side of the ridge opposite the first slab portion.

[0130] The P-doped region is located at the first slab portion and extends along the first sidewall 312 of the waveguide ridge, thereby creating an "L-shaped" dopant region. Similarly, the N-doped region is located at the second slab portion and extends along the second sidewall 313 of the waveguide ridge, the second sidewall being opposite and parallel to the first sidewall. The intrinsic region 314 of the SiGe waveguide is sandwiched between the first and second sidewalls, which creates a PIN junction across which a bias can be applied, which is used to control the optical properties of the SiGe and thereby modulate the optical signal passing through the modulator.

[0131] In addition to replacing the SiGeSn growth steps and fabrication steps with SiGe growth steps and fabrication steps, the EAM can be fabricated by Figures 2A-2M Described steps to perform.

[0132] Fabrication of EAMs with other bulk materials such as InGaAs and InGaAsP can also be achieved by Figures 2A-2M The steps described are to be performed,

[0133] Further embodiments of the present invention relate to quantum well materials that exhibit a quantum-confined Stark effect (QCSE). Figure 4A and 4B as well as Figures 5A-5N Describing the first of these embodiments, Figure 4A and 4B Schematic diagrams in cross-sectional form along the light propagation direction are shown respectively, Figures 5A-5N Example steps in an embodiment of a method of manufacturing an EAM are shown.

[0134] In this embodiment, the portion of the BOX layer that has been removed is replaced not only with a crystalline rare earth oxide (CREO) layer and a silicon layer on top of the silicon, but also with a SiGe transition buffer layer that acts as an interface between the CREO and the waveguide structure. The regrown silicon layer, CREO layer, and SiGe transition layer together have a thickness that is equal to or substantially equal to the thickness of the BOX layer in the adjacent region.

[0135] The waveguide structure 421 is also different from the previous embodiments. The waveguide structure 421 takes the form of a ridge made of SiGe MQW material with doped regions above the MQW structure and below the MQW structure. In this way, the PIN junction is vertical rather than horizontal. However, the doped regions are shaped so that the electrodes contacting them are still placed on either side of the ridge. As with the previous embodiments, a bias applied across these electrodes (and therefore across the PIN junction) creates a modulation region within the waveguide.

[0136] In more detail, Figure 4A and 4B In the illustrated embodiment, the P-doped region is located below the SiGe MQW structure, between the SiGe transition buffer layer and the SiGe MQW structure. The P-doped region 411 extends outward to the first side of the waveguide, thereby creating a plate-like region, and the first electrode 422 can be placed on top of the plate-like region to contact the P-doped region. Most of the area below the top electrode on the second side of the plate is etched away to minimize parasitic capacitance for high speed. Not all of the P-SiGe buffer is etched away, so that the P-SiGe buffer extends to the second side, but extends significantly less than the first side. The N-doped region 413 is located at the top of the SiGe MQW material of the ridge, leaving an undoped region 403 of the SiGe MQW between the P-doped region and the N-doped region. The second electrode 423 contacts the top of the waveguide at the N-doped region and extends along the side ridge of the waveguide, thereby forming a contact point at the side of the waveguide ridge opposite to the first electrode 422.

[0137] like Figure 4A As shown in , the waveguide structure may include inlet and outlet interface structures between the MQW material and the input and output waveguides, each of which is formed of silicon. The purpose of these structures is to minimize the losses at the interface region and to maximize the strength of the signals coupled into and out of the MQW waveguides. In the embodiment shown, the interface structure includes amorphous silicon 440, with an additional layer of Si3N4 441 located between the amorphous silicon and the silicon, and also between the amorphous silicon and the MQW waveguides.

[0138] To manufacture Figure 4A and 4B The structure of the present invention first provides an SOI waveguide and as described above Figure 2A-2E Create a "no box" area as described. Figure 5AAs shown in , the SiGe MQW waveguide material is then epitaxially grown inside the cavity. This step of epitaxially growing the MQW structure involves growing the following layers: a SiGe transition layer on top of the CREO layer; a P-doped SiGe buffer layer on top of the SiGe transition buffer layer; a SiGe MQW structure on top of the P-doped layer; and an N-doped SiGe layer on top of the MQW layer. An example of a detailed MQW structure is shown in Figure 4C Shown in.

[0139] The quantum well material may have a layer thickness of less than 200 nm. Spacer layers are typically located above the QW material and below the QW material, between the doped regions and the QW layers.

[0140] After epitaxial growth, a hard mask of Si3N4 is deposited on top of the N-doped layer, and chemical mechanical polishing (CMP) is performed to produce a flat surface ( Figure 5C ). Next, dry etching is performed so that the Si outside the cavity has the same height as the height of the MQW stack in the cavity.

[0141] Once the SOI surface has been leveled, deposit a SiO2 layer and deposit a photoresist ( Figure 5D ), the photoresist is exposed for etching areas to create trenches (3-5 µm) down through the MQW material layer to obtain areas at the entrance and exit of the MQW waveguide, creating interfaces with silicon input and output waveguides ( Figure 5E ).

[0142] Once the trench has been etched, the amorphous silicon ( Figure 5G ) to trim the trenches, a 240 nm Si3N4 layer with a refractive index of 2.6 was deposited to coat the base and sidewalls of the trenches ( Fig. 5F ), where any excess amorphous silicon is removed from the SOI surrounding the cavity via dry etching and CMP ( Figure 5H ). The upper surface of Si3N4 on the substrate is flush with the upper surface of BOX. Figure 5D-5I All depict cross-sectional views along the direction of light propagation.

[0143] Then the SiO2 deposition is performed ( Fig.5I ), deposition of photoresist ( Figure 5J ) and etching ( Figure 5K ) to produce the waveguide sidewalls. Initially an etch is performed to etch the N-doped layers and the MQW layers, but not the P-doped layers. A separate etch ( Figure 5L ) to etch away areas of the P-doped layer as described below, which are only on one side of the waveguide ridge below the top electrode, leaving the underlying SiGe transition layer exposed on that side to minimize parasitic capacitance.

[0144] A silicon oxide layer will be formed over the device and vias will be created over the P-doped and N-doped regions ( Figure 5M ), allowing metal contacts to be deposited directly on top of the P-doped and N-doped layers ( Figure 5N ). These metal contacts serve as electrodes across which a bias voltage is applied to operate the resulting PIN junction.

[0145] refer to Fig. 6A and 6B Further embodiments of the optical device according to the invention are described. Fig. 6A and 6B Schematic diagrams of an optoelectronic device including a quantum well material exhibiting a quantum confined Stark effect (QCSE) along the light propagation direction and in cross-section are shown respectively. The optoelectronic device of this embodiment may take the form of a part of a laser or may form an EAM.

[0146] In this embodiment, the epitaxially grown stack (EPI stack) is based on AlInGaAs multiple quantum well material 603 .

[0147] and Figure 4A -C is the same as the embodiments of 5A-N, Fig. 6A and 6B This embodiment of exhibits a vertical PIN junction. However, compared to the embodiments of Figures 4 and 5, the N-doped regions of the embodiment of Figure 6 are located at the base of the stack, closest to the CREO layer, while the P-doped regions are located at the top of the stack.

[0148] Starting from the base of the stack and building up towards the top of the stack, the stack includes: N-doped InP buffer layer 612; InGaAsP layer 610; AlInGaAs multiple quantum well material 603; P-doped InP layer 613; P-doped InGaAsP layer 614; and P-doped InGaAs layer 615.

[0149] The N-doped InP layer is directly on top of the InP transition layer, which in turn is directly on top of the CREO layer. The first metal electrode 622 contacts the N-doped InP buffer layer 612, and the second metal electrode contacts the P-doped InGaAs layer at the top of the stack. The second electrode is shaped so that it extends from the top of the stack (which is also the sidewall of the waveguide) and laterally away from the sidewall of the waveguide so that it is on the opposite side of the waveguide from the first electrode. In this way, although the PIN junction across the stack is vertical, the electrodes are placed in a lateral arrangement and both can be approached from the same side of the SOI.

[0150] In addition to the more complex structure of the EPI stack, Fig. 6A and 6BThe manufacturing process of the equipment is similar to the above Figures 5A-5N Same as those described.

[0151] The fabrication process for devices with InGaNAs MQWs is similar to that described above, except that the EPI stack has a more complex structure. Figures 5A-5N Same as those described.

[0152] Figure 7 A schematic top view of an EAM 700 according to some embodiments of the present invention is shown. Broadly speaking, light enters the device from either the left or right hand side and travels along a silicon waveguide located within the 1 µm silicon device layer before entering the EAM located in the center. The EAM includes an optically active stack that includes III-V multiple quantum wells (MQWs), bulk InGaAsP layers, or bulk AlInGaAs layers. Figures 8A-8D Shows Figure 7 Various cross sections of the device shown in .

[0153] Fig. 8A Shown along Figure 7 Here, a silicon waveguide in a silicon device layer on either side of a III-V MQW or InGaAsP layer is shown. The III-V layer may be an AlInGaAs layer including multiple quantum wells.

[0154] A bridge waveguide is located between each silicon waveguide and the EAM, in this example provided by a portion of amorphous silicon (a-Si) sandwiched between spacers formed of silicon nitride. The silicon nitride spacers act as an anti-reflective coating.

[0155] The p-doped and n-doped regions of the optically active stack are connected to corresponding electrodes, allowing an electric field to be applied across the optically active layers of the optically active stack. The device is covered with a silicon dioxide layer and has a silicon nitride layer located between the cover layer and the corresponding silicon waveguides.

[0156] like Figure 8B As shown most clearly in FIG, a first electrode contacts an n-doped region located below the optically active layer, while a second electrode contacts a p-doped region located above the optically active layer. Of course, these doping polarities can be reversed. A crystalline oxide layer (in this example a crystalline rare earth oxide, but it could equally be another crystalline oxide as described above) is located between the silicon substrate and the optically active layer. The crystalline oxide layer reduces the degree to which the lattice mismatch within the EAM device is present.

[0157] The optically active stack may include the following layers, with layer numbering decreasing from the uppermost layer (16) to the lowermost layer (1) of the optically active stack:

[0158]

[0159] Alternatively, the optically active stack may comprise the following layers, with layer numbering decreasing from the uppermost layer (10) to the lowermost layer (1) of the optically active stack:

[0160]

[0161] Figure 8C yes Figure 7 FIG. 1 is a cross-sectional view of the device in FIG. 1 along line CC. Here, the silicon ridge waveguide can be more clearly seen protruding from the upper surface of the silicon-on-insulator layer. The silicon waveguide has a silicon nitride layer disposed on top, and on top of the silicon nitride layer is the silicon dioxide capping layer discussed previously.

[0162] Fig.8D Shows Figure 7 A cross-sectional view of the device in FIG. 5 along line DD, i.e. midway through the bridge waveguide. As can be seen here, the amorphous silicon or alpha silicon effectively matches the geometry of the silicon waveguide adjacent to it.

[0163] Figure 9a -9w(ii) illustrates the manufacturing process Figure 7 The method of EAM shown in . In a previous step not shown, a silicon-on-insulator wafer with a 1 µm device layer is provided. The device layer can optionally be covered with a silicon nitride layer (e.g., a Si3N4 layer, which is silicon-rich and has a refractive index of 2.7).

[0164] In the first step, if Figure 9a , a silicon-on-insulator wafer includes: a silicon substrate, a buried oxide (BOX) layer directly on top of the silicon substrate, and a silicon-on-insulator or silicon device layer directly on top of the BOX layer that has been etched so as to remove a portion of the silicon device layer, a portion of the BOX layer below the portion of the silicon device layer, and a portion of the silicon substrate below the portion of the BOX layer. The result is a cavity extending from the uppermost surface of the wafer down into a portion of the silicon substrate. An optional silicon nitride layer is shown covering the silicon device layer, which optional silicon nitride layer is also etched in the process.

[0165] In subsequent steps, such as Figure 9b As shown in FIG. 1 , the sidewalls of the cavity are lined with a 20 nm silicon nitride liner via a non-isomorphic etch. Fig.9cAs shown, an optically active stack is epitaxially grown in the cavity. Due to the nature of epitaxial growth, small facetings will exist in at least the locations indicated. The optically active stack includes a layer of crystalline oxide as a layer adjacent to the exposed silicon substrate, in some embodiments, the crystalline oxide is a crystalline rare earth oxide (CREO). If the epitaxial growth is a blanket growth, a poly layer (e.g., polycrystalline III-V) is deposited on top of the exposed silicon nitride layer, as shown in FIG. 9C ; however, if the epitaxial growth is selective, no poly layer is deposited on top of the exposed silicon nitride layer and thus the deposition is skipped. Figure 9d The optically active stack is grown so as to have an uppermost surface aligned with an uppermost surface of a silicon nitride layer above the device layer. Thus, the waveguide modes of the silicon device layer waveguides (fabricated later and discussed below) are aligned with the waveguide modes of the optically active stack waveguides (fabricated later and discussed below). Figure 9d As shown in , the next step is to deposit a silicon dioxide layer as a hard mask on the uppermost layer of the optically active stack and etch away the portion of the poly material (poly) located near the cavity. This etch relieves wafer stress.

[0166] exist Fig.9e In the steps shown in Figure 9d The structure shown in FIG. 1 is subjected to a chemical-mechanical polishing process in order to remove the remaining poly-type material and in order to leave a thinner silicon dioxide layer adjacent to the uppermost layer of the optically active stack. The thinner silicon dioxide layer may have a thickness of about 20 nm. Thereafter, as Figure 9f As shown in , a silicon dioxide hard mask is deposited and a photoresist is patterned to facilitate the next step of etching the faceted areas.

[0167] The etching result is Figure 9g , where the trenches extend from either side of the optically active stack. The etch removes most, if not all, of the facet defects discussed previously. As shown, the etch is stopped midway through the n-doped layer of the optically active stack. Next, as shown Figure 9h As shown in , silicon-rich silicon nitride (e.g., Si3N4) is deposited on the exposed surface of the structure. The silicon-rich silicon nitride may have a refractive index of about 2.7. The sidewalls of the trenches are coated with silicon nitride having a thickness between 230 nm and 260 nm. The bed of the trenches is coated with silicon nitride such that the uppermost portion of each silicon nitride bed is aligned with the top surface of the corresponding adjacent BOX layer, as shown in . Figure 9h as shown in .

[0168] In the next step, if Figure 9iAs shown in , amorphous silicon is deposited in bulk on the structure, filling the cavity and providing a layer on top of the silicon nitride layer above the device layer. The amorphous silicon layer is then etched, as shown in Figure 9j , leaving two discrete regions of amorphous silicon located above and within the now filled trenches, which relieves the wafer stress caused by the amorphous silicon layer.

[0169] Then, if Figure 9k As shown in , the structure undergoes a chemical-mechanical polishing process, leaving a silicon dioxide layer about 100 nm high on top of the uppermost layer of the optically active stack. The etching also removes the upper parts of the two uppermost silicon nitride layers. In a further step, as Figure 9l As shown in , the amorphous silicon is etched back so that the resulting structure has an upper surface flush with the upper surface of the 1 µm silicon device layer. In other words, since the silicon nitride layer in the bed of the trench has an upper surface aligned with the upper surface of the BOX layer, and the amorphous silicon is deposited on top of the silicon nitride layer, the amorphous silicon has a height extending from the uppermost surface of the BOX layer to the uppermost surface of the silicon device layer, that is, it has the same height as the silicon device layer.

[0170] exist Figure 9l Following the steps shown in , additional silicon nitride is deposited to fill the space previously occupied by the now etched amorphous silicon. This results in Figure 9m Due to the nature of this deposition, a defect region results above each trench. Figure 9n As shown in , the structure undergoes an additional chemical-mechanical polishing process, resulting in the removal of defects.

[0171] exist Figure 9n Following the steps shown in , a silicon dioxide capping layer is deposited over the structure and a silicon nitride hard mask is provided over the silicon dioxide layer. These are used in subsequent steps to fabricate the waveguides.

[0172] Figure 9p (i) and Figure 9p (ii) show the Figure 7 9q(i) and 9q(ii) (also cross sections along B-B' and C-C', respectively) such that the n-doped layers of the optically active stack are exposed. This etching provides a ridge waveguide that will ultimately be provided within the optically active stack. It is noteworthy that the silicon nitride layer located above the silicon device layer is not etched.

[0173] Next, as shown in Figures 9s(i) and 9s(ii) (also cross sections along BB' and CC'), a silicon dioxide layer is deposited and a photoresist is provided that covers the waveguide structure within the optically active stack but does not cover the silicon nitride and device layers that are adjacent to the optically active stack in the guiding direction. This is most clearly seen by comparing the BB' and CC' cross sections, where no photoresist is seen in the CC' cross section.

[0174] After deposition of this photoresist, the unmasked portion is then etched, thereby removing the upper silicon dioxide layer above the silicon device layer and exposing the silicon nitride waveguide, resulting in the structure shown in Figure 9t(ii) (cross section along C-C'). It is noteworthy that, apart from the removal of the photoresist, the structure seen along cross section B-B' and illustrated in Figure 9t(i) is unchanged from the structure shown in Figure 9s(i). This etch provides the SOI waveguide, which includes an upper silicon nitride layer and a silicon dioxide capping layer. The light is primarily confined to the silicon device layer, and the silicon nitride layer on top of the device layer serves as an upper capping layer

[0175] The photoresist is then removed and a further layer of silicon dioxide is deposited on all upper exposed surfaces of the structure. Next, as shown in Figures 9u(i) and 9u(ii) (cross sections BB' and CC' respectively), a further etch is performed to provide a trench and transparent area for the top electrode and thereby remove the silicon nitride layer above the uppermost layer of the optically active stack. By performing this etch, the parasitic capacitance within the final device is reduced. A layer of silicon dioxide is provided between the trench and the layer of the optically active stack above the crystalline oxide layer so that the electrode is insulated from this layer of the optically active stack when placed.

[0176] Next, as shown in FIG. 9v (i) of the cross section along BB', contact vias are opened for the n-doped and p-doped regions of the optically active stack so that the upper surface of these regions is exposed. Subsequently, as shown in FIG. 9w (i) of the cross section along BB', a metallization process is performed to provide a first and a second electrode. The first electrode contacts the p-doped region and the second electrode contacts the n-doped region. FIG. 9w (ii) (cross section along CC') reflects FIG. 9v (ii) and FIG. 9u (ii) in that this region of the structure is not changed during these steps of the manufacturing process.

[0177] Figure 10a-10v A variant method of fabricating an electro-absorption modulator (EAM) according to some embodiments of the present invention using the Franz-Keldysh effect on a 3 µm silicon-on-insulator wafer is demonstrated.

[0178] In an initial step not shown, a silicon-on-insulator wafer is provided with a silicon device layer (also referred to as a silicon-on-insulator or SOI layer) having a height of 3 µm as measured from the uppermost surface of a buried oxide (BOX) layer to the uppermost surface of the device layer. The BOX layer is over a silicon substrate having a (111) crystallographic alignment. An optional silicon dioxide layer is disposed over the silicon device layer such that the silicon device layer is sandwiched between the silicon dioxide layer and the buried oxide layer. In some examples, the buried oxide layer is formed of silicon dioxide.

[0179] Later, in Fig.10a In the steps shown in , a portion of the silicon device layer, a portion of the BOX layer below the portion of the silicon device layer, and a portion of the silicon substrate below the portion of the BOX layer are etched away. The result is a cavity as seen in FIG. 10A . The cavity extends from the uppermost surface of the wafer down into a portion of the silicon substrate. When present, the silicon dioxide layer is also partially etched.

[0180] Then, if Fig.10b As shown in , the sidewalls of the cavity are lined with a 20 nm silicon nitride liner via a non-isomorphic etch. Fig.10c As shown in , an optically active stack is epitaxially grown in the cavity. Due to the nature of epitaxial growth, small flats will exist in at least the locations indicated. The optically active cavity includes a layer of crystalline oxide as a layer adjacent to the exposed silicon substrate, in some embodiments, the crystalline oxide is a crystalline rare earth oxide (CREO). The optically active layer of the optically active stack, in this example, an InGaAsP layer is grown so as to have a bottommost surface aligned with the bottommost surface of the adjacent silicon-on-insulator layer / device layer. If the growth of the optically active stack is performed by cap growth, a poly layer (e.g., polycrystalline III-V) is deposited on top of the exposed silicon nitride layer, such as Fig.10c However, if the growth of the optically active stack is carried out by a selective growth process, no poly layer is deposited on top of the exposed silicon nitride layer, and thus Fig.10d The steps in are skipped. In the next step, if Fig.10d As shown, a silicon dioxide layer is deposited as a hard mask on the uppermost layer of the optically active stack, and a portion of the poly material is etched away near the cavity. This etch releases wafer stress.

[0181] The optically active stack may be formed of the following layers, with the layer numbering decreasing from the uppermost layer (6) to the lowermost layer (1) of the optically active stack:

[0182]

[0183] Return to this method, such as Fig.10eAs shown in , after etching has been performed to partially remove the poly material, the structure undergoes chemical-mechanical polishing to remove the remaining poly material and thereby leave a silicon dioxide layer of approximately 20 nm on the uppermost surface of the structure. Fig.10f As shown in FIG. 1 , a silicon dioxide layer is provided and then a photoresist is patterned. Figure 9f Likewise, the photoresist at least partially covers the optically active stack and completely covers the device silicon layers located on either side of the optically active stack.

[0184] After deposition of the photoresist, an etch is performed to provide trenches extending down to the silicon substrate. The result of this etch is Figure 10g The etching removes the small facet defects discussed previously. Figure 9g The corresponding etching performed is compared, Figure 10g The etching in passes through all layers of the optically active stack and partially into the underlying silicon substrate.

[0185] After the etching step, Fig.10h In the step shown in , silicon-rich silicon nitride (e.g., Si3N4) is deposited on the exposed surface of the structure. The silicon-rich silicon nitride may have a refractive index of about 2.7. The sidewalls of the trenches are coated with silicon nitride having a thickness between 230 nm and 260 nm. The trench beds are coated with silicon nitride such that the uppermost portion of each silicon nitride bed is aligned with the top surface of the adjacent BOX layer.

[0186] In the next step, if Fig.10i As shown in , amorphous silicon is deposited in bulk over the structure, filling the cavity and providing a layer on top of the silicon nitride layer located above the device layer. The amorphous silicon layer is then etched, as shown in Fig.10j As shown in , two discrete amorphous silicon regions are left above and within each of the now filled trenches, which relieves the wafer stress caused by the amorphous silicon layer.

[0187] Then, if Figure 10k As shown in , the structure undergoes a chemical-mechanical polishing process, leaving a silicon dioxide layer about 20 nm high on top of the uppermost layer of the optically active stack. The etch also removes the remaining silicon nitride layer above the device layer.

[0188] Figures 101(i) and 101(ii) show the Figure 7 The BB' and CC' cross sections show subsequent fabrication steps. It can be seen that a further silicon dioxide layer is deposited across the exposed upper surface of the structure, and then a photoresist is provided and patterned. The photoresist is provided on a portion of the optically active stack and on a portion of the silicon device layer adjacent to the optically active stack in the guiding direction.

[0189] Thus, when etched, a waveguide structure is provided in the optically active stack and in the silicon device layer adjacent to the optically active stack as shown in Figures 10m(i) and 10m(ii) (cross sections through B-B' and C-C', respectively). After this etching, a further silicon dioxide layer is provided, wherein the thickness of the further silicon dioxide layer is between 20 nm and 50 nm, as shown in Figures 10m(i) and 10m(ii) (cross sections through B-B' and C-C', respectively). Fig.10c as shown in .

[0190] Then, if Fig.10o As shown in , a photoresist is provided on a portion of the structure, leaving a gap that exposes a first sidewall of a waveguide in the optically active stack and a first lateral region of the optically active stack adjacent to the sidewall. These exposed regions are then doped with an n-type dopant (e.g., silicon or silicon ions) to provide an n-doped region extending from the first sidewall of the optically active stack downwardly and across the first lateral region adjacent thereto. The photoresist is then removed.

[0191] Then apply another photoresist such as Figure 10p , thereby leaving the exposed second sidewall optically active stack and the second lateral region adjacent thereto. These exposed regions of the optically active stack are then doped with a p-type dopant (e.g., Be or Zn) to provide a p-doped region extending down the first sidewall of the optically active stack and across the second lateral region adjacent thereto. The photoresist is then removed.

[0192] Further photoresist is then applied, leaving a portion of the first lateral region exposed, such as Figure 10q The exposed region is then doped with additional n-type dopants (e.g., silicon or silicon ions) to provide a heavily n-doped (n+) region within the first lateral region. The photoresist is then removed. Additional photoresist is then applied, leaving a portion of the second lateral region exposed (in some embodiments, equivalent in size to the first lateral region), as shown in FIG. Figure 10s . The exposed region is then doped with an additional p-type dopant (e.g., Be) to provide a heavily p-doped (p+) region within the second lateral region. The photoresist is then removed. The resulting structure is a waveguide in which two opposing sidewalls are doped with dopants of opposite polarity, and a lateral region adjacent to each of these sidewalls that is doped to a higher concentration than the adjacent sidewalls.

[0193] Then, if Figure 10t As shown in , an additional silicon dioxide layer is provided over the entire device, which silicon dioxide layer has a thickness of about 500 nm in some embodiments. The structure is then subjected to a rapid thermal process annealing between 700°C and 850°C.

[0194] After the annealing step, contact vias are opened through the silicon dioxide layer to each of the heavily doped regions. Figure 10u Thus, subsequently, a metallization process may be used to provide electrical contacts to each of the heavily doped regions, such as Figure 10v as shown in .

[0195] Although the present invention has been described in conjunction with the above exemplary embodiments, many equivalent modifications and variations will be apparent to those skilled in the art when this disclosure is given. Therefore, the exemplary embodiments of the present invention set forth above are considered to be illustrative rather than restrictive. Various changes may be made to the described embodiments without departing from the spirit and scope of the present invention.

[0196] All references mentioned above are hereby incorporated by reference.

Claims

1. An electroabsorption modulator (EAM), comprising: A silicon-on-insulator (SOI) substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; a waveguide region wherein a portion of the silicon device layer and a portion of the BOX layer below the portion of the device layer have been removed, the portion of the BOX layer having been replaced with a layer of crystalline oxide and a layer of silicon on top of the silicon; and A waveguide structure is located directly on top of the crystalline oxide layer, the waveguide structure including a P-doped region and an N-doped region with an intrinsic region therebetween, thereby producing a PIN junction, across which a bias can be applied to produce a modulation region.

2. The EAM of claim 1, wherein the waveguide structure is made of one or more of the following materials: SiGeSn, SiGe, InGaAs, AlInGaAs and InGaAsP.

3. The EAM of claim 1, wherein the crystalline oxide layer has a thickness of 20 nm to 400 nm.

4. The EAM of claim 1, wherein the silicon support layer is Si(111) and the replacement silicon layer is Si(111).

5. The EAM of claim 1, wherein the waveguide structure is a rib waveguide, the rib waveguide comprising: a waveguide ridge on a plate, wherein a first plate portion is on a first side of the ridge and a second plate portion is on a second side of the ridge; as well as Wherein the waveguide ridge, the first plate portion and the second plate portion are all formed of the same material as one another.

6. The EAM of claim 5, wherein the P-doped region is located at the first plate and the N-doped region is located at the second plate.

7. The EAM of claim 6, wherein the P-doped region extends into a first sidewall of the ridge and / or wherein the N-doped region extends into a second sidewall of the ridge.

8. The EAM of claim 6, further comprising a first metal contact at the first plate electrically connected to the P-doped region and a second metal contact at the second plate portion electrically connected to the N-doped region.

9. An EAM according to any one of the preceding claims, wherein the SOI substrate is a 3 μm SOI platform.

10. The EAM of claim 1, wherein the waveguide structure is made of one or more of the following materials: SiGe multiple quantum well (SiGe MQW), AlInGaAs MQW, InGaAsP MQW and InGaNAs MQW. The EAM of claim 10 , wherein the SOI substrate is a 1 μm SOI platform.

12. A method of manufacturing an optoelectronic device, the method comprising: Providing a silicon-on-insulator substrate, the substrate comprising: a silicon support layer; a buried oxide BOX layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; etching through the BOX layer and a portion of the silicon device layer to create a cavity in the substrate exposing a portion of the silicon support layer; epitaxially growing a replacement layer of silicon on top of the exposed portion of the silicon support layer; epitaxially growing a layer of crystalline oxide on top of the replacement layer of silicon, the replacement layer of silicon and the crystalline oxide layer replacing the portion of the BOX layer that has been etched away; epitaxially growing a layer of a first material on top of the crystalline oxide layer; and A waveguide structure is fabricated within the layer of the first material, the waveguide structure comprising a P-doped region and an N-doped region with an intrinsic region therebetween, thereby creating a PIN junction across which a bias can be applied to function as a modulation region.

13. The method of claim 12, wherein the first material is one or more of the following materials: SiGeSn, SiGe, InGaAs, AlInGaAs, InGaAsP, SiGe multiple quantum well (SiGe MQW), AlInGaAs MQW, InGaAsP MQW and InGaNAs MQW.

14. The method according to claim 12, wherein the step of manufacturing the waveguide structure comprises: The first material layer is etched to form a rib waveguide of the first material, the rib waveguide comprising a ridge on a plate, the plate comprising a first plate portion on a first side of the ridge and a second plate portion on a second side of the ridge. 15 . The method of claim 14 , wherein the P-doped region is located at the first plate portion, and the N-doped region is located at the second plate portion. 16 . The method of claim 15 , wherein the P-doped region extends into a first sidewall of the ridge and / or wherein the N-doped region extends into a second sidewall of the ridge.

17. The method of any one of claims 12 to 16, wherein the silicon support layer is Si(111); and the replacement silicon is Si(111).

18. The method according to any one of claims 12 to 16, wherein the optoelectronic device is an electro-absorption modulator (EAM).

19. An optoelectronic device, comprising: A silicon-on-insulator (SOI) substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; a waveguide region wherein a portion of the silicon device layer and a portion of the BOX layer below the portion of the device layer have been removed, the portion of the BOX layer having been replaced with a layer of crystalline oxide and a layer of silicon on top of the silicon; and A waveguide structure is located directly on top of the crystalline oxide layer, the waveguide structure including a P-doped region and an N-doped region with an intrinsic region therebetween, thereby producing a PIN junction, across which a bias can be applied to produce a modulation region.

20. The optoelectronic device of claim 19, wherein the optoelectronic device is an EAM or a laser, or a photodetector.

21. An optoelectronic device according to claim 19 or claim 20, wherein the waveguide structure is an AlInGaAs MQW waveguide structure.

22. The optoelectronic device of claim 19, wherein the waveguide structure is an InGaNAs MQW waveguide structure.

23. An electro-absorption modulator (EAM), comprising: Silicon on insulator SOI substrate, comprising: Silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; a waveguide region, wherein a portion of the silicon device layer, a portion of the BOX layer below the portion of the device layer, and a portion of the silicon support layer below the portion of the BOX layer have been removed, at least a portion of the portion of the silicon support layer having been replaced with a layer of crystalline oxide on top of the remaining silicon support layer; and A waveguide structure is located directly on top of the crystalline oxide layer, the waveguide structure including a P-doped region and an N-doped region with an intrinsic region therebetween, thereby producing a PIN junction, across which a bias can be applied to produce a modulation region.

24. An electro-absorption modulator (EAM) according to claim 23, wherein at least a portion of said portion of said silicon support layer and said portion of said BOX layer has been replaced with a layer of crystalline oxide.

25. The electro-absorption modulator (EAM) of claim 23, wherein a passive waveguide provided in the silicon device layer and adjacent to the waveguide region is coupled to the waveguide region via a bridge waveguide.

26. The electro-absorption modulator (EAM) of claim 25, wherein the bridge waveguide comprises a liner channel filled with a filling material having a refractive index similar to the refractive index of a material forming a sidewall adjacent to the bridge waveguide.

27. An electro-absorption modulator (EAM) according to claim 26, wherein the pad is formed of silicon nitride.

28. The electro-absorption modulator (EAM) of claim 26, wherein a lowermost surface of the sidewall of the channel and a top surface of a portion of the liner located in the base of the channel are aligned with a top surface of the buried oxide layer.

29. The electro-absorption modulator (EAM) of claim 26, wherein the spacer has a thickness of at least 200 nm and no greater than 280 nm.

30. The electro-absorption modulator (EAM) of claim 26, wherein the fill material is amorphous silicon.

31. An electro-absorption modulator (EAM) according to any one of claims 23 to 30, wherein the waveguide structure is formed from a plurality of layers, at least one layer being formed from Indium Phosphide.

32. A method of manufacturing an electroabsorption modulator (EAM), the method comprising: Providing a silicon-on-insulator substrate, the substrate comprising: a silicon support layer; a buried oxide BOX layer on top of the silicon support layer, and a silicon device layer on top of the BOX layer; etching through the silicon device layer, the BOX layer, and a portion of the silicon support layer to create a cavity in the substrate exposing a portion of the silicon support layer; epitaxially growing a layer of crystalline oxide on top of the exposed portion of the silicon supporting layer, the crystalline oxide layer replacing a portion of the portion of the silicon supporting layer that has been etched away; epitaxially growing a layer of a first material on top of the crystalline oxide layer; and A waveguide structure is fabricated within the layer of the first material, the waveguide structure comprising a P-doped region and an N-doped region with an intrinsic region therebetween, thereby creating a PIN junction across which a bias can be applied to function as a modulation region.

33. The method according to claim 32, wherein the step of manufacturing the waveguide structure comprises the following sub-steps: etching one or more channels adjacent to the first material to remove any edge defects thereof; lining the one or more channels with a liner to provide a liner channel; as well as The liner channel is filled with a fill material having a refractive index similar to a refractive index of a material forming the sidewalls such that the fill material forms a bridge waveguide in the channel between a passive waveguide in the silicon device layer and the waveguide structure.

34. The method of claim 33, wherein the liner is formed of silicon nitride.

35. The method of claim 33, wherein the liner has a thickness of at least 200 nm and no greater than 280 nm.

36. The method of any one of claims 33 to 35, wherein the filling material with which the liner channel is filled comprises amorphous silicon.

Images